36th week of 2022 patent applcation highlights part 56 |
Patent application number | Title | Published |
20220285201 | WAFER ASSEMBLY FOR MEMS FABRICATION - A wafer assembly for use in a MEMS fabrication process. The wafer package includes: a MEMS wafer having a first side and an opposite second side; a silicone-free peel tape releasably attached to the first side of the wafer; a wafer bonding tape attached to the peel tape; and a carrier substrate releasably attached to the first wafer bonding tape. | 2022-09-08 |
20220285202 | WAFER LIFT PIN SYSTEM - A wafer lift pin system is capable of dynamically modulating or adjusting the flow of gas into and out of lift pins of the wafer lift pin system to achieve and maintain a consistent pressure in supply lines that supply the gas to the lift pins. This enables the wafer lift pin system to precisely control the speed, acceleration, and deceleration of the lift pins to achieve consistent and repeatable lift pin rise times and fall times. A controller and various sensors and valves may control the gas pressures in the wafer lift pin system based on various factors, such as historic rise times, historic fall times, and/or the condition of the lift pins. This enables smoother and more controlled automatic operation of the lift pins, which reduces and/or minimizes wafer shifting and wafer instability, which may reduce processing defects and maintain or improve processing yields. | 2022-09-08 |
20220285203 | DOUBLE PATTERNING TECHNIQUES FOR FORMING A DEEP TRENCH ISOLATION STRUCTURE - Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches. | 2022-09-08 |
20220285204 | SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE - A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole. | 2022-09-08 |
20220285205 | SELECTIVE ETCHING PROCESS FOR SiGe AND DOPED EPITAXIAL SILICON - The present disclosure relates to a fabricating procedure of a radio frequency device, in which a precursor wafer including active layers, SiGe layers, and a silicon handle substrate is firstly provided. Each active layer is formed from doped epitaxial silicon and underneath a corresponding SiGe layer. The silicon handle substrate is over each SiGe layer. Next, the silicon handle substrate is removed completely, and the SiGe layer is removed completely. An etch passivation film is then formed over each active layer. Herein, removing each SiGe layer and forming the etch passivation film over each active layer utilize a same reactive chemistry combination, which reacts differently to the SiGe layer and the active layer. The reactive chemistry combination is capable of producing a variable performance, which is an etching performance of the SiGe layer or a forming performance of the etch passivation film over the active layer. | 2022-09-08 |
20220285206 | USING A LINER LAYER TO ENLARGE PROCESS WINDOW FOR A CONTACT VIA - In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure. | 2022-09-08 |
20220285207 | SEMICONDUCTOR DEVICE - A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film. | 2022-09-08 |
20220285208 | SEMICONDUCTOR CHIP STRUCTURE - A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer. | 2022-09-08 |
20220285209 | Conductive Feature of a Semiconductor Device and Method of Forming Same - A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening. | 2022-09-08 |
20220285210 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature. | 2022-09-08 |
20220285211 | METHODS AND SYSTEMS FOR FILLING A GAP - Disclosed are methods and systems for filling a gap. An exemplary method comprises providing a substrate to a reaction chamber. The substrate comprises the gap. The method further comprises at least partially filling the gap with a gap filling fluid. The methods and systems are useful, for example, in the field of integrated circuit manufacture. | 2022-09-08 |
20220285212 | SUBTRACTIVE METALS AND SUBTRACTIVE METAL SEMICONDUCTOR STRUCTURES - Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less. | 2022-09-08 |
20220285213 | MICROELECTRONIC ASSEMBLY FROM PROCESSED SUBSTRATE - Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary. | 2022-09-08 |
20220285214 | THE NOVEL DOUBLE PATTERNING APPROACH BY DIRECT METAL ETCH - In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance. | 2022-09-08 |
20220285215 | CONTACT FEATURES OF SEMICONDCUTOR DEVICES - A semiconductor device includes a conductive feature, a dielectric layer disposed over the conductive feature, and a contact feature extending through the dielectric layer. The contact feature has an upper portion and a lower portion. The upper portion is spaced apart from the dielectric layer with a spacer layer. The lower portion is electrically coupled to the conductive feature and in contact with the dielectric layer. | 2022-09-08 |
20220285216 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED VIAS - A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via. | 2022-09-08 |
20220285217 | WAFER THINNING METHOD - The wafer thinning method of the present disclosure includes: providing a wafer having a front surface and a back surface opposite to the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; dicing the wafer with a dicing blade; ablating the wafer by performing a chemical solution or plasma process on the back surface of the wafer to thin the wafer; and separating the wafer into a plurality of dies. | 2022-09-08 |
20220285218 | LASER LIFT-OFF METHOD FOR SEPARATING SUBSTRATE AND SEMICONDUCTOR-EPITAXIAL STRUCTURE - The present disclosure provides a laser lift-off method for separating substrate and semiconductor-epitaxial structure, which includes: providing at least one semiconductor device, wherein the semiconductor device includes a substrate and at least one semiconductor-epitaxial structure disposed in a stack-up manner; irradiating a laser onto an edge area of the semiconductor device to separate portions of the substrate and the semiconductor-epitaxial structure in the edge area; and pressing against the edge area of the semiconductor device vis a pressing device, then irradiating the laser onto an inner area of the semiconductor device to separate portions of the substrate and the semiconductor-epitaxial structure in the inner area wherein gas is generated during separating the portions of the substrate and the semiconductor-epitaxial structure in the inner area and evacuated from the edge area, to prevent damage of the semiconductor-epitaxial structure during the separating process. | 2022-09-08 |
20220285219 | SEMICONDUCTOR CHIP, PROCESSED WAFER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP - A manufacturing method for a semiconductor chip includes: preparing a GaN wafer; producing a processed wafer by forming an epitaxial film on a surface of the GaN wafer to have chip formation regions adjacent to a first surface of the processed wafer; forming a first surface-side element component of a semiconductor element in each chip formation region; forming a wafer transformation layer along a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam; dividing the processed wafer at the wafer transformation layer into a chip formation wafer and a recycle wafer; extracting a semiconductor chip from the chip formation wafer; and after the preparing the GaN wafer and before the dividing the processed wafer, irradiating an inside of the gallium nitride wafer or the processed wafer with a laser beam to form a mark by deposition of gallium. | 2022-09-08 |
20220285220 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor. | 2022-09-08 |
20220285221 | GRAPHENE LAYER FOR LOW RESISTANCE CONTACTS AND DAMASCENE INTERCONNECTS - The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer. | 2022-09-08 |
20220285222 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer. | 2022-09-08 |
20220285223 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials. | 2022-09-08 |
20220285224 | SEMICONDUCTOR DEVICE STRUCTURE WITH SPACER - A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall. | 2022-09-08 |
20220285225 | Integrated Circuit Device With Low Threshold Voltage - A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide. | 2022-09-08 |
20220285226 | APPARATUS AND METHODS FOR THREE DIMENSIONAL RETICLE DEFECT SMART REPAIR - One or more embodiments of the present disclosure describe an artificial intelligence assisted substrate defect repair apparatus and method. The AI assisted defect repair apparatus employs an object detection algorithm. Based on the plurality of images taken by detectors located at different respective positions, the detectors capture various views of an object including a defect. The composition information as well as the morphology information (e.g., shape, size, location, height, depth, width, length, or the like) of the defect and the object are obtained based on the plurality of images. The object detection algorithm analyzes the images and determines the type of defect and the recommends a material (e.g., etching gas) and the associated information (e.g., supply time of the etching gas, flow rate of the etching gas, etc.) for fixing the defect. | 2022-09-08 |
20220285227 | PIXEL CLASSIFICATION OF FILM NON-UNIFORMITY BASED ON PROCESSING OF SUBSTRATE IMAGES - A method of classification of a film non-uniformity on a substrate includes obtaining a color image of a substrate with the color image comprising a plurality of color channels, obtaining a standard color for the color image of the substrate, for each respective pixel along a path in the color image determining a difference vector between the a color of the respective pixel and the standard color to generate a sequence of difference vectors, and sorting the pixels along the path into a plurality of regions including at least one normal region and at least one abnormal region based on the sequence of difference vectors, including comparing a multiplicity of the difference vectors in the sequence to a threshold. | 2022-09-08 |
20220285228 | METHOD FOR EVALUATING SEMICONDUCTOR SUBSTRATE - A method for evaluating electrical characteristics of a semiconductor substrate, the method including the steps of: forming a p-n junction on a surface of the semiconductor substrate; mounting the semiconductor substrate on a wafer chuck provided with an equipment for performing light irradiation on the surface of the semiconductor substrate and an equipment for measuring the quantity of the light for the irradiation; performing light irradiation on the surface of the semiconductor substrate for a predetermined time; and measuring an amount of carriers generated after the light irradiation of the p-n junction at least after turning off the light irradiation. This provides a method for evaluating a semiconductor substrate that allows the same evaluation in a wafer state as when an actual solid-state image sensor has been formed without producing a device by using process equipment when evaluating characteristics corresponding to residual image characteristics of a wafer. | 2022-09-08 |
20220285229 | METHOD AND SYSTEM FOR CONTROLLING PROFILE OF CRITICAL DIMENSION - An etching apparatus is provided to be able to rotate or tilt a substrate holder on which a to-be-processed substrate is placed. According to a profile of a pre-process critical dimension of the substrate, the etching apparatus may rotate or tilt the substrate holder during an etching process in order to achieve a desired profile of a post-process critical dimension of the substrate that is related to the pre-process critical dimension. | 2022-09-08 |
20220285230 | SYSTEM AND METHODS FOR CONTROLLING AN AMOUNT OF PRIMER IN A PRIMER APPLICATION GAS - A system for controlling an amount of primer in a primer application gas, includes a first sensor for detecting a first content in the primer application gas that is fed into a chamber containing a semiconductor wafer, a second sensor for detecting a second content in an exhaust gas that is exhausted from the chamber, and a flow control device that controls the amount of primer in the primer application gas based on a first sensor signal from the first sensor and a second sensor signal from the second sensor. | 2022-09-08 |
20220285231 | SEMICONDUCTOR ELEMENT CHARACTERISTIC VALUE ESTIMATION METHOD AND SEMICONDUCTOR ELEMENT CHARACTERISTIC VALUE ESTIMATION SYSTEM - A semiconductor element characteristic value estimation system is provided. The semiconductor element characteristic value estimation system includes an input portion, a database, and a processing portion. A first step list, a second step list, and a characteristic value of a semiconductor element are input to the input portion. The database has a function of storing a group of step lists and a group of characteristic values of semiconductor elements. The processing portion has a function of performing comparison between two step lists selected from the first step list and the group of step lists; a function of performing a test using two or more characteristic values of semiconductor elements selected from the characteristic value of the semiconductor element and the group of characteristic values of the semiconductor elements; a function of performing regression analysis of parameters for a step and two or more characteristic values of semiconductor elements selected from the characteristic value of the semiconductor element and the group of characteristic values of the semiconductor elements; and a function of estimating a characteristic value of a semiconductor element from the second step list. | 2022-09-08 |
20220285232 | CONTROLLING CONCENTRATION PROFILES FOR DEPOSITED FILMS USING MACHINE LEARNING - Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined. In response to an identification of the respective set of deposition process settings with a level of confidence that satisfies a level of confidence criterion, one or more operations of the deposition process are performed in accordance with the respective set of deposition process settings. | 2022-09-08 |
20220285233 | ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDING - Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment. | 2022-09-08 |
20220285234 | ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDING - A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer. | 2022-09-08 |
20220285235 | Semiconductor testkey pattern and test method thereof - The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns. | 2022-09-08 |
20220285236 | MITIGATING SURFACE DAMAGE OF PROBE PADS IN PREPARATION FOR DIRECT BONDING OF A SUBSTRATE - Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads. | 2022-09-08 |
20220285237 | BONDED SUBSTRATE, AND BONDED SUBSTRATE MANUFACTURING METHOD - A bonded substrate includes a ceramic substrate, a copper plate, and a bonding layer. The ceramic substrate has a main surface having a flat region having a maximum height Rz of 10 μm or less. The ceramic substrate has a particle-defect hole being exposed to the main surface, imparting flatness lower than flatness of the flat region to a part of the main surface, and having a depth of 10 μm or more and 60 μm or less. The copper plate includes a first portion disposed over the flat region and a second portion filling the particle-defect hole. The bonding layer includes a third portion covering the flat region and a fourth portion filling the particle-defect hole, and the second portion and the fourth portion fill 80% or more of a volume of the particle-defect hole. The bonding layer bonds the copper plate to the main surface. | 2022-09-08 |
20220285238 | BONDED SUBSTRATE AND BONDED SUBSTRATE MANUFACTURING METHOD - The bonded substrate includes the silicon nitride ceramic substrate, a copper plate, the bonding layer, and penetrating regions. The copper plate and the bonding layer are patterned into a predetermined shape, and are disposed over a main surface of the silicon nitride ceramic substrate. The bonding layer bonds the copper plate to the main surface of the silicon nitride ceramic substrate. The penetrating regions each include one or more penetrating portions penetrating continuously from the main surface of the substrate into the silicon nitride ceramic substrate to a depth of 3 μm or more and 20 μm or less, and contain silver, and the number of penetrating regions present per square millimeter of the main surface of the substrate is one or more and 30 or less. | 2022-09-08 |
20220285239 | MOLDED SEMICONDUCTOR PACKAGE HAVING A SUBSTRATE WITH BEVELLED EDGE - A molded semiconductor package includes: semiconductor dies attached to a first side of a leadframe and electrically interconnected to form a power electronic circuit; a substrate attached to a second side of the leadframe opposite the first side, and including a metal body and electrically insulative material that separates the metal body from the leadframe; and a molding compound encapsulating the dies. The metal body includes a first surface in contact with the electrically insulative material, a second surface opposite the first surface and which is not covered by the molding compound, and a bevelled edge extending between the first and second surfaces. The bevelled edge of the metal body has a first sloped side face that extends from the first surface to an apex of the bevelled edge, and a second sloped side face that extends from the apex to the second surface. Methods of producing the package are also described. | 2022-09-08 |
20220285240 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PROTECTION LAYERS - The present disclosure provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die, forming a first mask layer on the second die, forming a first opening along the first mask layer and the second die, and extending to the first die, forming isolation layers on sidewalls of the first opening, forming protection layers covering upper portions of the isolation layers, and forming a conductive filler layer in the first opening. | 2022-09-08 |
20220285241 | METHOD OF FORMING SEMICONDUCTOR PACKAGES HAVING THERMAL THROUGH VIAS (TTV) - A method of forming a semiconductor package includes the following steps. A redistribution layer structure is formed over a first die and a dummy die, wherein the redistribution layer structure is directly electrically connected to the first die. An insulating layer is formed, wherein the insulating layer is disposed opposite to the redistribution layer structure with respect to the first die. At least one thermal through via is formed in the insulating layer. | 2022-09-08 |
20220285242 | SEMICONDUCTOR DEVICE - A semiconductor chip ( | 2022-09-08 |
20220285243 | POWER MODULE - It is an object of the present invention to improve a heat radiation property of a metal wire on a semiconductor chip in a power module. A power module includes: a plurality of metal wires connected to a surface of at least one semiconductor chip; and a thermal conductive sheet having contact with the metal wire. The metal wire includes: at least one first metal wire connecting a surface of the semiconductor chip and a circuit pattern and at least one second metal wire connecting two points on the surface of the semiconductor chip and having the same potential as the first metal wire. The thermal conductive sheet includes a graphite sheet, and a sheet surface of the thermal conductive sheet has contact with the at least one first metal wire and the at least one second metal wire. | 2022-09-08 |
20220285244 | SEMICONDUCTOR DEVICE WITH HIGH HEAT DISSIPATION PROPERTY USING HEXAGONAL BORON NITRIDE AND METHOD OF MANUFACTURING THE SAME - The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices. | 2022-09-08 |
20220285245 | SEMICONDUCTOR MODULE - A semiconductor module includes a substrate, a semiconductor element and a heat sink plate. The substrate is included in a circuit board. The semiconductor element is disposed at the heat sink plate inside the substrate. A fluid is sealed inside the heat sink plate. | 2022-09-08 |
20220285246 | SEMICONDUCTOR POWER MODULE - A semiconductor power module is configured in such a way that a protruding portion of a heat sink is inserted into a penetration hole of a jacket, that an end face portion of the protruding portion and a cooling fin are exposed in a flow path, that a front-end portion of the cooling fin abuts on an inner wall surface of the flow path, that a packing is mounted in a groove portion formed between an inner wall portion of the penetration hole and a side wall portion, of the protruding portion of the heat sink, that faces the inner wall portion, that the inner wall portion of the penetration hole and the side wall portion of the protruding portion press the packing in the radial direction thereof, that a spring member presses the front-end portion of the cooling fin to the inner wall surface of the flow path. | 2022-09-08 |
20220285247 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - Disclosed is a high voltage semiconductor device. More particularly, the present disclosure relates to a semiconductor device capable of improving the breakdown voltage characteristics in an off-state and in an on-state by electrically connecting a first source metal to a source in a core region and in corner regions. | 2022-09-08 |
20220285248 | VERTICAL TRANSISTORS WITH GATE CONNECTION GRID - In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric. | 2022-09-08 |
20220285249 | BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN - A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound. | 2022-09-08 |
20220285250 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment comprises a semiconductor element, a first terminal, a plurality of second terminals, and an encloser. The semiconductor element is rectangular. The first terminal has an upper surface to which a back surface of the semiconductor element is bonded. The second terminals are arranged around the first terminal. The second terminals are arranged at four corners of the encloser to be exposed from the bottom surface, and sides of the semiconductor element are opposed to the first side, the second side, the third side, and the fourth side, respectively. The first terminal is apart from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and the first terminal is partly exposed from the second side surface and the fourth side surface. | 2022-09-08 |
20220285251 | SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package substrate and a method of manufacturing the same are provided. The semiconductor package substrate includes: a base layer including a conductive material, having a first surface and a second surface opposite the first surface, and having a first groove or first trench in the first surface and a second groove or second trench in the second surface; a first resin buried in the first groove or first trench in the first surface of the base layer; and a groove in at least one corner of the first surface of the base layer and having a depth based on the first surface is 1/2 or more of a thickness of the base layer. | 2022-09-08 |
20220285252 | METAL COMPONENT - There is provided a metal component used for manufacturing a semiconductor device, including: a base material having an electrical conductivity; a nickel layer formed on a surface of the base material and containing nickel as a main component; and a noble metal layer formed on a surface of the nickel layer. The nickel layer includes a first nickel layer not containing phosphorus, and a second nickel layer containing 0.01 to 1 in percent by weight of phosphorus. According to the metal component of the present disclosure, a thickness of the nickel layer can be reduced while good characteristics can be maintained. | 2022-09-08 |
20220285253 | Electronic Module Having a Groove Anchoring Terminal Pins - A module has electronic components mounted to a Printed Circuit Board (PCB) with multiple patterned conductive layers connecting to conductive slot metal around a conductive slot. A groove is cut through a top molding encapsulant above and into the conductive slot but does not cut through a bottom molding encapsulant. A terminal pin is inserted into the groove and pushed down into the conductive slot. When heated, embedded solder previously applied to the conductive slot metal flows between the end of the terminal pin and the conductive slot metal to form a solder bond. An end of the PCB past the conductive slot has no metal traces, preventing shorts. Epoxy can be placed into the groove around the terminal pin or a hole formed in the terminal pin to increase strength of the anchored terminal pin. The molding around the groove protects terminal pins from shorting from the side. | 2022-09-08 |
20220285254 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element and a lead part. The semiconductor element is mounted on a circuit pattern provided on an insulating substrate. The lead part has a plate shape and is bonded to the semiconductor element with a first bonding material interposed therebetween. The lead part includes a lead body and a bonding component. The lead body includes an opening part provided corresponding to a mounting position of the semiconductor element. The bonding component is provided in the opening part and on the semiconductor element. The bonding component is bonded at a lower surface thereof to the semiconductor element by the first bonding material and bonded at an outer peripheral part thereof to an inner periphery of the opening part by a second bonding material. | 2022-09-08 |
20220285255 | WIRING BOARD WITH EMBEDDED INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME - A method of fabricating a wiring board with an embedded interposer substrate includes preparing a main substrate, forming a recess on the main substrate, placing an interposer substrate into the recess, electrically connecting a second pad of the interposer substrate and the first pad of the main substrate, and filling a gap between the interposer substrate and the main substrate with an underfill. The recess exposes a first pad of the main substrate. A second pad of interposer substrate and the first pad of the main substrate are made of the same metal and formed in different outer surface profiles. The underfill entirely touches side surfaces and a bottom surface of the interposer substrate. | 2022-09-08 |
20220285256 | WAFER LEVEL PACKAGING HAVING REDISTRIBUTION LAYER FORMED UTILIZING LASER DIRECT STRUCTURING - A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dice, affixing a carrier to a front side of the plurality of integrated circuit dice, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dice, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die. | 2022-09-08 |
20220285257 | INTERMEDIATE SUBSTRATE AND FABRICATION METHOD THEREOF - An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits. | 2022-09-08 |
20220285258 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH STRESS-RELIEVING STRUCTURES - The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. | 2022-09-08 |
20220285259 | INTERCONNECTS ON MULTIPLE SIDES OF A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region. | 2022-09-08 |
20220285260 | METALLIZATION STRUCTURE OF DISTRIBUTED GATE DRIVE FOR IMPROVING MONOLITHIC FET ROBUSTNESS - A metallization structure of distributed gate drive enabling the switching behavior of different MOSFET arrays and fingers to be more unified while maintaining the same Rdson and Qg performance. This balances the transient current between MOSFET arrays and fingers during switching, allowing the device to operate at a much higher current. | 2022-09-08 |
20220285261 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure. | 2022-09-08 |
20220285262 | SEMICONDUCTOR DEVICE - A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate, The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure. | 2022-09-08 |
20220285263 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING - A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain. | 2022-09-08 |
20220285264 | METAL PLATE CORNER STRUCTURE ON METAL INSULATOR METAL - A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded. | 2022-09-08 |
20220285265 | INTEGRATED CIRCUIT STRUCTURE OF CAPACITIVE DEVICE - An integrated circuit structure includes a first capacitor structure, disposed in a first layer on a semiconductor substrate and comprising a plurality of capacitors; a second capacitor structure, adjacent to first capacitor structure in the first layer, wherein the second capacitor structure and the first capacitor structure are arranged as a. strip-shaped structure; a first conductive plate, disposed at one end of the strip-shaped structure in the first layer; and a second conductive plate, disposed in a second layer on the semiconductor substrate over the strip-shaped structure and extending toward the other end of the strip-shaped structure from the one end of the strip-shaped structure. | 2022-09-08 |
20220285266 | NOVEL SELF-ALIGNED VIA STRUCTURE BY SELECTIVE DEPOSITION - In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region. | 2022-09-08 |
20220285267 | FAN-OUT WAFER LEVEL PACKAGING OF SEMICONDUCTOR DEVICES - In a general aspect, a semiconductor device assembly can include a semiconductor die having a back side and a front side, the back side being coupled with a base, the front side including active circuitry. The assembly can include a first resin encapsulation layer disposed on a first portion of the front side. The first resin encapsulation layer can be patterned to define a first opening exposing a second portion of the front side through the first resin encapsulation layer. The assembly can include a signal distribution structure that is disposed on the first resin encapsulation layer, and electrically coupled with the front side through the first opening. The assembly can include a second resin encapsulation layer disposed on a first portion of the signal distribution structure, the second resin encapsulation layer being patterned to define a second opening that exposes a second portion of the signal distribution structure. | 2022-09-08 |
20220285268 | SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME - An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer. | 2022-09-08 |
20220285269 | MODIFIED FUSE STRUCTURE AND METHOD OF USE - An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode. | 2022-09-08 |
20220285270 | SEMICONDUCTOR DEVICE WITH FUSE AND ANTI-FUSE STRUCTURES - The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure. | 2022-09-08 |
20220285271 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a staircase portion, a columnar body, and a contact. The columnar body is provided in a second region of a stacked body, penetrating the stacked body in a stacking direction, and having a plurality of memory cells at each positions facing the plurality of conductive layers. The contact is connected to a terrace surface. Further, the staircases included in the staircase portion are each formed to ascend for each first step having conductive layers of the plurality of conductive layers in a second direction intersecting the stacking direction and a first direction. The terrace surfaces arranged in the first direction of the terrace surfaces of the staircases are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction. | 2022-09-08 |
20220285272 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first source finger, a first gate finger, a first drain finger, a second source finger, a second gate finger, a second drain finger, a first gate wiring, wherein a width of the first gate wiring in the extension direction at a first region where the first gate finger connects to the first gate wiring is smaller than a width of the first gate wiring in the extension direction at a second region located between the first source finger and the second source finger, and an end of the first region near the second gate finger in the extension direction is located closer to the second gate finger than an end of the second region near the second gate finger in the extension direction. | 2022-09-08 |
20220285273 | High Density 3D Interconnect Configuration - Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible. | 2022-09-08 |
20220285274 | WELL TAP FOR AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF FORMING SUCH A WELL TAP - An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height. | 2022-09-08 |
20220285275 | CONTACT STRUCTURE AND METHOD OF FORMING THE SAME - Aspects of the disclosure provide a semiconductor device. The semiconductor device can include a trench formed in a first dielectric layer, a trench filler layer that fills a portion of the trench, a conductive layer over the trench filler layer, and a second dielectric layer over the conductive layer. The second dielectric layer is disposed in the trench. The semiconductor device can also include a contact structure configured to connect to the conductive layer through a hole in the second dielectric layer. | 2022-09-08 |
20220285276 | SEMICONDUCTING DEVICES, BACK END OF LINE PORTIONS FOR SEMICONDUCTING DEVICES, AND DIELECTRIC MATERIALS INCORPORATING DEUTERIUM - Semiconducting devices, and more specifically back end of line (BEOL) portions for semiconducting devices that may include dielectric materials incorporating deuterium are disclosed. The semiconducting devices may include a back end of line (BEOL) portion electrically coupled to a front end of line (FEOL) portion. The BEOL portion may include at least one BEOL level having a dielectric layer. The dielectric layer may include at least one section formed from a low-k material including deuterium (D). The BEOL level(s) may also include an etch stop layer disposed over the dielectric layer, and at least one conductive structure disposed within the dielectric layer. The at least one conductive structure may extend through the dielectric layer and the etch stop layer, respectively. | 2022-09-08 |
20220285277 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. | 2022-09-08 |
20220285278 | VIA STRUCTURES HAVING TAPERED PROFILES FOR EMBEDDED INTERCONNECT BRIDGE SUBSTRATES - Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate. | 2022-09-08 |
20220285279 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a stacked die including a lower portion and an upper portion stacked upon the lower portion. The lower portion includes a first patterned conductive pad, a first conductive connector passing through the first patterned conductive pad, a first patterned dielectric layer covering the first patterned conductive pad and laterally isolating the first conductive connector from the first patterned conductive pad. The upper portion includes a second conductive connector bonded to the first conductive connector, and a second patterned dielectric layer bonded to the first patterned dielectric layer. | 2022-09-08 |
20220285280 | INTEGRATED CIRCUITS (ICs) WITH MULTI-ROW COLUMNAR DIE INTERCONNECTS AND IC PACKAGES INCLUDING HIGH DENSITY DIE-TO-DIE (D2D) INTERCONNECTS - An integrated circuit (IC) package including ICs with multi-row columnar die interconnects has increased die-to-die (D2D) interconnect density in a conductive layer. Positioning the die interconnects in die interconnect column clusters, that each include a plurality of die interconnect rows and two columns, reduces the linear dimension occupied by the die interconnects and leaves room for more D2D interconnects. A die interconnect column cluster pitch is a distance between columns of adjacent die interconnect column clusters and this distance is greater than a die interconnect pitch between columns within the column clusters. Die interconnects may be disposed in the space between the multi-row column clusters and additional die interconnects can be disposed at the D2D interconnect pitch between the die interconnect column clusters. IC packages with ICs including the multi-row columnar die interconnects have a greater number of D2D interconnects for better IC integration. | 2022-09-08 |
20220285281 | SEMICONDUCTOR DEVICES WITH FLEXIBLE CONNECTOR ARRAY - A semiconductor device includes an array of flexible connectors configured to mitigate thermomechanical stresses. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector includes a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire has a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration. The first shape includes at least two apices spaced apart from each other in a vertical dimension by a first distance, and the second shape includes the two apices spaced apart from each other in the vertical dimension by a second distance different than the first distance. | 2022-09-08 |
20220285282 | SUBSTRATE STRUCTURES AND SEMICONDUCTOR STRUCTURES - A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component. | 2022-09-08 |
20220285283 | Silicon Carbide Device and Method for Forming a Silicon Carbide Device - A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate. | 2022-09-08 |
20220285284 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other. | 2022-09-08 |
20220285285 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns. | 2022-09-08 |
20220285286 | PACKAGE COMPRISING METAL LAYER CONFIGURED FOR ELECTROMAGNETIC INTERFERENCE SHIELD AND HEAT DISSIPATION - A package that includes a substrate, an integrated device coupled to the substrate, an encapsulation layer located over the substrate, at least one encapsulation layer interconnect located in the encapsulation layer, and a metal layer located over the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnect is coupled to the substrate. The metal layer is configured as an electromagnetic interference (EMI) shield for the package. The metal layer is located over a backside of the integrated device. | 2022-09-08 |
20220285287 | PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF - Packaging structure and fabrication method are provided. The method includes: providing semiconductor chips; providing soldering pads on the semiconductor chips, a metal bump on each soldering pad, and a first plastic encapsulation layer on functional surfaces of the semiconductor chips; providing a carrier plate; adhering the first plastic encapsulation layer on the functional surfaces of the semiconductor chips to the carrier plate; forming a first shielding layer covering non-functional surfaces and sidewalls of the semiconductor chips; forming a second shielding layer on the first shielding layer; forming a second plastic encapsulation layer on the second shielding layer and on the carrier plate between semiconductor chips; peeling off the carrier plate to form a pre-packaging plate; removing a portion of the first plastic encapsulation layer to expose the metal bumps; forming an external contact structure on the backside of the pre-packaging plate and connected to each metal bump. | 2022-09-08 |
20220285288 | INTEGRATED CIRCUIT DIE PACKAGE STIFFENERS OF METAL ALLOYS HAVING EXCEPTIONALLY HIGH CTE - A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa. | 2022-09-08 |
20220285289 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region. | 2022-09-08 |
20220285290 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads. | 2022-09-08 |
20220285291 | PRINTABLE COMPONENT MODULES WITH FLEXIBLE, POLYMER, OR ORGANIC MODULE SUBSTRATES - A micro-component module comprises a module substrate, a component disposed on the module substrate, and at least a portion of a module tether in contact with the module substrate. The module substrate can be flexible or can comprise an organic material, or both. The module tether can be more brittle and less flexible than the module substrate. The component can be less flexible than the module substrate and can comprise at least a portion of a component tether. An encapsulation layer can be disposed over the component and module substrate. The component can be disposed in a mechanically neutral stress plane of the micro-component module. A micro-component module system can comprise a micro-component module disposed on a flexible system substrate, for example by micro-transfer printing. A micro-component module can comprise an internal module cavity in the module substrate with internal module tethers physically connecting the module substrate to internal anchors. | 2022-09-08 |
20220285292 | SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME - Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer. | 2022-09-08 |
20220285293 | INTEGRATED SYSTEM-IN-PACKAGE WITH RADIATION SHIELDING - A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads. | 2022-09-08 |
20220285294 | PACKAGE DEVICE - An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance. | 2022-09-08 |
20220285295 | ORGANIC INTERPOSER INCLUDING A DUAL-LAYER INDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME - An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper. | 2022-09-08 |
20220285296 | CAVITY RESONATOR FOR ENHANCING RADIO-FREQUENCY PERFORMANCE AND METHODS FOR FORMING THE SAME - Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer | 2022-09-08 |
20220285297 | SEMICONDUCTOR PACKAGE HAVING IMPROVED THERMAL INTERFACE BETWEEN SEMICONDUCTOR DIE AND HEAT SPREADING STRUCTURE - A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element. | 2022-09-08 |
20220285298 | HYBRID POCKET POST AND TAILORED VIA DIELECTRIC FOR 3D-INTEGRATED ELECTRICAL DEVICE - An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation. | 2022-09-08 |
20220285299 | VIA STRUCTURE FOR SEMICONDUCTOR DIES - A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer. | 2022-09-08 |
20220285300 | SEMICONDUCTOR DEVICE WITH EDGE-PROTECTING SPACERS OVER BONDING PAD - The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. | 2022-09-08 |