| 36th week of 2011 patent applcation highlights part 24 |
| Patent application number | Title | Published |
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| 20110216513 | ELECTRO DEVICE EMBEDDED PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - An electro device embedded printed circuit board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, a printed circuit board embedded with an electro device, in which a pair of electrodes are formed on either end, includes: a core substrate in which a first cavity is formed; a first passive device embedded in the first cavity and being thinner than the core substrate; and a second passive device stacked on an upper side of the first passive device such that the second passive device is embedded in the first cavity. The first passive device and the second passive device are stacked to cross each other. | 2011-09-08 |
| 20110216514 | COMBINED MULTILAYER CIRCUIT BOARD HAVING EMBEDDED COMPONENTS AND MANUFACTURING METHOD OF THE SAME - A combined multilayered circuit board is provided. The combined multilayered circuit board includes a plurality of multilayered circuit boards, at least one of the plurality circuit boards being formed with an embedded electronic component and an internal chamber receiving the embedded electronic component. The internal chamber is full of air. The combined multilayered circuit board further includes at least one glue layer interposed between each of the plurality of multiple circuit boards for bonding the plurality of multilayered circuit boards together. | 2011-09-08 |
| 20110216515 | ELECTRO DEVICE EMBEDDED PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - An electro device embedded printed circuit board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, an electro device embedded printed circuit board is manufactured by: adhering a first electro device on a supporting body through a face-down method; adhering a second electro device on an upper surface of the first electro device through a face-up method; stacking a pure resin layer and a reinforcing layer on an upper side of the supporting body, wherein the first electro device and the second electro device are embedded in the pure resin layer; removing the supporting body; stacking an insulation layer on a lower side of the first electro device, a reinforcing material having been impregnated in the insulation layer; and patterning a circuit on each of the reinforcing layer and the insulation layer. | 2011-09-08 |
| 20110216516 | Semiconductor Module, Socket For The Same, And Semiconductor Module/Socket Assembly - A semiconductor module, a socket for the same, and a semiconductor module/socket assembly are disclosed. The semiconductor module includes a printed circuit board including a plurality of semiconductor devices, a plurality of insulating layers and a plurality of metal layers, the plurality of insulating layers and the plurality of metal layers are alternately stacked. Exposed portions of the metal layers are exposed to the outside of the semiconductor module at a first and a second ends of the printed circuit board. The first end and the second end are at opposite ends of the printed circuit board. | 2011-09-08 |
| 20110216517 | ELECTRICAL CONNECTION INTERFACES AND METHODS FOR ADJACENTLY POSITIONED CIRCUIT COMPONENTS - Electrical components, such as packaged integrated circuit devices that are mountable on a substrate surface, are provided with at least one exposed electrical contact on a side surface of the component that will be substantially perpendicular to the substrate surface when the component is mounted. Two such components can be mounted side-by-side on the substrate surface with the above-mentioned contacts close to one another between the above-mentioned side surfaces. An electrical connection between the contacts can be made (or perfected) by depositing an electrically conductive connector material in contact with both of the contacts between the above-mentioned side surfaces. | 2011-09-08 |
| 20110216518 | Self-Cooled Thyristor Valve - The present invention relates to a self-cooled thyistor device for ultra-high voltage fault current limiter. a self-cooled thyristor valve, it adopts horizontal structure consisted by frames, frames is divided into upper and below two spaces by crossbeams, the bottom of frames is supported by insulators. There is a cross plate between two vertical said frames, the cross plate mounts resistors connect with a high potential plate and capacitor through two wires. There is a thyistor string in said frame upper space, which is constituted of thyistors and cooler series. The thyistor string is compressed tightly by press-fit mechanism, thyistor string crosses current transformers. There are high potential plates on both sides of the thyistor, the number of the potential plates is equal to that of thyistor. One side of the high potential plates links frames, said current transformers connects with high potential plates. There are capacitors and resistors connected with the bottom plate of said frames in the below space. The small and well-structured invention meets the requirement of the energy on continuous trigger condition, improves the global reliability of thyristor valve. | 2011-09-08 |
| 20110216519 | PHOTOGRAPHIC DEVICES - A photographic system includes a first light grid including a plurality of cells, and a first alignment feature disposed on the first light grid. The system further includes a bezel including a retainer for retaining at least the first light grid, and an alignment feature for aligning at least the first light grid within the light grid retainer, wherein the first alignment feature of the first light grid aligns with the alignment feature of the bezel. | 2011-09-08 |
| 20110216520 | PHOTOGRAPHIC SYSTEM - A photographic system includes a first light grid including cells, and a first alignment feature. A bezel including a retainer for retaining at least the first light grid, and an alignment feature for aligning at least the first light grid within said light grid retainer. A formable portion including a reflective surface, wherein the formable portion is for retainably formed into a snoot, wherein said bezel is disposed at a distal end of the formable portion, and wherein the reflective surface is for reflecting light from a photographic light source within the formable portion. A base portion coupled to the formable portion, wherein the base portion is for coupling to the photographic light source. | 2011-09-08 |
| 20110216521 | LIGHT DIFFUSION AND CONDENSING FIXTURE - Certain embodiments of the invention may include system apparatus for providing a light diffusion and condensing fixture. According to an example embodiment, a light fixture is configured for illuminating subjects and it includes an enclosure cavity. The enclosure defines a cavity with an opening and one or more reflective inner surfaces. The light fixture also includes a frame structure defining an optical aperture and the frame structure is disposed proximate to the opening. The light fixture also includes two or more film tensioners associated with the frame structure. The light fixture also includes at least one light source positioned between the one or more reflective surface and a plane defined by the optical aperture. The light fixture further includes at least one optical film comprising at least one lenticular lens surface and the at least one optical film is suspended substantially parallel to the optical aperture by the two or more tensioners. | 2011-09-08 |
| 20110216522 | Efficient LED-Based Illumination Module With High Color Rendering Index - An illumination module includes a light mixing cavity with an interior surface area and window that are physically separated from an LED. A portion of the window is coated with a first wavelength converting material and a portion of the interior surface area is coated with a second wavelength converting material. The window may be coated with LuAG:Ce. The window may also be coated with a third wavelength converting material with a peak emission wavelength between 615-655 nm where the spectral response of light emitted from the window is within 20% of a blackbody radiator at the same CCT. The LED may emit a light that is converted by the light mixing cavity with a color conversion efficiency ratio greater than 130 lm/W where the light mixing cavity includes two photo-luminescent materials with a peak emission wavelengths between 508-528 nm and 615-655 nm. | 2011-09-08 |
| 20110216523 | NON-UNIFORM DIFFUSER TO SCATTER LIGHT INTO UNIFORM EMISSION PATTERN - A lighting device comprising a light source and a diffuser spaced from the light source. The lighting device further comprises a wavelength conversion material disposed between the light source and the diffuser and spaced from the light source and the diffuser, wherein the diffuser is shaped such that there are different distances between the diffuser and said conversion material at different emission angles. In other embodiments the diffuser includes areas with different diffusing characteristics. Some lamps are arranged to meet A19 and Energy Star lighting standards. | 2011-09-08 |
| 20110216524 | LOW POWER LOW COST ILLUMINATED KEYBOARDS AND KEYPADS - Methods are provided for adapting existing manufacturing processes for non-illuminated data-entry devices and mouses to the manufacture of illuminated data-entry devices. Luminescent sheets of one or more colors underlying optically transmissive device components provide illumination of the components visual to a user of the device. The optically transmissive components may be doped with phosphors or tinted to provide components that emit light of different colors. The intensity of illumination of the luminescent sheet may be controlled by the user and may vary in response to the background light of the environment. | 2011-09-08 |
| 20110216525 | ENHANCED BEER TAP HANDLE - In varying embodiments, an enhanced beer tap handle is disclosed whereby an illumination mechanism is coupled to an existing beer tap handle in order draw attention to the beer tap handle. Consequently, a competitive advantage is achieved by the beer manufacturer employing the enhanced beer tap handle relative to a non-illuminated beer tap handle. An aspect of the invention is an enhanced beer tap handle. The beer tap handle comprises a beer tap comprising a clamping nut and a stud and an illumination mechanism coupled on top of the clamping nut via the stud for illuminating the beer tap during operation. | 2011-09-08 |
| 20110216526 | ILLUMINABLE SHOWER HEAD - Illuminable shower head, comprising a main body, a hydroelectric device arranged in the main body, a circuit board, an illuminant and a water outlet device arranged in front of the main body; the hydroelectric device is electrically connected with the circuit board and the illuminant; wherein said water outlet device is made of transparent material, said illuminant comprises a backlight and a plurality of LED lights, said backlight is disposed upon said water outlet device, said LED lights are disposed on the side surface of the periphery of the backlight and illuminate toward the backlight. The light emitted from the LED lights 51 can be conducted and unified by the backlight 52 and then illuminates the whole water output panel of the shower head, so the whole water output panel of the shower head will be luminous; moreover, the luminous water output panel will have the function of illumination. | 2011-09-08 |
| 20110216527 | BACKLIGHT MODULE - A backlight module includes a back plate, a plurality of lamps, a lamp fixing base, and a diffusion plate. The back plate has a cavity. The lamps are disposed on or above the back plate. The lamp fixing base is disposed on the back plate for fixing the lamps. The lamp fixing base has a supporting portion extending along a direction away from the back plate. An orthogonal projection of the supporting portion on the back plate is within a boundary of the cavity. The diffusion plate is disposed above or over the back plate, and the supporting portion is suitable for supporting the diffusion plate. | 2011-09-08 |
| 20110216528 | MODULAR DRIVER FOR ILLUMINATION AND HAVING DRIVER HEAD CARTRIDGE - A modular driver for illumination and having a driver head cartridge comprises: a grip; an inner frame disposed within the grip, the rear end of the inner frame being provided with a plurality of recesses, one side at the front end of the inner frame defining an assembly section, the other side defining a battery containing section; a circuit board mounted on the assembly section of the inner frame, an LED lamp, an actuating switch and a power supply pin being integrated on the circuit board; and a rear cap disposed on the end of the grip, the rear cap being provided with a through hole, the rear cap being turned so that the through hole can be disposed with respect to one of the recesses. | 2011-09-08 |
| 20110216529 | SOLAR LAMP - A solar lamp includes a solar panel, a reserve power unit, a luminescence module and a transmission module. The solar panel connecting the reserve power unit transforms solar energy into electric energy, and stores electric energy into the reserve power unit. The luminescence module connecting the reserve power unit receives electric energy outputting from the reserve power unit. The transmission module comprises a port, wherein one end of the port connects the reserve power unit, and the other one end of the port electrically connects an electronic product. Therefore, the solar lamp would supply electric energy into the electronic product by the transmission module, or the electronic product would supply electric energy into the solar lamp by the transmission module. | 2011-09-08 |
| 20110216530 | Solar Power Illuminated Book - A solar powered self-illuminating book comprising a first cover having an outer surface and an inner surface; a second cover, wherein the first and second covers are positionable in a closed orientation in which the second cover is opposed to the first cover; one or more pages connected between the first and second cover; one or more solar panels disposed in the outer surface of the first cover and exposed to the environment, a rechargeable battery electrically connected to each of the one or more solar panels; and one or more LED's embedded within the one or more pages which are electrically connected to the rechargeable battery. | 2011-09-08 |
| 20110216531 | Wirelessly connectable light source - The present invention provides a wirelessly connectable light source, which includes a woven member, an electrical conductor, a receiver circuit, and a light-emitting element. The woven member includes a body and an extension section extending from the body. The conductor is arranged in the body and the receiver circuit is electrically connected to the conductor. The light-emitting element is arranged inside the body and includes a light emission section and two conductive sections. The light emission section emits light projecting outside the body of the woven member. Light emitting from the light emission section is projected outside the body of the woven member. The two conductive sections are electrically connected to the conductor. Through integration of the extension section of the woven member to an article and coupling of a charging device to the article, the charging device may perform electrical charging to the receiver circuit so as to supply electrical power to the light-emitting element for giving off light. | 2011-09-08 |
| 20110216532 | Folding Rechargeable Worklight - An LED worklight having a center core and a first panel and a second panel coupled to the center core. The first panel includes a first array of LEDs mounted to a first circuit board disposed within a first opening formed within the first panel and a first lens disposed over the first array of LEDs. The second panel includes features similar to the first panel. The second panel is rotatable around the center core from a 0 degree closed orientation to about a 360 degree orientation, and is positionable at any intermediate angle therebetween. The LED worklight includes a retractable hook for mounting to an elevated object. The LED worklight also includes at least one magnet to mount the LED worklight to vertical/vertically angling surfaces. The array of LEDs mounted to the first panel and the second panel can be controlled independently of one another. | 2011-09-08 |
| 20110216533 | ELECTRONIC GLOW STICK DEVICE WITH ALTERNATING FLASHER - A lighting device including an elongate illuminated portion having translucent side walls spaced about a long axis of the illuminated portion. The device further includes a light source configured to direct light along a length of the illuminated portion and out the translucent side walls. An actuator extends in a biased position oppositely from the light source in a deactivated position. A circuit is electrically coupled between the actuator and light source for activating the light to a first lighting function for so long as the actuator is moved to a compressed position, detecting the actuator being moved back to its biased position, and activating the light to a second lighting function for so long as the actuator is moved back to the compressed position. | 2011-09-08 |
| 20110216534 | Light Emitting Diode Recessed Light Fixture - A recessed light fixture includes an LED module, which includes a single LED package that is configured to generate all light emitted by the recessed light fixture. For example, the LED package can include multiple LEDs mounted to a common substrate. The LED package can be coupled to a heat sink for dissipating heat from the LEDs. The heat sink can include a core member from which fins extend. Each fin can include one or more straight and/or curved portions. A reflector housing may be coupled to the heat sink and configured to receive a reflector. The reflector can have any geometry, such as a bell-shaped geometry including two radii of curvature that join together at an inflection point. An optic coupler can be coupled to the reflector housing and configured to cover electrical connections at the substrate and to guide light emitted by the LED package. | 2011-09-08 |
| 20110216535 | Fresnel Reflection Device for Concentration or Collimation - An apparatus for concentrating solar radiation includes a number of modules. Each module has three receivers for receiving reflected radiation and a reflecting surface. The receivers form a triangle in a plane approximately parallel to the reflecting surface. The reflecting surface has a number of reflectors. Each of the reflectors includes three mirrored facets which are each oriented such that light reflected from the facet is directed to one of the three receivers. Further, each of the reflectors is positioned with respect to the receivers and the other reflectors to reduce facet shading. | 2011-09-08 |
| 20110216536 | ILLUMINATION DEVICE - An illumination device that includes a plurality of LED chips and a heat-dissipating unit including a fan configured to ventilate air. The plurality of LED chips are cooled as heat generated in the plurality of LED chips is transferred to the air ventilated by the fan. | 2011-09-08 |
| 20110216537 | LED Device for Wide Beam Generation - An apparatus and method is characterized by providing an optical transfer function between a predetermined illuminated surface pattern, such as a street light pattern, and a predetermined energy distribution pattern of a light source, such as that from an LED. A lens is formed having a shape defined by the optical transfer function. The optical transfer function is derived by generating an energy distribution pattern using the predetermined energy distribution pattern of the light source. Then the projection of the energy distribution pattern onto the illuminated surface is generated. The projection is then compared to the predetermined illuminated surface pattern to determine if it acceptably matches. The process continues reiteratively until an acceptable match is achieved. Alternatively, the lens shape is numerically or analytically determined by a functional relationship between the shape and the predetermined illuminated surface pattern and predetermined energy distribution pattern of a light source as inputs. | 2011-09-08 |
| 20110216538 | LED-BASED LIGHTING FIXTURES FOR SURFACE ILLUMINATION WITH IMPROVED HEAT DISSIPATION AND MANUFACTURABILITY - LED-based lighting apparatus and assembly methods in which mechanical and/or thermal coupling between respective components is accomplished via a transfer of force from one component to another. In one example, a multiple-LED assembly is disposed in thermal communication with a heat sink that forms part of a housing. A primary optical element situated within a pressure-transfer member is disposed above and optically aligned with each LED. A shared secondary optical facility forming another part of the housing is disposed above and compressively coupled to the pressure-transfer members. A force exerted by the second optical facility is transferred via the pressure-transfer members so as to press the LED assembly toward the heat sink, thereby facilitating heat transfer. In one aspect, the LED assembly is secured in the housing without the need for adhesives. In another aspect, the secondary optical facility does not directly exert pressure onto any primary optical element, thereby reducing optical misalignment. | 2011-09-08 |
| 20110216539 | ROTATORY TABLE LAMP - A rotatory table lamp includes a base, a holder, a connection element, a rotation mechanism, a first lamp and a second lamp. One end of the holder is fixed in the center of the bas, and the other end is received in the connection element. The rotation mechanism is rotatably received in the connection element, the holder and the base. The first lamp is fixed on the connection element. The second lamp is fixed on the rotation mechanism, and is as the same structure of the first lamp. | 2011-09-08 |
| 20110216540 | LAMP LIGHT DIRECTOR REFLECTOR - A lamp light director reflector (LLDR) for being installed on a lamp having a light bulb including a housing having a convex exterior surface and a convex reflective interior surface; a hole on a top portion of the exterior surface configured to accommodate a harp nut base of the lamp therein, in a first position; and a slit on the top portion of the exterior surface configured to accommodate a harp of the lamp therein, in a second position wherein the housing is configured to be installed on the lamp such that the reflective interior surface faces the light bulb of the lamp. The first position is at a top of the lamp harp resting upon the harp, and the lamp harp passes through the slit in the second position resting atop the lamp bulb. | 2011-09-08 |
| 20110216541 | Light source apparatus - A light source apparatus that is used in a document reading apparatus that reads document-reflecting light from the document includes a first reflection mirror; a second reflection mirror; and a light guiding member that comprises a light emitting element mounted to one longitudinal end of the light guiding member and a light emitting face in a longitudinal direction, where the first and second reflection mirrors are arranged in parallel to the light guiding member and reflect light from the light emitting face of light guiding member toward a document placement face and where an end point of an optical axis of a first light reflection face is located on the document placement face between an end point of an optical axis of the first reflection mirror and an end point of an optical axis of the second reflection, mirror. | 2011-09-08 |
| 20110216542 | OPTICAL SKY-SUN DIFFUSER - An embodiment of a solid optical sky-sun diffuser, which comprises a transparent solid matrix embedding a dispersion of transparent nanoparticles having an average size d in the range 10 nm≦d≦240 nm; wherein: the ratio between the blue and red scattering optical densities γ≡Log [T(450 nm)]/Log [T(630 nm)] of said diffuser falls in the range 5≦γ≦2.5, where T(λ) is the Monochromatic Normalized Collinear Transmittance; in at least one propagation direction, said Monochromatic Normalized Collinear Transmittance is T(450 nm)≦0.4; in at least one propagation direction said Monochromatic Normalized Collinear Transmittance is T(450 nm)≦0.9, said propagation direction being the same or different from that at which said Monochromatic Normalized Collinear Transmittance is T(450 mm)≦0.4. | 2011-09-08 |
| 20110216543 | LENS MEMBER AND OPTICAL UNIT INCLUDING THE SAME - A lens member of obtaining light-collecting properties even if using a light source with a large light-emitting surface area has a first lens portion refracting light to exit outward in radial directions perpendicular to a central axis of the lens member and a second lens portion totally internally reflecting the light that exited through the first lens portion. The first lens portion has a light incident surface disposed to face a light source and a conical light exit surface centered at the central axis of the lens member and slanted so that the distance between the conical surface and the light incident surface increases as the distance from the central axis increases outward in the radial directions perpendicular to the central axis. The second lens portion has an inner circumferential surface receiving light from the first lens portion and an outer circumferential surface positioned outward of the inner circumferential surface in the radial directions perpendicular to the central axis. The outer circumferential surface totally reflects light received through the inner circumferential surface in a direction away from the first lens portion toward the second lens portion in parallel to the direction of extension of the central axis. | 2011-09-08 |
| 20110216544 | LED Device for Wide Beam Generation - An apparatus and method is characterized by providing an optical transfer function between a predetermined illuminated surface pattern, such as a street light pattern, and a predetermined energy distribution pattern of a light source, such as that from an LED. A lens is formed having a shape defined by the optical transfer function. The optical transfer function is derived by generating an energy distribution pattern using the predetermined energy distribution pattern of the light source. Then the projection of the energy distribution pattern onto the illuminated surface is generated. The projection is then compared to the predetermined illuminated surface pattern to determine if it acceptably matches. The process continues reiteratively until an acceptable match is achieved. Alternatively, the lens shape is numerically or analytically determined by a functional relationship between the shape and the predetermined illuminated surface pattern and predetermined energy distribution pattern of a light source as inputs. | 2011-09-08 |
| 20110216545 | CONNECTING SYSTEM FOR IMPLEMENTING BRANCHES ON CONTINUOUS CONDUCTORS - A housing for connecting a plurality of branch lines to the insulated conductors of an intermediate portion of a cable from which the outer sheath layer has been removed, comprising a rectangular base member containing an open-topped base chamber, and a pair of opposed end walls containing openings for receiving spaced insulated portions of the cable on opposite sides of the cable intermediate portion. A plurality of insulation-piercing electrical devices are arranged in the base chamber in electrical engagement with the insulated conductors, respectively, and a plurality of interchangeable cover members are each adapted for seating on the base member to close the base chamber, with each of the cover members containing an electrical component arranged for connection with at least one of the electrical devices. | 2011-09-08 |
| 20110216546 | LAMPHOLDER WITH OCCUPANCY SENSOR - An electrical device is described having surface mounting structure for mounting the electrical device in one of at least three different mounting patterns. In one embodiment, the electrical device is a lampholder having an occupancy sensor. In this embodiment, the occupancy sensor defines a coverage area and an un-coverage area when the lampholder is mounted to a surface, such as a ceiling, via the surface mounting structure; and, the surface mounting structure includes four sets of keyholes enabling the lampholder to be mounted to fasteners on the surface in one of a plurality of different mounting patterns for positioning the un-coverage area in a desired location, such as, for example, opposite the closest entry point to a room. The coverage area corresponds to a detection field of the occupancy sensor. Motion in the detection field is detected by the occupancy sensor. | 2011-09-08 |
| 20110216547 | LIGHTING APPARATUS - In one embodiment, a lighting apparatus includes a base electrically grounded and a substrate provided in the base in which an emitting element is mounted. A transmissive cover is arranged in the front side of the substrate, and a metallic holding element is fixed to the base for supporting a peripheral portion of the cover by pressing the peripheral portion from the front side. | 2011-09-08 |
| 20110216548 | Vehicle Lighting System - An illumination controller comprise at least one sensor configured to sense position and motion of an operator of a banking vehicle, an illumination adjustment actuator, and a controller configured to determine angular velocity and/or linear acceleration, and banking angle of the vehicle from the sensed position and motion signals. The controller controls the illumination adjustment actuator to direct the illumination in anticipation of and during a turn. | 2011-09-08 |
| 20110216549 | VEHICLE LIGHT UNIT AND VEHICLE LIGHT - A vehicle light unit can convert an LED light source to a linear light emitting state and can be incorporated into a vehicle light. The vehicle light unit can include a first to fourth lens part in front of an LED light source. The first to third lens parts can convert the point light source or the LED light source into a linear light emitting portion with improved light utilization efficiency by providing first to fourth total reflection surfaces utilizing internal reflection to the third lens part. The light rays through the linear light emitting portion can be incident on the fourth lens part. The fourth lens part can include a plate-shaped light guiding portion with a plurality of total reflection surfaces on one surface and corresponding lens cut portions on the other opposite surface. | 2011-09-08 |
| 20110216550 | VEHICLE LIGHT - A vehicle light can prevent or suppress uneven luminance chromaticity or uneven intensity distribution of light caused by reflection of blue laser beams emitted from a laser light source and reflected by the surface of a metal plate located around fluorescent material. The vehicle light can include a metal plate, a fluorescent material provided on a surface of the metal plate. The fluorescent material can serve as a light source for emitting light beams as a result of excitation by a blue laser beam. A laser light source can be configured to emit the blue laser beam to be incident on the fluorescent material. A reflection suppressing member can be provided to cover the surface of the metal plate around the fluorescent material and can be configured to suppress the reflection of the blue laser beam emitted by the laser light source. | 2011-09-08 |
| 20110216551 | LAMP HOLDING FIXTURE FOR HEADLAMPS - The invention relates to a lamp holding fixture for headlamps, particularly for vehicle headlamps, comprising a ring element with a radial holding surface that a base of the lamp rests against and further comprising a tubular holding body made of an electrically conductive material such that said holding body, when the lamp is at its mounting position, extends between an electrically conductive section of a reflector and an electrically conductive housing of a lamp igniter, wherein the tubular holding body is assigned fixing material for holding the lamp in its mounting position and wherein the tubular holding body features a plurality of first contact springs distributed in peripheral direction over a side facing the reflector and a plurality of second contact springs distributed in peripheral direction over another side facing the igniter. | 2011-09-08 |
| 20110216552 | LIGHT EMITTING DEVICE - An embodiment of the invention provides a light emitting device in which a semiconductor laser diode is used as a light source to emit visible light in a wide range. The light emitting device includes a semiconductor laser diode that emits a laser beam; and a luminescent component that is provided while separated from the semiconductor laser diode and absorbs the laser beam to emit the visible light. In the light emitting device, the luminescent component includes an optical path through which the laser beam is incident to a center portion of the luminescent component. | 2011-09-08 |
| 20110216553 | SCANNER MODULE AND IMAGE SCANNING APPARATUS EMPLOYING THE SAME - A scanner module and an image scanning apparatus employ an illuminator that includes at least one light emitting diode, a light guide to change the direction of the light from the light emitting diode, and a light source holder to which the light emitting diode is mounted, the light source holder being positioned in relation to the light guide such that the light source holder covers an incidence face of the light guide, on which the light from the light source is incident, the surface of light source holder facing the incidence face reflecting light incident thereupon. The reflection of light by the light source holder reduces the possibility of leakage of light, and can enhance luminous intensity of light of the illuminator. | 2011-09-08 |
| 20110216554 | LIGHT EMITTING DEVICE - An embodiment of the invention provides a light emitting device in which a semiconductor laser diode is used as a light source to efficiently obtain visible light having high uniformity of a luminance distribution. The light emitting device has a semiconductor laser diode that emits a laser beam. And the device has a light guide component that includes an upper surface, a lower surface, two side faces opposite each other, and two end faces opposite each other, the laser beam being incident from a first end face of the light guide component, the light guide component having indentation in the lower surface, the laser beam being reflected by the lower surface and emitted in an upper surface direction. The light emitting device also has a luminous component that is provided on an upper surface side of the light guide component and absorbs the laser beam emitted from the light guide component and emits visible light. And the device has a substance that is in contact with the lower surface and two side faces of the light guide component, a refractive index of the substance being lower than that of the light guide component. | 2011-09-08 |
| 20110216555 | LED DEVICE FOR BACKLIGHT MODULE - A light emitting diode (LED) device applied to a backlight module includes a substrate, a plurality of sub-substrates, a plurality of light emitting chips, and a plurality of package lenses. The sub-substrates are installed on the substrate, and the light emitting chips are installed on the sub-substrates respectively. The package lenses are installed on the light emitting chips respectively, and each package lens is in a solid semi-elliptical shape and includes a long axis and a short axis perpendicular to the long axis. | 2011-09-08 |
| 20110216556 | BACKLIGHT ASSEMBLY AND DISPLAY APPARATUS HAVING THE SAME - A display apparatus includes a light guide plate guiding a light, a light source arranged in a side portion of the light guide plate to generate the light, a display panel receiving the light from the light guide plate to display an image, a frame including a sidewall and a support part extended from the sidewall to support the display panel, and an optical member arranged between the light guide plate and the display panel to control a path of the light exiting from the light guide plate. The optical member includes a first side portion and a second side portion, a side surface of the first side portion faces a side surface of the support part, and the second side portion is positioned between the support part and the light guide plate. | 2011-09-08 |
| 20110216557 | INVERTER CIRCUIT - This inverter circuit includes first and second switching elements and an output transformer which is provided with a first primary winding connected in series between said first and second switching elements, and also with a secondary winding for obtaining an output voltage. The inverter circuit is further provided with a first voltage supply, a second voltage supply, and a control unit. The first voltage supply applies voltage to said first switching element via said first primary winding. And the second voltage supply applies voltage to said second switching element via said second primary winding. The control unit turns said first switching element and said second switching element alternatingly ON and OFF. This inverter circuit also includes first and second regeneration snubber circuits for regenerating the charge charged into snubber capacitors. | 2011-09-08 |
| 20110216558 | POWER FACTOR CORRECTION CONVERTER - A low-cost PFC converter capable of detecting an inductor current including a DC component and performing appropriate correction of a power factor with low loss includes a diode bridge that rectifies an AC voltage input from an AC input power supply Vac, a series circuit including an inductor and a switching element, a rectifying and smoothing circuit that is connected in parallel to the switching element and that includes a diode and a smoothing capacitor, and a digital signal processing circuit that performs on/off control on the switching element so that an input current input from the AC input power supply Vac has a similar waveform with respect to an AC voltage. A current flowing through the inductor during an off period of the switching element is detected using a current detecting resistor, and a decreased voltage of the current detecting resistor is sampled at the middle of the off period of the switching element, thereby detecting an average value of the input current. | 2011-09-08 |
| 20110216559 | Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter - A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control. | 2011-09-08 |
| 20110216560 | TWO STAGE ISOLATED SWITCH-MODE AC/DC CONVERTER - An AC/DC two stage converter includes a non-isolated switch-mode regulated AC/DC voltage step-down first stage converter comprising an AC input and a first DC output. The AC voltage applied to the AC input is rectified and switch-mode regulated to a first DC voltage at the first DC output. The first DC voltage is lower than a peak voltage of the AC voltage applied to the AC input. An isolated switch-mode regulated DC/DC second stage converter includes a second DC input coupled to the first DC output and at least one second DC output, wherein the first DC voltage is switch-mode regulated to a second DC voltage at a second DC output. | 2011-09-08 |
| 20110216561 | Low-Inductance Power Semiconductor Assembly - A power semiconductor assembly includes at least two bridge branches each including at least two circuit breakers connected to a phase output. Each of the circuit breakers has at least two parallel-connected switching elements integrated into a semiconductor chip. Each of the circuit breakers is arranged in a power semiconductor module and the individual power semiconductor modules are arranged adjacent to one another in a first direction. The semiconductor chips of a particular circuit breaker are arranged adjacent to one another in the corresponding power semiconductor module in a second direction extending perpendicular to the first direction. | 2011-09-08 |
| 20110216562 | DC-TO-DC POWER CONVERSION - This disclosure includes systems and methods for managing the interaction between inverter-based DC and other power systems. In one embodiment, a 3-phase isolation transformer is fluxed to create a 3-phase rotating field from the output of a source inverter. An inductive filter turns that output into three sine waves. A secondary inverter regenerates the system, sometimes after the isolation transformer is fluxed, and by advancing or retarding the secondary inverter's phase, current (and, thus, the DC voltage and power direction) is controlled. In another embodiment, an inverter is supplied by a DC source. The inverter is controlled to match its output voltage, current, and phase to a live AC grid, then the two are connected. The inverter frequency is then driven to advance the phase of the inverter in relation to the grid. Alternatively, the inverter voltage is then driven at a level greater than that of the grid. | 2011-09-08 |
| 20110216563 | HEMT/GaN Half-Bridge Circuit - A half-bridge circuit in accordance with an embodiment of the present application includes an input voltage terminal operable to receive an input voltage, a first bi-directional switch, a second bi-directional switch connected in series with the first bi-directional switch, wherein the first and second bi-directional switches are connected to the input voltage terminal such that the input voltage is provided across the first and second bi-directional switches and a controller operable to turn the first and second bi-directional switches ON and OFF such that a desired voltage is provided at an midpoint node positioned between the first bi-directional switch and the second bi-directional switch. The first bi-directional switch and the second bi-directional switch are high electron mobility transistors structured to allow for conduction in two directions when ON and to prevent conduction in any direction when OFF. | 2011-09-08 |
| 20110216564 | Eighteen Pulse Rectification Scheme For Use With Variable Frequency Drives - An AC/DC converter system comprises an input circuit for connection to a three phase AC source. An isolation transformer comprises a set of primary windings and first and second sets of secondary windings magnetically coupled to the set of primary windings. The first and second sets of secondary windings are phase shifted by select amounts from the set of primary windings. The set of primary windings is connected to the input circuit. An AC/DC converter comprises first, second and third three phase rectifiers, the first three phase rectifier being powered by the first set of secondary windings, the second three phase rectifier being powered by the second set of secondary windings, and the third three phase rectifier being powered by the input circuit. An impedance matching inductor is electrically connected between the input circuit and the third three phase rectifier. An output circuit is connected between the AC/DC converter and a DC load. | 2011-09-08 |
| 20110216565 | ONE-CYCLE CONTROLLED POWER FACTOR CORRECTION METHOD - A one cycle control method for power factor correction based on a boost circuit and a main control chip of system comprises the steps of: ( | 2011-09-08 |
| 20110216566 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a rectifier circuit, by using a transistor whose off-state current is small as a so-called diode-connected MOS transistor included in the rectifier circuit, breakdown which is caused when a reverse bias is applied is prevented. Thus, an object is to provide a rectifier circuit whose reliability is increased and rectification efficiency is improved. A gate and a drain of a transistor are both connected to a terminal of the rectifier circuit to which an AC signal is input. In the transistor, an oxide semiconductor is used for a channel formation region and the off-state current at room temperature is less than or equal to 10 | 2011-09-08 |
| 20110216567 | Single switch inverter - A novel concept of converting a DC input to an AC output with a single active switch is disclosed. A series of topologies are developed to support the needs of different applications. Particular requirements for driving modern lighting devices are also addressed and supporting solutions are elaborated. | 2011-09-08 |
| 20110216568 | SYSTEM INTERCONNECTION INVERTER - The present invention includes: an inverter | 2011-09-08 |
| 20110216569 | CONTENT ADDRESSABLE MEMORY DEVICE - A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A. | 2011-09-08 |
| 20110216570 | RANK SELECT USING A GLOBAL SELECT PIN - Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks. | 2011-09-08 |
| 20110216571 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line. | 2011-09-08 |
| 20110216572 | ELECTRICALLY PROGRAMMABLE FUSE BIT - One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged. | 2011-09-08 |
| 20110216573 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter. | 2011-09-08 |
| 20110216574 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage. | 2011-09-08 |
| 20110216575 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY APPARATUS - According to one embodiment, a nonvolatile memory device includes a recording layer and a conductive first layer. The recording layer includes a main group element, a transition element, and oxygen. The recording layer is capable of recording information by changing reversibly between a high resistance state and a low resistance state. The first layer is made of at least one selected from a metal, a metal oxide, a metal nitride, and a metal carbide. The first layer is provided adjacent to the recording layer. The first layer includes the main group element with a concentration lower than a concentration of the main group element of the recording layer. | 2011-09-08 |
| 20110216576 | INFORMATION RECORDING/REPRODUCING DEVICE - According to one embodiment, an information recording/reproducing device includes a recording layer and a driver section. The recording layer has a first layer including a first compound. The first compound includes a mixed crystal of a first oxide containing a first metallic element and a second oxide. The second oxide has a crystal structure being same as the first oxide and contains a second metallic element different from the first metallic element. The driver section is configured to produce state change in the recording layer to record information by at least one of application of voltage to the recording layer and passage of current to the recording layer. Composition ratio of an element having a smaller ionic radius of the first and second metallic elements is not less than percolation threshold of a lattice formed of ions of the first and second metallic elements based on the crystal structure. | 2011-09-08 |
| 20110216577 | VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE - The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element ( | 2011-09-08 |
| 20110216578 | System for Retaining State Data - According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles. | 2011-09-08 |
| 20110216579 | SEMICONDUCTOR DEVICE - A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current. | 2011-09-08 |
| 20110216580 | MRAM-BASED MEMORY DEVICE WITH ROTATED GATE - A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction. | 2011-09-08 |
| 20110216581 | SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell. | 2011-09-08 |
| 20110216582 | INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a recording layer and a driving unit. The recording layer includes a first layer containing a first compound. The first compound includes a first positive ion element. The first positive ion element is made of a transition metal element and serves as a first positive ion. The second positive ion element serves as a second positive ion. The driving unit is configured to generate a phase change in the recording layer and to record information by at least one of application of a voltage and application of a current to the recording layer. The coordination number of the first positive ion element at a position of a second coordination of the second positive ion element is 80% or more and less than 100% of the coordination number when the first compound is assumed to be a perfect crystal. | 2011-09-08 |
| 20110216583 | SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit. | 2011-09-08 |
| 20110216584 | Electromechanical switch, storage device comprising such an electromechanical switch and method for operating the same - An electromechanical switch is described, which comprises a conductive body and a plurality of carbon nanotubes being separate to each other, each of the carbon nanotubes being connected to at least one common terminal electrode with at least one of its ends, wherein in an open state of the switch each of the carbon nanotubes substantially projects along a surface of the conductive body and keeps up a gap to said surface, and wherein in a closed state of the switch at least one carbon nanotube is bend in a direction of the surface to close an electrical contact between said terminal electrode and the conductive body. The size of the gap between the respective carbon nanotube and the surface is different for each one of the plurality of carbon nanotubes. | 2011-09-08 |
| 20110216585 | METAL CONTAINING MATERIALS - Metal containing materials and methods of forming the same are disclosed. One such method includes substantially concurrently feeding a flow of precursor gas containing a metal of a metal containing material and a flow of source gas containing a reducing agent so that the precursor gas and the source gas react to form a thickness of the metal containing material. The flow of precursor gas is discontinued, and while the flow of precursor gas is discontinued, the flow of source gas continues to be fed to contact the thickness of the metal containing material. | 2011-09-08 |
| 20110216586 | Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding - Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell. | 2011-09-08 |
| 20110216587 | NONVOLATILE MEMORY DEVICE, METHODS OF PROGRAMING THE NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - Embodiments of the inventive concept provide a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a read/write circuit, and a backup circuit. The memory cell array includes a first memory block including a first word line having first memory cells and a second word line having second memory cells. Each of the first memory cells and second memory cells configured to store first-bit data and second-bit data. The read/write circuit is configured to program data into the first and second memory cells and read data stored in the first and second memory cells. The backup circuit is configured to, after first-bit data are programmed into the first word line, but before second-bit data are programmed into the first word line, store first-bit data stored in the second memory cells of the second word line | 2011-09-08 |
| 20110216588 | MULTI-BIT CELL MEMORY DEVICES USING ERROR CORRECTION CODING AND METHODS OF OPERATING THE SAME - A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits. | 2011-09-08 |
| 20110216589 | FLASH MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to the input data, and provides the converted data to the memory device. Accordingly, the memory system is capable of improving the reliability of programmed data by changing the bandwidth corresponding to data to be programmed. A method of storing data in a memory system is also disclosed. | 2011-09-08 |
| 20110216590 | NONVOLATILE MEMORY DEVICE USING INTERLEAVING TECHNOLOGY AND PROGRAMMMING METHOD THEREOF - A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2 | 2011-09-08 |
| 20110216591 | PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate. | 2011-09-08 |
| 20110216592 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines. | 2011-09-08 |
| 20110216593 | NAND FLASH MEMORY - A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group. | 2011-09-08 |
| 20110216594 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 2011-09-08 |
| 20110216595 | NAND FLASH MEMORY OF USING COMMON P-WELL AND METHOD OF OPERATING THE SAME - A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection. | 2011-09-08 |
| 20110216596 | Reliability Protection for Non-Volatile Memories - A non-volatile memory cell having enhanced protection against mobile ions. The electric field within the memory cell is controlled in a manner that minimizes migration of mobile ions toward the floating gate. Each conductive layer in the memory cell is biased to reduce the flow of mobile ions toward the floating gate. The memory cell is preferably manufactured using a conventional logic process. | 2011-09-08 |
| 20110216597 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality of first conductive layers are formed around the side surface of the columnar portion and the charge storage layer. A control circuit comprises a plurality of second conductive layers, an insulating layer, and a plurality of plug layers. The plurality of second conductive layers are formed in the same layers as the plurality of first conductive layers. The insulating layer is formed penetrating the plurality of second conductive layers in the perpendicular direction. The plurality of plug layers are formed penetrating the insulating layer in the perpendicular direction. The insulating layer has a rectangular shaped cross-section with a constricted portion in a horizontal direction to the substrate. The constricted portion is positioned on a long side of the cross-section. | 2011-09-08 |
| 20110216598 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 2011-09-08 |
| 20110216599 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a first even-numbered bit line, to execute a second data program in a first odd-numbered bit line, to execute a verify read of the programmed bit lines, to determine whether a value of the verify read is programmed up to a predetermined threshold value, and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line. | 2011-09-08 |
| 20110216600 | DRAIN SELECT GATE VOLTAGE MANAGEMENT - Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed. | 2011-09-08 |
| 20110216601 | CURRENT SINK SYSTEM BASED ON SAMPLE AND HOLD FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval. | 2011-09-08 |
| 20110216602 | FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME - Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device. | 2011-09-08 |
| 20110216603 | Non-Volatile Memory Device, Erasing Method Thereof, And Memory System Including The Same - Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate. | 2011-09-08 |
| 20110216604 | METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential. | 2011-09-08 |
| 20110216605 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL BIT LINES - Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer. | 2011-09-08 |
| 20110216606 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values. | 2011-09-08 |
| 20110216607 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 2011-09-08 |
| 20110216608 | TECHNIQUES FOR READING FROM AND/OR WRITING TO A SEMICONDUCTOR MEMORY DEVICE - Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also include a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further include a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry. | 2011-09-08 |
| 20110216609 | Read Circuitry for an Integrated Circuit Having Memory Cells and/or a Memory Cell Array, and Method of Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation. | 2011-09-08 |
| 20110216610 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - Disclosed is a semiconductor device in which substantial enhancement of a write margin without degradation of a static noise can be achieved while obviating an increase in physical circuit size. There are disposed a plurality of power supply lines for feeding a power supply voltage to each column of static memory cells that use complementary bit lines in common; a plurality of power switches, each being disposed for each of the power supply lines; and a plurality of short-circuit switches, each being so arranged as to provide short-circuiting between output nodes of different power switches. When a complementary bit line select signal indicates an unselected level, the power switch corresponding thereto is put in an ON state so that, in a read operation, a power supply voltage is fed via the short-circuit switch concerned to a selected memory cell column from the power supply line corresponding to a memory cell being unselected, or in a write operation, a power supply voltage fed via the short-circuit switch concerned to a selected memory cell column is stopped. | 2011-09-08 |
| 20110216611 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 2011-09-08 |
| 20110216612 | Device - A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number. | 2011-09-08 |
