| 36th week of 2011 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20110215313 | DIKETOPYRROLOPYRROLE POLYMERS FOR USE IN ORGANIC SEMICONDUCTOR DEVICES - The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (I), and at least one (repeating) unit(s) which is selected from repeating units of the formula (II), (III) and (IV); and polymers of the formula III, or IV and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors, organic photovoltaics (solar cells) and photodiodes. | 2011-09-08 |
| 20110215314 | DUAL GATE FIELD-EFFECT TRANSISTOR AND METHOD OF PRODUCING A DUAL GATE FIELD-EFFECT TRANSISTOR - The present invention relates to a dual gate field-effect transistor ( | 2011-09-08 |
| 20110215315 | SWITCHING ELEMENT AND METHOD FOR FABRICATING SAME - A switching element comprises a source electrode, a drain electrode arranged apart from the source electrode, an active layer in contact with the electrodes, and a gate electrode arranged apart from the source and drain electrodes and being in contact with the active layer with a gate insulating layer interposed therebetween. The active layer is formed of a dispersion film containing predetermined carbon nanotubes and a predetermined polyether compound. | 2011-09-08 |
| 20110215316 | LOW VOLTAGE-DRIVEN ORGANIC ELECTROLUMINESCENCE DEVICE, AND MANUFACTURING METHOD THEREOF - The present invention provides an organic light emitting device including an organic layer of two or more organic layers including a first electrode, a second electrode and an emission layer disposed between the two electrodes, wherein the organic layer includes a first injection or transport layer including a material having a LUMO energy level of −4 eV or lower and a second hole injection or transport layer including a material having a HOMO energy level of −4 eV or lower and a material having a LUMO energy level of −4 eV or lower, which is in contact with the first hole injection or transport layer and a method for manufacturing the organic light emitting device. | 2011-09-08 |
| 20110215317 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization. | 2011-09-08 |
| 20110215318 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. | 2011-09-08 |
| 20110215319 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. | 2011-09-08 |
| 20110215320 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided that includes: (a) forming a layer of dielectric material above a substrate; (b) forming an opening in the dielectric layer; (c) depositing a solution that includes a carbon-based switching material on the substrate; (d) rotating the substrate to cause the solution to flow into the opening and to form a carbon-based switching material layer within the opening; and (e) forming a memory element using the carbon-based switching material layer. Numerous other aspects are provided. | 2011-09-08 |
| 20110215321 | POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC - A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate. | 2011-09-08 |
| 20110215322 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm | 2011-09-08 |
| 20110215323 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion. | 2011-09-08 |
| 20110215324 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF - A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer. | 2011-09-08 |
| 20110215325 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly purified oxide semiconductor layer is formed in such a manner that a substance that firmly bonds during film formation to an impurity containing a hydrogen atom is introduced into a film formation chamber, the substance is reacted with the impurity containing a hydrogen atom remaining in the film formation chamber, and the substance is changed to a stable substance containing the hydrogen atom. The stable substance containing the hydrogen atom is exhausted without providing a metal atom of an oxide semiconductor layer with the hydrogen atom; therefore, a phenomenon in which a hydrogen atom or the like is taken into the oxide semiconductor layer can be prevented. As the substance that firmly bonds to the impurity containing a hydrogen atom, a substance containing a halogen element is preferable, for example. | 2011-09-08 |
| 20110215326 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization. | 2011-09-08 |
| 20110215327 | ACTIVE MATRIX LIQUID CRYSTAL DISPLAY DEVICE - A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large. | 2011-09-08 |
| 20110215328 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR, AND DISPLAY DEVICE - There is provided a thin film transistor, which has a uniform and good electric characteristic and has a simple configuration allowing decrease in number of manufacturing steps, and a method of manufacturing the thin film transistor, and a display device having the thin film transistor. The thin film transistor includes: a gate electrode; an oxide semiconductor film having a multilayer structure of an amorphous film and a crystallized film; and a source electrode and a drain electrode provided to contact the crystallized film. | 2011-09-08 |
| 20110215329 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device, formed to be transparent, includes a substrate; a plurality of thin film transistors disposed on the substrate; a passivation layer covering the plurality of thin film transistors; a plurality of pixel electrodes disposed on the passivation layer and connected electrically to the plurality of thin film transistors, and overlapping and covering the plurality of thin film transistors; a first conductive unit disposed on the passivation layer to be disconnected electrically from the pixel electrodes; a pixel defining layer formed on the passivation layer to cover edges of the pixel electrodes; an opposite electrode facing the plurality of pixel electrodes, and covering at least part of the first conductive unit; an organic layer, including an emission layer, disposed between the pixel electrodes and the opposite electrode; and a second conductive unit connected electrically to a portion of the opposite electrode and the first conductive unit. | 2011-09-08 |
| 20110215330 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light-emitting display device and a method of fabricating the same. The organic light-emitting display device includes: a substrate; a first electrode including a first metal layer disposed on the substrate and formed of titanium (Ti), aluminum (Al), a titanium or aluminum alloy, a second metal layer disposed on the first metal layer, and a transparent conductive layer disposed on the second metal layer; an organic layer disposed on the first electrode and including at least one organic emission layer; and a second electrode disposed on the organic layer. The method includes: forming a first electrode including a first metal layer formed of Ti, Al, or a titanium or aluminum alloy, a second metal layer, and a transparent conductive layer, on a substrate ; forming an organic layer including at least one organic emission layer on the first electrode; and forming a second electrode on the organic layer. | 2011-09-08 |
| 20110215331 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine. | 2011-09-08 |
| 20110215332 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×10 | 2011-09-08 |
| 20110215333 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus. | 2011-09-08 |
| 20110215334 | PHOTOCURABLE POLYMERIC DIELECTRICS AND METHODS OF PREPARATION AND USE THEREOF - Disclosed are polymer-based dielectric compositions (e.g., formulations) and materials (e.g. films) and associated devices. The polymers generally include photocrosslinkable pendant groups; for example, the polymers can include one or more coumarin-containing pendant groups. | 2011-09-08 |
| 20110215335 | Organic light emitting diode display and manufacturing method thereof - An organic light emitting diode display includes a substrate main body, a semiconductor layer and a first capacitor electrode on the substrate main body, bottom surfaces of the semiconductor layer and first capacitor electrode being substantially coplanar, and each of the semiconductor layer and first capacitor electrode including an impurity-doped polysilicon layer, a gate insulating layer on the semiconductor layer and the first capacitor electrode, a gate electrode on the semiconductor layer with the gate insulating layer therebetween, and a second capacitor electrode on the first capacitor electrode with the gate insulating layer therebetween, the second capacitor electrode including a convex electrode portion and a concave electrode portion, the concave electrode portion being thinner than each of the convex electrode portion and the gate electrode. | 2011-09-08 |
| 20110215336 | LAMINATED STRUCTURE, MULTILAYER WIRING BOARD, ACTIVE MATRIX SUBSTRATE, IMAGE DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING LAMINATED STRUCTURE - A method for manufacturing a laminated structure includes a step of supplying a droplet of a functional fluid selectively to at least a first region of a high surface energy area formed in a wettability variable layer of the laminated structure. In the step, the droplet is supplied by inkjet printing, and a center position of the droplet is determined in such a manner as to satisfy both Equations (1) and (2) below: | 2011-09-08 |
| 20110215337 | ELECTRIC OPTICAL DEVICE AND ELECTRONIC DEVICE - An electric optical device includes a transistor that includes a semiconductor layer having a source region connected to a data line, a drain region connected to a pixel electrode, and a channel region, and a gate electrode, a first light blocking film that is formed to be wider than the gate electrode and that is connected to the gate electrode via a first contact hole which is opened in a first insulating film disposed on the gate electrode, and a second light blocking film that is provided between the semiconductor layer and a substrate and is connected to the first light blocking film via a second contact hole which is opened to penetrate the first insulating film, a gate insulating film, and a second insulating film. | 2011-09-08 |
| 20110215338 | SEMICONDUCTOR DEVICES WITH HETEROJUNCTION BARRIER REGIONS AND METHODS OF FABRICATING SAME - An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed. | 2011-09-08 |
| 20110215339 | Termination and contact structures for a high voltage GaN-based heterojunction transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer. | 2011-09-08 |
| 20110215340 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device according to the present invention includes: a GaN substrate | 2011-09-08 |
| 20110215341 | Biometric Sensor Assembly With Integrated Visual Indicator - A biometric sensor assembly comprises a substrate to which is mounted a die containing sensor circuitry, at least one conductive bezel having a visual indicator region formed therein, and electrically connected to said die by way of said substrate, a light source, and a light-directing region directing light from the light source to the visual indicator region. The die, the light-directing region, and the bezel are encased in an encapsulation structure such that a portion of a surface of the die and the visual indication region are exposed or at most thinly covered by the encapsulation structure. The light-directing region directs light emitted by the light source within the encapsulation structure to the visual indicator region. Desired indicia in the visual indicator region may thereby be illuminated, while the die and bezel, and optionally the light source, are protected by the encapsulation structure. | 2011-09-08 |
| 20110215342 | LED PACKAGING WITH INTEGRATED OPTICS AND METHODS OF MANUFACTURING THE SAME - Methods and structures are provided for wafer-level packaging of light-emitting diodes (LEDs). An array of LED die are mounted on a packaging substrate. The substrate may include an array of patterned metal contacts on a front side. The metal contacts may be in electrical communication with control logic formed in the substrate. The LEDs mounted on the packaging substrate may also be encapsulated individually or in groups and then singulated, or the LEDs mounted on the packaging substrate may be integrated with a micro-mirror array or an array of lenses. | 2011-09-08 |
| 20110215343 | Semiconductor device and optical pickup device - By increasing the width of a lead terminal | 2011-09-08 |
| 20110215344 | LOW POWER GRADED BASE SiGe HBT LIGHT MODULATOR - A graded base silicon-germanium (SiGe) heterojunction bipolar transistor (HBT)-based electro-optical (EO) modulator includes a graded base HBT and a light beam directed under the graded base HBT and passing through the free carrier plasma within for the purpose of inducing a phase modulation of the light beam. | 2011-09-08 |
| 20110215345 | SOLID STATE LAMP WITH THERMAL SPREADING ELEMENTS AND LIGHT DIRECTING OPTICS - Lamps and bulbs are disclosed generally comprising different combinations and arrangements of a light source, one or more wavelength conversion materials, regions or layers which are positioned separately or remotely with respect to the light source, and a separate diffusing layer. This arrangement allows for the fabrication of lamps and bulbs that are efficient, reliable and cost effective and can provide an essentially omni-directional emission pattern, even with a light source comprised of a co-planar arrangement of LEDs. The lamps according to the present invention can also comprise thermal management features that provide for efficient dissipation of heat from the LEDs, which in turn allows the LEDs to operate at lower temperatures. The lamps can also comprise optical elements to help change the emission pattern from the generally directional (e.g. Lambertian) pattern of the LEDs to a more omni-directional pattern. | 2011-09-08 |
| 20110215346 | LIGHT EMITTING DIODE - AC LED according to the present invention comprises a substrate, and at least one serial array having a plurality of light emitting cells connected in series on the substrate. Each of the light emitting cells comprises a lower semiconductor layer consisting of a first conductive compound semiconductor layer formed on top of the substrate, an upper semiconductor layer consisting of a second conductive compound semiconductor layer formed on top of the lower semiconductor layer, an active layer interposed between the lower and upper semiconductor layers, a lower electrode formed on the lower semiconductor layer exposed at a first corner of the substrate, an upper electrode layer formed on the upper semiconductor layer, and an upper electrode pad formed on the upper electrode layer exposed at a second corner of the substrate. The upper electrode pad and the lower electrode are respectively disposed at the corners diagonally opposite to each other, and the respective light emitting cells are arranged so that the upper electrode pad and the lower electrode of one of the light emitting cells are symmetric with respect to those of adjacent another of the light emitting cells. | 2011-09-08 |
| 20110215347 | Increasing Contrast In Electronic Color Displays Via Surface Texturing Of LEDs - In an embodiment, the invention provides a light source comprising a plurality of light-emitting semiconductor chips, a plurality of electrical leads and an encapsulant. The plurality of electrical leads is connected to the plurality of light-emitting semiconductor chips. The encapsulant completely encases the plurality of semiconductor chips. The encapsulant partially encases the plurality of electrical leads. | 2011-09-08 |
| 20110215348 | Reflection Mode Package for Optical Devices Using Gallium and Nitrogen Containing Materials - An optical device includes an LED formed on a substrate and a wavelength conversion material, which may be stacked or pixilated, within vicinity of the LED. A wavelength selective surface blocks direct emission of the LED device and transmits selected wavelengths of emission caused by an interaction with the wavelength conversion material. | 2011-09-08 |
| 20110215349 | LIGHT EMITTING DEVICE AND LIGHT UNIT HAVING THE SAME - A light emitting device includes a body having a recess; a barrier section protruding upward over a bottom surface of the recess and dividing the bottom surface of the recess into a plurality of regions; a plurality of light emitting diodes including a first diode disposed in a first region of the bottom surface of the recess and a second diode disposed in a second region of the bottom surface of the recess; a plurality of lead electrodes spaced apart from each other in the recess and selectively connected to the light emitting diodes; wires connecting the lead electrodes to the light emitting diodes; a resin layer in the recess; and at least one concave part in the barrier section. The concave part has a height lower than a top surface of the barrier section and higher than the bottom surface of the recess and the wires are provided in the concave part to connect the lead electrodes to the light emitting diodes disposed in opposition to each other. | 2011-09-08 |
| 20110215350 | LIGHT EMITTING DEVICE AND METHOD THEREOF - Disclosed are a method of fabricating a light emitting device includes the steps of: forming a plurality of compound semiconductor layers on a substrate, the substrate including a plurality of chip regions and isolation region; selectively etching the compound semiconductor layers to form a light emitting structure on each chip region and form a buffer structure on the isolation region; forming a conductive support member on the light emitting structure and the buffer structure; removing the substrate by using a laser lift off process; and dividing the conductive support member into the a plurality of chips of the chip regions, wherein the buffer structure is spaced apart from the light emitting structure. | 2011-09-08 |
| 20110215351 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light-emitting device includes an n-type semiconductor layer including a nitride semiconductor, a p-type semiconductor layer including a nitride semiconductor, a light-emitting portion and a stacked body. The light-emitting portion is provided between the n-type and p-type semiconductor layers and includes a barrier layer and a well layer. The well layer is stacked with the barrier layer. The stacked body is provided between the light-emitting portion and the n-type semiconductor layer and includes a first layer and a second layer. The second layer is stacked with the first layer. Average In composition ratio of the stacked body is higher than 0.4 times average In composition ratio of the light-emitting portion. The layer thickness t | 2011-09-08 |
| 20110215352 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, LIGHT EMITTING DEVICE PACKAGE - Disclosed is a method of manufacturing a light emitting device. The light emitting device includes a nitride semiconductor layer, an electrode on the nitride semiconductor layer, a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer under the nitride semiconductor layer, and a conductive layer under the light emitting structure. The nitride semiconductor layer has band gap energy lower than band gap energy of the first conductive type semiconductor layer. | 2011-09-08 |
| 20110215353 | LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - A light emitting device package comprises a substrate, an electrode on the substrate, a light emitting device on the substrate and electrically connected to the electrode layer, and a pattern enclosing the light emitting device. | 2011-09-08 |
| 20110215354 | Double Flip-Chip LED Package Components - A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first and a second bond pad on a surface of the carrier chip; and a third and a fourth bond pad on the surface of the carrier chip and electrically connected to the first and the second bond pads, respectively. The first, the second, the third, and the fourth bond pads are on a same surface of the carrier chip. The LED package component further includes a first and a second metal bump bonding the first and the second bond pads, respectively, onto the LED chip through flip-chip bonding; and a window-type module substrate bonded onto the third and the fourth bond pads through flip-chip bonding. The window-type module substrate includes a window, with the LED chip configured to emit light toward the window. | 2011-09-08 |
| 20110215355 | PHOTONIC CRYSTAL PHOSPHOR LIGHT CONVERSION STRUCTURES FOR LIGHT EMITTING DEVICES - Solid state light emitting devices include a solid state light emitting die and a photonic crystal phosphor light conversion structure. The photonic crystal phosphor light conversion structure may include a solid phosphor layer that includes dielectric nanostructures therein and may be on a light emitting surface of the solid state light emitting die. The photonic crystal phosphor light conversion structure may be attached to the light emitting surface of the solid state light emitting die via an adhesive layer. The photonic crystal phosphor light conversion structure may also be directly on a light emitting surface of the solid state light emitting die. Related methods are also disclosed. | 2011-09-08 |
| 20110215356 | LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING LIGHT EMITTING ELEMENT - According to embodiment, a light emitting element includes a light emitting layer having a first major surface and a second major surface, a first electrode provided on the first major surface side of the light emitting layer, and a second electrode provided on the second major surface side of the light emitting layer and having a basic outline. Furthermore, the light emitting element includes a current blocking portion provided between the first electrode and the light emitting layer or between the second electrode and the light emitting layer, and has an outline with a protrusion-depression pattern with respect to a virtual outline similar in shape to the basic outline of the second electrode. | 2011-09-08 |
| 20110215357 | LED PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An LED package structure for increasing heat-dissipating efficiency includes providing a substrate element; removing one part of the substrate element in order to form at least two substrate bodies separated from each other and at least one gap between the at least two substrate bodies; forming at least one | 2011-09-08 |
| 20110215358 | LIGHT EMITTING DEVICE - A light emitting device of the embodiment includes a light emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer; a first cavity passing through the first semiconductor layer and the active layer to expose the second semiconductor layer; a first electrode extending to the outside of the first cavity from the second semiconductor layer in the first cavity; a second electrode disposed on an outer peripheral region of a bottom surface of the first semiconductor layer and spaced apart from the first electrode while surrounding a lateral side of the first electrode; and a first insulating layer between the first electrode and the light emitting structure. | 2011-09-08 |
| 20110215359 | LIGHT EMITTING DEVICE - A light emitting device is provided. A light emitting device comprises a substrate, a first lead frame and a second lead frame on the substrate, an installation portion electrically connected to the first lead frame or the second lead frame, the installation portion being thinner than the first lead frame or the second lead frames, a light emitting diode on the installation portion, and a conductive member electrically connecting at least one of the lead frames to the light emitting diode. | 2011-09-08 |
| 20110215360 | LED Flip-Chip Package Structure with Dummy Bumps - A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip. | 2011-09-08 |
| 20110215361 | Thermally-Enhanced Hybrid LED Package Components - A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first bond pad and a second bond pad on a surface of the carrier chip and bonded onto the LED chip through flip-chip bonding, and a third bond pad and a fourth bond pad on the surface of the carrier chip and electrically connected to the first bond pad and the second bond pad, respectively. The first bond pad and the second bond pad are on a same side of the carrier chip facing the LED chip. The carrier chip further includes at least one through substrate via (TSV) connected to the first and second bond pads. | 2011-09-08 |
| 20110215362 | ILLUMINATION DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, an illumination device includes an anode, a metal layer, a cathode, an organic electroluminescent unit, first and second insulating layers, and a plurality of conductive piercing layers. The metal layer has an electrical resistance lower than that of the anode. The cathode is provided between the anode and the metal layer. The organic electroluminescent unit is provided between the anode and the cathode. The first insulating layer is provided between the cathode and the metal layer. The conductive piercing layers pierce the organic electroluminescent unit, the cathode, and the first insulating layer along a direction from the anode toward the metal layer to electrically connect the anode to the metal layer, and are separate entities from the metal layer. The second insulating layer is provided between the organic electroluminescent unit and the conductive piercing layers and between the cathode and the conductive piercing layers. | 2011-09-08 |
| 20110215363 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, and a second electrode. The stacked structural body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting portion. The stacked structural body has a first major surface on a side of the second semiconductor layer. The first electrode is provided on the first semiconductor. The second electrode is provided on the second semiconductor layer. The first electrode includes a first pad portion and a first extending portion that extends from the first pad portion along a first extending direction. The first extending portion includes a first width-increasing portion. A width of the first width-increasing portion along a direction orthogonal to the first extending direction is increased from the first pad portion toward an end of the first extending portion. | 2011-09-08 |
| 20110215364 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting element includes a conductive substrate, a bonding portion, an intermediate metal film, a first electrode, a semiconductor stacked body and a second electrode. The bonding portion is provided on the support substrate and including a first metal film. The intermediate metal film is provided on the bonding portion and having a larger linear expansion coefficient than the first metal film. The first electrode is provided on the intermediate metal film and includes a second metal film having a larger linear expansion coefficient than the intermediate metal film. The semiconductor stacked body is provided on the first electrode and including a light emitting portion. The second electrode is provided on the semiconductor stacked body. | 2011-09-08 |
| 20110215365 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A light emitting element package includes a package substrate, at least one light emitting element, a first encapsulation layer and a second encapsulation layer. The at least one light emitting element is mounted on the package substrate. The first encapsulation layer is mounted on the package substrate for encapsulation the at least one light emitting element. The second encapsulation layer is configured for encapsulation a back side of the at least one light emitting element. | 2011-09-08 |
| 20110215366 | Light emitting device - A light emitting device ( | 2011-09-08 |
| 20110215367 | ORGANIC ELECTROLUMINESCENCE ELEMENT AND LIGHT-EMITTING APPARATUS HAVING THE SAME - An organic EL element has a substrate, a first electrode, an organic compound layer, and a second electrode. The second electrode has a base layer and a metal layer, and light generated in this organic EL element is transmitted through the second electrode. The base layer is closer to the substrate than the metal layer and is a mixed layer containing lithium, oxygen, and magnesium, whereas the metal layer contains silver and has a thickness in the range of 5.0 to 20 nm, inclusive. | 2011-09-08 |
| 20110215368 | LIGHT-EMITTING DIODE WITH WIRE-PIERCING LEAD FRAME - A wire-piercing light-emitting diode (LED) a lead frame having a first lead and a second lead. The first lead has a first transition portion and a first bottom portion with a first cutting member, and the second lead having a second transition portion and a second bottom portion with a second cutting member. | 2011-09-08 |
| 20110215369 | LUMINESCENCE DIODE CHIP - A luminescence diode chip includes a semiconductor layer sequence having an active layer suitable for generating electromagnetic radiation, and a first electrical connection layer, which touches and makes electrically conductive contact with the semiconductor layer sequence. The first electrical connection layer touches and makes contact with the semiconductor layer sequence in particular with a plurality of contact areas. In the case of the luminescence diode chip, an inhomogeneous current density distribution or current distribution is set in a targeted manner in the semiconductor layer sequence by means of an inhomogeneous distribution of an area density of the contact areas along a main plane of extent of the semiconductor layer sequence. | 2011-09-08 |
| 20110215370 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device having high light extraction efficiency is provided. The semiconductor light-emitting device includes a light transmissive substrate; a nitride semiconductor layer of a first conduction type formed on or above a top face side of the light transmissive substrate; an active layer made of nitride semiconductor formed on a top face of the nitride semiconductor layer of the first conduction type; a nitride semiconductor layer of a second conduction type formed on a top face of the active layer; a dielectric layer formed on a bottom face of the light transmissive substrate and having a refractive index lower than that of the light transmissive substrate; and a metal layer formed on a bottom face of the dielectric layer. And an interface between the light transmissive substrate and the dielectric layer is a uneven face, and an interface between the dielectric layer and the metal layer is a flat face. | 2011-09-08 |
| 20110215371 | THYRISTOR BASED MEMORY CELLS, DEVICES AND SYSTEMS INCLUDING THE SAME AND METHODS FOR FORMING THE SAME - Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F | 2011-09-08 |
| 20110215372 | ESD Protection Devices - An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path. | 2011-09-08 |
| 20110215373 | SYSTEM AND METHOD FOR MANUFACTURING DOUBLE EPI N-TYPE LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR TRANSISTORS - A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current. | 2011-09-08 |
| 20110215374 | POWER SEMICONDUCTOR DEVICE HAVING ADJUSTABLE OUTPUT CAPACITANCE AND MANUFACTURING METHOD THEREOF - A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor. | 2011-09-08 |
| 20110215375 | MULTI-COMPONENT STRAIN-INDUCING SEMICONDUCTOR REGIONS - A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface. | 2011-09-08 |
| 20110215376 | PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION - A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator. | 2011-09-08 |
| 20110215377 | Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region - A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region. | 2011-09-08 |
| 20110215378 | High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same - High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer. | 2011-09-08 |
| 20110215379 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a semiconductor stack formed on a substrate, and having a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode and a drain electrode are formed on the semiconductor stack so as to be separated from each other. A gate electrode is formed between the source electrode and the drain electrode so as to be separated from the source electrode and the drain electrode. A hole injection portion is formed near the drain electrode. The hole injection portion has a p-type third nitride semiconductor layer, and a hole injection electrode formed on the third nitride semiconductor layer. The hole injection electrode and the drain electrode have substantially the same potential. | 2011-09-08 |
| 20110215380 | ELECTRONIC DEVICES WITH IMPROVED OHMIC CONTACT - In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s). | 2011-09-08 |
| 20110215381 | SOLID STATE IMAGING DEVICE - Each pixel of a solid state imaging device comprises a first semiconductor layer formed on a substrate, having a first-conductive type; a second semiconductor layer formed thereon, having a second-conductivity type; a third semiconductor layer formed in the upper side of the second semiconductor layer, having the first-conductivity type; a fourth semiconductor layer formed in the outer side of the third semiconductor layer, having the second-conductivity type; a gate conductor layer formed on the lower side of the second semiconductor layer via an insulating film; and a fifth semiconductor layer formed on the top surfaces of the second semiconductor layer and third semiconductor layer, having the second-conductivity type, wherein the fifth semiconductor layer and fourth semiconductor layer are connected to each other, and at least the third semiconductor layer, upper region of the second semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer are formed in an island. | 2011-09-08 |
| 20110215382 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode. | 2011-09-08 |
| 20110215383 | FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid | 2011-09-08 |
| 20110215384 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In manufacturing processes of a semiconductor device including a shallow trench element isolation region and an interlayer insulating film of a multilayer structure, it is necessary to repeatedly use CMP, but since the CMP itself is costly, the repeated use of the CMP is a cause to increase the manufacturing cost. | 2011-09-08 |
| 20110215385 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device which achieves miniaturization as well as suppressing a defect. Further, another object is to provide a semiconductor device which achieves miniaturization as well as keeping favorable characteristics. Is provided a semiconductor device including: a source wiring and a drain wiring each of which include a first conductive layer and a second conductive layer having a smaller thickness than the first conductive layer; an insulating layer which has an opening portion and is provided over the source wiring and the drain wiring; an oxide semiconductor layer which is in contact with part of the second conductive layer of the source wiring or the drain wiring in the opening portion; a gate insulating layer provided over the oxide semiconductor layer; and a gate electrode provided over the gate insulating layer. | 2011-09-08 |
| 20110215386 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Unintended full siliciding of a polysilicon gate electrode is prevented. | 2011-09-08 |
| 20110215387 | Semiconductor Constructions - The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist. | 2011-09-08 |
| 20110215388 | PIN CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A pin capacitor of a semiconductor device includes a first isolation layer formed in a substrate and defining a dummy active area, a plurality of gates formed over the first isolation layer, a spacer formed at both sidewalls of each of the gates, and a plug formed over the dummy active area and in contact with the spacer. The substrate and the plug are coupled to a ground unit, and the gate is coupled to a pad unit. That is, the pin capacitor includes a first capacitor including the gate, the isolation layer, and the substrate and a second capacitor including the gate, the spacer, and the plug, which are coupled in parallel to each other. | 2011-09-08 |
| 20110215389 | DRAM CELL TRANSISTOR DEVICE AND METHOD - A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region. | 2011-09-08 |
| 20110215390 | Semiconductor Devices and Methods of Fabricating the Same - A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug. | 2011-09-08 |
| 20110215391 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an isolation region, a semiconductor region, a groove, and an insulating film. The semiconductor region is defined by the isolation region. The groove is in the semiconductor region. The groove has first and second ends. At least one of the first and second ends reaches the isolation region. The insulating film is in the groove. | 2011-09-08 |
| 20110215392 | Semiconductor Devices and Methods of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration. | 2011-09-08 |
| 20110215393 | ON-CHIP PLASMA CHARGING SENSOR - A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage. | 2011-09-08 |
| 20110215394 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug. | 2011-09-08 |
| 20110215395 | MULTI-TRANSISTOR MEMORY CELL - The invention relates to a multi-transistor, e.g. two-transistor memory cell arranged on a semiconductor substrate | 2011-09-08 |
| 20110215396 | SEMICONDUCTOR CELLS, ARRAYS, DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME - Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device. | 2011-09-08 |
| 20110215397 | HIGH CELL DENSITY TRENCHED POWER SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The fabrication method of a high cell density trenched power semiconductor structure is provided. The fabrication method comprises the steps of: a) forming at least a gate trench in a substrate with a silicon oxide patterned layer formed thereon, said silicon oxide patterned layer having at least an open aligned to the gate trench; b) forming a polysilicon gate in the gate trench; c) forming a dielectric structure in the open, the dielectric structure has a sidewall thereof being lined with an etching protection layer; d) removing the silicon oxide patterned layer by selective etching; and e) forming a spacer on a side surface of the dielectric structure to define at least a contact window. | 2011-09-08 |
| 20110215398 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region. | 2011-09-08 |
| 20110215399 | P-CHANNEL POWER MOSFET - In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p | 2011-09-08 |
| 20110215400 | SEMICONDUCTOR DEVICE - To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP | 2011-09-08 |
| 20110215401 | Semiconductor Device and Its Manufacturing Method - In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region. | 2011-09-08 |
| 20110215402 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a gate on a substrate, a source region at a first side of the gate, a first conductive type body region under the source region, a second conductive type drain region at a second side of the gate, a device isolation region in the substrate between the source region and the drain region and overlapping part of the gate, and a first buried layer extending in a direction from the source region to the drain region, the first buried layer under the body region, overlapping part of the device isolation region, and not overlapping the drain region. | 2011-09-08 |
| 20110215403 | High Voltage Metal Oxide Semiconductor Device and Method for Making Same - The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device). | 2011-09-08 |
| 20110215404 | Method and Apparatus of Forming ESD Protection Device - The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region. | 2011-09-08 |
| 20110215405 | PREVENTION OF OXYGEN ABSORPTION INTO HIGH-K GATE DIELECTRIC OF SILICON-ON-INSULATOR BASED FINFET DEVICES - A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing. | 2011-09-08 |
| 20110215406 | THIN FILM TRANSISTOR AND ELECTRONIC DEVICE - A thin film transistor capable of stably obtaining good performance is provided. The thin film transistor includes an organic semiconductor layer, and a protective layer and a source electrode and a drain electrode formed on the organic semiconductor layer. The protective layer is disposed at least in a region between the source electrode and the drain electrode. | 2011-09-08 |
| 20110215407 | SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures. | 2011-09-08 |
| 20110215408 | FLOATING BODY CELL STRUCTURES, DEVICES INCLUDING SAME, AND METHODS FOR FORMING SAME - Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed. | 2011-09-08 |
| 20110215409 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 2011-09-08 |
| 20110215410 | I/O and Power ESD Protection Circuits By Enhancing Substrate-Bias in Deep-Submicron CMOS Process - A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps. | 2011-09-08 |
| 20110215411 | Method for Forming an Independent Bottom Gate Connection For Buried Interconnection Including Bottom Gate of a Planar Double Gate MOSFET - A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate ( | 2011-09-08 |
| 20110215412 | STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION - A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing. | 2011-09-08 |
