36th week of 2012 patent applcation highlights part 34 |
Patent application number | Title | Published |
20120225491 | PORTABLE DETECTION DEVICES AND METHODS FOR DETECTION OF BIOMARKERS AND OTHER ANALYTES - A detection device and method for detecting one or more analytes of interest in a test sample are provided. Some embodiments use analyte-specific binding partners that are conjugated to quantum dots (Qdots) for use in detecting the presence and/or quantity of the analytes of interest in a test sample. FRET based methods may to used enhance the quantum dot (Qdot) signal through complexing of the quantum dots with lanthanide chelates, such as terbium. Some embodiments of the invention provide a novel disposable testing device that contains, all in one, the components necessary for carrying out the novel assay detection system of the invention. The disposable testing device may be used at home, for example, to detect and quantitate, at ultrasensitive levels, multiple analytes in a biological sample with no requirement for professional assistance. | 2012-09-06 |
20120225492 | Starch Binding Domain and Use Thereof - The present invention provides a method for identifying starch binding sites of starch binding domain in CBM family. The CBM family is consisting of CBM20, CBM21, CBM25, CBM26, CBM34, and CBM41. The method further comprises predicting starch binding sites of starch binding domain in CBM family using the identified starch binding sites of starch binding domain with same topology. | 2012-09-06 |
20120225493 | Electronic-Chemometric Controlled System and Process for the Analysis of Analytes - A series of electronic-chemometric control processes to enhance the selectivity, concentration, analysis, and detec tion of chemical species (analytes) in the gas phase, such as when using SERS-based techniques. Controls consist variously of: 1) feedback of electronic signals corresponding to changes of static and variable parameters in targeted chemical species that vary according to a reduction, increase, maximization, linearization, or improved confidence in one or more chemometric output parameters; 2) methods for spatially locating the source of an analyte species; and, 3) variable duty cycling to save power and materials according to altered physical and environmental conditions within a monitored zone. | 2012-09-06 |
20120225494 | DNA LIGANDS FOR AFLATOXIN AND ZEARALENONE - The present invention relates to DNA ligands capable of binding to aflatoxin and zearalenone. The invention relates also to methods for determining the presence and concentration of aflatoxin and zearalenone in samples such as agricultural and food products, and to methods for removing or reducing the level of aflatoxin and zearalenone in samples such as agricultural and food products. The invention further relates to methods for identifying DNA ligands capable of binding to aflatoxin and zearalenone. The invention further relates to new DNA sequences. | 2012-09-06 |
20120225495 | DEVICE FOR DISTRIBUTING PARTICLES IN A FLUID AND METHODS THEREOF - A vial and particles for distributing reagent bound particles in a fluid, a kit, and methods for distributing particles in a fluid. | 2012-09-06 |
20120225496 | ORGANIC COLORED MICROPARTICLES, DIAGNOSTIC REAGENT KIT CONTAINING THE SAME, AND IN VITRO DIAGNOSIS METHOD - Provided are an immunochromatography kit that is highly sensitive and capable of multicoloration, and organic colored microparticles that are ideal as an element of the immunochromatography kit. Organic colored microparticles having an average grain size between 10 and 1,000 nm and a color intensity between 1.0 and 5.0 are prepared using cellulose as the starting material. When the organic colored microparticles are used as a label in an immunochromatography kit, the immunochromatography kit is of a high sensitivity than conventional technology. The immunochromatography kit is also capable of multicoloration and is useful for rapid diagnosis. | 2012-09-06 |
20120225497 | ZWITTERION-CONTAINING ACRIDINIUM COMPOUNDS - Hydrophilic, chemiluminescent acridinium compounds containing zwitterions are disclosed. These acridinium compounds, when used as chemiluminescent labels in immunochemistry assays and the like, exhibit decreased non-specific binding to solid phases and provide increased assay sensitivity. | 2012-09-06 |
20120225498 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of semiconductor device includes forming plural elements on a substrate, forming a silicon compound film so as to bury between a plurality of elements, and modifying the silicon compound film to a silicon dioxide film by radiating microwaves. | 2012-09-06 |
20120225499 | Method for Use in Making Electronic Devices Having Thin-Film Magnetic Components - Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness. | 2012-09-06 |
20120225500 | TRANSPARENT NONVOLATILE MEMORY THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process. | 2012-09-06 |
20120225501 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRICAL CUTOFF METHOD FOR USING FUSE PATTERN OF THE SAME - Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective. | 2012-09-06 |
20120225502 | PLASMA ETCHING METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A plasma etching method includes a preparation process for performing a plasma etching process using a processing gas including a first processing gas containing carbon (C) and fluorine (F), a ratio (C/F) of the first processing gas having a first value, and obtaining a residual amount of the mask layer corresponding to a variation point where a variation amount of the bowing CD is increased; a first plasma etching process using the processing gas including the first processing gas until a residual amount of the mask layer reaches the variation point; and a second plasma etching process performed after the first plasma etching process. The second plasma etching process is performed by using a processing gas including at least a second processing gas containing carbon (C) and fluorine (F), and a ratio (C/F) of the second processing gas is smaller than the first value. | 2012-09-06 |
20120225503 | DOPANT MARKER FOR PRECISE RECESS CONTROL - A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants. | 2012-09-06 |
20120225504 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material. | 2012-09-06 |
20120225505 | METHOD OF BONDING A SEMICONDUCTOR DEVICE USING A COMPLIANT BONDING STRUCTURE - A compliant bonding structure is disposed between a semiconductor device and a mount. In some embodiments, the device is a light emitting device. When the semiconductor light emitting device is attached to the mount, for example by providing ultrasonic energy to the semiconductor light emitting device, the compliant bonding structure collapses to partially fill a space between the semiconductor light emitting device and the mount. In some embodiments, the compliant bonding structure is plurality of metal bumps that undergo plastic deformation during bonding. In some embodiments, the compliant bonding structure is a porous metal layer. | 2012-09-06 |
20120225506 | HERMETICALLY-SEALED PACKAGES FOR ELECTRONIC COMPONENTS HAVING REDUCED UNUSED AREAS - Hermetically-sealed packages for electronic components, e.g., OLEDs, are provided. The packages have a first glass substrate ( | 2012-09-06 |
20120225507 | SUSPENSIONS FOR PROTECTING SEMICONDUCTOR MATERIALS AND METHODS FOR PRODUCING SEMICONDUCTOR BODIES - A suspension for protecting a semiconductor material includes a polymeric matrix as carrier medium, inorganic particles, and at least one of an absorber dye or a plasticizer. | 2012-09-06 |
20120225508 | PACKAGE SUBSTRATE FOR PTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME - Disclosed is a package substrate for an optical element, which includes a base substrate, a first circuit layer formed on the base substrate and including a mounting portion, an optical element mounted on the mounting portion, one or more trenches formed into a predetermined pattern around the mounting portion by removing portions of the first circuit layer so that the first circuit layer and the optical element are electrically connected to each other, and a fluorescent resin material applied on an area defined by the trenches so as to cover the optical element, and in which such trenches are formed on the first circuit layer so that the optical element and the first circuit layer are electrically connected to each other, thus maintaining the shape of the fluorescent resin material and obviating the need to form a via under the optical element. A method of manufacturing the package substrate for an optical element is also provided. | 2012-09-06 |
20120225509 | LED Flip-Chip Package Structure with Dummy Bumps - A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip. | 2012-09-06 |
20120225510 | METHOD FOR ENCAPSULATING A SUBSTRATE AND METHOD FOR FABRICATING A LIGHT EMITTING DIODE DEVICE - The present invention relates to a method for encapsulating a substrate, which comprises: | 2012-09-06 |
20120225511 | LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display includes a first substrate, a gate line and first and second data lines disposed on the first substrate, a first thin film transistor connected to the gate line and the first data line, a second thin film transistor connected to the gate line and the second data line, a color filter disposed on the first substrate, a protrusion disposed on the color filter, a first pixel electrode including a first linear electrode disposed on the protrusion and connected to the first thin film transistor, a second pixel electrode including a second linear electrode disposed on the protrusion and connected to the second thin film transistor, a second substrate disposed facing the first substrate, and blue phase liquid crystal disposed between the first substrate and the second substrate. | 2012-09-06 |
20120225512 | METHOD AND APPARATUS TO FABRICATE POLYMER ARRAYS ON PATTERNED WAFERS USING ELECTROCHEMICAL SYNTHESIS - A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed. | 2012-09-06 |
20120225513 | Method of Creating Micro-Scale Silver Telluride Grains Covered with Bismuth Nanoparticles - Provided is a method of enhancing thermoelectric performance by surrounding crystalline semiconductors with nanoparticles by contacting a bismuth telluride material with a silver salt under a substantially inert atmosphere and a temperature approximately near the silver salt decomposition temperature; and recovering a metallic bismuth decorated material comprising silver telluride crystal grains. | 2012-09-06 |
20120225514 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An optical component is fixed precisely on a sensor chip. After a sensor chip including a front surface having a sensor plane with a plurality of light receiving elements is mounted face-up over a wiring substrate, an adhesive is disposed on the front surface of the sensor chip at a plurality of positions, and a plurality of spacers having adherence is formed by curing this adhesive. Then, an adhesive paste is disposed on the front surface of the sensor chip. Then, an optical component held by a bonding tool is disposed on the front surface via the spacer and the adhesive. After that, the bonding tool is separated from the optical component and the optical component is fixed by curing the adhesive in a state in which a load is not applied to the optical component. | 2012-09-06 |
20120225515 | LASER DOPING TECHNIQUES FOR HIGH-EFFICIENCY CRYSTALLINE SEMICONDUCTOR SOLAR CELLS - Various laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films. | 2012-09-06 |
20120225516 | METHOD FOR FABRICATING IMAGE SENSOR - A method for fabricating an image sensor is provided. A substrate is provided, and then a plurality of photoresist patterns is formed on the substrate. The photoresist patterns are arranged in a first array, wherein a top view of each photoresist pattern has a substantially square shape and a distance between two neighboring photoresist patterns decreases from a center of the first array toward an edge of the first array. Then, a thermal reflow step is performed to convert the photoresist patterns into a plurality of microlenses arranged in a second array. | 2012-09-06 |
20120225517 | TEXTURING SURFACE OF LIGHT-ABSORBING SUBSTRATE - Etched substrates, and particularly, light-absorbing etched substrates, and methods for making such substrates are described. | 2012-09-06 |
20120225518 | Method and Apparatus to Detect the Alignment of a Substrate - A method of detecting the alignment of a substrate during a sequence of printing steps, comprises detecting in a detection unit a position of at least one printing track that forms a printed pattern onto a surface of the substrate in a first printing station, determining a reference point in at least a portion of the printing track, comparing the actual position of the reference point with an expected or previously detected position of the reference point, determining an offset between the actual position and the expected or previously detected position of the reference point, adjusting the reciprocal position between the printing head of a second printing station and the substrate to account for the determined offset, and then printing a second pattern over the first pattern. | 2012-09-06 |
20120225519 | PREPARATION OF SOLAR MODULES - The present invention relates to a method for the production of solar modules, in which air inclusions are prevented. | 2012-09-06 |
20120225520 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a transistor including an oxide semiconductor having favorable electrical characteristics and a manufacturing method thereof. A semiconductor device includes an oxide semiconductor film and an insulating film over a substrate. An end portion of the oxide semiconductor film is in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. The semiconductor device further includes a gate insulating film over and in contact with the oxide semiconductor film, a gate electrode with a sidewall insulating film over the gate insulating film, and a source electrode and a drain electrode in contact with the sidewall insulating film, the oxide semiconductor film, and the insulating film. | 2012-09-06 |
20120225521 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a method of manufacturing the same are disclosed. The single-layer board on chip package substrate in accordance with an embodiment of the present invention includes an insulator, which has a window perforated therethrough, a wiring pattern, a wire bonding pad and a solder ball pad, which are embedded in one surface of the insulator, and a solder resist layer, which is formed on the one surface of the insulator such that the solder resist layer covers the wiring pattern but at least portions of the wire bonding pad and the solder ball pad are exposed. | 2012-09-06 |
20120225522 | Package 3D Interconnection and Method of Making Same - A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members. | 2012-09-06 |
20120225523 | Method for Attaching Wide Bus Memory and Serial Memory to a Processor within a Chip Scale Package Footprint - A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate. | 2012-09-06 |
20120225524 | METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE - The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor. | 2012-09-06 |
20120225525 | MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate - Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided. | 2012-09-06 |
20120225526 | NANOWIRE AND LARGER GaN BASED HEMTS - Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form III-N post(s) followed by formation of the shell member(s). | 2012-09-06 |
20120225527 | HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE - A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction. | 2012-09-06 |
20120225528 | FLOATING GATE FLASH CELL DEVICE AND METHOD FOR PARTIALLY ETCHING SILICON GATE TO FORM THE SAME - A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques. | 2012-09-06 |
20120225529 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 2012-09-06 |
20120225530 | METHODS OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed. | 2012-09-06 |
20120225531 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR - A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer. | 2012-09-06 |
20120225532 | METHOD FOR CONTROLLING A RESISTIVE PROPERTY IN A RESISTIVE ELEMENT USING A GAS CLUSTER ION BEAM - A method for controlling a resistive property or conductive property in a resistive element using a gas cluster ion beam (GCIB) is described. In one embodiment, the method may include controlling a resistive switching behavior in a resistive switching random-access memory device using a gas cluster ion beam (GCIB). | 2012-09-06 |
20120225533 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a variable resistance memory device and a method of manufacturing the variable resistance memory device, the generation of a seam, or void, is avoided in the device that, if present, may otherwise reduce the reliability of the resulting device. | 2012-09-06 |
20120225534 | SELF-ALIGNED CROSS-POINT PHASE CHANGE MEMORY-SWITCH ARRAY - Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same. | 2012-09-06 |
20120225535 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a resistance element which is, when forming the resistance element including a resistor having a small thickness, less liable to cause disconnection of the resistor. Tip regions of electrodes which are formed by stacking a barrier metal film and an aluminum electrode film are formed so as to be single-layer barrier metal electrodes, and the resistor for electrically connecting the parallel barrier metal electrodes to each other is formed by lift-off. | 2012-09-06 |
20120225536 | SEMICONDUCTOR STRUCTURES HAVING DIRECTLY BONDED DIAMOND HEAT SINKS AND METHODS FOR MAKING SUCH STRUCTURES - A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO | 2012-09-06 |
20120225537 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a combined wafer; obtaining a first intermediate wafer by forming an active layer; obtaining a second intermediate wafer by forming a front-side electrode on the first intermediate wafer; supporting the second intermediate wafer by adhering an adhesive tape at the front-side electrode side; removing the supporting layer while supporting the second intermediate wafer using the adhesive tape; forming a backside electrode on the main surfaces of SiC substrates exposedby the removal of the supporting layer; adhering an adhesive tape at the backside electrode side and removing the adhesive tape at the front-side electrode side so as to support the plurality of SiC substrates using the adhesive tape; and obtaining a plurality of semiconductor devices by cutting the SiC substrates with the SiC substrates being supported by the adhesive tape provided at the backside electrode side. | 2012-09-06 |
20120225538 | METHODS OF DISPOSING ALIGNMENT KEYS AND METHODS OF FABRICATING SEMICONDUCTOR CHIPS USING THE SAME - A method of disposing alignment keys may include preparing a substrate including a shot group which includes a plurality of chip regions, and each of chip regions includes a key region. The method further includes forming at least one alignment key in each of the key regions of the substrate. Each of the alignment keys may be adapted to be used for at least one of a plurality of exposure processes which may be different from each other, and center points of the key regions may be located at points shifted from center points of the chip regions by the same distance along the same direction. | 2012-09-06 |
20120225539 | DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES - Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, the layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods. | 2012-09-06 |
20120225540 | Method for fabricating a porous semiconductor body region - A method for fabricating a porous semiconductor body region, comprising: | 2012-09-06 |
20120225541 | Nitride Semiconductor Structure - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth. | 2012-09-06 |
20120225542 | METHOD FOR PREPARING MULTILAYER OF NANOCRYSTALS, AND ORGANIC-INORGANIC HYBRID ELECTROLUMINESCENCE DEVICE COMPRISING MULTILAYER OF NANOCRYSTALS PREPARED BY THE METHOD - A method for preparing a multilayer of nanocrystals. The method includes the steps of (i) coating nanocrystals surface-coordinated by a photosensitive compound, or a mixed solution of a photosensitive compound and nanocrystals surface-coordinated by a material miscible with the photosensitive compound, on a substrate, drying the coated substrate, and exposing the dried substrate to UV light to form a first monolayer of nanocrystals, and (ii) repeating the procedure of step (i) to form one or more monolayers of nanocrystals on the first monolayer of nanocrystals. Further, an organic-inorganic hybrid electroluminescence device using a multilayer of nanocrystals prepared by the method as a luminescent layer. | 2012-09-06 |
20120225543 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a highly reliable semiconductor device with less change in threshold voltage is provided. An insulating film from which oxygen can be released by heating is formed in contact with an oxide semiconductor layer, and light irradiation treatment is performed on a gate electrode or a metal layer formed in a region which overlaps with the gate electrode, so that oxygen is added into the oxide semiconductor layer in a region which overlaps with the gate electrode. Accordingly, oxygen vacancies or interface states in the oxide semiconductor layer in a region which overlaps with the gate electrode can be reduced. | 2012-09-06 |
20120225544 | Method for producing a semiconductor component - Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×10 | 2012-09-06 |
20120225545 | Method of Fabricating Semiconductor Device - The present invention provides a method of fabricating a semiconductor device. A substrate is provided. A first region and a second region are defined on the substrate. A first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed on the first region. The sacrifice layer and the sacrifice gate layer are disposed on the second region of the substrate. Next, a first etching step is performed to remove the sacrifice gate layer in the first region and the second region. Then, a second etching step is performed to remove the sacrifice layer in the first region and the second region to expose the substrate of the second region. Lastly, a second interfacial layer is formed on the substrate of the second region. | 2012-09-06 |
20120225546 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A method of manufacturing a nonvolatile semiconductor storage device includes applying a first mask lying across a line pattern located in a first region for forming a first gate electrode and a line pattern located in a second region for forming a second gate electrode; slimming sidewalls of unmasked line patterns; forming a blanket film across the first region and the second region and partially removing the blanket film so as to remain along the slimmed sidewalls of the line patterns; applying a second mask above the line patterns located in the first region and removing the line patterns in the second region such that the masked line patterns in the first region remain; anisotropically etching the first film using the blanket film and the remaining line patterns as a mask; and etching a charge storage layer using the first film as a mask. | 2012-09-06 |
20120225547 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region. | 2012-09-06 |
20120225548 | METHODS OF FORMING DIELECTRIC LAYERS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant. | 2012-09-06 |
20120225549 | REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE - An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires. | 2012-09-06 |
20120225550 | HYBRID PITCH-SPLIT PATTERN-SPLIT LITHOGRAPHY PROCESS - An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks. | 2012-09-06 |
20120225551 | PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAPHY PROCESS - An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern. | 2012-09-06 |
20120225552 | TWO-TRACK CROSS-CONNECTS IN DOUBLE-PATTERNED METAL LAYERS USING A FORBIDDEN ZONE - An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines. | 2012-09-06 |
20120225553 | FORMATION OF A MASKING LAYER ON A DIELECTRIC REGION TO FACILITATE FORMATION OF A CAPPING LAYER ON ELECTRICALLY CONDUCTIVE REGIONS SEPARATED BY THE DIELECTRIC REGION - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 2012-09-06 |
20120225554 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING BOWING PREVENTION FILM - A method of manufacturing a semiconductor device, the method including sequentially forming a lower material film, a middle material film, and an upper material film on a semiconductor substrate; and forming an opening that vertically penetrates the upper material film, the middle material film, and the lower material film by etching the upper material film, the middle material film, and the lower material film, wherein the middle material film and the upper material film are formed of material films having etch rates lower than an etch rate of the lower material film with respect to an etchant for etching the lower material film. | 2012-09-06 |
20120225555 | Stable, concentratable chemical mechanical polishing composition and methods relating thereto - A chemical mechanical polishing composition useful for chemical mechanical polishing a semiconductor wafer containing an interconnect metal is provided, comprising, as initial components: water; an azole inhibitor; an alkali metal organic surfactant; a hydrotrope; a phosphorus containing agent; a water soluble cellulose; optionally, a non-saccharide water soluble polymer; optionally, a water soluble acid compound of formula I, wherein R is selected from a hydrogen and a C | 2012-09-06 |
20120225556 | Stable, concentratable, water soluble cellulose free chemical mechanical polishing composition - A chemical mechanical polishing composition useful for chemical mechanical polishing a semiconductor wafer containing an interconnect metal is provided, comprising, as initial components: water; an azole inhibitor; an alkali metal organic surfactant; a hydrotrope; a phosphorus containing agent; optionally, a non-saccharide water soluble polymer; optionally, a water soluble acid compound of formula I, wherein R is selected from a hydrogen and a C | 2012-09-06 |
20120225557 | SILICON GERMANIUM MASK FOR DEEP SILICON ETCHING - Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF | 2012-09-06 |
20120225558 | METHODS FOR CONTACT CLEAN - Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure. | 2012-09-06 |
20120225559 | CAVITY OPEN PROCESS TO IMPROVE UNDERCUT - A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer. | 2012-09-06 |
20120225560 | MANUFACTURING METHOD OF INTEGRATED CIRCUITS BASED ON FORMATION OF LINES AND TRENCHES - The disclosure relates to a method for etching a target layer, comprising: depositing a hard mask layer onto a target layer and onto the hard mask layer, a first photosensitive layer, exposing the first photosensitive layer through a first mask to transfer first patterns into the photosensitive layer, transferring the first patterns into the hard mask layer, depositing onto the hard mask layer etched a second photosensitive layer, exposing the second photosensitive layer through a second mask to transfer second patterns into the second photosensitive layer, transferring the second patterns into the hard mask layer by etching this layer, and transferring the first and second patterns into the target layer through the hard mask, the second patterns forming lines, and the first patterns forming trenches cutting the lines in the hard mask. | 2012-09-06 |
20120225561 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND COMPUTER-READABLE STORAGE MEDIUM - There is provided a semiconductor device manufacturing method for forming a step-shaped structure in a substrate by etching the substrate having thereon a multilayer film and a photoresist film on the multilayer film and serving as an etching mask. The multilayer film is formed by alternately layering a first film having a first permittivity and a second film having a second permittivity different from the first permittivity. The method includes a first process for plasma-etching the first film by using the photoresist film as a mask; a second process for exposing the photoresist film to hydrogen-containing plasma; a third process for trimming the photoresist film; and a fourth process for etching the second film by using the trimmed photoresist film and the plasma-etched first film as a mask. The step-shaped structure is formed in the multilayer film by repeatedly performing the first process to the fourth process in this sequence. | 2012-09-06 |
20120225562 | Methods Of Removing Noble Metal-Containing Nanoparticles - Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun. | 2012-09-06 |
20120225563 | ETCHING LIQUID FOR ETCHING SILICON SUBSTRATE REAR SURFACE IN THROUGH SILICON VIA PROCESS AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP HAVING THROUGH SILICON VIA USING THE ETCHING LIQUID - Disclosed are an etching liquid which is used for etching a silicon substrate rear surface in a through silicon via process, etches only a silicon substrate without etching a connecting plug composed of a metal such as copper, tungsten, etc., or polysilicon or the like, and has an excellent etching rate; and a method for manufacturing a semiconductor chip having a through silicon via using the same. The etching liquid is an etching liquid for etching a silicon substrate rear surface in a through silicon via process containing potassium hydroxide, hydroxylamine, and water; and the method for manufacturing a semiconductor chip includes a silicon substrate rear surface etching step using the etching liquid. | 2012-09-06 |
20120225564 | VAPOR DEPOSITION DEVICE, VAPOR DEPOSITION METHOD, AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD - In the disclosed vapor deposition method, by using a structure wherein an inner diameter of a group-V source gas introduction piping is greater than an outer diameter a group-III source gas introduction piping, and the group-III source gas introduction piping is inserted one-to-one into the interior of the group-V source gas introduction piping, the group-III source gas piping is thereby prevented from being cooled by a cooling mechanism, and hardening of metallic materials upon the surface of the wall of the piping is alleviated. It is thus possible to provide a vapor deposition device, a vapor deposition method, and a semiconductor element manufacturing method, which are capable of efficaciously introducing easily hardening metallic materials into a reactor without the metallic materials adhering to a showerhead or a piping, and to carry out efficacious doping. | 2012-09-06 |
20120225565 | REDUCED PATTERN LOADING USING SILICON OXIDE MULTI-LAYERS - Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications. | 2012-09-06 |
20120225566 | SUBSTRATE PROCESSING APPARATUS AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The temperature of a substrate is elevated rapidly while improving the temperature uniformity of the substrate. The substrate is loaded into a process chamber, the loaded substrate is supported on a first substrate support unit, a gas is supplied to the process chamber, the temperature of the substrate supported on the first substrate support unit is elevated in a state of increasing the pressure in the process chamber to higher than the pressure during loading of the substrate or in a state of increasing the pressure in the process chamber to higher than the pressure during processing for the surface of the substrate, the substrate supported on the first substrate support unit is transferred to the second substrate support unit and supported thereon after lapse of a predetermined time, and the surface of substrate is processed while heating the substrate supported on the second substrate support unit. | 2012-09-06 |
20120225567 | PROCESS FOR WET PASSIVATION OF BOND PADS FOR PROTECTION AGAINST SUBSEQUENT TMAH-BASED PROCESSING - A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array. | 2012-09-06 |
20120225568 | ANNEALING METHOD AND ANNEALING APPARATUS - An annealing method irradiates a target object, having a film formed on its surface, with a laser beam to perform an annealing process to the target object. The surface of the target object is irradiated with the laser beam obliquely at an incident angle that is determined to achieve an improved laser absorptance of the film. | 2012-09-06 |
20120225569 | ELECTRONIC APPARATUS WITH PLUG - An electronic apparatus with a plug is provided, which relates to the field of electronic technologies, and solves a technical problem of the plug is easily damaged when the plug in a state of extending out of a port is impacted by a force in a direction in which the plug retracts into the port. The electronic apparatus with a plug includes a housing opened with a port, a plug passing through the port, and a circuit board located inside the housing and electrically connected to the plug, where a locking mechanism is disposed between the plug and the housing, the locking mechanism is configured to lock the plug when the plug is in a state of extending out of the port, and the locking mechanism automatically becomes ineffective when the plug is impacted by the force in the direction in which the plug retracts into the port. | 2012-09-06 |
20120225570 | COAXIAL CONNECTOR FOR BOARD, PAIR OF CHAIN TERMINALS AND METHOD OF MANUFACTURING COAXIAL CONNECTOR FOR BOARD - Manufacturing efficiency of a connector is greatly improved, and the manufacturing costs and the product cost can be reduced. | 2012-09-06 |
20120225571 | CLAMP ASSEMBLY AND CONDUCTIVE CUSHION WITH MOLDED-IN GROUNDING FOIL - Systems and methods for securing and electrically grounding objects or payloads are provided herein. Clamp assemblies and the manufacture of clamp assemblies in accordance with the present technology can provide reliable and redundant electrical grounding and secure cushioned fastening. In one embodiment, an electrically grounding cushioned clamp assembly includes an elastomer cushion with a longitudinal opening extending therethrough. The clamp assembly can include an engaging surface configured to engage a payload and an electrically conductive comb strip disposed at least partially in the longitudinal opening. Portions of the comb strip can be exposed adjacent to the engaging surface to contact the payload and provide a plurality of electrical grounding paths. | 2012-09-06 |
20120225572 | ELECTRONIC DEVICE AND INFRARED RECEIVING DEVICE THEREOF - An electronic device includes a housing, a circuit board, an infrared receiving device and a protection cover. The protection cover is engaged in the window of the housing to cover the infrared receiving device. The protection cover includes a blocking plate, a side wall extending outwardly from the blocking plate, and two clasping ears respectively located at two opposite sides of the side wall. The blocking plate is attached to the housing, and the two clasping ears of the protection cover provide a permanent means of securing the protection cover to the housing. | 2012-09-06 |
20120225573 | TURBO MACHINE ELECTRICAL CONNECTION ELEMENT - An electrical connection element for a turbine engine, including conductors connected to a connector by a tubular coupling surrounding one end of the conductors, and an insert providing protection against wear of the conductors being mounted in the tubular coupling. The insert includes a substantially tubular central body containing the conductors and provided over at least a fraction of its length with a series of spacers bearing against an inside surface of the tubular coupling of the connection element so as to hold the central body at a distance from the inside surface. | 2012-09-06 |
20120225574 | CONNECTOR - A connector has a first housing ( | 2012-09-06 |
20120225575 | ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTOR ASSEMBLY - A configuration in which a stand-alone plug connector is directly fitted to the wall of a product case, and in the fitting state of the stand-alone plug connector, the contact part of a contact comes in contact with the contact part of a wiring pattern conductive path exposed on the surface of a fit connecting hole, and the electrical connection of a signal transmitting medium can be performed in a simple configuration. | 2012-09-06 |
20120225576 | CONNECTOR - Each housing ( | 2012-09-06 |
20120225577 | CONNECTOR - The connector includes an electrically insulating one-part or multi-part housing, in which at least one contact element is arranged, which is accessible via a first opening of the housing by a contact element of a complimentary second connector, and which is connectable with an electrical cable that can be introduced through a second opening of the housing. The housing of the assembled connector, which is made from a first material, includes at least a first coupling element, which corresponds to at least one second coupling element that is included on a tubular element, which is manufactured from a second material which after processing includes a higher mechanical strength than the first material, and wherein the housing is releasably held within the tubular element by the releasably interlinked coupling elements. | 2012-09-06 |
20120225578 | Electrical connection, cord anchor and method of anchoring same - A cord anchor device is used in conjunction with an electrical cord itself to prevent an electrical plug from becoming dislodged from an electrical socket of an electrical outlet assembly. Several embodiments and attachment methods are disclosed including methods where the electrical cord may be attached by “looping and threading” the electrical cord through the cord anchor device. | 2012-09-06 |
20120225579 | FPC CONNECTOR - To provide a connector capable of assuring contact pressure between a terminal and a flat cable without disposing a metal beam supporting an actuator. In the connector of the Present Application, a housing has a convexity-opposing a terminal, and an actuator has a concavity mating with the convexity. An axle disposed in the concavity is inserted into a bearing disposed on the convexity. The actuator has a cam fitting between the convexity and the terminal, and is disposed so as to be able to turn between a sandwiched position at which a flat cable is sandwiched between the cam and the terminal and a release position at which the sandwiching is released. | 2012-09-06 |
20120225580 | SIGNAL TRANSFER APPARATUS - A signal transfer apparatus includes a plurality of input connectors to which a plurality of signals are input from a first electronic device; and a single output connector which is connected to the plurality of input connectors and transfers the plurality of signals to a second electronic device. The length of a plurality of cables connecting the single output connector and the plurality of input connectors differs from each other so that the plurality of input connectors do not overlap each other. | 2012-09-06 |
20120225581 | COAXIAL CABLE CONNECTOR HAVING ELECTRICAL CONTINUITY MEMBER - A coaxial connector comprising a connector body; a nut, axially rotatable with respect to the connector body, the nut having a first forward end configured for threadably attaching to an interface port and a second rearward end; and a continuity member, electrically contacting the nut; wherein the connector is configured to maintain return loss below -40 dBvM when the connector is installed on the interface port, so as to be only engaged with one thread of the interface port is provided. | 2012-09-06 |
20120225582 | SEALED ELECTRICAL SPLICE ASSEMBLY - A sealed electrical splice assembly includes a housing defining a cavity and including an opening. A conductive bus plate is retained in the cavity. A plurality of electrically conductive terminals are received in the cavity are electrically connected to the bus plate. The plurality of terminals are connected to a plurality of wire conductors. A seal plug is disposed in the cavity through the opening adapted to sealingly engage an interior surface of the housing surrounding the seal plug. An end cover overlies the seal plug disposed in the opening. The cavity receives the plurality of terminals through the end cover and the seal plug thereby allowing the seal plug to sealingly engage the plurality of wire conductors. | 2012-09-06 |
20120225583 | CONNECTOR WITH TERMINAL RETENTION - A connector includes a shield that supports a housing. The housing includes a tongue that extends in a mating region defined by the shield. The tongue includes grooves (which may be on both sides of the shield) that support a plurality of terminals. The grooves each include a retention feature that secures the terminal in the groove while allowing a mating terminal to engage the terminals in the grooves without first engage the tongue. | 2012-09-06 |
20120225584 | Communications Plugs Having Capacitors that Inject Offending Crosstalk After a Plug-Jack Mating Point and Related Connectors and Methods - Communications plugs are provided that include a plug housing. A plurality of plug contacts are mounted in a row at least partly within the plug housing. The plug contacts are arranged as differential pairs of plug contacts. Each of the differential pairs of plug contacts has a tip plug contact and a ring plug contact. A first capacitor is provided that is configured to inject crosstalk from a first of the tip plug contacts to a first of the ring plug contacts at a point in time that is after the point in time when a signal transmitted through the first of the tip plug contacts to a contact of a mating jack reaches the contact of the mating jack. | 2012-09-06 |
20120225585 | ELECTRICAL CONNECTOR WITH EQUAL WIDTH CONNECTION PART - An electrical connector includes a plurality of transmission terminals and an insulation plate. The transmission terminals are g installed in parallel manner relative to one another, and each includes a first end, a second end and an equal-width connection part interconnecting the first end and the second end. The equal-width connection parts have the same width. The insulation plate is disposed among the transmission terminals so as to fix the transmission terminals in position with the first ends and the second ends protruding respectively and outwardly from the insulation plate. | 2012-09-06 |
20120225586 | ELECTRICAL CONNECTOR - An electrical connector is used for electrically connecting a chip module and includes: an insulating body, having a plurality of receiving slots; and a plurality of terminals, disposed in the receiving slots and each having a base plate, a contact arm and at least one extending arm, in which the base plate is fixed in the receiving slot, the contact arm is located on one side of the base plate and has a contact portion conducting the chip module, the contact portion is higher than the base plate and is exposed outside the receiving slot, and the extending arm is in a bent shape and has a lower end connected to the contact arm and an upper end connected to the base plate. | 2012-09-06 |
20120225587 | CONNECTOR - Areas at outer edge sides of a draw-out area for wires ( | 2012-09-06 |
20120225588 | CARD EDGE CONNECTOR - A card edge connector is provided for mating with a printed circuit board (PCB) having a card edge. The connector includes a housing having a card slot. The card slot is configured to receive the card edge of the PCB therein. The card slot includes opposing first and second sides. Signal contacts are held by the housing. The signal contacts include signal mating segments arranged in opposing first and second rows that extend along the opposing first and second sides, respectively, of the card slot. The signal mating segments are arranged in differential signal pairs, wherein the signal mating segments within a differential pair are arranged within the same row of the first and second rows. A ground contact is held by the housing. The ground contact includes a base and first and second ground mating segments that extend outwardly from the base. The first and second ground mating segments are arranged along the first and second sides, respectively, of the card slot such that the first and second ground mating segments are configured to engage the card edge therebetween. The first and second ground mating segments include springs that resiliently deflect when engaged by the card edge. | 2012-09-06 |
20120225589 | Adapter particularly for adapting light emitting diodes to commercial lamp-holders - An adapter, particularly for adapting light emitting diodes to commercial lamp-holders, comprising a printed circuit for driving light emitting diodes; the printed circuit has, along its longer sides, engagement elements with a complementary thread of a lamp-holder and, along one of its shorter sides, elastic elements for contact with a lower electric power supply region of the lamp-holder. | 2012-09-06 |
20120225590 | CONNECTOR CONSTRUCTIONS FOR ELECTRONIC APPLICATIONS - An electronic wiping torsional connector for use in connecting to mating contacts on an insulating base. The connector includes a plurality of contacts | 2012-09-06 |