| 36th week of 2012 patent applcation highlights part 23 |
| Patent application number | Title | Published |
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| 20120224390 | INTEGRATED LIGHT PIPE AND PERIMETER CHASSIS - A thin-profile portable electronic device with a display is described. The display can include a display assembly with an integrally formed light pipe and perimeter chassis. The light pipe can be utilized to provide back-lighting for the display. The light pipe and the perimeter chassis can be integrally formed to improve the stiffness of the light pipe and allow the over-all height of the display to be reduced. In one embodiment, the light pipe and the perimeter chassis can be formed using a co-molding process, such as an injection molding process. | 2012-09-06 |
| 20120224391 | LED LIGHTING DEVICE WHICH HAS STABLE STRUCTURE AND IS EASILY ASSEMBLED AND DISASSEMBLED - Disclosed is an LED lighting device which is easily assembled and disassembled and has a stable assemblability without structural shaking. The LED lighting device is able to improve a heat radiating characteristic and optical efficiency. The LED lighting device according to the embodiment includes a lower case; a light source unit disposed on one side of the lower case; a light guide plate disposed in parallel with the light source unit; and an upper case disposed on the light guide plate and coupled to the lower case in an attachable and removable way. | 2012-09-06 |
| 20120224392 | LIGHTING MODULE AND LIGHTING APPARATUS INCLUDING THE SAME - The lighting module includes: a case including an opening from which light is emitted, a base portion corresponding to the opening, and a seat on at least one side of the base portion; a light source unit disposed on the seat; a light guide plate placed within the case and optically connected with the light source unit; and a diffusing plate placed within the case and placed below the light guide plate, wherein the lighting source unit includes a substrate, a plurality of light emitting diodes (LEDs) disposed on the substrate, and a sub-reflector which is disposed on the substrate and covers the plurality of the LEDs, and wherein at least 90% of the light emitted from the LEDs is directly irradiated onto the light guide plate. | 2012-09-06 |
| 20120224393 | LED BACKLIGHT MODULE - Disclosed herein is an LED backlight module, which includes a metallic plate, a metallic sidewall, a connecting portion, a light guide and an LED ribbon. The metallic sidewall is substantially perpendicular to the metallic plate and located beside a side edge of the metallic plate. The metallic side-plate has a lower edge extending downwards to a position beneath a lower surface of the metallic plate. The connecting portion extends in a direction towards the side edge of the metallic plate from the lower edge of the metallic sidewall, and is further connected to the side edge of the metallic plate. The light guide is disposed above the metallic plate, and the LED ribbon for emitting a light into the light guide is disposed on the metallic sidewall. | 2012-09-06 |
| 20120224394 | Backlight Module and Backplate of the Backlight Module - A backlight module and a backplate for use in the backlight module are disclosed. The backlight module comprises a light guide plate, a light source and a backplate; the backplate comprises a baseplate, side plates extending upwards from two opposite sides of the baseplate respectively, and top plates extending from the two side plates respectively and towards each other, and the side plates, the top plates and the baseplate together form recesses for receiving the light source, with two opposite edges of the light guide plate being disposed in the recesses; a fixing post is disposed at an end of the baseplate, and a fixing groove is formed in the light guide plate corresponding to the fixing post, with the fixing post being fitted in the fixing groove; and display panel positioning blocks are disposed at both ends of an upper surface of each of the top plates. Therefore, the backlight module of the present invention is compact in structure. | 2012-09-06 |
| 20120224395 | LIGHT BULB UTILIZING A REPLACEABLE LED LIGHT SOURCE - The present invention is a light bulb featuring a removable LED light source. The preferred source being a lighting source with a three dimensional lead frame as disclosed in the parent applications to this application. Control circuitry is included to convert electrical power into power usable by the LEDs. | 2012-09-06 |
| 20120224396 | DC POWER SUPPLY - In a DC power supply in which a DC power source and a transformer are connected via a power conversion circuit and a secondary winding of the transformer is connected to a load via a rectifier diode bridge and a filter circuit to supply power to the load, a resonance reactor is provided on an output side of the transformer, a resonant switch circuit including a parallel circuit of a diode and a semiconductor switch and a resonant capacitor is connected in parallel to the rectifier diode bridge and a snubber circuit including a snubber capacitor, a snubber diode and a diode for discharge is connected to a serial resonant circuit including the resonance reactor and the resonant capacitor in the resonant switch circuit to absorb a surge voltage. | 2012-09-06 |
| 20120224397 | DEVICES AND METHODS OF CONSTANT OUTPUT CURRENT AND VOLTAGE CONTROL FOR POWER SUPPLIES - Power controllers, control methods and related integrated circuits for power supplies are disclosed. A power supply has a power switch and an inductive device. An exemplifying power controller comprises a first current source, a discharge time sensor, a representative current generator, and a pulse width modulator. The first current source generates a target current pouring to a compensation node. The discharge time sensor determines a discharge time of the inductive device. The representative current generator generates a representative current representing an inductor current of the inductive device. The pulse width modulator determines an output power of the power supply according to the compensation voltage at the compensation node. The representative current drains from the compensation node during the discharge time. | 2012-09-06 |
| 20120224398 | Charge-transfer conditioning circuit - A conditioning circuit for the transfer of electric charge, which includes a converter module including an energy-storage element applied to which is an input voltage (Vi) and a respective field-effect-transistor switch controlled by a respective driving signal (Vpa, Vpb) for selectively enabling transfer of charge from the energy-storage element to an energy-storage circuit. The field-effect-transistor switch includes a corresponding field-effect transistor and a biasing circuit for biasing a substrate of the transistor, the biasing circuit being connected between the substrate and a reference node at a potential suitable for enabling operation of the transistor in the linear region or in the region of saturation, the biasing circuit being configured for providing a limiting resistance in regard to the current that flows from the reference node in the transistor when it operates in the inhibition region. | 2012-09-06 |
| 20120224399 | METHOD AND APPARATUS TO REDUCE AUDIO FREQUENCIES IN A SWITCHING POWER SUPPLY - An example controller for use in a power supply regulator includes a switch signal generator, a modulation circuit, and a multi-cycle modulator circuit. The modulation circuit modulates the period of a modulation switching signal when an equivalent switching frequency is greater than a reference frequency and fixes the switching period when the equivalent switching frequency is less than the reference frequency. The multi-cycle modulator circuit enables the switch signal generator to provide a switch signal uninterrupted if the equivalent switching frequency is greater than the reference frequency and disables the switch signal generator for a first time period and then enables the switch signal generator for a second time period when the equivalent frequency is less than the reference frequency. The multi-cycle modulator circuit varies the first time period to regulate the output. | 2012-09-06 |
| 20120224400 | ELECTRICAL EQUIPMENT - A television includes a power supply circuit including a transformer that converts input voltage to output voltage, an input voltage monitoring circuit that monitors the input voltage based on a voltage value of a primary side or a secondary side of the transformer, and a control unit that determines whether or not the input voltage exceeds a specified value based on monitoring results of the input voltage monitoring circuit and provides a warning or notification that the input voltage is excessive when it is determined that the input voltage exceeds the specified value. | 2012-09-06 |
| 20120224401 | Variable Input Voltage PFC Circuits, Systems and Power Supplies With Phase Shifted Power Rails - A method of generating an output voltage from a variable input voltage with a power factor correction (PFC) system is disclosed. The PFC system includes a first power rail and a second power rail connected in parallel between an input for receiving the input voltage and an output for outputting the output voltage. The method includes operating one or both of the first power rail and the second power rail to generate the output based, at least in part, on whether the input voltage exceeds a threshold voltage. Power supplies and PFC systems suitable for performing the method are also disclosed. | 2012-09-06 |
| 20120224402 | POWER SEMICONDUCTOR MODULE AND POWER SEMICONDUCTOR CIRCUIT CONFIGURATION - A power semiconductor module having a substrate, at least two power semiconductor switches being situated on the substrate and connected in parallel, at least one intermediate circuit terminal for connecting the power semiconductor switches to a first supply voltage potential and at least two intermediate circuit terminals for connecting the power semiconductor switches to a second supply voltage potential, one of the supply voltage potentials being negative and the other being positive. | 2012-09-06 |
| 20120224403 | METHOD FOR CONTROLLING THREE-PHASE CURRENT CONVERTER - A method is for controlling a three-phase current converter. First, subtract a second reference current signal representing the predicted current of the three-phase terminals in the present switching cycle from a first reference current signal representing the predicted current of the three-phase terminals in the next switching cycle to obtain a predicted variation. Then, subtract a feedback current signal representing the feedback current of the three-phase terminals in the previous switching cycle from the second reference current signal delayed by one switching cycle to obtain a current error. Multiply the current error by an error coefficient then add the predicted variation to obtain a current variation. Finally, obtain duty ratios of a plurality of switches, according to the current variation and inductance of the first to the third inductor. The three-phase current converter converts electric power between a DC terminal and the three-phase terminals, according to the duty ratio. | 2012-09-06 |
| 20120224404 | ENHANCED PROGRAMMING AND ERASURE SCHEMES FOR ANALOG MEMORY CELLS - A method for data storage includes setting a group of analog memory cells to respective analog values by performing an iterative process that applies a sequence of pulses to the memory cells in the group. During the iterative process, a progress of the iterative process is assessed, and a parameter of the iterative process is modified responsively to the assessed progress. The iterative process is continued in accordance with the modified parameter. | 2012-09-06 |
| 20120224405 | SEMICONDUCTOR DEVICE - A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. | 2012-09-06 |
| 20120224406 | Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. | 2012-09-06 |
| 20120224407 | INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR - Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges. | 2012-09-06 |
| 20120224408 | THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE - A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed. | 2012-09-06 |
| 20120224409 | THREE DIMENSIONAL MEMORY SYSTEM WITH PAGE OF DATA ACROSS WORD LINES - A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit. | 2012-09-06 |
| 20120224410 | THREE DIMENSIONAL MEMORY SYSTEM WITH INTELLIGENT SELECT CIRCUIT - A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit. | 2012-09-06 |
| 20120224411 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND FORMING METHOD - According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing. | 2012-09-06 |
| 20120224412 | SEMICONDUCTOR STORAGE DEVICE AND TEST METHOD THEREOF - A memory includes memory cells each storing data according to a change in a resistance state, and reference cells referred to in order to detect data stored in the memory cells. Sense amplifiers compare reference data in the reference cells with data in the memory cells to detect the data in the memory cells. A counter counts a number N | 2012-09-06 |
| 20120224413 | Non-Volatile Storage System Using Opposite Polarity Programming Signals For MIM Memory Cell - A reversible resistance-switching metal-insulator-metal (MIM) stack is provided which can be set to a low resistance state with a first polarity signal and reset to a higher resistance state with a second polarity signal. The first polarity signal is opposite in polarity than the second polarity signal. In one approach, the MIM stack includes a carbon-based reversible resistivity switching material such as a carbon nanotube material. The MIM stack can further include one or more additional reversible resistivity switching materials such as metal oxide above and/or below the carbon-based reversible resistivity switching material. In another approach, a metal oxide layer is between separate layers of carbon-based reversible resistivity switching material. | 2012-09-06 |
| 20120224414 | Solid-State Memory Cell with Improved Read Stability - A solid-state memory in which stability assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an isolation gate connected between one of the storage nodes and the input of the opposite inverter. The isolation gate may be realized by complementary | 2012-09-06 |
| 20120224415 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter. | 2012-09-06 |
| 20120224416 | MAGNETIC MEMORY AND MAGNETIC MEMORY APPARATUS - A magnetic memory includes a first magnetic layer, a second magnetic layer, a third magnetic layer, a first intermediate layer, a second intermediate layer, an insulator film, and an electrode. The third magnetic layer is provided between the first magnetic layer and the second magnetic layer in a first direction being perpendicular to the plane of both the first magnetic layer and the second magnetic layer. The insulator film is provided on the third magnetic layer in a second direction perpendicular to the first direction. The electrode is provided on the insulator film so that the insulator is sandwiched between the third magnetic layer and the electrode in the second direction. In addition, a positive voltage is applied to the electrode and a first current passes from the first magnetic layer to the second magnetic layer, thereby writing information to the second magnetic layer. | 2012-09-06 |
| 20120224417 | DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT - A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching. | 2012-09-06 |
| 20120224418 | MULTI-BIT MEMORY WITH SELECTABLE MAGNETIC LAYER - An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed. | 2012-09-06 |
| 20120224419 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment includes wells in a semiconductor substrate, fins formed on the wells, gate electrodes provided on one side and another opposite side of each fin via a gate insulating film to form a channel region in the fin, impurity-diffused layers that each form a potential barrier that confines holes in a body region within the channel region, and source/drain layers each formed at the fin such that the channel region is sandwiched between the source layer and the drain layer. At the time of writing of data ‘1’, a gate voltage is set to a negative potential, a well bias voltage is set to a positive potential, and a drain voltage is set to a positive potential. | 2012-09-06 |
| 20120224420 | SEMICONDUCTOR MEMORY DEVICE AND DECODING METHOD - A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio. | 2012-09-06 |
| 20120224421 | SYSTEM AND METHOD OF DECODING DATA FROM MEMORY BASED ON SENSING INFORMATION AND DECODED DATA OF NEIGHBORING STORAGE ELEMENTS - Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the decoding of the first group of storage elements. | 2012-09-06 |
| 20120224422 | Nonvolatile Semiconductor Memory Device - A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area. | 2012-09-06 |
| 20120224423 | PROGRAMMING AND ERASURE SCHEMES FOR ANALOG MEMORY CELLS - A method for data storage, in a memory that includes multiple analog memory cells, includes setting a parameter of an iterative process applied to a group of the memory cells based on one or more data values stored in at least one of the memory cells in the memory. The iterative process is performed in the group of the memory cells in accordance with the set parameter. | 2012-09-06 |
| 20120224424 | NONVOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME, AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a first drain selection transistor with the same structure as the memory transistors and a second drain selection transistor with the same structure as the source selection transistor. The nonvolatile memory device further includes an even drain selection line connected to the first drain selection transistors of the even strings and the second drain selection transistors of the odd strings and an odd drain selection line connected to the second drain selection transistors of the even strings and the first drain selection transistors of the odd strings. | 2012-09-06 |
| 20120224425 | Using Temperature Sensors with a Memory Device - In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data. | 2012-09-06 |
| 20120224426 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected one of the plurality of vertical strings, selecting a sensing manner corresponding to the judged channel length, and performing a sensing operation according to the selected sensing manner. The plurality of vertical strings may extend in a direction perpendicular to a substrate of the nonvolatile memory device. | 2012-09-06 |
| 20120224427 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a block dividing unit groups l word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying unit has an erasing verifying operation performed on memory cells subjected to the erasing operation, on a divisional block basis. | 2012-09-06 |
| 20120224428 | CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE - A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage. | 2012-09-06 |
| 20120224429 | METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES - Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS | 2012-09-06 |
| 20120224430 | READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device. | 2012-09-06 |
| 20120224431 | PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY - For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programmed during the prior programming operation. | 2012-09-06 |
| 20120224432 | OVER-ERASE VERIFICATION AND REPAIR METHODS FOR FLASH MEMORY - Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually. | 2012-09-06 |
| 20120224433 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A semiconductor device includes a differential circuit and a power supply circuit that provides a power supply to the differential circuit. Current to be supplied to the differential circuit by the power supply circuit is controlled, based on logics of a burn-in mode signal and an activation control signal for the differential circuit. | 2012-09-06 |
| 20120224434 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 2012-09-06 |
| 20120224435 | MULTIPLE-PORT MEMORY DEVICE COMPRISING SINGLE-PORT MEMORY DEVICE WITH SUPPORTING CONTROL CIRCUITRY - A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device. In an illustrative embodiment, the single-port memory device operates at a clock rate that is an integer multiple of a clock rate of first and second memory drivers that supply the input signals to and receive the output signals from the respective first and second ports of the multiple-port memory device. | 2012-09-06 |
| 20120224436 | Setting a Reference Voltage in a Memory Controller Trained to a Memory Device - Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison. | 2012-09-06 |
| 20120224437 | NON-VOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT WITH AN IMPROVED WRITE PERFORMANCE - A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage. | 2012-09-06 |
| 20120224438 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a fin formed on a semiconductor substrate, a gate electrode provided on both sides of the fin via a gate dielectric film, a depletion layer that forms a potential barrier, which confines a hole in a body region between channel regions of the fin, in the fin, and a source/drain layer formed in the fin to sandwich the gate electrode are included. | 2012-09-06 |
| 20120224439 | MASK-WRITE APPARATUS FOR A SRAM CELL - Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation. | 2012-09-06 |
| 20120224440 | MEMORY DEVICE AND METHOD OF WRITING DATA TO A MEMORY DEVICE - In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline. | 2012-09-06 |
| 20120224441 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a plurality of column selection signals based on a page size control signal; a first page block configured to enable a plurality of first memory cells selected by the plurality of row selection signals in response to the first block enable signal, and activate data access of memory cells selected among the plurality of selected first memory cells by the plurality of column selection signals and the option column selection signal; and a second page block configured to enable a plurality of second memory cells selected by the plurality of row selection signals in response to the second block enable signal, and activate data access of memory cells selected among the plurality of selected second memory cells by the plurality of column selection signals and the option column selection signal. | 2012-09-06 |
| 20120224442 | CIRCUIT WITH REMOTE AMPLIFIER - A circuit comprises a first driver, a second driver, and a remote sense amplifier. The first driver is configured to generate a first data signal on a first data line. The second driver is configured to generate a control signal on a control signal line. An RC delay of the control signal line is less than an RC delay of the first data line. The remote sense amplifier is configured to receive the first data signal, a second data signal on a second data line, and the control signal. The control signal line is configured for the control signal to enable the remote sense amplifier to amplify the voltage difference between the first data signal and the second data signal at inputs of the remote sense amplifier, if the voltage difference reaches a predetermined value. | 2012-09-06 |
| 20120224443 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit. | 2012-09-06 |
| 20120224444 | METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device. | 2012-09-06 |
| 20120224445 | Apparatus and method to measure energy capacity of a backup power supply without compromising power delivery - A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements. | 2012-09-06 |
| 20120224446 | Capacitor Charge Balance System - “A circuit includes a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage receives charge current via a common charging terminal. A controller is configured to separately measure a stored potential of each capacitor stage in the series arrangement. The circuit includes logic to selectively remove a controlled amount of charge from each capacitor stage individually (discharge logic), and logic to operate the discharge logic to maintain each capacitor stage in the series arrangement at a substantially equal stored potential (balancing logic).” | 2012-09-06 |
| 20120224447 | SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR SELECTIVELY ACTIVATING CIRCUIT AREAS - A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command. | 2012-09-06 |
| 20120224448 | DELAY EFFICIENT GATER REPEATER - A gater repeater circuit is disclosed. In one embodiment, the circuit includes an activation circuit coupled to receive an input signal and a clock signal and configured to activate an output circuit. The output circuit is configured to drive an output signal. The output circuit includes first and second devices configured to drive the output signal to first and second states, respectively. A feedback circuit is configured to provide a delayed version of the output signal. A deactivation circuit is coupled to receive the clock signal and the delayed version of the output signal, and is configured to, when the clock signal is in the first state, cause the deactivation of an active one of the first and second devices. When the clock is in the second state, the circuit is configured to cause the second device to drive the output signal to the second state. | 2012-09-06 |
| 20120224449 | BARREL MIXER ANGLE ADJUSTER - Typical barrel mixers ( | 2012-09-06 |
| 20120224450 | BIOCONTAINER - A biocontainer. The biocontainer includes a first flexible wall, a second flexible wall opposite the first flexible wall, a first end, a second end opposite the first end, a third end extending between the first and second ends, a fourth end extending between the first and second ends and opposite the third end, and a first relief section extending from the first end. | 2012-09-06 |
| 20120224451 | VENTURI APPARATUS - A Venturi apparatus includes: a body defining a receptacle chamber configured to receive a first fluid, a transition passageway in fluid communication with the receptacle chamber and configured to receive the first fluid from the receptacle chamber, a mixing chamber in fluid communication with the transition passageway and configured to receive the first fluid from the transition passageway, and a sidearm passageway in fluid communication with the mixing chamber and extending to an outer surface of the body and configured to allow a second fluid to pass from an exterior of the into the mixing chamber; and a fluid flow regulator connected to the body, configured to affect a flow of the first fluid from the receptacle chamber into the mixing chamber, and including a valve mechanism configured to selectively engage the body to inhibit flow of the first fluid from the receptacle chamber into the mixing chamber. | 2012-09-06 |
| 20120224452 | VERTEBROPLASTY CEMENT MIXER INJECTOR DEVICE - A system and apparatus for mixing and dispensing a composition, such as a vertebroplasty composition, is disclosed. | 2012-09-06 |
| 20120224453 | METHOD AND DEVICE FOR ALTERNATING DEPTHS MARINE SEISMIC ACQUISITION - System and method for enriching a bandwidth of seismic data related to a subsurface of a body of water. The system includes streamers and sources that are towed at alternating depths during consecutive and/or adjacent line of sails or during the same line of sail. | 2012-09-06 |
| 20120224454 | METHOD AND DEVICE TO ACQUIRE MARINE SEISMIC DATA - The invention concerns a method to acquire seismic waves by means of a streamer towed by a vessel and comprising a plurality of seismic receivers. The streamer comprises a head portion that is slanted relative to the water surface and a tail portion having at least one section with a different slant. | 2012-09-06 |
| 20120224455 | RESONANCE METHOD FOR MEASURING THE ELECTROACOUSTIC CONSTANT AND PERMEABILITY OF ROCK FORMATIONS - Disclosed is a method for estimating a property of an earth formation penetrated by a borehole. The method includes: transmitting acoustic waves into the formation from an acoustic source disposed in the borehole and away from a wall of the borehole; generating radial acoustic eigenwaves within a space between the wall of the borehole and the acoustic source using the transmitted acoustic waves; receiving an acoustic signal with an acoustic receiver disposed at the wall of the borehole; sensing an electric field signal with an electric field sensor disposed at the wall of the borehole; and estimating the property using the received acoustic signal and the sensed electric field signal. | 2012-09-06 |
| 20120224456 | SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR SOURCE LOCALIZATION USING AUDIBLE SOUND AND ULTRASOUND - A method of signal processing includes calculating a range based on information from a reflected ultrasonic signal. Based on the calculated range, one among a plurality of direction-of-arrival (DOA) estimation operations is selected. The method also includes performing the selected operation to calculate an estimated direction of arrival (DOA) of an audio-frequency component of a multichannel signal. Examples of DOA estimation operations include operations based on phase differences between channels of the multichannel signal and operations based on a difference in gain between signals that are based on channels of the multichannel signal. | 2012-09-06 |
| 20120224457 | SERVER FOR GROUPING DEVICES BASED ON SOUNDS COLLECTED AND METHOD THEREFORE - A method of grouping devices which are connected to a server, and a server applying the same, are provided. The method includes receiving sounds collected from the plurality of devices, respectively, detecting devices from among the plurality of devices which are located nearby each other, using information regarding a time slot at which the sounds are collected and the collected sounds, and grouping the detected devices into one group. The server includes a communicating unit which receives collected sounds from the plurality of devices, respectively; and a control unit which controls devices from among the plurality of devices which are detected to be located nearby each other, using information regarding a time slot at which the sounds are collected and the collected sounds, and grouping the detected devices into one group. | 2012-09-06 |
| 20120224458 | Container Cap with a Timer - The invention is a container cap with a timer. The timer has a centralized activation pin or mechanism that activates the timer when the cap is secured to a container. The timer is used to determine how much time has passed since the cap was secured to the container. The timer cap of the present invention is streamlined, easier to use, more reliable, and has a lower manufacturing cost than currently available timer caps. | 2012-09-06 |
| 20120224459 | YAHRZEIT SYSTEM AND METHOD - A method of and system for providing an electronic Yahrzeit display corresponding to the current date including determining a current date, performing a search in a database storing a plurality of Yahrzeit entries to identify the Yahrzeit entries having an anniversary of the death date corresponding to the current date, and electronically displaying the identified Yahrzeit entries in a rotating manner, wherein each of the identified Yahrzeit entries are displayed for a predetermined amount of time, wherein the method and system may convert dates between a plurality of calendars. | 2012-09-06 |
| 20120224460 | PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC DEVICE AND RADIO TIMEPIECE - A piezoelectric vibrator, an oscillator, an electronic device and a ratio timepiece are provided which are capable of increasing a capacitance C0 while achieving miniaturization and cost reduction. The piezoelectric vibrator includes a base substrate, a lid substrate, a piezoelectric vibrating reed on which an excitation electrode is formed, and external electrodes. An electrode pattern for capacitance adjustment, which extends along a routing electrode, is provided extending from a routing electrode. | 2012-09-06 |
| 20120224461 | ATTACHABLE TIMEPIECE - One embodiment of the present invention provides an attachable timepiece, comprising: an upper chamber forming a housing for timepiece elements, the upper chamber including a front face having a time display; a lower chamber that is detachable from the upper chamber by way of a locking system; and a means for attaching the timepiece to an object. | 2012-09-06 |
| 20120224462 | PICKUP HEAD, INFORMATION RECORDING METHOD AND REPRODUCING METHOD - According to one embodiment, a pickup head includes a plurality of light sources, a first objective lens, second objective lens, a driving unit, a first control unit, a second control unit, light receiving units. The first objective lens focuses a first light beam at a first recording layer. The second objective lens focuses a second light beam at a second recording layer. The driving unit moves the first objective lens and the second objective lens in a first direction and a second direction. The first control unit corrects displacement from target track along the first direction. The second control unit controls a moving direction of a position of the second light spot in the second direction. | 2012-09-06 |
| 20120224463 | AUTOMATION DISK FEEDING DEVICE - The present invention relates to an improved automation disk feeding device, comprising: a base, a pushing member, two disk feeding members, and a cover, wherein the base has a operation space, a supporting member and a disk exporting hole. In the present invention, a driving device is used to drive the pushing member to slide forward and backward on the operation space, such that a disk stored in a disk storing district of the cover is able to be exported via the disk exporting hole; Moreover, the disk feeding members are not formed integrally with the base but capable of being assembling to and disassembling from the base, so that, the applications of the improved automation disk feeding device can be increased by way of changing the disk feeding members with different shaped slide ways. | 2012-09-06 |
| 20120224464 | SERVO CONTROLLER AND SERVO SYSTEM INCLUDING THE SAME - A servo controller in a system includes a kick/brake control unit and a compensation unit. The kick/brake control unit determines an internal parameter based on an external control signal and an operation state of a plant. The compensation unit generates a driving control signal based on an error signal supplied from the plant and the internal parameter, and supplies the driving control signal to the plant. The plant performs a steady-state operation during a first operation mode and a target moving operation during a second operation mode based on the driving control signal. | 2012-09-06 |
| 20120224465 | RECORDING REPRODUCING APPARATUS AND RECORDING REPRODUCING METHOD - If a recording error has occurred during RAW, then subsequent recording reproducing processing is omitted in a predetermined range, and all blocks omitted in the processing are handled as defective blocks, DFL-registered, and recorded in a replacement area. As a result, it becomes possible to hold down the number of times of recording processing accompanied by seek processing in the RAW processing, and transfer rate lowering can be solved. | 2012-09-06 |
| 20120224466 | Semiconductor Device, Write Strategy Generating Method, and Write Strategy Generating Program - A semiconductor device mounted in an optical disk apparatus controls writing and reading of data in and from an optical disk. The device performs first processing for adjusting a write strategy in such a manner that based on error information corresponding to a shift in the phase of a reproduction signal with respect to a channel clock signal for data reproduction, which is generated based on the reproduction signal read from the optical disk, the value of the error information related to a plurality of recording marks to be evaluated becomes minimum as a whole. The device also performs second processing for adjusting a write strategy in such a manner that the value of the error information related to a desired recording mark becomes small. | 2012-09-06 |
| 20120224467 | Recording Parameter Setting Device, Program Thereof, Computer-Readable Recording Medium Containing the Program, Information Recording Medium, Recording/Reproducing Device, and Recording Parameter Setting Method - Recording mark forming method utilizing a device including a laser and a laser drive carried by a pickup having a movement drive wherein a control controls the drives to irradiate a recording medium with laser pulse sequences to form recording marks having recording mark lengths between a predetermined and maximum lengths, a top section, a last section including a cooling period, and an intermediate period. Heat of mark front edges is controlled by top section recording parameters classified according to recording mark lengths and recording parameters of first through maximum recording mark lengths are classified into a same group. Heat of mark rear edges is controlled by cooling start positions for cooling periods classified according to recording mark lengths. Cooling start positions for a second predetermined mark length through the maximum mark length are classified into a same group. The second mark length is longer than the first mark length. | 2012-09-06 |
| 20120224468 | METHOD AND APPARATUS FOR PERSISTENT CONNECTIONS TO A DEVICE THROUGH THE USE OF MULTIPLE PHYSICAL NETWORK CONNECTIONS AND CONNECTION HAND-OFFS BETWEEN MULTIPLE BANDS, MODES AND NETWORKS - Embodiments communicate messages between mobile devices and destination devices. An exemplary embodiment includes a first border server operable to establish a first communication connection to the mobile device over a first network operating under a first protocol, a second border server operable to establish a second communication connection to the mobile device over a second network operating under a second protocol, and a transport management server communicatively coupled to the first border server and the second border server, and operable to establish a third communication connection to the destination device over a third network operating under a third protocol. The first protocol is configured to communicate a first encapsulated portion of the message. The second protocol is configured to communicate a second encapsulated portion of the message. The third protocol is configured to communicate the first encapsulated portion of the message and the second encapsulated portion of the message. | 2012-09-06 |
| 20120224469 | NETWORK FAULT DETECTION METHOD AND APPARATUS - A method of detecting media plane faults within a communications network. The method comprises, following the establishment of a media plane connection between first and second end point nodes within the network, where the connection transits one or more intermediate nodes within the media plane, sending session test requests from the first end point towards the second end point across a supervision session established over the media plane, and sending session test acknowledgements from the second end point to the first end point, the session test acknowledgements identifying a first border of the supervision session. The method further comprises, in the event of a media plane fault, responding to the sending of a further session test request by returning a further session test acknowledgement identifying a second border of the supervision session. The media plane fault can be detected by comparing the first and second supervision session borders contained in session test acknowledgements. | 2012-09-06 |
| 20120224470 | METHOD AND APPARATUS FOR SETTING RADIO LINK OF TERMINAL IN WHICH MULTIPLE CARRIERS ARE INTEGRATED IN MOBILE COMMUNICATION SYSTEM - The present invention relates to an apparatus and a method, wherein a terminal in which multiple carriers are integrated and sets a radio link by detecting and recovering radio link failure in a mobile communication system. The method comprises the steps of: setting a radio link in one serving cell in multiple carriers; checking a radio state of a primary carrier if failure of the radio link is detected; searching other cells adjacent to the serving cell by driving a timer, if the radio state is not matched with a preset radio condition; stopping the driving of the timer if the radio state is recovered while the timer is driven; and inactivating one of the multiple carriers. | 2012-09-06 |
| 20120224471 | METHOD AND SYSTEM FOR RING PROTECTION SWITCHING - The present invention provides a protection switching method of a node having communication failure in a ring, in a communication network. In one embodiment, this is accomplished by checking for loss of signal (LOS) at the non-ERPS device or at least one of the node in a communication channel, checking periodically for Continuity Check Message (CCM) at both the node, wherein the CCMs are periodically transmitted from both the node through at least one non-ERPS device, appropriately setting a Remote Destination Indication (RDI) bit in the Continuity Check Message (CCM) generated from at least one node and transmits the same via the non-ERPS device or through the non-ERPS device or through a disjoint communication channel, and blocking port of the node towards the non-ERPS device upon receipt of the fault notification and transmitting signal fail notification message on both the ports in the ring. | 2012-09-06 |
| 20120224472 | METHOD FOR RELAYING OF BASE STATION, METHOD FOR RELAYING OF TERMINAL AND METHOD FOR TRANSMITTING - A method of relaying in a base station (BS) includes: setting, when a backhaul link of a first BS is damaged, a relay link using a second BS, which is an adjacent BS of the first BS as a serving BS; and releasing the relay link after the backhaul link is recovered. | 2012-09-06 |
| 20120224473 | HEADER CONVERSION TECHNIQUE - A header conversion device allowing reduced amount of hardware and memory and high-speed line switching is disclosed. In an ATM switching device having redundant incoming line systems, a header conversion table stores a set of header conversion information for one of the redundant incoming line systems. A header converter converts the header of an ATM cell received from each of the redundant incoming line systems by referring the same set of header conversion information. | 2012-09-06 |
| 20120224474 | SYSTEMS AND METHODS FOR DISTRIBUTED DATA ROUTING IN A WIRELESS NETWORK - Various systems and methods described herein relate to distributed data routing over a wireless network. An exemplary method comprises receiving routing data by a routing element of a point to point wireless network, the routing data comprising routing criteria and a plurality of path identifiers which identify a plurality of paths through the wireless network, storing the routing data by the routing element, receiving a packet of data, determining a destination node of the packet of data, the destination node being identified using the routing data as accessible by two or more paths of the plurality of paths, determining, based on the routing criteria of the routing data, at least one path of the plurality of paths to transmit the packet of data to reach the destination node, and transmitting the packet of data to a first node of the determined at least one path of the wireless network. | 2012-09-06 |
| 20120224475 | METHODS AND SYSTEMS FOR AUTOMATICALLY IDENTIFYING A LOGICAL CIRCUIT FAILURE IN A DATA NETWORK - A disclosed example method to identify a failure in a logical circuit involves receiving non-requested trap data from a plurality of switches forming a logical circuit. The logical circuit spans first, second, and third logical networks. The example method also involves polling first and second switches of the logical circuit exclusive of others of the plurality of switches of the logical circuit. The first switch forms a first network-to-network interface between the first logical network and the second logical network. The second switch forms a second network-to-network interface between the second logical network and the third logical network. The first and second switches are selected for polling based on the trap data indicating a problem at the first and second switches. The example method also involves identifying a failure of the logical circuit without manual intervention based on the polling. | 2012-09-06 |
| 20120224476 | Method and Apparatus for Maintaining Traffic Continuity - A method for maintaining traffic continuity through a Traffic Offload Function (TOF) entity includes the following steps: the TOF entity receives a downlink packet of offload traffic of a User Equipment (UE), where the downlink packet of the offload traffic is sent by a Packet Data Network (PDN); the TOF entity sends a Core Network (CN) paging message to the UE; the TOF entity receives a paging response sent by the UE to the CN, where the paging response includes a service request message of the UE; and the TOF entity forwards the service request message to the CN so that the CN sets up a Radio Access Bearer (RAB) after the service request message is received. With the method, the communication between the CN and the UE can be restored to guarantee the transmission of traffic. Accordingly, a TOF entity is also disclosed according to the present invention. | 2012-09-06 |
| 20120224477 | PRUNED FORWARDING SET FOR SCALABLE TUNNELING APPLICATIONS IN DISTRIBUTED USER PLANE - A method and system for reducing congestion and latency in a communication system by creating a pruned forwarding set for scalable tunneling applications. The communication system provides a communication link between a mobile communication device and a network, such as the Internet. The method entails using information included within a data packet to determine a corresponding tunnel peer address, which is then resolved onto a set of paths. Each path includes respective adjacency information. A determination of whether to prune each respective path is made by using the respective adjacency information. The pruned set of paths is used to identify available paths for the communication link. By pruning in this manner, the line card being used as the home slot for a given session may also be used as the egress slot, thereby reducing congestion and latency in the communication system. | 2012-09-06 |
| 20120224478 | HIGH SPEED DATA TRANSMISSION UTILIZING A HIGH FREQUENCY PHYSICAL LAYER FOR A WIRELESS PERSONAL AREA NETWORK DEVICE - Wireless devices may utilize a Bluetooth stack to setup a data transmission session with other devices. The data transmission session may include a Bluetooth physical layer or a medium access control/physical layer that permits wireless devices to perform discovery, pairing, and security setup operations. When a radio interface of a wireless device is insufficient to enable performing a required data communication, such as a high data rate communication, a data transmission session may be established with at least one medium access control/physical layer of a plurality of other medium access control/physical layers to accommodate the required data communication. | 2012-09-06 |
| 20120224479 | METHOD AND ARRANGEMENT FOR TRANSFERRING INFORMATION IN A PACKET RADIO SERVICE - A method and an arrangement for transferring information including delay sensitive data, such as speech and video data, in a packet radio service is provided. Data blocks are transmitted from a mobile station to a radio resource entity during a first active data transfer period using an uplink temporary block flow (TBF) connection. The uplink TBF connection is maintained during a passive period that follows the first active data transfer period, wherein during the passive period the mobile station does not send data blocks to the radio resource entity. | 2012-09-06 |
| 20120224480 | TECHNIQUE FOR THROUGHPUT CONTROL FOR PACKET SWITCHES - A method for selective admission of traffic packets to a telecommunication switch having a limited throughput T and a common input queue, wherein the traffic packets comprise packets pre-assigned to higher and lower classes; in case of congestion at the common input queue of the switch, the method performs selective admission of the packets to the switch according to classes pre-assigned to them and depending on dynamic, recently utilized throughput of the switch. | 2012-09-06 |
| 20120224481 | TRAFFIC MANAGEMENT IN DISTRIBUTED WIRELESS NETWORKS - Wireless networks and devices are ubiquitous today. For service providers to offer customers QoS and Service Level Agreements (SLAs) means in part providing resilient connectivity of wireless devices with good signal strength, good Signal to Noise and Interference Ratio (SNIR), and adequate useable bandwidth. Doing so requires that devices transmitting and receiving packets use over-the-air bandwidth efficiently and manage over-the-air congestion. According to embodiments of the invention QoS measurements and controls are incorporated only in the network (i.e. APs or controllers) and therefore QoS and SLAs can be achieved with all deployed client stations versus standards based approaches that require additional capabilities in network nodes, client stations and in most cases modifications to the applications. SLAs can be provided exploiting embodiments of the invention for traffic prioritization, capacity improvements through load distribution, and adjacent channel interference mitigation discretely or in combination with standards based mechanisms. | 2012-09-06 |
| 20120224482 | CREDIT FEEDBACK SYSTEM FOR PARALLEL DATA FLOW CONTROL - A producer node receives data that is to be transmitted to a consumer node. The producer node receives a credit indication from the consumer node indicating that a portion of credit has been extended to the producer node. The credit portion specifies the amount of data that is to be sent to the consumer node. The producer node sends the amount of data specified in the credit indication to the consumer node. The consumer node receives data that is to be processed. The consumer node returns the portion of credit indicated in the credit indication to a credit pool, where, upon addition to the credit pool, the credit is made available for distribution to the producer node. The consumer node sends a new credit indication to the producer node indicating a specified amount of data that is to be sent to the consumer node to be processed. | 2012-09-06 |
| 20120224483 | TRAFFIC MANAGEMENT IN DISTRIBUTED WIRELESS NETWORKS - Wireless networks and devices are ubiquitous today. For service providers to offer customers QoS and Service Level Agreements (SLAs) means in part providing resilient connectivity of wireless devices with good signal strength, good Signal to Noise and Interference Ratio (SNIR), and adequate useable bandwidth. Doing so requires that devices transmitting and receiving packets use over-the-air bandwidth efficiently and manage over-the-air congestion. According to embodiments of the invention QoS measurements and controls are incorporated only in the network (i.e. APs or controllers) and therefore QoS and SLAs can be achieved with all deployed client stations versus standards based approaches that require additional capabilities in network nodes, client stations and in most cases modifications to the applications. SLAs can be provided exploiting embodiments of the invention for traffic prioritization, capacity improvements through load distribution, and adjacent channel interference mitigation discretely or in combination with standards based mechanisms. | 2012-09-06 |
| 20120224484 | TRAFFIC MANAGEMENT IN DISTRIBUTED WIRELESS NETWORKS - Wireless networks and devices are ubiquitous today. For service providers to offer customers QoS and Service Level Agreements (SLAs) means in part providing resilient connectivity of wireless devices with good signal strength, good Signal to Noise and Interference Ratio (SNIR), and adequate useable bandwidth. Doing so requires that devices transmitting and receiving packets use over-the-air bandwidth efficiently and manage over-the-air congestion. According to embodiments of the invention QoS measurements and controls are incorporated only in the network (i.e. APs or controllers) and therefore QoS and SLAs can be achieved with all deployed client stations versus standards based approaches that require additional capabilities in network nodes, client stations and in most cases modifications to the applications. SLAs can be provided exploiting embodiments of the invention for traffic prioritization, capacity improvements through load distribution, and adjacent channel interference mitigation discretely or in combination with standards based mechanisms. | 2012-09-06 |
| 20120224485 | ARCHITECTURE FOR WLAN OFFLOAD IN A WIRELESS DEVICE - Architecture for performing WLAN offload in a wireless device is disclosed. In an exemplary embodiment, an apparatus includes an application section configured to form IP packets from data to be transmitted, a modem section configured to apply a cellular protocol to the IP packets to form cellular protocol packets, an endpoint configured to encapsulate the cellular protocol packets to form outer IP tunnel packets, and a WLAN interface configured to transmit the outer IP tunnel packets over a WLAN communication channel. In another exemplary embodiment, an apparatus includes a WLAN interface configured to receive outer IP tunnel packets over a WLAN communication channel, an endpoint configured to extract cellular protocol packets from the outer IP tunnel packets, a modem processor configured to remove a cellular protocol from the cellular protocol packets to form IP packets, and an application processor configured to extract received data from the IP packets. | 2012-09-06 |
| 20120224486 | LOAD-BALANCING VIA MODULUS DISTRIBUTION AND TCP FLOW REDIRECTION DUE TO SERVER OVERLOAD - A method, switch, and/or computer program product routes IP packet flows. An Ethernet switch receives an IP packet flow. Each of the packets in the IP packet flow has a header that contains a same 5-tuple. A load balancing control engine determines whether servers in a group of servers are balanced in their utilization according to 5-tuple redirection rules contained in the load balancing control engine. In response to the load balancing control engine determining, according to the 5-tuple redirection rules, that the servers are balanced, the Ethernet switch routes the IP packet flow to the servers. In response to the load balancing control engine determining that the servers are unbalanced, the load balancing control engine instructs the Ethernet switch to redirect the IP packet flow to a server that is relatively less busy than other servers. | 2012-09-06 |
| 20120224487 | System and Method for Accepting Information from Routing Messages Into a List - A system and method adds and manages entries on a list of entries of routing information to allow the top entry to be used for routing to a destination corresponding to the list. Costs of a wireless link may be a function of the success rate experienced on that wireless link. | 2012-09-06 |
| 20120224488 | METHOD OF CONNECTIVITY MONITORING BY SUBSCRIBER LINE TERMINATING APPARATUS - A method carrying out connectivity monitoring of an entire network by: transmitting a CCM frame in which the transmission source is set to a multicast MAC address, from a higher level side (center side) terminating device to a plurality of lower level side (base point side) terminating devices; transmitting a CCM frame in which a unicast MAC address is set, from the lower level side terminating devices to the higher level side terminating device; transmitting a CCM frame in which a multicast MAC address is set, from a controller to the higher level side terminating device or the lower level side terminating devices; and transmitting a CCM frame in which a unicast MAC address is set, from the higher level side terminating device or the lower level side terminating devices to the controller. | 2012-09-06 |
| 20120224489 | System, Apparatus and Method for Making Statistics on Point Protocol Negotiation State in Wireless System - The disclosure discloses a system for making statistics on Point to Point Protocol (PPP) negotiation state in a wireless system, which includes at least one user terminal and a packet data serving node that realizes a communication a connection with the user terminal via the PPP, and the system further includes a base station controller and a call detail information recorder; wherein the base station controller is communicatively connected to the user terminal, and is configured to capture a PPP negotiation packet of the user terminal, analyze a PPP negotiation flow in the PPP negotiation packet and send an analysis result to the call detail information recorder; and the call detail information recorder is communicatively connected to the base station controller, and is configured to make statistics on various state data of a PPP negotiation in the wireless system according to the analysis result. The disclosure further discloses an apparatus and method for making statistics on PPP negotiation state in a wireless system. The disclosure can make statistics on a reason for the PPP negotiation failure caused by a wireless system conveniently, and accurately reflect whether performance of the whole wireless packet data system is good or poor. | 2012-09-06 |
