| 36th week of 2012 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20120223690 | DC-DC CONVERTER CONTROL CIRCUIT AND CONTROL METHOD - A control circuit of a DC-DC converter that has a switching element, including an error amplifier that amplifies a difference between a reference voltage and a feedback voltage corresponding to an output voltage of the DC-DC converter, a voltage reduction comparator that outputs an interrupt signal when the feedback voltage is lower than a voltage reduction threshold that has a value lower than that of the reference voltage, and a pulse-width modulation (PWM) signal generator circuit. The PWM signal generator circuit generates a PWM signal of a predetermined frequency based on the voltage difference when no interrupt signal is generated, or otherwise generates a switch drive signal to activate the switching element for a first period of time corresponding to the difference output by the error amplifier, and to deactivate the switching element for a second period of time after the first period of time has elapsed. | 2012-09-06 |
| 20120223691 | DIGITAL PULSE-FREQUENCY MODULATION CONTROLLER FOR SWITCH-MODE POWER SUPPLIES WITH FREQUENCY TARGETING AND ULTRASONIC MODES - A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and the time of the pulses reaches a minimum threshold. | 2012-09-06 |
| 20120223692 | SENSORLESS SELF-TUNING DIGITAL CURRENT PROGRAMMED MODE (CPM) CONTROLLER WITH MULTIPLE PARAMETER ESTIMATION AND THERMAL STRESS EQUALIZATION - A multiphase controller for a DC-to-DC power supply includes logic to estimate parameters for multiple phases that provide a combined output at a load. The estimated parameters include a current estimate and an effective resistance estimates for each phase so that a power estimate for each phase can be produced. The logic adjusts the operation of the phases using the power estimate for each phase. | 2012-09-06 |
| 20120223693 | METHODS AND APPARATUS FOR DC-DC CONVERSION USING DIGITALLY CONTROLLED ADAPTIVE PULSE FREQUENCY MODULATION - A method and apparatus for regulating voltage comprising calculating a first PFM on time and a second PFM on time and selecting one the PFM on times according to a selection criteria. Then activating and deactivating at least one switch according to the selected PFM on time. | 2012-09-06 |
| 20120223694 | Operating a Semiconductor Component Having a Breakthrough Voltage - Methods and apparatuses are provided for operating a semiconductor component using a DC/DC-converter. The DC/DC-converter has its duty cycle controlled. | 2012-09-06 |
| 20120223695 | ELECTRONIC DEVICE AND METHOD FOR A LIMITER IN AN AC APPLICATION - An electronic device, including a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit. | 2012-09-06 |
| 20120223696 | Systems and Methods for Current Sensing Over an Extended Area - Methods and systems for providing current sensing over an extended area, such as a substrate of an integrated circuit, are described. The described methods and systems particularly describe a circuit layout procedure and configuration that can be used to carry out current sensing at diverse locations in the extended area. | 2012-09-06 |
| 20120223697 | SENSOR FOR MEASURING ELECTRICAL CHARACTERISTICS - Provided is a sensor for measuring electrical characteristics. The sensor includes a printed circuit board defining a round through-hole into which a power transmission line is inserted; a voltage sensor including a ring-shaped electrode and a first terminal portion to measure a voltage formed in the power transmission line, the electrode being fixed against the inner periphery of the through-hole to measure a voltage formed in the power transmission line, and the first terminal portion having one end in contact with one side of the electrode and the other end exposed through one side of the printed circuit board; and a current sensor including a pickup coil and a second terminal portion to measure current flowing in the transmission line. | 2012-09-06 |
| 20120223698 | FAN SPEED TESTING SYSTEM - A fan speed testing system for testing the rotational speed of a first fan, includes a switch module, a comparison module and a load module. The switch module outputs control signals. The comparison module receives the control signals and provides a first voltage according to the control signals. The load module receives the first voltage and outputs a second voltage to the first fan. The load module feeds the second voltage received by the first fan back to the comparison module. The comparison module adjusts the first voltage to the load module according to the second voltage received from the load module. | 2012-09-06 |
| 20120223699 | 360-DEGREE ANGLE SENSOR - This disclosure is directed to techniques for magnetic field angular position sensing. A device designed in accordance with this disclosure may include a magnetoresistive sensor configured to generate a signal indicative of an angular position of a magnetic field, the signal having an angular range of 180 degrees, a first polarity sensor configured to generate a signal indicative of a polarity of the magnetic field sensed from a first location, and a second polarity sensor configured to generate a signal indicative of a polarity of the magnetic field sensed from a second location different from the first location. | 2012-09-06 |
| 20120223700 | STEERING POSITION AND TORQUE SENSOR - A sensor circuit for use with a shaft assembly rotatably mounted in a housing and having an input shaft, an output shaft and a torsion bar which connects the input and output shafts together. A CR coil mounted to the housing around the shaft assembly is energized and generates an electromagnetic field. An RX coil is mounted to and rotates with the shaft assembly and has an output connected to a power circuit to generate electrical energy when excited by the electromagnetic field from the first coil. The power circuit powers an angle sensor which transmits a signal back to the first coil representative of the angle between the input and output shafts. | 2012-09-06 |
| 20120223701 | LINEAR POSITION SENSOR - A device for measuring the position of a target includes a track, which includes a primary winding ( | 2012-09-06 |
| 20120223702 | SPRING LOADED GEAR DRIVEN RESOLVER - A resolver apparatus can include a resolver driven gear, a resolver stator, a resolver rotor coupled to the resolver stator and a resolver rotor drive shaft coupled to the resolver rotor, wherein the resolver rotor drive shaft is spring loaded to the resolver driven gear. | 2012-09-06 |
| 20120223703 | SENSOR ARRANGEMENT - A sensor arrangement ( | 2012-09-06 |
| 20120223704 | MAGNETIC SENSOR - A magnetic sensor includes a magneto-electric transducer, a switch circuit, an amplifier circuit, a subtractor circuit, and a selector circuit. The subtractor circuit performs a first subtraction process of generating a first subtraction voltage by subtracting an amplification voltage obtained under an immediately prior first bias state from an amplification voltage obtained under a second bias state and a second subtraction process of generating a second subtraction voltage by subtracting an amplification voltage obtained under an immediately prior second bias state from an amplification voltage obtained under a first bias state in a serial and parallel manner. The selector circuit alternately selects the first subtraction voltage and the second subtraction voltage to output a select voltage. | 2012-09-06 |
| 20120223705 | MAGNETIC RESONANCE SYSTEM WITH IMPLANTABLE COMPONENTS AND METHODS OF USE THEREOF - Nuclear magnetic resonance systems and methods of use thereof are provided. The systems employ implantable radiofrequency coils ( | 2012-09-06 |
| 20120223706 | Method and apparatus for generating an effective equivalent of simultaneous transmission to a targeted tissue using a conventional transceiver array - The present invention is a method and apparatus for generating an effective equivalent of a simultaneous transmission of excitation signals to a targeted living tissue using an existing MRI system assembly or transceiver apparatus which structurally has a small number of independent transmit channels in operative communication with a large number of individual transmission RF coils. The inventive methodology and apparatus is suitable for use with any conventionally known and used transceiver apparatus which operationally complies with the requisite difference existing between the lesser available numbers of independent transmission channels and the greater number of individual transmit RF coils. For this reason, the methodology is broadly and generally useful for many different applications of magnetic resonance imaging technology. | 2012-09-06 |
| 20120223707 | Method and device for establishing excitation parameters for MR imaging - A method and a device for establishing excitation parameters, in particular for establishing an excitation profile, for MR imaging, are proposed. Elements of a k-space covariance matrix are determined for signal noise in k-space data which is captured using a plurality of receive channels in the context of data captured at an examination object. Elements of at least one image space covariance matrix are mathematically determined for a plurality of voxels of the examination object as a function of the k-space covariance matrix. The excitation parameters are established as a function of the determined elements of the at least one image space covariance matrix. | 2012-09-06 |
| 20120223708 | IMPLANTABLE OR INSERTABLE NUCLEAR MAGNETIC RESONANT IMAGING SYSTEM - Nuclear Magnetic Resonant Imaging (also called Magnetic Resonant Imaging or “MRI”) devices which are implantable, internal or insertable are provided. The disclosure describes ways to miniaturize, simplify, calibrate, cool, and increase the utility of MRI systems for structural investigative purposes, and for biological investigation and potential treatment. It teaches use of target objects of fixed size, shape and position for calibration and comparison to obtain accurate images. It further teaches cooling of objects under test by electrically conductive leads or electrically isolated leads; varying the magnetic field of the probe to move chemicals or ferrous metallic objects within the subject. The invention also teaches comparison of objects using review of the frequency components of a received signal rather than by a pictorial representation. | 2012-09-06 |
| 20120223709 | SIMULTANEOUS TX-RX FOR MRI SYSTEMS AND OTHER ANTENNA DEVICES - Apparatus and method that are more efficient and flexible, and obtain and connect high-power RF transmit signals (TX) to RF-coil devices in an MR machine or other devices and simultaneously receive signals (RX) and separate net receive signals NRX) of interest by subtracting or filtering to remove the subtractable portion of the transmit signal (STX) from the RX and preamplifying the NRX and signal processing the preamplified NRX. In some embodiments, signal processing further removes artifacts of the transmitted signal, e.g., by digitizing the NRX signal, storing the digitized NRX signal in a memory, and performing digital signal processing. In some embodiments, the present invention also includes pre-distorting the TX signals in order to be better able to identify and/or remove the remaining artifacts of the transmitted signal from the NRX signal. This solution also applies to other high-power RF-transmit-antennae signals. | 2012-09-06 |
| 20120223710 | Method of generating 2D or 3D maps of MRI T1 and T2 relaxation times - A method of generating 2D or 3D maps of MRI T | 2012-09-06 |
| 20120223711 | APPARATUS AND METHOD FOR DECREASING BIO-EFFECTS OF MAGNETIC GRADIENT FIELD GRADIENTS - An apparatus and a method for increasing the magnitude of the magnetic gradient for MRI without causing nerve stimulation. As an example, the short ramp time of magnetic gradients, for example less than 150 microseconds is contemplated. These short ramp-time magnetic gradients are used for the imaging of structures with short relaxations times, such as teeth, without causing nerve stimulation. The apparatus comprises a generator of magnetic gradients of at least 1 milliTeslas in magnitude with at least one gradient ramp time shorter than 150 microseconds and which induces no peripheral nerve stimulation. | 2012-09-06 |
| 20120223712 | APPARATUS AND METHOD FOR MAGNETIC RESONANCE MEASUREMENT AND MAPPING OF ELECTRICAL IMPEDANCE, COMPLEX PERMITTIVITY AND COMPLEX CONDUCTIVITY AS APPLIED TO DETECTION AND EVALUATION OF SAMPLE PATHOLOGY - A method of measurement of or mapping the distribution of complex permittivity, complex conductivity, complex impedance, or electric loss angle during magnetic resonance imaging or analysis. The method includes applying a time-varying electric field of a Faraday shield to a sample and cross-correlating the line spectrum signal so produced with the voltage applied to the Faraday shield in a detection circuit. The method permits non-contrast magnetic resonance screening for breast cancer in vivo and/or continuous measurement of electrical characteristics of materials at variable frequencies in vitro. A system of detecting and evaluating sample pathology includes a Faraday shield device that includes parallel electrodes oriented orthogonal to the static magnetic field of a MRI device to produce a time varying electric field. A detector is coupled to the MRI device to detect at least one of a complex permittivity, a complex conductivity, and an electrical impedance of the sample. | 2012-09-06 |
| 20120223713 | METHOD AND MAGNETIC RESONANCE SYSTEM TO AUTOMATICALLY DETERMINE PARAMETERS OF A FLOW MEASUREMENT - In a method and a magnetic resonance system to automatically determine parameters of a phase contrast flow measurement, a phase contrast pre-measurement with a flow coding sequence is implemented in a predetermined volume segment of an examination subject, and the flow coding sequence is varied in terms of its parameters so that a pre-measurement is respectively implemented for multiple different parameter sets of the flow coding sequence. A model is automatically determined with which a dimension of a phase error can be determined for each parameter set in the flow measurement, in that phase values of the pre-measurement which is implemented with the flow coding sequence with the respective parameter set are analyzed. Those parameters of the flow measurement at which the dimension of the phase error is smallest are automatically determined. | 2012-09-06 |
| 20120223714 | LOCAL COIL - The present embodiments relate to a local coil for a magnetic resonance tomography system. The local coil includes a preamplifier for amplification of a signal received by the local coil from an examination object in a receive phase of the local coil. The local coil also includes a detuning device for detuning the local coil in a transmit phase of the local coil, and a rectification device for supplying voltage to the preamplifier. | 2012-09-06 |
| 20120223715 | PET-MRI CONVERGENCE SYSTEM - A positron emission tomography (PET)-magnetic resonance imaging (MRI) convergence system. In one aspect, the invention may be a PET-MRI convergence system including: a cylindrical magnet bore which includes an outer wall and an inner wall; a gradient magnet which is disposed adjacent to the inner wall of the magnet bore; a MRI RF coil which is disposed adjacent to the inner wall of the gradient magnet, emits an RF pulse signal and detects MRI data corresponding to the RF pulse signal; and a PET detector which is spaced apart from the MRI RF coil and is disposed adjacent to the inner wall of the gradient magnet, and detects PET data. | 2012-09-06 |
| 20120223716 | SAMPLE HOLDER FOR ELECTRICITY-DETECTION ELECTRON SPIN RESONANCE DEVICE - A sample holder structure is provided with which it is possible to reduce current noise derived from electromagnetic induction, etc. in electricity-detection electron spin resonance spectroscopy. Also provided is a process for producing the structure. The material of the sample holder, which is used in an electricity-detection electron spin resonance device, is an FR-4 resin, alumina, glass, or Teflon. The sample holder has four wiring leads formed on the surface thereof. The four wiring leads each has a three-layer structure composed of a nickel layer, a gold layer, and a resist layer which have been arranged in the order from the sample holder surface, and the sample holder has the shape of the letter T. The sample holder has, formed in the end thereof, a gold pad for affixing a sample, and the gold pad has a multilayer structure composed of a nickel layer and a gold layer arranged in this order from the sample holder surface. In the T-shaped head part of the sample holder, the four wiring leads are spaced wider from each other. | 2012-09-06 |
| 20120223717 | METHOD AND APPARATUS FOR MEASURING THE ELECTRICAL IMPEDANCE PROPERTIES OF GEOLOGICAL FORMATIONS USING MULTIPLE SIMULTANEOUS CURRENT SOURCES - A system for measuring geological data is disclosed. The system includes several transceivers distributed over a geographical area. Each of the transceivers has at least one transmitter and at least one receiver. The transceivers are in communication with each other. The receivers are adapted to measure at least one electrical signal. The transmitters are adapted to inject an electrical current into a subsurface area. The transmitters operate simultaneously to inject the electrical current into the subsurface area simultaneously from a number of locations | 2012-09-06 |
| 20120223718 | High voltage DC power for electromagnetic survey source - A marine electromagnetic survey system includes a power cable configured to couple to a power supply at one axial end, and to a head unit at the other end. The power supply includes a source of direct current which is coupled to the power cable. The head unit includes equipment configured to output a lower voltage at a higher current than the source of direct current. At least one electromagnetic antenna is coupled to the head unit and is configured to receive the output of the head unit equipment. | 2012-09-06 |
| 20120223719 | FAULT DETECTION DEVICE, ELECTRICAL INSTRUMENT AND FAULT DETECTION METHOD - A fault detection device includes an interface electrically connected to an electrical instrument to transfer commercial power to the electrical instrument, transmit a command for driving one of a plurality of loads included in the electrical instrument to the electrical instrument, and detect current flowing in one of the plurality of loads of the electrical instrument; and a terminal configured to receive a current signal corresponding to the current flowing in one of the plurality of loads from the interface, determine whether the one load has a fault on the basis of the received current signal and display whether the load has a fault. A faulty load is determined by detecting current of only a load suspected to have a fault when a fault is generated in the electrical instrument so as to improve fault detection accuracy. | 2012-09-06 |
| 20120223720 | Method And System For Detecting And Locating By Reflectometry Electrical Faults In Metal Structures - The invention aims to provide for detecting and locating by reflectometry electrical faults in a network of metal structures able to receive electrical cables and perform the return-current function of these cables. The invention consists in injecting a probe signal into a conductor, associated with the structures, then in analyzing the reflected signal by comparison with a reference signal. | 2012-09-06 |
| 20120223721 | System and Method for Bonded Configuration Pad Continuity Check - A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected. | 2012-09-06 |
| 20120223722 | Voltage Measurement Device and Voltage Measurement System - A voltage measurement device, includes: a multiplexer that includes a plurality of input terminals at which voltage signals are inputted; a control circuit that performs voltage measurement by acquiring the voltage signal at a selected input terminal from the multiplexer; and a decision circuit that makes a decision as to whether or not an abnormality has occurred, based upon voltage values measured by the control circuit, wherein: the plurality of input terminals include input terminals at which voltage signals from a plurality of subjects of measurement are inputted, and an input terminal at which a potential for diagnosis is inputted; the control circuit, when performing voltage measurement for the plurality of subjects of measurement, measures voltages at the input terminals at which the voltage signals from the plurality of subjects of measurement are inputted, and a voltage at the input terminal at which the potential for diagnosis is inputted. | 2012-09-06 |
| 20120223723 | Sensor - The invention disclosed enables sensing of the electrical permittivity of an object. A sensor is provided that includes a dielectric layer that presents a surface defining the base of a volume in which a test object may be placed and an electrically active layer beneath the dielectric layer, comprising a first set of electrodes that extend in a first direction and a second set of electrodes that extend in a second direction that is perpendicular to the first direction. By applying a signal to a first electrode in said first set of electrodes, an electric field is generated that extends outside of the sensor. An output signal is then produced in each of the second electrode set by capacitive coupling to the first electrode. The electrical permittivity of the volume above the first receiver electrode is then determined based on the output signals in the said set of electrodes. | 2012-09-06 |
| 20120223724 | INDUCTIVE MEASURING DEVICE FOR DETECTING LENGTHS AND ANGLES - The invention relates to a measuring device for detecting absolution positions, comprising a sensor unit (N, M) as a planar coil structure and a scale having alternating areas of variable reluctance or conductivity along the measuring line. The invention is characterized in that the measuring device has at least two divisions (T | 2012-09-06 |
| 20120223725 | Touch Sensitive Device And Fabrication Method Thereof - The present invention relates to a touch sensitive device comprising a substrate, a mask layer, at least one touch sensing assembly partially masked by the mask layer, and an insulator formed between the mask layer and the touch sensing assembly for insulating the mask layer and the touch sensing assembly; wherein the mask layer, the touch sensing assembly, and the insulator are integrally formed on the substrate. | 2012-09-06 |
| 20120223726 | MEMS Sensor with Movable Z-Axis Sensing Element - A MEMS sensor includes a substrate and a MEMS structure coupled to the substrate. The MEMS structure has a mass movable with respect to the substrate. The MEMS sensor also includes a reference structure electrically coupled to the mass of the MEMS sensor. The reference structure is used to provide a reference to offset any environmental changes that may affect the MEMS sensor in order to increase the accuracy of its measurement. | 2012-09-06 |
| 20120223727 | METHOD OF CONTROLLING ACTIVE MATERIAL ACTUATION UTILIZING AN OPERATIONAL ENVELOPE - A method of controlling and/or predicting the remaining useful life of an active material actuator, such as a shape memory alloy wire, includes obtaining historical actuation data of an inherent system variable, such as electrical resistance, over a secondary variable, such as time, determining a normal operating envelope having upper and lower bounds based on the data, determining a current profile for a given actuation cycle, and comparing the shape of the current profile to the envelope to determine an out-of-bounds event. | 2012-09-06 |
| 20120223728 | METHOD AND SYSTEM THAT DETERMINES THE VALUE OF A RESISTOR IN LINEAR AND NON-LINEAR RESISTOR SETS - The present subject matter refers to apparatus and methods for identifying a resistance level of a resistor. In an example, circuit configured to identify a resistor can include a plurality of current sources, each current source selectively coupled to the resistor to generate a resistor voltage, a comparator configured to compare the resistor voltage and a reference voltage, and to provide an output indicative of the comparison, and a controller configured to selectively couple a first one or more current sources of the plurality of current sources to the resistor, and to selectively couple a second one or more current sources of the plurality of current sources to the resistor in response to the output indicative of the comparison. | 2012-09-06 |
| 20120223729 | Adhesively Attached Stand-Offs On A Portable Pack For An Electronics Tester - The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit. | 2012-09-06 |
| 20120223730 | PROBE CARD POSITIONING MECHANISM AND INSPECTION APPARATUS - A probe card positioning mechanism in which, when a probe card used to inspect electrical characteristics of an object to be processed is detachably inserted in a head plate of an inspection apparatus or an insert ring fixed to the head plate, at least three positioning pins placed circumferentially with an interval therebetween on an outer circumference of the probe card are inserted in at least three corresponding positioning long holes formed in the head plate or the insert ring such that the probe card is positioned at a specified position of the head plate or the insert ring, wherein the positioning holes are formed as long holes being elongated in a width-wise direction of the probe card and the entire inner circumferential surface of the long holes is configured as a taper surface which is gradually declined along an insertion direction of the pins. | 2012-09-06 |
| 20120223731 | TEST BRACKET FOR CIRCUIT BOARD - A test bracket for testing a circuit board includes a base, two connection pieces, and a supporting member for supporting the circuit board. The base includes a board and two posts extending up from the board. The supporting member includes two poles and a number of ribs slidably connected between the poles. First ends of the connection pieces are respectively detachably connected to the posts of the base, and second ends of the connection pieces opposite to the first ends are respectively pivotably connected to the poles. | 2012-09-06 |
| 20120223732 | TRANSMISSION DEVICE AND METHOD OF TESTING TRANSMISSION CHARACTERISTIC OF DUT - There is provided a transmission device. The transmission device includes: an adapter device ( | 2012-09-06 |
| 20120223733 | Solar Cell Characterization System with an Automated Continuous Neutral Density Filter - Techniques for solar cell electrical characterization are provided. In one aspect, a solar testing device is provided. The device includes a solar simulator; and a continuous neutral density filter in front of the solar simulator having regions of varying light attenuation levels ranging from transparent to opaque, the continuous neutral density filter having an area sufficiently large to filter all light generated by the solar simulator, and wherein a position of the continuous neutral density filter relative to the solar simulator is variable so as to control a light intensity produced by the device. A solar cell electrical characterization system and a method for performing a solar cell electrical characterization are also provided. | 2012-09-06 |
| 20120223734 | MEASUREMENT OF INSULATION RESISTANCE OF CONFIGURABLE PHOTOVOLTAIC PANELS IN A PHOTOVOLTAIC ARRAY - Methods for measuring insulation resistance in a photovoltaic (PV) array may include partitioning the PV array into groups of PV panels, isolating a group of PV panels selected for an insulation resistance measurement from other groups of panels by setting bypass selectors on each PV panel in the PV array, and making an insulation resistance measurement for the selected group. If a measured value of insulation resistance for a selected group corresponds to an insulation problem in a PV array component, a separate measurement of insulation resistance may be made for each PV panel in the selected group. Insulation resistance measurements may be made accurately and rapidly for large PV arrays without disconnecting and reconnecting cables between panels. Measurements may be made at frequent, regular intervals to permit changes in insulation resistance to be detected before damage from dielectric breakdown occurs. | 2012-09-06 |
| 20120223735 | DETECTION OF SINGLE BIT UPSET AT DYNAMIC LOGIC DUE TO SOFT ERROR IN REAL TIME - A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground. | 2012-09-06 |
| 20120223736 | TRANSCEIVING CIRCUIT AND TRANSCEIVING CIRCUIT RESISTANCE CALIBRATION METHOD - A transceiving circuit resistance calibrating method, which is applied to a transceiving circuit. The method includes: inputting a first current to a transmitter to generate a first output voltage, wherein the first current is generated according to a ratio between a predetermined voltage and an inner resistor of a chip; inputting a second current to a transmitter to generate a second output voltage, wherein the first current is generated according to a ratio between the predetermined voltage and a predetermined resistor; and adjusting a first adjustable resistance module according to a difference between the first output voltage and the second output voltage. | 2012-09-06 |
| 20120223737 | RECONFIGURABLE SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories. | 2012-09-06 |
| 20120223738 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 2012-09-06 |
| 20120223739 | FLIP-FLOP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals. | 2012-09-06 |
| 20120223740 | RESET/LOAD AND SIGNAL DISTRIBUTION NETWORK - A tree-like signal distribution network comprises a plurality of branches extending from a plurality of branching points. The distribution network comprises a plurality of control blocks, each control block being situated at a branching point of the tree-like distribution network, wherein each of the plurality of control blocks is arranged such that it can distribute a signal received from the tree-like distribution network, a locally generated signal, and a combination of a signal received from the tree-like distribution network and a locally generated signal. | 2012-09-06 |
| 20120223741 | POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS - In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein. | 2012-09-06 |
| 20120223742 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A DIGITAL CIRCUIT BY CONTROLLING THE CLOCK - A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use. | 2012-09-06 |
| 20120223743 | Time Base Generator and Method for Providing a First Clock Signal and a Second Clock Signal - A time base generator and method for providing a first clock signal and a second clock signal comprising generating the first clock signal at a first clock frequency, dividing the first clock frequency by a first integer to produce a first auxiliary signal, dividing the second clock signal by a second integer to produce a second auxiliary signal, generating an error signal by individually weighting and comparing cycle durations or phasing of the first and second auxiliary signals, and generating the second clock signal by a voltage-controlled oscillator controlled by the error signal such that two clock signals of slightly different frequencies with defined time or phase delay are provided. | 2012-09-06 |
| 20120223744 | CONTROL OF SEMICONDUCTOR COMPONENT - An exemplary method and a control circuit are disclosed for controlling a power semiconductor component by producing a control signal (Ucin) for controlling the component, forming a second control signal (Ucout) in the potential of the controlled component from the control signal (Ucin), measuring a current flowing through the component, and comparing the measured current with a set limit. A fault signal (Ufault) having a logical state is provided on the basis of the comparison between the measured current and the set limit, producing a component control signal (Uave) from the fault signal (Ufault) and the second control signal (Ucout). If a fault is indicated, the component control signal has a value between high and low states, and otherwise the state of the component control signal (Uave) equals the state of the second control signal (Ucout). | 2012-09-06 |
| 20120223745 | MONOLITHIC LOW IMPEDANCE DUAL GATE CURRENT SENSE MOSFET - A power switch includes a first power transistor having a first source electrode, a first gate electrode, and a first drain electrode, and a second power transistor having a second source electrode, a second gate electrode, and a second drain electrode. The power switch further includes a first pilot transistor which has a third source electrode, a third gate electrode, and a third drain electrode. The first, second and third drain electrodes are electrically connected together. The first and second source electrodes are electrically connected together. The first and third gate electrodes are electrically connected together and can be biased independently from the second gate electrode. The first power transistor is the same size as or smaller than the second power transistor and the first power transistor is larger than the first pilot transistor. | 2012-09-06 |
| 20120223746 | METHOD AND APPARATUS SWITCHING A SEMICONDUCTOR SWITCH WITH A MULTI-STAGE DRIVE CIRCUIT - A multi-stage drive circuit is to be coupled to a semiconductor switch having a drive terminal, a first terminal and a second terminal, to switch the semiconductor switch on and off. The multi-stage drive circuit includes a first drive circuit, a second drive circuit and a selector circuit. The first drive circuit is to be coupled to provide a first drive signal to the drive terminal of the semiconductor switch and the second drive circuit is to be coupled to provide a second drive signal to the drive terminal of the semiconductor switch. The selector circuit is to be coupled to turn on the first and second drive circuits to provide the first and second drive signals to the drive terminal, respectively. The selector circuit turns on the second drive circuit responsive to a voltage between the first and second terminals of the semiconductor switch falling to a threshold value. | 2012-09-06 |
| 20120223747 | Method and Apparatus for Producing Triangular Waveform with Low Audio Band Content - A triangular waveform generator includes a square waveform clock circuit and an integrating circuit. The integration circuit receives input from the square waveform clock circuit and generates a triangular waveform output. A feedback circuit is operatively connected to the integrating circuit to reduce the audio band noise content in the triangular waveform output. The feedback circuit acts as a DC balance without significant sacrifice in the linearity of the triangular waveform output. | 2012-09-06 |
| 20120223748 | CIRCUIT AND METHOD FOR APPLYING A THREE PHASE POWER SOURCE TO A THREE PHASE LOAD - A circuit and method of applying a three phase power source to a load such that each phase is applied to the load in a manner, such as a predetermined sequence, so as to reduce the electromagnetic interference (EMI) and heat generated in the switching devices during the application and removal of each phase to the load. | 2012-09-06 |
| 20120223749 | CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A clock synchronization circuit receives a base clock, a first synchronization signal for synchronizing the base clock and a system clock, and a selection signal containing information about the division ratio of the system clock, holds the first synchronization signal over a predetermined time on the basis of the selection signal, and outputs, in synchronization with the base clock, a second synchronization signal for synchronizing the base clock and the system clock. | 2012-09-06 |
| 20120223750 | TRANSCEIVER, VOLTAGE CONTROL OSCILLATOR THEREOF AND CONTROL METHOD THEREOF - A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock. | 2012-09-06 |
| 20120223751 | Generating an Oscillator Signal Having a Desired Frequency in a Continuous Frequency Range - A method of generating a first oscillator signal having a desired frequency in a first frequency range comprises generating in a voltage controlled oscillator unit a second oscillator signal having a frequency in a second frequency range of at least one octave. The method further comprises selecting said second continuous frequency range to have a lower endpoint in said first frequency range and an upper endpoint above said range; and selectively using the oscillator signal unchanged or dividing it by a division ratio selected from integer powers of the number 2 to obtain said first oscillator signal. By centering the VCO higher than otherwise required and using an additional divider, so that the VCO signal can selectively be used unchanged or divided, a sufficient margin below as well as above the desired range for e.g. drift and tolerances of the VCO is achieved. It also simplifies the VCO design. | 2012-09-06 |
| 20120223752 | PHASE LOCKED LOOP WITH CHARGE PUMP - A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal. | 2012-09-06 |
| 20120223753 | DIGITAL DELAY LINES - In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage. | 2012-09-06 |
| 20120223754 | DELAY CIRCUITRY - Integrated circuits with delay circuitry are provided. Delay circuitry may receive a clock signal and generate a corresponding delayed clock signal. The delayed clock signal generated using the delay circuitry may exhibit reduced duty cycle distortion in comparison to conventional systems. The delay circuitry may include a pulse generation circuit, a delay circuit, and a latching circuit. The pulse generation circuit may generate pulses in response to detecting rising edges or falling edges at its input. The pulses may propagate through the delay circuit. The latching circuit may generate (reconstruct) a delayed version of the clock signal in response to receiving the pulses at its control input. The delay circuitry may be used in duty cycle distortion correction circuitry, delay-locked loops, and other control circuitry. | 2012-09-06 |
| 20120223755 | DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals. | 2012-09-06 |
| 20120223756 | Method and System for High Speed, Low Power and Small Flip-Flops - A master-slave flip-flop may be operable to sense a signal, received by a slave circuit from a master circuit, at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in the slave circuit. The flip-flop may generate a corresponding output signal at an output terminal based on the sensing of the signal received by the slave circuit. The flip-flop may receive, in a feedback path of the slave circuit, a SET signal. An inverted version of the SET signal may be received via a gate terminal of a PMOS transistor in the master circuit. The flip-flop may receive, in a feedback path of the master circuit, a RESET signal. The RESET signal may also be received via a gate of a NMOS transistor in the master circuit. The flip-flop may disable an input terminal utilizing the SET signal and/or the RESET signal. | 2012-09-06 |
| 20120223757 | Method and Apparatus for Clock Calibration in a Clocked Digital Device - Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit. | 2012-09-06 |
| 20120223758 | Bidirectional Input/Output Circuit - Level-shifting devices and methods allow signals to be passed between input/output (I/O) ports. One such device comprises a first output driver that drives a first I/O port in response to a first control signal. A second output driver drives a second I/O port in response to a second control signal. A first comparator circuit, responsive to a first reference voltage and a voltage at the first I/O port, generates the second control signal. A limiter circuit limits driving of the second I/O port, by the second driver, to a limiting voltage that responsive to a the second I/O port over a first range of signaling voltages, and constrained to a set value over a second range. A voltage reference generating circuit generates a second reference voltage. A second comparator circuit generates the first control signal in response to the second reference voltage and the second I/O port. | 2012-09-06 |
| 20120223759 | RECEIVER CIRCUIT - A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal. | 2012-09-06 |
| 20120223760 | LEVEL SHIFT CIRCUIT - A level shift circuit including a level shift voltage generation circuit that receives an input signal having an amplitude between a voltage of a first voltage system power supply and a ground potential and performs conversion of the amplitude of the input signal to produce an output signal voltage with an amplitude between a voltage of a second voltage system power supply and the ground potential, a replica circuit monitoring a voltage corresponding to a logic threshold of the first voltage system power supply, the replica circuit, with the logic threshold of the first voltage system power supply as an input, monitoring and outputting a voltage corresponding to a logic threshold of the second voltage system power supply, and a bias generation circuit that receives an output from the replica circuit and generates a bias. | 2012-09-06 |
| 20120223761 | 360-DEGREE ANGLE DECODER - This disclosure is directed to techniques for decoding two or more signals that vary sinusoidally with respect to a parameter value to produce a decoded signal that varies linearly with respect to the parameter value. The techniques may include receiving a first signal and a second signal, the first signal varying with respect to a parameter value according to a first sinusoidal function having a period and a first phase, the second signal varying with respect to the parameter value according to a second sinusoidal function having the period and a second phase different from the first phase. The techniques may further include performing one or more arithmetic operations using the first signal, the second signal, and an offset value to generate a third signal that varies linearly with respect to the parameter value for at least one-half of the period of the first signal and the second signal. | 2012-09-06 |
| 20120223762 | PASS TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, AND SWITCHING BOX CIRCUIT INCLUDING THE PASS TRANSISTOR CIRCUIT - A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET. | 2012-09-06 |
| 20120223763 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which avoids an adverse effect of high temperatures due to a switching element and in which a circuit to prevent false firing is arranged on the same substrate as the switching element. An N-channel type MOSFET | 2012-09-06 |
| 20120223764 | ON-CHIP CONTROL OF THERMAL CYCLING - A method, system, and computer program product for on-chip control of thermal cycling in an integrated circuit (IC) are provided in the illustrative embodiments. A first circuit is configured on the IC for adjusting a first voltage being applied to a first part of the IC. A first temperature of the first part is measured at a first time. A determination is made that the first temperature is outside a temperature range defined by an upper temperature threshold and a lower temperature threshold. The first voltage is adjusted by reducing the first voltage when the first temperature exceeds the upper temperature threshold and by increasing the first voltage when the first temperature is below the lower temperature threshold, thereby causing the first temperature of the first part to attain a value within the temperature range. | 2012-09-06 |
| 20120223765 | Method and System for Passive Signal Detector for Chip Auto Power on and Power Down - While an IC chip is in idle mode with no power being supplied to the IC chip, the IC chip may be operable to detect a signal pulse received by the IC chip using energy associated with the signal pulse. The IC chip may be operable to control a control signal for a power switch using the energy associated with the signal pulse. The power switch may allow power to be provided to the IC chip based on the control signal. The IC chip may comprise a pulse detector, a latch circuit and an ON/OFF logic circuit within the IC chip. While the IC chip is fully powered and communication with a partner chip is finished, the IC chip may be operable to control the control signal to turn off the power switch for powering down the IC chip based on a turn-off signal. | 2012-09-06 |
| 20120223766 | INTEGRATED CIRCUITS WITH BI-DIRECTIONAL CHARGE PUMPS - Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load. | 2012-09-06 |
| 20120223767 | TWO-STAGE POST DRIVER CIRCUIT - A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress. | 2012-09-06 |
| 20120223768 | SEMICONDUCTOR DEVICE AND METHOD FOR FETCHING DATA - In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence. | 2012-09-06 |
| 20120223769 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data. | 2012-09-06 |
| 20120223770 | RESETTABLE HIGH-VOLTAGE CAPABLE HIGH IMPEDANCE BIASING NETWORK FOR CAPACITIVE SENSORS - A high-voltage MEMS biasing network. The network has a reset mode wherein a capacitive sensor is charged, and a functional mode wherein the MEMS biasing network provides a high impedance between the capacitive sensor and a bias voltage source. The network includes a biasing circuit, a mirror circuit, and a control circuit. The biasing circuit and the mirror circuit have a charging state and a high impedance state. The control circuit includes a first branch that controls the biasing circuit and a second branch that controls the mirror circuit. The biasing network receives a logic control signal, the first branch puts the biasing circuit into the charging state when the logic control signal is a first logic signal, and puts the biasing circuit into the high impedance state when the logic control signal is a second logic signal. | 2012-09-06 |
| 20120223771 | TEMPERATURE COMPENSATION AND COARSE TUNE BANK SWITCHES IN A LOW PHASE NOISE VCO - The LC tank of a VCO includes a main varactor circuit and temperature compensation varactor circuit coupled in parallel with the main varactor circuit. The main varactor is used for fine tuning. The temperature compensation varactor circuit has a capacitance-voltage characteristic that differs from a capacitance-voltage characteristic of the main varactor circuit such that the effects of common mode noise across the two varactor circuits are minimized. The LC tank also has a plurality of switchable capacitor circuits provided for coarse tuning. To prevent breakdown of the main thin oxide switch in each of the switchable capacitor circuits, each switchable capacitor circuit has a capacitive voltage divider circuit that reduces the voltage across the main thin oxide switch when the main switch is off. | 2012-09-06 |
| 20120223772 | MULTILEVEL CLASS-D AMPLIFIER - A multilevel class-D differential amplifier which can be operated in at least three modes includes a first power stage and a second power stage. In an idle mode, an output of the first power stage varies between a first voltage level and a second voltage level, wherein an output of the second power stage varies between the first voltage level and the second voltage level. In a PWM mode, the output of the first power stage varies between the first voltage level and the second voltage level, wherein the output of the second power stage varies between the first voltage level and the second voltage level. In a Multi-Level mode, the output of said first power stage varies between said second voltage level and a third voltage level, wherein said output of said second power stage is fixed at said first voltage level, and wherein said differential signal between said outputs of said power stages is pulse width modulated. | 2012-09-06 |
| 20120223773 | LINEAR MODE AND NON-LINEAR MODE QUADRATURE PA CIRCUITRY - Embodiments of the present disclosure relate to multi-mode multi-band radio frequency (RF) power amplifier (PA) circuitry, which includes a multi-mode multi-band quadrature RF PA coupled to multi-mode multi-band switching circuitry via a single output. The switching circuitry provides at least one non-linear mode output and multiple linear mode outputs. The non-linear mode output may be associated with at least one non-linear mode RF communications band and each linear mode output may be associated with a corresponding linear mode RF communications band. The outputs from the switching circuitry may be coupled to an antenna port via front-end aggregation circuitry. The quadrature nature of the quadrature PA path may provide tolerance for changes in antenna loading conditions. | 2012-09-06 |
| 20120223774 | LOOK-UP TABLE BASED CONFIGURATION OF MULTI-MODE MULTI-BAND RADIO FREQUENCY POWER AMPLIFIER CIRCUITRY - Circuitry, which includes multi-mode multi-band radio frequency (RF) power amplification circuitry, power amplifier (PA) control circuitry, and a PA-digital communications interface (DCI) is disclosed according to one embodiment of the circuitry. The PA control circuitry is coupled between the amplification circuitry and the PA-DCI, which is coupled to a digital communications bus, and configures the amplification circuitry. The amplification circuitry includes at least a first RF input and multiple RF outputs, such that at least some of the RF outputs are associated with multiple communications modes and at least some of the RF outputs are associated with multiple frequency bands. Configuration of the amplification circuitry associates one RF input with one RF output, and is correlated with configuration information defined by at least a first defined parameter set. The PA control circuitry stores at least a first look-up table (LUT), which provides the configuration information. | 2012-09-06 |
| 20120223775 | DOHERTY AMPLIFIER - The embodiment relates to a Doherty amplifier, wherein in order to perform impedance matching. The embodiment comprises an impedance converter and a connector. The impedance converter includes a plurality of lines having different lengths and disposes between an output end of a carrier amplifier and an output end of a peaking amplifier. The connector connects a line selected from the plurality of lines having different lengths of the impedance converter to the output end of the carrier amplifier and to the output end of the peaking amplifier. | 2012-09-06 |
| 20120223776 | POWER SUPPLY CONTROLLER FOR A MULTI-GAIN STEP RF POWER AMPLIFIER - A power supply controller controls the power supply voltage provided to a multi-gain step RF power amplifier to increase the efficiency of the RF power amplifier when the different gains of the RF power amplifier are selected and, thereby, reduce the power consumed by the multi-gain step RF power amplifier. | 2012-09-06 |
| 20120223777 | RF Power Amplifier Circuit With Mismatch Tolerance - A radio frequency (RF) power amplifier system adjusts the supply voltage provided to a power amplifier (PA) adaptively, responsive to the measured or estimated power of the RF output signal of the PA. The RF PA system includes a power amplifier (PA) which receives and amplifies an RF input signal to generate an RF output signal at a level suitable for transmission to an antenna. A PA supply voltage controller generates a supply voltage control signal, which is used to control the supply voltage to the final stage of the PA. The supply voltage control signal is generated responsive to the measured or estimated power of the PA RF output signal, and also may be responsive to a parameter indicative of impedance mismatch experienced at the PA output. By controlling this supply voltage to the RF PA, the efficiency of the PA is improved. | 2012-09-06 |
| 20120223778 | DIGITALLY CONTROLLED OSCILLATOR, AND PHASE LOCKED LOOP (PLL) CIRCUIT INCLUDING THE SAME - Disclosed is a digitally controlled oscillator which includes a ring oscillator; and a variable resistance bank connected between one power node of the ring oscillator and a power supply terminal and having the resistance value varied according to the number of active bits of a control code. The frequency of an clock signal output by the ring oscillator is changed non-linearly according to the resistance value of the variable resistance bank. The frequency of the output clock signal is changed stepwise linearly according to the number of active bits of the control code. | 2012-09-06 |
| 20120223779 | Voltage-controlled oscillator - This invention provides a voltage-controlled oscillator, comprising a first voltage-controlled oscillator circuit and a second voltage-controlled oscillator circuit. The first voltage-controlled oscillator circuit comprises a plurality of inductors, a plurality of variable capacitors, and a plurality of MOS transistors. The circuit configuration of the second voltage-controlled oscillator circuit is symmetrical to that of the first voltage-controlled oscillator circuit. The inductors of the first voltage-controlled oscillator circuit are cross-coupled to the inductors of the second voltage-controlled oscillator circuit. | 2012-09-06 |
| 20120223780 | VOLTAGE CONTROLLED OSCILLATOR CIRCUIT - According to one embodiment, a voltage control oscillating circuit is provided with a ring oscillator, a control current generating unit and a constant current generating unit. The ring oscillator has an odd number of inverters connected in a ring shape. The control current generating unit converts an input control voltage into a control current and to supply the control current to the ring oscillator as a first supply current. The constant current generating unit generates a constant current and to supply the generated constant current to the ring oscillator as a second supply current which is added to the control current. | 2012-09-06 |
| 20120223781 | NOISE REGULATED LINEAR VOLTAGE CONTROLLED OSCILLATOR - Described embodiments provide a voltage controlled oscillator (VCO) that includes an operational amplifier (opamp). The opamp has a positive power supply input coupled to a power supply voltage, a negative power supply input coupled to a ground node, an inverting input coupled to a control voltage of the VCO, a noninverting input that receives a feedback signal, and an output providing a transistor control voltage. A transistor having a gate terminal coupled to the output of the opamp, a source terminal coupled to the power supply voltage, and a drain terminal coupled to a resistor coupled to ground, generates an output current. A current mirror generates a mirror current based on the output current. A current controlled oscillator (ICO) is coupled to the current mirror, and sets the frequency of the VCO output signal based upon the mirror current. | 2012-09-06 |
| 20120223782 | COMPLEX NEGATIVE FEEDBACK FREQUENCY SELECTION OUTPUT CIRCUIT AND OSCILLATION CIRCUIT USING THE SAME - It is an object to provide a complex negative feedback frequency selection output circuit that can produce an output signal of a high resonance sharpness Q factor and an oscillation circuit using the same. The complex negative feedback frequency selection output circuit according to the present invention, frequency-selectively relays only the residual components of one of a signal in phase with (or a signal opposite in phase to) a feedback processed signal obtained by negative feeding back a feedback signal to an input frequency signal, with a rejected frequency band being left out, while relaying at least a real number component of the other, and comprises a feedback path which relays a difference signal between (or a sum signal of) the selectively relayed output and the relayed output of the real number component, as the feedback signal. The gain of a loop including this feedback path is variable and can be set manually or automatically. | 2012-09-06 |
| 20120223783 | OSCILLATOR CIRCUIT AND ELECTRONIC APPARATUS INCLUDING THE SAME - An amplifier circuit for amplifying output signal from the crystal oscillator circuit is connected to the output side of the crystal oscillator circuit. The amplifier circuit amplifies the difference between the output voltage of the crystal oscillator circuit and the input voltage of a CMOS inverter of the crystal oscillator circuit. For example, a differential amplifier is connected to the output side of the crystal oscillator circuit, then the output voltage of the crystal oscillator circuit and the input voltage of the CMOS inverter are connected to the inputs of the differential amplifier. | 2012-09-06 |
| 20120223784 | VIBRATOR ELEMENT, VIBRATOR, OSCILLATOR, AND ELECTRONIC APPARATUS - A quartz crystal vibrator element having the weight section is provided with the intermediate weight section formed to have an arm width W | 2012-09-06 |
| 20120223785 | CRYSTAL OSCILLATOR WITH REDUCED ACCELERATION SENSITIVITY - A crystal oscillator having a plurality of quartz crystals that are manufactured so that the directional orientation of the acceleration sensitivity vector is essentially the same for each crystal. This enables convenient mounting of the crystals to a circuit assembly with consistent alignment of the acceleration vectors. The crystals are aligned with the acceleration vectors in an essentially anti-parallel relationship and can be coupled to the oscillator circuit in either a series or parallel arrangement. Mounting the crystals in this manner substantially cancels the acceleration sensitivity of the composite resonator and oscillator, rendering it less sensitive to vibrational forces and shock events. | 2012-09-06 |
| 20120223786 | METHOD AND APPARATUS FOR ADAPTIVE IMPEDANCE MATCHING - A system that incorporates teachings of the present disclosure may include, for example, an apparatus having an RF matching network including one or more variable reactive elements, where the RF matching network has a first port coupled to a transceiver and second port coupled to an antenna. The RF matching network can modify signal power transferred between the first port and the second port according to one or more bias signals applied to the one or more variable reactive elements to vary a variable impedance of the RF matching network. The one or more variable reactive elements are coupled to a circuit that maps one or more control signals to the one or more bias signals, and wherein the one or more control signals are generated by a controller according to a mode of operation of a communication device. Additional embodiments are disclosed. | 2012-09-06 |
| 20120223787 | ANALOG PHASE SHIFTER - A high-frequency phase shifter | 2012-09-06 |
| 20120223788 | SEAL RING INDUCTOR AND METHOD OF FORMING THE SAME - Apparatuses and methods for providing inductance are disclosed. In one embodiment, a method for providing an inductor includes forming an electrical circuit on a substrate, forming a seal ring around the perimeter of the electrical circuit, providing a break in at least one layer of the seal ring, and electrically connecting the seal ring such that the seal ring operates as an inductor. | 2012-09-06 |
| 20120223789 | ELASTIC-WAVE FILTER DEVICE AND COMPOSITE DEVICE INCLUDING THE SAME - An elastic-wave filter device includes a first piezoelectric substrate, a second piezoelectric substrate, a first pillar-like wiring electrode, and a second pillar-like wiring electrode. The first and second substrates have a first and a second IDT electrodes on their top faces respectively. A lateral face of the second substrate confronts a lateral face of the first substrate. The first pillar-like electrode and the second pillar-like electrode are formed above the first and the second substrates respectively, and are electrically connected to the first and the second IDT electrodes respectively. The first substrate is thicker than the second substrate. A distance between a plane including the top face of the first substrate and a plane including the top face of the second substrate is smaller than a distance between a plane including an underside of the first substrate and a plane including an underside of the second substrate. | 2012-09-06 |
