| 36th week of 2012 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20120223290 | LIGHT-RECEIVING ELEMENT, LIGHT-RECEIVING ELEMENT ARRAY, METHOD FOR MANUFACTURING LIGHT-RECEIVING ELEMENT AND METHOD FOR MANUFACTURING LIGHT-RECEIVING ELEMENT ARRAY - A light-receiving element includes a group III-V compound semiconductor stacked structure that includes an absorption layer having a pn-junction therein. The stacked structure is formed on a group III-V compound semiconductor substrate. The absorption layer has a multi- quantum well structure composed of group III-V compound semiconductors, and the pn-junction is formed by selectively diffusing an impurity element into the absorption layer. A diffusion concentration distribution control layer composed of a III-V group semiconductor is disposed in contact with the absorption layer on a side of the absorption layer opposite the side adjacent to the group III-V compound semiconductor substrate. The bandgap energy of the diffusion concentration distribution control layer is smaller than that of the group III-V compound semiconductor substrate. The concentration of the impurity element selectively diffused in the diffusion concentration distribution control layer is 5×10 | 2012-09-06 |
| 20120223291 | QUANTUM DOT-FULLERENE JUNCTION BASED PHOTODETECTORS - A photodetector includes one or more photodiodes and a signal processing circuit. Each photodiode includes a transparent first electrode, a second electrode, and a heterojunction interposed between the first electrode and the second electrode. Each heterojunction includes a quantum dot layer and a fullerene layer disposed directly on the quantum dot layer. The signal processing circuit is in signal communication each the second electrode. The photodetector may be responsive to wavelengths in the infrared, visible, and/or ultraviolet ranges. The quantum dot layer may be treated with a chemistry that increases the charge carrier mobility of the quantum dot layer. | 2012-09-06 |
| 20120223292 | Multilayer-Interconnection First Integration Scheme for Graphene and Carbon Nanotube Transistor Based Integration - Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack. | 2012-09-06 |
| 20120223293 | Biodegradable Electronic Devices - Biodegradable electronic devices may include a biodegradable semiconducting material and a biodegradable substrate layer for providing mechanical support to the biodegradable semiconducting material. | 2012-09-06 |
| 20120223294 | SPIN FILTER DEVICE, METHOD FOR ITS MANUFACTURE AND ITS USE - The present invention relates to a method and a device for providing a current of spin-polarised electrons. More particularly, the present invention is suited for use in spin electronics or detection of spin-polarised electrons. | 2012-09-06 |
| 20120223295 | BISCARBAZOLE DERIVATIVES AND ORGANIC ELECTROLUMINESCENCE - Provided are an organic electroluminescence device having high current efficiency and a long lifetime, and a biscarbazole derivative for realizing the device. The biscarbazole derivative has a specific substituent. The organic EL device has a plurality of organic thin-film layers including a light emitting layer between a cathode and an anode, and at least one layer of the organic thin-film layers contains the biscarbazole derivative. | 2012-09-06 |
| 20120223296 | Organic Semiconducting Materials and Organic Component - An organic semiconductive material comprising at least one matrix material and at least one doping material, wherein the doping material is selected from an organic compound and wherein the matrix material is selected from an diamine compound, also an organic component and a mixture for producing a doped semiconductor layer. | 2012-09-06 |
| 20120223297 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A light-emitting element includes an anode, a cathode, a luminescent layer that is disposed between the anode and the cathode and emits light by applying a current between the anode and the cathode, and an organic layer that is disposed in contact with the anode and the luminescent layer between the anode and the luminescent layer and functions to transport holes. The organic layer includes a hole injection layer and a hole transport layer. The hole injection layer and the hole transport layer each contain an electron transport material that can transport electrons. The electron transport material content in the hole injection layer is different from that in the hole transport layer. | 2012-09-06 |
| 20120223298 | Triarylamine Derivative, Light-Emitting Substance, Light-Emitting Element, Light-Emitting Device, and Electronic Device - A triarylamine derivative represented by a general formula (G1) given below is provided. Note that in the formula, Ar represents either a substituted or unsubstituted phenyl group or a substituted or unsubstituted biphenyl group; α represents a substituted or unsubstituted naphthyl group; β represents either hydrogen or a substituted or unsubstituted naphthyl group; n and m each independently represent 1 or 2; and R | 2012-09-06 |
| 20120223299 | METAL/OXIDE ONE TIME PROGAMMABLE MEMORY - Embodiments include memory cells having an oxide material in contact with a metal material. In one embodiment, a memory cell includes titanium nitride, titanium oxynitride in contact with the titanium nitride and copper in contact with the titanium oxynitride. A plurality of such memory cells and respective access devices can be included in a memory array. The memory cell and access device are electrically connected between an access line and a data/sense line. An array can include a plurality of memory cells vertically stacked with respective access devices. Embodiments also include methods of forming memory cells and arrays and stacking memory arrays over one another. | 2012-09-06 |
| 20120223300 | THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride. | 2012-09-06 |
| 20120223301 | THIN FILM TRANSISTOR, MANUFACTURING METHOD OF SAME, AND DISPLAY DEVICE - According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer. | 2012-09-06 |
| 20120223302 | METHOD OF MANUFACTURING TRANSPARENT CONDUCTIVE FILM, THE TRANSPARENT CONDUCTIVE SUBSTRATE USING THE FILM, AS WELL AS DEVICE USING THE SUBSTRATE - By using a coating method, which is a method of manufacturing a transparent conductive film, with low-temperature heating lower than 300° C., a transparent conductive film with excellent transparency, conductivity, film strength, and resistance stability and a method of manufacturing this film are provided. In the method of manufacturing a transparent conductive film, a heat energy ray irradiating step is a step of irradiating with the energy rays while heating under an oxygen-containing atmosphere to a heating temperature lower than 300° C. to form the inorganic film, and the plasma processing step is a step of performing the plasma processing on the inorganic film under a non-oxidizing gas atmosphere at a substrate temperature lower than 300° C. to promote mineralization or crystallization of the film, thereby forming a conductive oxide fine-particle layer densely packed with conductive oxide fine particles having a metal oxide as a main component. | 2012-09-06 |
| 20120223303 | Offset Electrode TFT Structure - The present invention generally relates to an offset electrode TFT and a method of its manufacture. The offset electrode TFT is a TFT in which one electrode, either the source or the drain, surrounds the other electrode. The gate electrode continues to be below both the source and the drain electrodes. By redesigning the TFT, less voltage is necessary to transfer the voltage from the source to the drain electrode as compared to traditional bottom gate TFTs or top gate TFTs. The offset electrode TFT structure is applicable not only to silicon based TFTs, but also to transparent TFTs that include metal oxides such as zinc oxide or IGZO and metal oxynitrides such as ZnON. | 2012-09-06 |
| 20120223304 | SEMICONDUCTOR DEVICE - A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor. | 2012-09-06 |
| 20120223305 | SEMICONDUCTOR DEVICE - Provided is a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which a semiconductor film whose threshold voltage is difficult to control is used as an active layer. By using a silicon oxide film having a negative fixed charge as a film in contact with the active layer of the transistor or a film in the vicinity of the active layer, a negative electric field is always applied to the active layer due to the negative fixed charge and the threshold voltage of the transistor can be shifted in the positive direction. Thus, the highly reliable semiconductor device can be manufactured by giving stable electric characteristics to the transistor. | 2012-09-06 |
| 20120223306 | SEMICONDUCTOR DEVICE - With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased. | 2012-09-06 |
| 20120223307 | METHOD FOR MANUFACTURING TRANSISTOR - A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer. | 2012-09-06 |
| 20120223308 | THIN-FILM TRANSISTOR, PROCESS FOR PRODUCTION OF SAME, AND DISPLAY DEVICE EQUIPPED WITH SAME - The present invention provides a thin-film transistor capable of high-speed operation, a process for producing the same, and a display device including the same. The thin-film transistor of the present invention includes, on a substrate, in the order of: a gate electrode; a gate insulating film; an oxide semiconductor film; and a protective insulating film, the protective insulating film having a planar shape that is completely or substantially the same as the planar shape of the gate electrode. | 2012-09-06 |
| 20120223309 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 2012-09-06 |
| 20120223310 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween. | 2012-09-06 |
| 20120223311 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a gate electrode which includes a pair of first protrusions and a second protrusion provided between the pair of first protrusions; a gate insulating film covering the gate electrode; a semiconductor film which is in contact with the gate insulating film and overlaps with the pair of first protrusions and the second protrusion; and a pair of electrodes which is in contact with the semiconductor film and overlaps with the pair of first protrusions. The side edges of the semiconductor film are on the outer sides than the top surfaces of the pair of first protrusions in the direction of the channel width of the semiconductor film. The side edges of the pair of electrodes are on the outer sides than the top surfaces of the pair of first protrusions in the direction of the channel width of the semiconductor film. | 2012-09-06 |
| 20120223312 | Semiconductor Structure of a Display Device and Method for Fabricating the Same - A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode. | 2012-09-06 |
| 20120223313 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING SAME - Disclosed is a thin film transistor substrate which is provided with: a plurality of source lines | 2012-09-06 |
| 20120223314 | Solution-Processed High Mobility Inorganic Thin-Film Transistors - Thin film transistor devices comprising a dielectric component and an inorganic semiconductor component coupled thereto, wherein said coupled inorganic semiconductor component is obtainable by a process that comprises contact of said dielectric component and a fluid medium comprising said inorganic semiconductor component. | 2012-09-06 |
| 20120223315 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed is a display device including: a gate electrode; a semiconductor layer formed into an island shape on an upper side of the gate electrode; a side wall oxide film formed on a lateral surface of the semiconductor layer; and a drain electrode and a source electrode formed on an upper side of the semiconductor layer extending from a lateral side of the semiconductor layer, wherein the side wall oxide film has a thickness of 2.1 nm or more. | 2012-09-06 |
| 20120223316 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - Disclosed is a thin film transistor wherein an ON current is increased and a leak current is reduced. The channel layer | 2012-09-06 |
| 20120223317 | OHMIC CONTACT SCHEMES FOR GROUP III-V DEVICES HAVING A TWO-DIMENSIONAL ELECTRON GAS LAYER - A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer. | 2012-09-06 |
| 20120223318 | P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON INJECTION - A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer. | 2012-09-06 |
| 20120223319 | SEMICONDUCTOR DIODES WITH LOW REVERSE BIAS CURRENTS - A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents. | 2012-09-06 |
| 20120223320 | ELECTRODE CONFIGURATIONS FOR SEMICONDUCTOR DEVICES - A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure. | 2012-09-06 |
| 20120223321 | III-Nitride Transistor Stacked with FET in a Package - One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 2012-09-06 |
| 20120223322 | III-Nitride Transistor Stacked with Diode in a Package - One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 2012-09-06 |
| 20120223323 | WAFER, CRYSTAL GROWTH METHOD, AND SEMICONDUCTOR DEVICE - According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region. | 2012-09-06 |
| 20120223324 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence. | 2012-09-06 |
| 20120223325 | MICROELECRONIC ASSEMBLY WITH AN EMBEDDED WAVEGUIDE ADAPTER AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor. | 2012-09-06 |
| 20120223326 | LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode. | 2012-09-06 |
| 20120223327 | Programmable Gate III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a charged gate insulation body. | 2012-09-06 |
| 20120223328 | GROUP III NITRIDE EPITAXIAL LAMINATE SUBSTRATE - A Group III nitride epitaxial laminate substrate comprising a substrate, a buffer and a main laminate in this order, wherein the buffer includes an initial growth layer, a first superlattice laminate and a second superlattice laminate in this order, the first superlattice laminate includes five to 20 sets of first AlN layers and second GaN layers, the first AlN layers and the second GaN layers being alternately stacked, and each one set of the first AlN layer and the second GaN layer has a thickness of less than 44 nm, the second superlattice laminate includes a plurality of sets of first layers made of an AlN material or an AlGaN material and second layers made of an AlGaN material having a different band gap from the first layers, the first and second layers being alternately stacked. | 2012-09-06 |
| 20120223329 | Production Method of a Layered Body - Disclosed is a novel method for group III polarity growth on a sapphire substrate. Specifically disclosed is a method for producing a laminate wherein a group III nitride single crystal layer is laminated on a sapphire substrate by an MOCVD method. The method for producing a laminate comprises: a pretreatment step in which an oxygen source gas is supplied onto the sapphire substrate; a first growth step in which an initial single crystal layer that contains oxygen at a concentration of 5×10 | 2012-09-06 |
| 20120223330 | SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL - Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior. | 2012-09-06 |
| 20120223331 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance. | 2012-09-06 |
| 20120223332 | SEMICONDUCTOR RECTIFYING DEVICE - A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate. | 2012-09-06 |
| 20120223333 | SEMICONDUCTOR RECTIFIER DEVICE - A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm | 2012-09-06 |
| 20120223334 | DOPED DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 2012-09-06 |
| 20120223335 | METHOD OF MARKING SiC SEMICONDUCTOR WAFER AND SiC SEMICONDUCTOR WAFER - Marking of an SiC wafer with an identifier is realized by irradiation with a pulsed laser using a harmonic of a wavelength four times that of a YAG laser. A speed at which a laser head moves, an orbit in which the laser head moves, the output power and Q-switch frequency of a pulsed laser to be applied, and the like are determined such that pulse-irradiated marks formed as a result of irradiation with corresponding pulses of the pulsed laser do not overlap each other. | 2012-09-06 |
| 20120223336 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a collector layer of a first conductivity type and a drift layer of a second conductivity type in contact with said collector layer, said drift layer receiving a supply of carriers from said collector layer. The semiconductor device further includes a lattice defect formed to penetrate through said semiconductor substrate and enclose a predetermined portion of said semiconductor substrate, a sense emitter electrode formed on the top surface of said predetermined portion, and a collector electrode formed on the bottom surface of said predetermined portion. | 2012-09-06 |
| 20120223337 | NITRIDE SEMICONDUCTOR DIODE - In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly. | 2012-09-06 |
| 20120223338 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film. | 2012-09-06 |
| 20120223339 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction. | 2012-09-06 |
| 20120223340 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation. | 2012-09-06 |
| 20120223341 | LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE, DISPLAY, AND ELECTRONIC DEVICE - A light emitting element has an anode, a cathode, a light emitting layer which is provided between the anode and the cathode and emits light by energizing the anode and the cathode, and a functional layer (a hole injecting layer and a hole transporting layer) which is provided between the anode and the light emitting layer in contact therewith and has a function of transporting a hole, in which the hole injecting layer and the hole transporting layer each are constituted including an electron transporting material having electron transporting properties. The content of the electron transporting material contained in the hole injecting layer and the content thereof contained in the hole transporting layer are different from each other. | 2012-09-06 |
| 20120223342 | Light-Emitting Device and Lighting Device - A highly reliable light-emitting device or lighting device is provided. Further, a light-emitting device or lighting device with a high manufacturing yield is provided. Provided is a light-emitting device having a contact structure which includes a separation layer having a shape typified by a reverse tapered shape in which an outline of the bottom portion is inside an outline of an upper portion and which utilizes the difference between an amount of a light-emitting layer extending inside the outline and that of an upper electrode extending inside the outline. Further, when the outline of the separation layer which forms the contact portion has a depression and a projection, the length of the contact portion can be increased, and thus, contact resistance can be reduced. | 2012-09-06 |
| 20120223343 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package includes a first lead frame comprising a first hole cup, a second lead frame comprising a second hole cup and disposed to face the first lead frame with a gap disposed between the first lead frame and the second lead frame, a first light emitting diode chip disposed on the first hole cup, and a second light emitting diode chip disposed on the second hole cup, the first lead frame comprising a first enlarged region formed between the gap and the first hole cup, and the second lead frame comprising a second enlarged region formed between the gap and the second hole cup. | 2012-09-06 |
| 20120223344 | ARRAY OF SCALABLE CERAMIC DIODE CARRIERS HAVING LEDS - Ceramic diode carriers ( | 2012-09-06 |
| 20120223345 | LIGHT EMITTING UNIT AND DISPLAY DEVICE - A light emitting unit including plural kinds of light emitting elements with different light emitting wavelengths, wherein, among the light emitting elements, at least one kind of light emitting element includes a semiconductor layer configured by laminating a first conductive layer, an active layer and a second conductive layer and having a side surface exposed by the first conductive layer, the active layer and the second conductive layer; a first electrode electrically connected to the first conductive layer; a second electrode electrically connected to the second conductive layer; a first insulation layer contacting at least an exposed surface of the active layer in the surface of the semiconductor layer; and a metal layer contacting at least a surface, which is opposite to the exposed surface of the active layer, in the surface of the first insulation layer, and electrically separated from the first electrode and the second electrode. | 2012-09-06 |
| 20120223346 | Display Device - To provide a display device with low power consumption. The display device includes a plurality of pixels each having a light-emitting element having a structure in which light emitted from a light-emitting layer is resonated between a reflective electrode and a light-transmitting electrode, wherein no color filter layers are provided or color filter layers with high transmittance are provided in pixels for light with relatively short wavelengths (e.g., pixels for blue and/or green), and a color filter layer is selectively provided in pixels for light with a long wavelength (e.g., pixels for red), and thereby maintaining color reproducibility and consuming less power. | 2012-09-06 |
| 20120223347 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS - Provided are a light emitting device, a light emitting device package, and a lighting apparatus. The light emitting device includes: an n-type semiconductor layer including a first area and a second area in a plane; an active layer disposed on the n-type semiconductor layer in the first area; an electron barrier layer disposed on the active layer in the first area; and a p-type semiconductor layer disposed on the electron barrier layer in the first area. | 2012-09-06 |
| 20120223348 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer. A plurality of apertures penetrates the metal portion along the direction, each of the apertures viewed along the direction having equivalent circle diameters of not less than 10 nanometers and not more than 5 micrometers, and a Schottky barrier is provided between the second semiconductor layer and the metal portion. | 2012-09-06 |
| 20120223349 | FRONT SIDE EMITTING TYPE ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A front side emitting type organic light-emitting display device includes a substrate; an anode electrode formed over the substrate; an organic layer formed over the anode electrode; a cathode electrode formed over the organic layer; a pair of transparent conductive oxide layers disposed over the cathode electrode; and a metal layer interposed between the pair of transparent conductive oxide layers. | 2012-09-06 |
| 20120223350 | Light-Emitting Device, Lighting Device, Substrate, and Manufacturing Method of Substrate - To provide a substrate which is light and has high reliability and high light extraction efficiency from an organic EL element. To provide a substrate which includes a protective layer in a resin layer, an uneven structure on a light incident surface, and an opening which surrounds the uneven structure and through which the protective layer is exposed. To provide a light-emitting device which includes a resin layer provided with an uneven structure on a light incident surface over a protective layer, and a light-emitting element in the protective layer and a counter substrate which are bonded with a sealant. The protective layer and the resin layer have a property of transmitting visible light. The light-emitting element includes a light-transmitting first electrode over a resin layer, a layer containing a light-transmitting organic compound over the first electrode, and a second electrode over the layer containing a light-transmitting organic compound. | 2012-09-06 |
| 20120223351 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURE - A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers. | 2012-09-06 |
| 20120223352 | PHOSPHOR AND LED LIGHT EMITTING DEVICE USING THE SAME - An LED light emitting device is provided that has high color rendering properties and is excellent color uniformity and, at the same time, can realize even luminescence unattainable by conventional techniques. A phosphor having a composition represented by formula: (Sr | 2012-09-06 |
| 20120223353 | Light-Emitting Diode Structure - A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block. | 2012-09-06 |
| 20120223354 | SEMICONDUCTOR TWO-PHOTO DEVICE - A semiconductor, room-temperature, electrically excited, two-photon device with thick optically active layer is provided. The intrinsic AlGaAs active layer is sandwiched between two intrinsic graded waveguide layers having increased aluminum concentration at increased distance from the active layer. The waveguide structure is sandwiched between two cladding layers of high aluminum concentration, n and p doped respectively. The structure is epitaxially grown on a substrate and further comprises other layers such as buffer, graded layers and contact layers. An etched ridge provides lateral confinement for light. The device provides two-photons gain and may be used in light sources, optical amplifiers, pulse compressors and lasers. | 2012-09-06 |
| 20120223355 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. | 2012-09-06 |
| 20120223356 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device includes a first layer, a first electrode, a second electrode and a third electrode. The first layer is provided on a surface of the second semiconductor layer opposite to the light emitting layer and including conductive oxide. The first electrode is in contact with a part of the first layer and includes a reducible element for reducing the conductive oxide. The second electrode includes a first portion covering the first electrode and a second portion being in contact with the first layer, and the third electrode is electrically connected to the first semiconductor layer. | 2012-09-06 |
| 20120223357 | Semiconductor Light-Emitting Device - The present disclosure relates to a semiconductor light-emitting device, which includes: a first semiconductor layer having first conductivity; a second semiconductor layer having second conductivity different from the first conductivity; an active layer disposed between the first semiconductor layer and the second semiconductor layer and generating light by recombination of electrons and holes; a first pad electrode electrically connected to the second semiconductor layer; a high-resistance body partially disposed on the second semiconductor layer; and a branch electrode disposed on the second semiconductor layer, partially extending over the high-resistance body, and electrically connected to the first pad electrode. | 2012-09-06 |
| 20120223358 | METHOD OF TUNING WORK FUNCTION OF METAL NANOSTRUCTURE-BASED TRANSPARENT CONDUCTOR - The present disclosure relates to methods for tuning the work function of a metal nanostructure-based conductive film by forming a dipole surface layer on individual metal nanostructures. | 2012-09-06 |
| 20120223359 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor light emitting device. The semiconductor light emitting device includes: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; an insulation layer on the second conductive semiconductor layer and including a first hole therein; a second electrode on the second conductive semiconductor layer; and a first electrode on the insulation layer and including a connection portion electrically connected to the first conductive semiconductor layer. The second electrode includes a plurality of line patterns. The connection portion of the first electrode is disposed between the plurality of line patterns of the second electrode and is disposed in the first hole of the insulation layer. | 2012-09-06 |
| 20120223360 | Optoelectronic Component and Method for Producing an Opto-Electronic Component - An opto-electronic component has a carrier element ( | 2012-09-06 |
| 20120223361 | LOW-POWER CONSUMPTION TUNNELING FIELD-EFFECT TRANSISTOR WITH FINGER-SHAPED GATE STRUCTURE - The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size. | 2012-09-06 |
| 20120223362 | Compound Semiconductor Device on Virtual Substrate - A method of fabrication of barrier diode based infrared detectors, utilizing the growth of unstrained, not relaxed III-V compound semiconductor material layers having a lattice constant over 6 Angstrom, is provided. The growth is performed by the means of Molecular Beam Epitaxy (MBE) or Metal-Organic Vapor Phase Epitaxy (MOVPE). The method comprises the use of bulk crystalline substrates and the growth of a transitional layer of GaInAsSb with graded composition, followed by an optional thick layer of GaInAsSb of constant composition, lattice matched to the said III-V compound semiconductor material layers, the said optional layer of GaInAsSb of constant composition serving as a virtual substrate. The method provides high crystalline quality layers suitable for semiconductor device fabrication that can effectively interact with electromagnetic radiation of the mid-infrared spectral range with a wavelength between about 2 micrometers to about 16 micrometers. | 2012-09-06 |
| 20120223363 | TRANSISTOR WITH AN EMBEDDED STRAIN-INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION - In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices. | 2012-09-06 |
| 20120223364 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer. | 2012-09-06 |
| 20120223365 | III-Nitride Semiconductor Structures with Strain Absorbing Interlayer Transition Modules - There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure. | 2012-09-06 |
| 20120223366 | HIGH VOLTAGE GAN TRANSISTOR - A multiple field plate transistor includes an active region, with a source, drain, and gate. A first spacer layer is between the source and the gate and a second spacer layer between the drain and the gate. A first field plate on the first spacer layer and a second field plate on the second spacer layer are connected to the gate. A third field plate connected to the source is on a third spacer layer, which is on the gate and the first and second field plates and spacer layers. The transistor exhibits a blocking voltage of at least 600 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 5.0 or 5.3 mΩ-cm | 2012-09-06 |
| 20120223367 | Method For Fabricating Semiconductor Wafers For The Integration of Silicon Components With Hemts, And Appropriate Semiconductor Layer Arrangement - The invention describes a method for fabricating silicon semiconductor waferswith the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafersare used, the active semiconductor layer of which has the III-V semiconductor layers ( | 2012-09-06 |
| 20120223368 | Power Routing in Standard Cells - An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules. | 2012-09-06 |
| 20120223369 | Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors - Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors. | 2012-09-06 |
| 20120223370 | BIOCHEMICAL SENSOR AND METHOD OF MANUFACTURING THE SAME - A biochemical sensor and a method of manufacturing the same are disclosed. The biochemical sensor includes a substrate, a gate arranged on one side of the substrate, a gate insulating layer arranged on one side of the gate opposite to the substrate, an active layer arranged on one side of the gate insulating layer opposite to the gate, a source and a drain arranged on one side of the active layer opposite to the gate insulating layer, and a biochemical sensing layer arranged on one side of the active layer opposite to the gate insulating layer and between the source and the drain. | 2012-09-06 |
| 20120223371 | VIRTUAL SEMICONDUCTOR NANOWIRE, AND METHODS OF USING SAME - A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone. | 2012-09-06 |
| 20120223372 | TWO-STEP SILICIDE FORMATION - An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer. | 2012-09-06 |
| 20120223373 | SEMICONDUCTOR DEVICE INCLUDING A CRYSTAL SEMICONDUCTOR LAYER, ITS FABRICATION AND ITS OPERATION - In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed. | 2012-09-06 |
| 20120223374 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion. | 2012-09-06 |
| 20120223375 | SEMICONDUCTOR DEVICE - To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner. | 2012-09-06 |
| 20120223376 | SEMICONDUCTOR DEVICE - p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed. | 2012-09-06 |
| 20120223377 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 2012-09-06 |
| 20120223378 | Floating Gate Semiconductor Memory Device and Method for Producing Such a Device - Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device. | 2012-09-06 |
| 20120223379 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures. | 2012-09-06 |
| 20120223380 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 2012-09-06 |
| 20120223381 | Non-volatile memory structure and method for manufacturing the same - A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer. | 2012-09-06 |
| 20120223382 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure. | 2012-09-06 |
| 20120223383 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 2012-09-06 |
| 20120223384 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view. | 2012-09-06 |
| 20120223385 | ELECTRONIC SYSTEMS, THIN FILM TRANSISTORS, METHODS OF MANUFACTURING THIN FILM TRANSISTORS AND THIN FILM TRANSISTOR ARRAYS - Thin film transistors (TFT) and methods of manufacturing the same. A TFT includes a line-shaped gate of uniform thickness. A cross-section of the gate is curved where a side surface and a top surface meet. The gate includes one, or two or more gate lines. | 2012-09-06 |
| 20120223386 | Asymmetric FinFET devices - Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin. | 2012-09-06 |
| 20120223387 | TUNNELING DEVICE AND METHOD FOR FORMING THE SAME - The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall. | 2012-09-06 |
| 20120223388 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER - In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures. | 2012-09-06 |
| 20120223389 | SEMICONDUCTOR STRUCTURE WITH IMPROVED CHANNEL STACK AND METHOD FOR FABRICATION THEREOF - A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer. | 2012-09-06 |
