| 36th week of 2013 patent applcation highlights part 12 |
| Patent application number | Title | Published |
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| 20130228856 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 2013-09-05 |
| 20130228857 | METHOD OF FORMING AN ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS - A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate. | 2013-09-05 |
| 20130228858 | POWER MOSFET SEMICONDUCTOR - A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region. | 2013-09-05 |
| 20130228859 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region. | 2013-09-05 |
| 20130228860 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 2013-09-05 |
| 20130228861 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration. | 2013-09-05 |
| 20130228862 | SEMICONDUCTOR DEVICE HAVING A STRAINED REGION - The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region. | 2013-09-05 |
| 20130228863 | FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD - A fin field effect transistor (FET) including a fin structure and a method for forming the fin FET are provided. In an exemplary method, the fin FET can be formed by forming at least one fin seed, including a top surface and sidewalls, on a substrate. A first semiconductor layer can then be formed at least on the sidewalls of the at least one fin seed. A second semiconductor layer can be formed on the first semiconductor layer. The second semiconductor layer and the at least one fin seed can be made of a same material. The first semiconductor layer can be removed to form a fin structure including the at least one fin seed and the second semiconductor layer. | 2013-09-05 |
| 20130228864 | FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD - A fin field effect transistor (Fin FET) and a method for forming the Fin FET are provided. In an exemplary method, the Fin FET can be formed by providing a dielectric layer on a semiconductor substrate. The dielectric layer and the semiconductor substrate can be etched to form a groove including a second sub-groove, formed through the dielectric layer, and a first sub-groove, formed in the semiconductor substrate and connected to the second sub-groove. A fin can then be formed in the groove. The fin can have a top surface higher than a top surface of the dielectric layer. A gate structure can then be formed at least partially around a length portion of the fin on the top surface of the dielectric layer. | 2013-09-05 |
| 20130228865 | FIN FIELD EFFECT TRANSISTOR - A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin. | 2013-09-05 |
| 20130228866 | Semiconductor Devices and Manufacturing and Design Methods Thereof - Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin. | 2013-09-05 |
| 20130228867 | SEMICONDUCTOR DEVICE PROTECTED FROM ELECTROSTATIC DISCHARGE - According to one embodiment, a semiconductor device includes a first semiconductor chip, at least one second semiconductor chip, a first connector, and a second connector. The first semiconductor chip includes a first input pad, first protection circuit, and first internal circuit. The at least one second semiconductor chip includes a second input pad, second protection circuit, and second internal circuit. The first connector electrically connects the first and second input pads. The second connector connects the first protection circuit and first input pad of the first semiconductor chip. The second protection circuit of the at least one second semiconductor chip is not connected to the second input pad. | 2013-09-05 |
| 20130228868 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES - A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion. | 2013-09-05 |
| 20130228869 | SEMICONDUCTOR DEVICE - An SGT-based static memory cell which is a six-transistor SRAM cell includes an SGT driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an SGT selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an SGT load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor. A voltage applied to the second gate electrode is lower than a voltage applied to a first-conductivity-type high-concentration semiconductor layer on the upper part of the island-shaped semiconductor layer of the selection transistor. | 2013-09-05 |
| 20130228870 | SEMICONDUCTOR DEVICE INCLUDING TRENCHES HAVING PARTICULAR STRUCTURES - A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second part of the source/drain of the first region is different from the cross-sectional shape of the second part of the source/drain of the second region. | 2013-09-05 |
| 20130228871 | PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer. | 2013-09-05 |
| 20130228872 | GATE STRAIN INDUCED WORK FUNCTION ENGINEERING - A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions. | 2013-09-05 |
| 20130228873 | Apparatus and Method for High Voltage MOS Transistor - A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor. | 2013-09-05 |
| 20130228874 | Memory Arrays and Methods of Forming Electrical Contacts - Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays. | 2013-09-05 |
| 20130228875 | Apparatus and Method for FinFETs - A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region. | 2013-09-05 |
| 20130228876 | FinFET Design with LDD Extensions - System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions. | 2013-09-05 |
| 20130228877 | SEMICONDUCTOR DEVICE HAVING PLURAL STANDARD CELLS - Disclosed herein is a device that includes: a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; and a first power supply wiring extending in the first direction along one end of the first standard cells in a second direction. The field-effect transistor including a gate electrode formed on a gate wiring layer. The first power supply wiring being formed on the gate wiring layer. | 2013-09-05 |
| 20130228878 | POLY RESISTOR DESIGN FOR REPLACEMENT GATE TECHNOLOGY - A semiconductor device and method for fabricating a semiconductor device are disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region of the substrate, wherein the passive region includes at least one resistive structure disposed on an isolation region, the at least one resistive structure in a lower plane than the at least one transistor | 2013-09-05 |
| 20130228879 | SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS - An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion. | 2013-09-05 |
| 20130228880 | INTEGRATED SENSOR STRUCTURE - Embodiments of the present invention provide a method for manufacturing an integrated sensor structure. In one step, a semiconductor substrate having integrated readout electronics and a metallization structure is provided, the metallization structure including tungsten and being exposed on a surface of the semiconductor substrate. In another step, a sensor layer is deposited onto the surface of the semiconductor substrate, the semiconductor substrate having the integrated readout electronics and the metallization structure being exposed, when depositing the sensor layer, to a temperature which is above a maximum temperature used when generating the integrated readout electronics such that the sensor layer is connected to the integrated readout electronics via the metallization structure. | 2013-09-05 |
| 20130228881 | HIGH ASPECT RATIO CAPACITIVELY COUPLED MEMS DEVICES - A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode. | 2013-09-05 |
| 20130228882 | Magnetic Tunnel Junction (MTJ) Structure in Magnetic Random Access Memory - Methods and apparatuses for a magnetic tunnel junction (MTJ) which can be used in as a magnetic random access memory cell are disclosed. The MTJ comprises a free layer and an insulator layer. The MTJ further comprises a pinned layer with a first region, a second region, and a third region. The second region is of a first length and of a first thickness, and the first region and the third region are of a second length and of a second thickness. A ratio of the first thickness to the second thickness may be larger than 1.2. A ratio of the second length to the first length is larger than 0.5. The first thickness may be larger than a spin diffusion length of a material for the pinned layer. So formed MTJ results in increased tunneling magnetic resistance ratio and reduced critical switch current of the MTJ. | 2013-09-05 |
| 20130228883 | Magnetic Tunnel Junction Device - The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment. | 2013-09-05 |
| 20130228884 | MAGNETIC STACK HAVING ASSIST LAYERS - A magnetic tunnel junction having a ferromagnetic free layer and a ferromagnetic pinned reference layer, each having an out-of-plane magnetic anisotropy and an out-of-plane magnetization orientation, the ferromagnetic free layer switchable by spin torque. The magnetic tunnel junction includes a ferromagnetic assist layer proximate the free layer, the assist layer having a low magnetic anisotropy less than 700 Oe and positioned to apply a magnetic field on the free layer. | 2013-09-05 |
| 20130228885 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer. | 2013-09-05 |
| 20130228886 | Method and Apparatus for Backside Illumination Sensor - Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter. | 2013-09-05 |
| 20130228887 | PHOTODETECTOR WITH SURFACE PLASMON RESONANCE - Methods and structures for providing single-color or multi-color photo-detectors leveraging plasmon resonance for performance benefits. In one example, a radiation detector includes a semiconductor absorber layer having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer coupled to the absorber layer and having a second electrical conductivity type, and a plasmonic resonator coupled to the collector layer and having a periodic structure including a plurality of features arranged in a regularly repeating pattern. | 2013-09-05 |
| 20130228888 | METHOD FOR MANUFACTURING SOLID STATE IMAGE FORMING DEVICE, AND SOLID STATE IMAGE FORMING DEVICE - A method for manufacturing a solid state image forming device in one embodiment includes forming a transparent resin layer on a semiconductor substrate having a plurality of photodiode layers formed thereon in a lattice, through R, G, and B color filters that are formed according to a Bayer arrangement; forming a plurality of first microlens mother dies on the transparent resin layer at the positions corresponding to the G color filters in such a manner that the outer peripheries thereof are separated from each other; forming a plurality of second microlens mother dies in such a manner that they are formed to fill the gap between the first microlens mother dies and the outer peripheries thereof are separated from each other; and etching the transparent resin layer with the plurality of first microlens mother dies and the plurality of second microlens mother dies being used as masks. | 2013-09-05 |
| 20130228889 | SILICON PHOTOELECTRIC MULTIPLIER WITH MULTIPLE READ-OUT - A silicon-based photoelectric multiplier comprises a plurality of cells and a number of read-out lines, and at least one of a number read-out pads or a ring-like line, wherein the plurality of cells may be divided into a number of segments, and each one of the read-out lines may be electrically connected with the cells of at least one segment. | 2013-09-05 |
| 20130228890 | POWER SEMICONDUCTOR MODULE WITH METHOD FOR MANUFACTURING A SINTERED POWER SEMICONDUCTOR MODULE - Method of manufacturing sinterable electrical components for jointly sintering with active components, the components in planar shape being provided with at least one planar lower face meant for sintering, and an electrical contact area on the face opposite to the sintering face being available in the form of a metallic contact face, whose upper side is contactable by means of a commonly known method of the group: wire bonding or soldering or sintering or pressure contacting, the component being a temperature sensor, whose lower face is provided with a sinterable metallisation on a ceramic body, said ceramic body having two electrical contact faces for continued electrical connection. | 2013-09-05 |
| 20130228891 | MULTI-TRENCH TERMINATION STRUCTURE FOR SEMICONDUCTOR DEVICE AND MANUFACTURING MEHTOD THEREOF - A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device. | 2013-09-05 |
| 20130228892 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions. | 2013-09-05 |
| 20130228893 | TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved. | 2013-09-05 |
| 20130228894 | STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR - The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material. | 2013-09-05 |
| 20130228895 | PACKAGE SUBSTRATE AND SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor element, a capacitor, and a package substrate. The capacitor supplies transient current to the semiconductor element. The semiconductor element and the capacitor are mounted on the package substrate. The semiconductor element includes an integrated circuit, a first connecting part, and a second connecting part. The capacitor includes a third connecting part and a fourth connecting part. The package substrate includes a first metallic layer, a second metallic layer, and a dielectric layer. The first metallic layer includes a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region. The first conductive region is connected via a fifth connecting part to the second metallic layer. The third conductive region is connected via a sixth connecting part to the second metallic layer. The second and fourth conductive regions are connected to each other inside the first metallic layer. | 2013-09-05 |
| 20130228896 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a substrate structure layer including a substrate having a well and a diffusion region thereon, an interconnect layer including a pair of power supply lines arranged at a preset spacing from the substrate structure layer; the interconnect layer also including an input side interconnect and an output side interconnect between the pair of power supply lines, a standard cell having a logic circuit on the substrate; the logic circuit being electrically connected to the pair of power supply lines, the input side interconnect and the output side interconnect, and one or more capacitances arranged between the substrate structure layer and the interconnect layer and arranged in a region between the pair of power supply lines, the region being inclusive of a region superposed with the pair of power supply lines. | 2013-09-05 |
| 20130228897 | Electrical Connections for Chip Scale Packaging - Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch. | 2013-09-05 |
| 20130228898 | SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SUBSTRATE - Disclosed herein is a device that includes: a first semiconductor chip having a first internal circuit formed in a first substrate; and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate. The plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line. The first and second penetrating electrodes are in a floating state without electrically connected to the first internal circuit. The third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit. The fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit. The third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode. | 2013-09-05 |
| 20130228899 | MECHANISM OF PATTERNING A SEMICONDUCTOR DEVICE AND PRODUCT RESULTING THEREFROM - The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric. | 2013-09-05 |
| 20130228900 | Gate conductor with a diffusion barrier - A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. | 2013-09-05 |
| 20130228901 | MATERIALS AND METHODS FOR STRESS REDUCTION IN SEMICONDUCTOR WAFER PASSIVATION LAYERS - The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers. | 2013-09-05 |
| 20130228902 | SEMICONDUCTOR LAMINATE, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF - Provided is a method for manufacturing a semiconductor device. Also provided are: a semiconductor device which can be obtained by the method; and a dispersion that can be used in the method. A method for manufacturing a semiconductor device ( | 2013-09-05 |
| 20130228903 | Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device - Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer. | 2013-09-05 |
| 20130228904 | Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. | 2013-09-05 |
| 20130228905 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE - A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallisation region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallisation region. | 2013-09-05 |
| 20130228906 | INTERCONNECT FOR AN OPTOELECTRONIC DEVICE - Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first and second ends. A stress relief feature is disposed in the interconnect body. The stress relief feature includes a slot disposed entirely within the interconnect body without extending through to the inner surface, without extending through to the outer surface, without extending through to the first end, and without extending through to the second end of the interconnect body. | 2013-09-05 |
| 20130228907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. | 2013-09-05 |
| 20130228908 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a resin sealed semiconductor device with improved reliability. After positioning a cap (lid) so as to cover semiconductor chips and wires, resin is supplied into a space formed by the cap, so that a sealing body is formed to cover the semiconductor chips and the wires. In the step of forming the sealing body, the resin is supplied from an opening formed at a corner of the cap in the planar view. The sealing body is exposed at the corner of the cap, so that the exposed part of the sealing body can be kept away from the wires. | 2013-09-05 |
| 20130228909 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a cooling device, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is brazed to an outer surface of the cooling device. The semiconductor element is brazed to the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end of the external connection terminal, and at least part of the cooling device. | 2013-09-05 |
| 20130228910 | POWER CONVERSION DEVICE - A power conversion device is provided with a plurality of semiconductor modules. Each semiconductor module includes a heat dissipation member, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is fixed to the heat dissipation member. The semiconductor element is mounted on the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end, and at least part of the heat dissipation member. The semiconductor modules each form a unit. | 2013-09-05 |
| 20130228911 | LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME - A low-profile microelectronic package includes a die ( | 2013-09-05 |
| 20130228912 | Apparatus for Chip Thermal Stress Relief - Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board. | 2013-09-05 |
| 20130228913 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 2013-09-05 |
| 20130228914 | Heat Sink Apparatus for Microelectronic Devices - One embodiment of the present invention is a heat sink apparatus for cooling a semiconductor device includes: (a) a rigid support ring having a top surface and a bottom surface; (b) a thermally conductive bottom sheet having a top and a bottom surface, wherein the top surface of the sheet is attached to the bottom surface of the rigid support ring; and (c) a channel for cooling fluid formed by a volume contained by the rigid support ring, the sheet, and an enclosure; wherein the sheet is held in tension by the rigid support ring, thereby reducing the macroscopic coefficient of thermal expansion (CTE) of the sheet. In use, thermally induced mechanical stress in a semiconductor device attached to the bottom surface of the sheet may be ameliorated by the reduction in macroscopic CTE, thereby increasing reliability of an assembly as it is cycled in temperature during normal operation. | 2013-09-05 |
| 20130228915 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs. | 2013-09-05 |
| 20130228916 | TWO-SOLDER METHOD FOR SELF-ALIGNING SOLDER BUMPS IN SEMICONDUCTOR ASSEMBLY - A semiconductor device ( | 2013-09-05 |
| 20130228917 | Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLP-MLP) - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation. | 2013-09-05 |
| 20130228918 | THREE-DIMENSIONAL INTEGRATED CIRCUIT WHICH INCORPORATES A GLASS INTERPOSER AND METHOD FOR FABRICATING THE SAME - A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C. | 2013-09-05 |
| 20130228919 | Semiconductor Device and Method of Forming Protective Coating Over Interconnect Structure to Inhibit Surface Oxidation - A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium. | 2013-09-05 |
| 20130228920 | PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE - A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias. | 2013-09-05 |
| 20130228921 | SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF - A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure. | 2013-09-05 |
| 20130228922 | SEMICONDUCTOR DEVICE STRUCTURES AND PRINTED CIRCUIT BOARDS COMPRISING SEMICONDUCTOR DEVICES - The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed. | 2013-09-05 |
| 20130228923 | METHODS AND LAYERS FOR METALLIZATION - One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device. | 2013-09-05 |
| 20130228924 | COPPER INTERCONNECTS HAVING A TITANIUM-PLATINUM-TITANIUM ASSEMBLY BETWEEN COPPER AND COMPOUND SEMICONDUCTOR - Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd). | 2013-09-05 |
| 20130228925 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - A hybrid interconnect structure is provided that includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 2013-09-05 |
| 20130228926 | INTERCONNECTION STRUCTURE - Provided is an interconnection structure that, in a display device such as an organic EL display or a liquid crystal display, has superior workability during wet etching even without providing an etch stop layer. The interconnection structure has, in the given order, a substrate, a semiconductor layer of a thin film transistor, and a metal interconnection film, and has a barrier layer between the semiconductor layer and the metal interconnection film. The semiconductor layer comprises an oxide semiconductor, the barrier layer has a layered structure of a high-melting-point metal thin film and a Si thin film, and the Si thin film is directly connected to the semiconductor layer. | 2013-09-05 |
| 20130228927 | INTERCONNECT STRUCTURES - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure. | 2013-09-05 |
| 20130228928 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a stacked body, a second conductive layer, a second insulating layer, a tubular semiconductor pillar, an insulating film and an occlusion film. The second conductive layer is provided on the stacked body. The second insulating layer is provided on the second conductive layer. The tubular semiconductor pillar is provided in such a manner as to pass through the second insulating layer, the second conductive layer and the stacked body. The insulating film is provided between the semiconductor pillar, and the second insulating layer, the second conductive layer and the stacked body. The occlusion film occludes the tube in a lower portion of the portion passing through the second insulating layer in the semiconductor pillar. The tube below the occlusion film in the semiconductor pillar is an air gap. | 2013-09-05 |
| 20130228929 | Protection Layers for Conductive Pads and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line. | 2013-09-05 |
| 20130228930 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 μm to 10 μm from the edge of the concave to the bottom of the concave. | 2013-09-05 |
| 20130228931 | SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS - There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning. | 2013-09-05 |
| 20130228932 | Package on Package Structure - A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit. | 2013-09-05 |
| 20130228933 | BEOL Interconnect With Carbon Nanotubes - An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode. | 2013-09-05 |
| 20130228934 | INTEGRATED CIRCUIT DEVICES INCLUDING INTERCONNECTIONS INSULATED BY AIR GAPS AND METHODS OF FABRICATING THE SAME - Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections. | 2013-09-05 |
| 20130228935 | SEMICONDUCTOR DEVICE HAVING SIGNAL LINE AND POWER SUPPLY LINE INTERSECTING WITH EACH OTHER - Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring. | 2013-09-05 |
| 20130228936 | METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL - A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate. | 2013-09-05 |
| 20130228937 | Micromechanical Sound Transducer Arrangement and a Corresponding Production Method - A micromechanical sound transducer arrangement includes an electrical printed circuit board having a front side and a rear side. A micromechanical sound transducer structure is applied to the front side using the flip-chip method. The printed circuit board defines an opening for emitting soundwaves in the region of the micromechanical sound transducer structure. | 2013-09-05 |
| 20130228938 | HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM - A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias. | 2013-09-05 |
| 20130228939 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 2013-09-05 |
| 20130228940 | Spray Device to be Mounted on an Electric Vehicle - A spray device mounted on a non-motor vehicle (T-car) selected from among commercial or novel electric vehicles so as to improve air quality inside a tunnel by spraying water during operation, collecting pollutants floating inside a subway tunnel, and collecting and sinking fine dust generated by means of the operation of a train onto the road. The spray device is mounted on a lower portion of the non-motorized vehicle (T-car) from among commercial or new electromotive cars, pressurized water is supplied to a distribution pipe on a discharging side by means of a pressurizing motor and a pump, and a jet is sprayed through a spray nozzle coupled to the distribution pipe. Also, it is possible to automatically spray a jet onto a rail surface while a train moves on a ground-level railway using a sensor and a control board. | 2013-09-05 |
| 20130228941 | AIR INTRODUCTION SYSTEM AND METHOD FOR COOLING TOWERS - A system and a method for promoting improved air flow through a cooling tower and reduced inner air pressure losses caused by rain in the rain zone of a cooling tower. Aerodynamic modules are mounted on the lower edge of the cooling tower shell in order to deflect the downward-flowing air about the lower edge of the tower shell and into the rain zone. The aerodynamic modules can be modularly mounted, can be replaced, and do not affect the statics of the tower shell. Aerodynamic modules can also be built on the base area to deflect the incoming air over any obstacles. Troughs or dripping elements can also promote flow by reducing the rain falling in an outer area. | 2013-09-05 |
| 20130228942 | OPTICAL ELEMENT MOLDING DIE AND METHOD FOR MOLDING OPTICAL ELEMENT - An optical element molding die is designed for molding an optical element having a concave-convex structure. The optical element can be manufactured by a wet system that enables element formation over a large area and a curved surface, without using a lithographic process, and is advantageous in terms of mass production and equipment cost. The optical element molding die includes a substrate having a surface with a negative standard electrode potential in the oxidation reaction and an anodic oxidation layer provided on the substrate. A protective layer with the positive standard electrode potential is provided between the substrate and the anodic oxidation layer. | 2013-09-05 |
| 20130228943 | ANTIMICROBIAL MEDICAL DEVICES - The present invention provides methods for making an antimicrobial medical device, preferably an antimicrobial ophthalmic device, more preferably an antimicrobial extended-wear contact lens, which contains silver nano-particles distributed uniformly therein. The antimicrobial medical device can exhibit antimicrobial activity over an extended period of time. | 2013-09-05 |
| 20130228944 | METHOD OF MANUFACTURING COLOR CONVERTING MEMBER - A color converting member is capable of suppressing deterioration in a phosphor by a simple manufacturing process. A method of manufacturing a color converting member includes a process of molding a resin material into a shape. In the process, molding the resin material and the phosphor integrally into a shape is performed, after kneading a phosphor that converts one color light to another color light into the resin material. | 2013-09-05 |
| 20130228945 | METHOD AND ASSEMBLY FOR MANUFACTURING INGESTIBLE PRODUCTS - A method and assembly for manufacturing ingestible products from liquids and soft-solid ingestible matters, the method including the steps of hard freezing the liquid or soft-solid ingestible matter, granulating the hard-frozen ingestible matter, and thereafter either ( | 2013-09-05 |
| 20130228946 | PROCESS AND APPARATUS FOR REGISTERED EMBOSSING OF EXTENSIBLE PRINTED FILM OR OF A LAMINATE COMPRISING AN EXTENSIBLE PRINTED FILM - In an embodiment, a process for synchronized embossing of an extensible printed film or of a laminate product including an extensible printed film is disclosed. The process includes pre-heating the film; possible coupling of the pre-heated film with a substrate; passage of the film or of the laminate between an engraved embossing cylinder; and a pressing counter-cylinder, in which the extensible film is subjected to a controlled elongation, in the longitudinal direction only, during the pre-heating step, during which the film is in a thermoplastic state, and said controlled elongation is such as to synchronize the decoration printed on the film with the position of the embossing cylinder. | 2013-09-05 |
| 20130228947 | Devices and Method for Tissue Engineering - A method of fabricating a bioactive porous tissue scaffold is herein provided. Bioactive materials having a composition of biologically active materials that define a group of surface reactive glass, glass-ceramic, and ceramic materials that most commonly include a range of silicate, borate, and phosphate-based glass systems. These materials typically exhibit a narrow working range that require heating methods that use pore former combustion to control thermal variations during processing. | 2013-09-05 |
| 20130228948 | PROCESS FOR MAKING ABSORBENT COMPONENT - A process for making an absorbent component comprising the steps of providing individual sheets of pulp; attaching a first individual pulp sheet to one or more second individual pulp sheets to form a strip of pulp; feeding the strip of pulp into a defiberizer; defiberizing the strip of pulp to form defiberized fibers; and depositing the defiberized fibers onto a forming surface to form the absorbent component. | 2013-09-05 |
| 20130228949 | FABRICATION OF NATURAL CELLULOSE FIBER WITH FLAME-RETARDING CAPABILITY - A fabrication of natural cellulose fiber with flame-retarding capability comprises following steps. Blend pulp and solvent of N-methylmorpholine N-oxide (NMMO) to form slurry. Evaporate extra water content from slurry by a Thin Film Evaporator (TFE) to form dope. By Dry-Jet Wet Spinning, spin and extrude dope for coagulating and regenerating. Water-rinse and dry to form natural cellulose fiber. Soaking roll natural cellulose fiber by flame retardant of N-(hydroxymethyl)-3-(methoxy phosphorus acyl). Orderly dry, bake, neutralize, soaping clean, water rinse, baking dry, soaking rolled, alkaline clean, water rinse, dry and oil the natural cellulose fiber to produce natural cellulose fiber of flame retarding capacity. Because of cross-linking reaction for the flame retardant of N-(hydroxymethyl)-3-(methoxy phosphorus acyl) with natural cellulose fiber, the flame-retarding capability thereof meet requirements of testing standards in American ASTM D6413-1999 and ASTM D2863-1995. Moreover, the wastes thereof meet the requirements of environment protections without harm. | 2013-09-05 |
| 20130228950 | METHODS AND MATERIALS FOR FABRICATING MICROFLUIDIC DEVICES - Materials and methods are provided for fabricating microfluidic devices. The materials include low surface energy fluoropolymer compositions having multiple cure functional groups. The materials can include multiple photocurable and/or thermal-curable functional groups such that laminate devices can be fabricated. The materials also substantially do not swell in the presence of hydrocarbon solvents. | 2013-09-05 |
| 20130228951 | Wafer-Level Underfill and Over-Molding - A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes. | 2013-09-05 |
| 20130228952 | METHOD FOR PRODUCING HONEYCOMB STRUCTURES - To provide a method for manufacturing a honeycomb structure with which it is possible to flexibly cope with a change in the outer diameter of a honeycomb formed body including through-holes that should be plugged, a plugging failure less easily occurs, and it is possible to easily manufacture a honeycomb structure in which desired through-holes are plugged. The method for manufacturing a honeycomb structure includes a step for arranging a mask | 2013-09-05 |
| 20130228953 | Three-Dimensional Shaping Device And Three-Dimensional Shaping Method - Control means performs control such that a head section | 2013-09-05 |
| 20130228954 | APPARATUS AND METHOD FOR CORONA TREATING FILM FOR SELF OPENING BAGS - An apparatus for corona treating film includes a source of film material and at least one transport roller that is rotatably mounted in a frame. The transport roller has a longitudinal axis and has a width greater than the film. First and second treater heads have first and second leading edges, first and second trailing edges and are mounted parallel to the longitudinal axis. The second leading edge is parallel to and spaced from the first trailing edge by a second predetermined distance. The film is transported over the roller and a high voltage electric arc is provided to the first and second treater heads. The roller is grounded and provides a return path for the electric current provided to the first and second treater heads, thereby corona treating the front side or back side of the film if a second roller and third and fourth treater heads are used. | 2013-09-05 |
| 20130228955 | Method And System For Performing An Infrared Treatment - A method for performing an infrared treatment includes the steps of receiving an extruded product and feeding the extruded product to an oven including at least one lamp unit. The lamp unit includes a lamp, a reflective surface enclosing a first side of the lamp and positioned to direct radiation from the lamp, and a glass disposed between a second side of the lamp and an extruded product, wherein the glass separates the lamp and the extruded product. The method further includes the step of creating cross-linking between layers of the extruded product by directing the radiation at the extruded product. Still further, the method includes the steps of directing a first gas flow at a surface of the product and directing a second gas flow at the glass at an intensity, direction, and temperature that prevents the glass from becoming an infrared source. | 2013-09-05 |
