36th week of 2013 patent applcation highlights part 11 |
Patent application number | Title | Published |
20130228756 | Array Substrate and Method of Fabricating the Same - A fabricating method of an array substrate includes forming source and drain electrodes in each of pixel regions on a substrate; forming an organic semiconductor layer and a gate insulating layer on the source and drain electrodes, the organic semiconductor layer having an island shape and contacting facing ends of the source and drain electrodes, the gate insulating layer having a same plane shape as the organic semiconductor layer; forming a first passivation layer on the gate insulating layer; forming a gate electrode on the first passivation layer in the pixel region, the gate electrode corresponding to the gate insulating layer; forming a second passivation layer on the gate electrode, the second passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer, the pixel electrode contacting the drain electrode through the drain contact hole. | 2013-09-05 |
20130228757 | SERIES-CONNECTED ORGANIC ELECTROLUMINESCENT MODULE AND DISPLAY DEVICE INCLUDING THE SAME - A series-connected organic electroluminescent module includes: a plurality of electroluminescent bodies each including an organic light-emitting layer; at least one charge-generating body capable of generating holes and electrons while being irradiated, and disposed to connect respective adjacent two of the electroluminescent bodies so as to form a series-connection of the electroluminescent bodies and the charge-generating body; and an electrode unit including an anode and a cathode that are respectively electrically connected to two outermost ones of the electroluminescent bodies disposed at two opposite terminals of the series-connection of the electroluminescent bodies and the at least one charge-generating body. | 2013-09-05 |
20130228758 | Dendrimers Containing Luminescent Gold (III) Compounds for Organic Light-Emitting Devices and Their Preparation - A novel class of saturated or conjugated dendrimers containing at least one strong σ-donating group coordinated to cyclometalated tridentate gold(III) compounds having the chemical structure depicted by generic formula: | 2013-09-05 |
20130228759 | ORGANIC LIGHT EMITTING DIODE DEVICES - A non-coherent light emitting device having at least one organic light emitting or organic charge transporting layer and a structure providing a Bragg grating associated with the light emitting layer is described. The organic light emitting layer having liquid crystalline material is treated to provide alternating zones of isotropic and liquid crystalline material. The combination of alternating zones with the dichroic effects of the aligned zone produces a pseudo 2-D Bragg grating within the light emitting layer. | 2013-09-05 |
20130228760 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance. | 2013-09-05 |
20130228761 | LIGHT EMITTING DEVICE - A light emitting device includes: a first electrode, a conductor film, an organic layer having a light emitting layer made of an organic light emitting material provided therein, a semi-transmissive reflective film, a resistive layer, and a second electrode, all of which are laminated successively, wherein the conductor film transmits a part of light from the light emitting layer therethrough, the first electrode reflects the light having been transmitted through the conductor film, the second electrode transmits the light having been transmitted through the semi-transmissive reflective film therethrough, an average film thickness of the conductor film on the first electrode is from 1 nm to 6 nm, and an average film thickness of the semi-transmissive reflective film on the organic layer is from 1 nm to 6 nm. | 2013-09-05 |
20130228762 | Light-Emitting Element, Light-Emitting Device and Electronic Device - The present invention provides a light-emitting element inducing an electron-transporting layer and a hole-transporting layer between a first electrode and a second electrode; and a first layer and a second layer between the electron-transporting layer and the hole-transporting layer, wherein the first layer includes a first organic compound and an organic compound having a hole-transporting property, the second layer includes a second organic compound and an organic compound having an electron-transporting property, the first layer is formed in contact with the first electrode side of the second layer, the first organic compound and the second organic compound are the same compound, and a voltage is applied to the first electrode and the second electrode, so that both of the first organic compound and the second organic compound emit light. | 2013-09-05 |
20130228763 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention has an object of providing a light-emitting device including an OLED formed on a plastic substrate, which prevents degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light-emitting layer in the OLED (“barrier films”) and a film having a smaller stress than the barrier films (“stress relaxing film”), the film being interposed between the barrier films, are provided. Owing to a laminate structure, if a crack occurs in one of the barrier films, the other barrier film(s) can prevent moisture or oxygen from penetrating into the organic light emitting layer. The stress relaxing film, which has a smaller stress than the barrier films, is interposed between the barrier films, making it possible to reduce stress of the entire sealing film. Therefore, a crack due to stress hardly occurs. | 2013-09-05 |
20130228764 | ORGANIC EL ELEMENT - Organic EL element is formed by laminating two emitting layers between an anode and a cathode with a hole transporting non-emitting layer interposed between the two emitting layers. Emitting layer on an anode side is a hole transporting emitting layer, emitting layer on a cathode side is an electron transporting emitting layer. Non-emitting layer includes at least one energy transfer auxiliary material in a hole transporting material. In the organic EL element, the energy transfer auxiliary material transfers excitation energy in the non-emitting layer to the emitting layers adjacent to the non-emitting layer effectively, so that luminous efficiency of the emitting layers can be enhanced. It is difficult for holes to reach an electron transport layer so that the electron transport layer is not deteriorated, and the organic EL element can have a long life. | 2013-09-05 |
20130228765 | CARBAZOLE DERIVATIVE, AND LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE USING THE CARBAZOLE DERIVATIVE - It is an object of the present invention to provide a material which is excellent in a hole injecting property and a hole transporting property, and to provide a light emitting element and a light emitting device using a material which is excellent in a hole injecting property and a hole transporting property. The present invention provides a carbazole derivative represented by a general formula (1). The carbazole derivative according to the present invention is excellent in the hole injecting property. By using the carbazole derivative according to the present invention as a hole injecting material for a hole injecting layer of a light emitting element, a driving voltage can be reduced. In addition, a lower driving voltage, improvement of the luminous efficiency, a longer life time, and higher reliability can be realized by applying the material to a light emitting element or a light emitting device. | 2013-09-05 |
20130228766 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, LIGHTING DEVICE, AND ELECTRONIC DEVICE - An object is to provide a light-emitting element which exhibits light emission with high luminance and can be driven at low voltage. Another object is to provide a light-emitting device or an electronic device with reduced power consumption. Between an anode and a cathode, n (n is a natural number of two or more) EL layers are provided, where between a first EL layer and a second EL layer, a first layer containing any of an alkali metal, an alkaline earth metal, a rare earth metal, an alkali metal compound, an alkaline earth metal compound, and a rare earth metal compound, a second layer containing a material having a high electron-transporting property in contact with the first layer, and a region containing a material having a high hole-transporting property and an acceptor material in contact with the second layer are provided in this order from the anode side. | 2013-09-05 |
20130228767 | MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES - The present invention relates to a mixture comprising a) a polymer which contains at least one L=X structural unit, b) a triplet emitter compound and c) a carbazole compound or a soluble neutral molecule. The invention furthermore relates to organic electroluminescent devices which contain the mixture according to the invention. | 2013-09-05 |
20130228768 | QUINOLINO[3,2,1-KL]PHENOXAZINE COMPOUND AND ORGANIC LIGHT EMITTING ELEMENT USING THE SAME - Provided is an excellent organic light emitting element having high emission efficiency and a low drive voltage. The organic light emitting element includes an anode, a cathode, and an organic compound layer disposed between the anode and the cathode, in which the organic compound layer includes a quinolino[3,2,1-kl]phenoxazine compound represented by the following general formula [1]: | 2013-09-05 |
20130228769 | DOUBLE-SIDED LUMINESCENT ORGANIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed are a double-sided luminescent organic light emitting device and the manufacturing method thereof. The double-sided luminescent organic light emitting device comprises a transparent substrate ( | 2013-09-05 |
20130228770 | INDOLOPHENOXAZINE COMPOUND AND ORGANIC LIGHT EMITTING DEVICE USING THE SAME - Provided is an organic light emitting device having high emission efficiency and excellent driving durability. The organic light emitting device includes an anode, a cathode, and an organic compound layer disposed between the anode and the cathode, in which the organic compound layer includes an indolophenoxazine compound represented by the following general formula [1]: | 2013-09-05 |
20130228771 | SEMICONDUCTOR STRUCTURE AND METHOD FOR ITS PRODUCTION - The present invention relates to a semiconductor structure and a method for its production, the semiconductor structure comprising at least one conductor region | 2013-09-05 |
20130228772 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes a substrate; a gate electrode on the substrate; a semiconductor pattern on the gate electrode; a source electrode on the semiconductor pattern; a drain electrode on the semiconductor pattern and spaced apart from the source electrode; a pixel electrode connected to the drain electrode; and a common electrode partially overlapped with the pixel electrode. The semiconductor pattern is in a same layer of the thin film transistor substrate as the pixel electrode and has an electrical property different from an electrical property of the pixel electrode. | 2013-09-05 |
20130228773 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A memory device which consumes low power and which is shared by a plurality of processors is provided. In addition, a memory device whose capacity is high and which is shared by a plurality of processors is provided. A data write transistor of a memory device is manufactured with a material capable of achieving a sufficiently low off-state current of a transistor (e.g., an oxide semiconductor material that is a wide band gap semiconductor). The memory device has a memory cell including at least one data write transistor, at least one data storage transistor, and at least two data read transistors. | 2013-09-05 |
20130228774 | SEMICONDUCTOR DEVICE - To inhibit a metal element contained in a glass substrate from being diffused into a gate insulating film or an oxide semiconductor film. A semiconductor device includes a glass substrate, a base insulating film formed using metal oxide over the glass substrate, a gate electrode formed over the base insulating film, a gate insulating film formed over the gate electrode, an oxide semiconductor film which is formed over the gate insulating film and overlapping with the gate electrode, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In a region of the base insulating film that is present in a range of 3 nm or less from a surface of the base insulating film, the concentration of a metal element contained in the glass substrate is less than or equal to 1×10 | 2013-09-05 |
20130228775 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR FORMING OXIDE FILM - One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×10 | 2013-09-05 |
20130228776 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured. | 2013-09-05 |
20130228777 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a bottom-gate thin film transistor using the stack of the first oxide semiconductor layer and the second oxide semiconductor layer, an oxide insulating layer serving as a channel protective layer is formed over and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the insulating layer, an oxide insulating layer covering a peripheral portion (including a side surface) of the stack of the oxide semiconductor layers is formed. | 2013-09-05 |
20130228778 | Methods of Extracting Fin Heights and Overlap Capacitance and Structures for Performing the Same - A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance. | 2013-09-05 |
20130228779 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes out a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose out the fourth cavity. | 2013-09-05 |
20130228780 | METHOD OF FORMATION OF COHERENT WAVY NANOSTRUCTURES (VARIANTS) - The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps. | 2013-09-05 |
20130228781 | FABRICATION METHOD OF A PIXEL STRUCTURE AND A PIXEL STRUCTURE - A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion. | 2013-09-05 |
20130228782 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor. | 2013-09-05 |
20130228783 | Display Device and Method for Driving the Same - A semiconductor device having a configuration hardly generating variations in the current value due to a deteriorated EL element is to be provided. A capacitance element is disposed between the gate and the source of a driving TFT, video signals are inputted to the gate electrode, and then it is in the floating state. Suppose an EL element is deteriorated and the anode potential rises, that is, the source potential of the driving TFT rises, the potential of the gate electrode of the driving TFT, being in the floating state by coupling of the capacitance element, is to rise by the same amount. Accordingly, even when the anode potential rises due to the deteriorated EL element, the rise is added to the gate electrode potential as it is, and the gate-source voltage of the driving TFT is allowed to be constant. | 2013-09-05 |
20130228784 | LUMINESCENT DEVICE AND PROCESS OF MANUFACTURING THE SAME - In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used. | 2013-09-05 |
20130228785 | LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE - An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support | 2013-09-05 |
20130228786 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device including a thin film transistor (TFT) on a substrate; an organic light emitting diode (OLED) electrically connected to the TFT, the OLED including a pixel electrode, an organic layer, and an opposite electrode; a pixel defining layer (PDL) on the pixel electrode, the PDL including an opening that exposes at least one portion of the pixel electrode; and a light scattering layer between the pixel electrode and the organic layer. | 2013-09-05 |
20130228787 | SEMICONDUCTOR DEVICE - A semiconductor device has a shield plate electrode connected to a source terminal electrode near a drain electrode. The source terminal electrode is arranged between an active region AA and a drain terminal electrode, and a shield plate electrode is connected to the source terminal electrode. | 2013-09-05 |
20130228788 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes, a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, the source finger electrode is close to the gate finger electrode; a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, the drain finger electrode faces the source finger electrode via the gate finger electrode; and a shield plate electrode which is arranged on the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode via an insulating layer, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other. | 2013-09-05 |
20130228789 | SEMICONDUCTOR DEVICE - A semiconductor device has a shield plate electrode short-circuited to a source electrode near the drain electrode. The shield plate electrode is connected to the source terminal electrode which has a VIA hole via the first line of air-bridge structure or overlay structure. | 2013-09-05 |
20130228790 | SEMICONDUCTOR DEVICE - A semiconductor device, comprising: a substrate; a plurality of gate finger electrodes which are arranged on the substrate; a plurality of source finger electrodes which are arranged on the substrate, each source finger electrode is close to the gate finger electrode; a plurality of drain finger electrodes which are arranged on the substrate, each drain finger electrode faces the source finger electrode via the gate finger electrode; a shield plate electrode which is arranged via an insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other; and a slot VIA hole which is formed in the substrate under the source finger electrode and is connected to the source finger electrode. | 2013-09-05 |
20130228791 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting device includes a first conductive semiconductor layer including a V-shaped recess in a cross-sectional view. An active layer is disposed on the first conductive semiconductor layer, conforming to the shape of the V-shaped recess. An intermediate layer is disposed on the active layer and is doped with a first impurity. A second conductive semiconductor layer is disposed on the intermediate layer. The intermediate layer includes a first intermediate layer and a second intermediate layer. The first intermediate layer is disposed on the active layer, conforming to the shape of the V-shape recess. The second intermediate layer is disposed on the first intermediate layer and includes a protrusion to fill the V-shaped recess. | 2013-09-05 |
20130228792 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a substrate having a through hole formed in a thickness direction thereof and a conductive nanowire provided in at least a portion of the through hole, and a light emitting structure formed on the substrate and including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. | 2013-09-05 |
20130228793 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer. | 2013-09-05 |
20130228794 | Stacked Half-Bridge Package with a Common Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 2013-09-05 |
20130228795 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode. | 2013-09-05 |
20130228796 | HIGH VOLTAGE SEMICONDUCTOR DEVICES INCLUDING ELECTRIC ARC SUPPRESSION MATERIAL AND METHODS OF FORMING THE SAME - A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess. | 2013-09-05 |
20130228797 | SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - To provide a silicon carbide substrate having at least one or more main surfaces, including: a plurality of encapsulated regions inside, wherein the plurality of encapsulated regions are distributed in a direction approximately parallel to one of the main surfaces, with each encapsulated region positioned at a distance of 100 nm or more and 100 μm or less from the main surfaces to inside a substrate, and each encapsulated region having a width of 100 nm or more and 100 μm or less in a direction parallel to the main surfaces. | 2013-09-05 |
20130228798 | LIGHT-EMITTING DIODE CHIP AND METHOD FOR PRODUCING THE SAME - A light-emitting diode chip is specified, comprising
| 2013-09-05 |
20130228799 | METHOD FOR PRODUCING A SILICONE FOIL, SILICONE FOIL AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT COMPRISING A SILICONE FOIL - A method of producing a silicone foil for use in an optoelectronic semiconductor component by molding including introducing a mold foil into a mold, introducing a carrier foil into the mold, wherein the carrier foil is fitted on a substrate foil and the substrate foil projects laterally beyond the carrier foil at least in places within a cavity of the mold, providing and applying a silicone base composition to the mold foil or to the carrier foil, molding the silicone base composition for the silicone foil in the mold between the mold foil and the carrier foil, wherein the silicone base composition is brought into contact with the substrate foil in at least one overlap region laterally alongside the carrier foil, removing the mold foil from the silicone foil, and separating the overlap region. | 2013-09-05 |
20130228800 | White-Light Emitter Having a Molded Phosphor Sheet and Method of Making Same - A white-light emitter is disclosed, in which a silicone sheet is laminated between a pair of optically clear plastic sheets. The silicone sheet lacks the ability to retain its shape, while the three sheets, when sealed together, can retain a shape. The silicone sheet includes at least one phosphor, with a phosphor concentration between two percent and ten percent. The silicone sheet may be produced by molding. Compared to comparable silicone parts made by extrusion, the molded parts may show less part-to-part variation in color temperature, may be run in significantly smaller batches or as one-offs, and may allow the silicone and phosphor material to be mixed by hand or with a relatively simple mixing machine. In some cases, the sheets are sealed together at their perimeters and include a margin around the phosphor sheet. In some cases, the phosphor sheet includes a mixture of different phosphors. | 2013-09-05 |
20130228801 | Organic Light Emitting Diode Display and Method for Manufacturing the Same - An organic light emitting diode display includes a substrate, first electrodes patterned on the substrate, pixel defining layers on the substrate to separate the first electrodes corresponding to pixel units, light emitting layers on the first electrodes and separated corresponding to the pixel units, and a second electrode on the light emitting layers, wherein the pixel defining layers have pores. | 2013-09-05 |
20130228802 | LIGHT-EMITTING DIODE DEVICE - A two dimensional array light-emitting diode device is disclosed, which includes a transparent substrate including a first surface; a plurality of adjacent light-emitting diode units arranged on the first surface, wherein each of the light-emitting diode units including a plurality of sides and a circumference; and a plurality of conductive connecting structures arranged on the first surface, electrically connecting the plurality of light-emitting diode units mentioned above; wherein the sides of each of the light-emitting diode units have a plurality of vertical distances between the closest light-emitting diode units, and when the plurality of vertical distances larger than 50 μm, the sides are not near the closest light-emitting diode units; wherein the ratio of the total length of the sides not near the light-emitting diode units of each light-emitting diode unit and the circumference of the light-emitting diode unit is larger than 50%. | 2013-09-05 |
20130228803 | LIGHT-EMITTING DEVICE, LIGHTING DEVICE, LIGHT-EMITTING DEVICE ASSEMBLY, AND METHOD FOR PRODUCING LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate including a mirror surface region on its upper surface, a semiconductor light-emitting element disposed in the mirror surface region, and an encapsulating layer joined onto the upper surface of the substrate. The encapsulating layer includes a lower layer that is in contact with the upper surface of the substrate, covers the surrounding of the semiconductor light-emitting element, and contains phosphor; and an upper layer that is positioned on the lower layer, and has a larger phosphor content per unit area than that of the lower layer. | 2013-09-05 |
20130228804 | METHOD AND SYSTEM FOR FORMING LED LIGHT EMITTERS - A method for forming a flexible sheet of LED light emitters includes forming a micro lens sheet having a plurality of micro lenses, forming a phosphor sheet including a wave-length converting material, forming a flexible circuit sheet, forming a ceramic substrate sheet including a plurality of LED light emitters, and forming a support substrate including a thermally conductive material. The method also includes attaching the above sheets to form a stack including, from top to bottom, the micro lens sheet, the phosphor sheet, the flexible circuit sheet, the ceramic substrate sheet, and the support substrate. | 2013-09-05 |
20130228805 | LIGHT-EMITTING ELEMENT PACKAGE AND DISPLAY DEVICE - A light-emitting element package includes plural substrates and plural light-emitting elements disposed on each of the substrates. The light-emitting elements are arranged on each substrate so that an arrangement of the light-emitting elements on each substrate becomes same in an arrangement state in which the substrates are arranged with a regular pitch along a first direction and a second direction which are directions perpendicular to the substrate. The light-emitting elements are arranged on each substrate so that a pitch of the light-emitting elements on each substrate is equal to a pitch of the light-emitting elements between the neighboring substrates in the arrangement state of the substrates. | 2013-09-05 |
20130228806 | LIGHT EMITTING DEVICE WITH GRADED COMPOSITION HOLE TUNNELING LAYER - A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device. | 2013-09-05 |
20130228807 | METHOD OF SEPARATING NITRIDE FILMS FROM GROWTH SUBSTRATES BY SELECTIVE PHOTO-ENHANCED WET OXIDATION AND ASSOCIATED SEMICONDUCTOR STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a semiconductor structure may comprise: a first substrate structure; a III-nitride structure bonded with the first substrate structure; a plurality of air gaps formed between the first substrate structure and the III-nitride structure; and a III-oxide layer formed on surfaces around the air gaps, wherein a portion of the III-nitride structure including surfaces around the air gaps is transformed into the III-oxide layer by a selective photo-enhanced wet oxidation, and the III-oxide layer is formed between an untransformed portion of the III-nitride structure and the first substrate structure. | 2013-09-05 |
20130228808 | Light emitter with metal-oxide coating - A light emitting device based on a AlInGaN materials system wherein a coating is used to improve the extraction of light from a device. A coating has a very low optical loss and an index of refraction greater than 2. In a preferred embodiment the coating is made from Ta | 2013-09-05 |
20130228809 | SEMICONDUCTOR STRUCTURE FOR SUBSTRATE SEPARATION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes a temporary substrate; a first semiconductor layer positioned on the temporary substrate; a dielectric layer comprising a plurality of patterned nano-scaled protrusions disposed on the first semiconductor layer; a dielectric layer surrounding the plurality of patterned nano-scaled protrusions and disposed on the first semiconductor layer; and a second semiconductor layer positioned on the dielectric layer, wherein the top surfaces of the patterned nano-scaled protrusions are in contact with the bottom of the second semiconductor layer. An etching process is performed on the semiconductor structure to separate the first semiconductor layer and the second semiconductor layer, in order to detach the temporary substrate from the second semiconductor layer and transfer the second semiconductor layer to a permanent substrate. | 2013-09-05 |
20130228810 | SOLID STATE LIGHTING LUMINAIRE AND A FABRICATION METHOD THEREOF - A solid state lighting luminaire, which comprises a solid state light source, an encapsulated structure, and a first phosphor, is provided. The encapsulated structure encapsulates the solid state light source and has an outside illuminating surface. The first phosphor is patterned to cover a portion of the outside illuminating surface for down-converting the illumination from the solid state light source. | 2013-09-05 |
20130228811 | LIGHT SOURCE DEVICE HAVING LIGHT EMITTING DIODE - An LED light source device includes an LED light source, a first powder layer located at a light path of the LED light source and a lamp shell located around the LED light source and the first powder layer. The lamp shell defines a receiving room. A second powder layer is formed on an inner surface of the lamp shell. The first powder layer and the second powder layer each have a characteristic of scattering light. | 2013-09-05 |
20130228812 | LIGHT EMITTING DEVICE AND BACKLIGHT SYSTEM USING THE SAME - A light emitting device is provided that includes a light emitting element emitting primary light, and a wavelength conversion portion provided on the light emitting element, absorbing a part of the primary light and emitting secondary light, in which the wavelength conversion portion is made of a plurality of resin layers including at least a first wavelength conversion portion made of a resin layer containing a rare earth-activated phosphor or a transition metal element-activated phosphor, and a second wavelength conversion portion made of a resin layer containing a nanocrystalline phosphor. The first wavelength conversion portion is disposed closer to the light emitting element than the second wavelength conversion portion is. | 2013-09-05 |
20130228813 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device, a method of manufacturing the same and a light emitting device package. The light emitting device of the embodiment includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers; a fluorescent layer on the light emitting structure; and a light extracting structure on the fluorescent layer. The light extracting structure extracts light, which is generated in the light emitting structure and incident into an interfacial surface between the fluorescent layer and the light extracting structure, to an outside of the light emitting structure. | 2013-09-05 |
20130228814 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor light-emitting device is provided. The semiconductor light-emitting device may include a light-emitting structure, an electrode, an ohmic layer, an electrode layer, an adhesion layer, and a channel layer. The light-emitting structure may include a compound semiconductor layer. The electrode may be disposed on the light-emitting structure. The ohmic layer may be disposed under the light-emitting structure. The electrode layer may include a reflective metal under the ohmic layer. The adhesion layer may be disposed under the electrode layer. The channel layer may be disposed along a bottom edge of the light-emitting structure. | 2013-09-05 |
20130228815 | VERTICAL SOLID-STATE TRANSDUCERS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS - Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side. | 2013-09-05 |
20130228816 | Light Emitting Device - A light emitting device includes a second metal layer, a second semiconductor layer on the second metal layer, an active layer on the second semiconductor layer, a first semiconductor layer on the active layer, a first metal layer on the first semiconductor layer, an insulating layer between the second metal layer and the second semiconductor layer at a peripheral portion of an upper surface of the second metal layer, and a passivation layer surrounding lateral surfaces of the insulating layer, the second semiconductor layer, the active layer, and the first semiconductor layer, the passivation layer being on the second metal layer, wherein a lateral surface of the insulating layer is adjacent to a lateral surface of the second metal layer, and wherein a lowermost surface of the passivation layer is disposed lower than a lowermost surface of the insulating layer. | 2013-09-05 |
20130228817 | WAFER-LEVEL PACKAGE STRUCTURE OF LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package. | 2013-09-05 |
20130228818 | OPTICAL DEVICE - A semiconductor light emitting device includes a laminate section in which p-type layer | 2013-09-05 |
20130228819 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate. A first and a second electrical contact layer are arranged at least in regions between the carrier substrate and the semiconductor layer sequence and are electrically insulated from one another by an electrically insulating layer. A mirror layer is arranged between the semiconductor layer sequence and the carrier substrate. The minor layer adjoins partial regions of the first electrical contact layer and partial regions of the electrically insulating layer. The partial regions of the electrically insulating layer which adjoin the mirror layer are covered by the second electrical contact layer in such a way that at no point do they adjoin a surrounding medium of the optoelectronic semiconductor chip. | 2013-09-05 |
20130228820 | Optoelectronic Semiconductor Component and Method for Producing it - An optoelectronic semiconductor component includes a carrier and a semiconductor chip. The semiconductor chip includes an active layer for generating electromagnetic radiation. The carrier includes electrical conductor tracks on a top side for making electrical contact with the semiconductor chip. The semiconductor chip is fixed on the carrier. The carrier contains Si3N4 or molybdenum. A method for producing such a component is furthermore specified. | 2013-09-05 |
20130228821 | Dendritic Metal Structures, Methods for Making Dendritic Metal Structures, and Devices Including Them - The present invention relates generally to dendritic metal structures and devices including them. The present invention also relates particularly to methods for making dendritic metal structures without the use of solid electrolyte materials. In one aspect, a method for constructing a dendritic metal structure includes providing a substrate having a surface and a cathode disposed on the surface; providing an anode comprising a metal; and disposing a liquid on the surface of the substrate, such that the liquid is in electrical contact with the anode and the cathode; and then applying a bias voltage across the cathode and the anode sufficient to grow the dendritic metal structure extending from the cathode. The methods described herein can be used to grow dedritic metal electrodes, which can be useful in devices such as LEDs, touchscreens, solar cells and photodetectors. | 2013-09-05 |
20130228822 | VERTICAL POWER COMPONENT - A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring. | 2013-09-05 |
20130228823 | REVERSE-CONDUCTING SEMICONDUCTOR DEVICE - A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A first layer of a first conductivity type is created on a collector side before a second layer of a second conductivity type is created on the collector side. An electrical contact in direct electrical contact with the first and second layers is created on the collector side. A shadow mask is applied on the collector side, and a third layer of the first conductivity type is created through the shadow mask. At least one electrically conductive island, which is part of a second electrical contact in the finalized RC-IGBT, is created through the shadow mask. The island is used as a mask for creating the second layer, and those parts of the third layer which are covered by the island form the second layer. | 2013-09-05 |
20130228824 | SEMICONDUCTOR ELECTROSTATIC PROTECTION CIRCUIT DEVICE - An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region. | 2013-09-05 |
20130228825 | Method of Forming EPI Film in Substrate Trench - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation. | 2013-09-05 |
20130228826 | MOS Devices with Modulated Performance and Methods for Forming the Same - A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance. | 2013-09-05 |
20130228827 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND TRANSISTOR CIRCUIT - A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor. | 2013-09-05 |
20130228828 | RANGE SENSOR AND RANGE IMAGE SENSOR - A range sensor includes a charge generating region, a signal charge collecting region, an unnecessary charge collecting region, a photogate electrode, a transfer electrode, and an unnecessary charge collecting gate electrode. Outer peripheries of the charge generating region extend to sides of a polygonal pixel region except for corner portions thereof. The signal charge collecting region is disposed at a center portion of the pixel region and inside the charge generating region so as to be surrounded by the charge generating region. The unnecessary charge collecting region is disposed in the corner portion of the pixel region and outside the charge generating region. The photogate electrode is disposed on the charge generating region. The transfer electrode is disposed between the signal charge collecting region and the charge generating region. The unnecessary charge collecting gate electrode is disposed between the unnecessary charge collecting region and the charge generating region. | 2013-09-05 |
20130228829 | TWO-TRANSISTOR PIXEL ARRAY - A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device. | 2013-09-05 |
20130228830 | GATE STRUCTURE FOR SEMICONDUCTOR DEVICE - A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin. | 2013-09-05 |
20130228831 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness. | 2013-09-05 |
20130228832 | FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD - A fin field effect transistor and a method for forming the fin field effect transistor are provided. In an exemplary method, the Fin FET can be formed by forming a dielectric layer and a fin on a semiconductor substrate. The fin can be formed throughout an entire thickness of the dielectric layer and a top surface of the fin is higher than a top surface of the dielectric layer. The fin can be annealed using a hydrogen-containing gas and a repairing gas containing at least an element corresponding to a material of the fin. A gate structure can be formed on the top surface of the dielectric layer and at least on sidewalls of a length portion of the fin after the annealing process. | 2013-09-05 |
20130228833 | SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES - A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration. | 2013-09-05 |
20130228834 | CONTACT ETCH STOP LAYERS OF A FIELD EFFECT TRANSISTOR - A field effect transistor, the field effect transistor includes a substrate including a surface and a gate structure including sidewalls and a top surface, the gate structure being positioned over the substrate. The field effect transistor further includes a spacer adjacent to the sidewalls of the gate structure and a first contact etch stop layer over the spacer and extending along the surface of the substrate. The field effect transistor further includes an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure. The field effect transistor further includes a second contact etch stop layer over at least a portion of the top surface of the gate structure. | 2013-09-05 |
20130228835 | SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE - An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region. | 2013-09-05 |
20130228836 | NON-PLANAR SEMICONDUCTOR STRUCTURE - A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure. | 2013-09-05 |
20130228837 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 MPa to −700 MPa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted. Preferably, the support film has a rate etched by hydrofluoric acid of 1.0 nm/sec or less and more preferably, the support film includes a silicon carbon nitride film. | 2013-09-05 |
20130228838 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential. | 2013-09-05 |
20130228839 | SEMICONDUCTOR MEMORY DEVICE - To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided. | 2013-09-05 |
20130228840 | EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION - A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. | 2013-09-05 |
20130228841 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing nonvolatile semiconductor memory device including forming a stacked body by alternately stacking an electrode layer and a layer-to-be-etched, and forming an oxidized layer between the layer-to-be-etched provided at least in any side of an upper side and a lower side of the electrode layer and the electrode layer. The method can include forming a groove which passes through the stacked body. The method can include embedding an insulating body within the groove. The method can include forming a hole which passes through the stacked body. The method can include selectively removing the layer-to-be-etched via the hole. The method can include forming a charge storage layer in an inner side of the hole. The method can include forming a channel body layer in an inner side of the charge storage layer. | 2013-09-05 |
20130228842 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer. | 2013-09-05 |
20130228843 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a memory gate pattern on a substrate, and a non-memory gate pattern on the substrate, the non-memory gate pattern being spaced apart from the memory gate pattern, wherein the non-memory gate pattern includes an ohmic layer, and the memory gate pattern is provided without an ohmic layer. | 2013-09-05 |
20130228844 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other. | 2013-09-05 |
20130228845 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 2013-09-05 |
20130228846 | NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH - The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line. | 2013-09-05 |
20130228847 | TFT Floating Gate Memory Cell Structures - A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 2013-09-05 |
20130228848 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a lower layer connection object, a stacked body, an insulating film, and a via. The stacked body has a plurality of insulating layers and a plurality of electrode layers alternately stacked on the lower layer connection object. The stacked body has a staircase structure unit. The via connects uppermost electrode layer at each step of the staircase structure unit and the lower layer connection object through the via hole. The via has an upper part provided on and in contact with a top face of the uppermost electrode layer, and a penetrating part provided to be thinner than the upper part inside the insulating film in the via hole. The penetrating part connects the upper part and the lower layer connection object. | 2013-09-05 |
20130228849 | NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF - A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film. | 2013-09-05 |
20130228850 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively. | 2013-09-05 |
20130228851 | MEMORY DEVICE PROTECTION LAYER - A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells. | 2013-09-05 |
20130228852 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask. | 2013-09-05 |
20130228853 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes: a substrate; a stacked body including a plurality of electrode layers and a plurality of insulating layers, both of them being alternately stacked on the substrate; a cap film provided in contact with the electrode layer within a hole formed to penetrate the stacked body; an insulating film provided on a side wall of the cap film and including a charge accumulation film; and a channel body provided on a side wall of the insulating film. The cap film includes a protrusion portion protruding toward the insulating film. In the cap film, a film thickness of a portion where the protrusion portion is provided in a direction in which the protrusion portion protrudes is larger than a film thickness of the other portions where the protrusion portion is not provided. | 2013-09-05 |
20130228854 | POWER FIELD EFFECT TRANSISTOR - A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate. | 2013-09-05 |
20130228855 | Vertical Semiconductor Device with Thinned Substrate - A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region. | 2013-09-05 |