36th week of 2014 patent applcation highlights part 13 |
Patent application number | Title | Published |
20140246716 | MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described. | 2014-09-04 |
20140246717 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions; a plurality of control gate electrodes; a charge storage layer; a first insulating film provided between the charge storage layer and first semiconductor regions; a second insulating film provided between the charge storage layer and control gate electrodes; and an element isolation region provided between the plurality of first semiconductor regions, and the element isolation region being in contact with the first insulating film and a first portion of the charge storage layer on the first insulating film side. Each of the plurality of control gate electrodes is in contact with a second portion other than the first portion of the charge storage layer. The charge storage layer includes a silicon-containing layer in contact with the first insulating film and a silicide-containing layer provided on the silicon-containing layer. | 2014-09-04 |
20140246718 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer. | 2014-09-04 |
20140246719 | Non-Volatile Push-Pull Non-Volatile Memory Cell Having Reduced Operation Disturb and Process for Manufacturing Same - A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel. | 2014-09-04 |
20140246720 | INTEGRATED CIRCUIT PROTECTED FROM SHORT CIRCUITS CAUSED BY SILICIDE - An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region. | 2014-09-04 |
20140246721 | SEMICONDUCTOR DEVICE - A semiconductor device including: a first conductivity type n-type drift layer; a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer; a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer; and a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer. Thus, it is possible to provide a semiconductor device having a stable and high breakdown voltage termination structure in which the length of a termination structure region is small as well as the immunity to the influence of external charge is high. | 2014-09-04 |
20140246722 | Power MOS Transistor with Improved Metal Contact - A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves. | 2014-09-04 |
20140246723 | METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR - A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide. | 2014-09-04 |
20140246724 | MEMORY DEVICES - Memory devices include a substrate including first to third regions, a memory element on the first region, a first transistor on the second region closer to the first region than to the third region and including a spacer filled with an insulating material, and a second transistor on the third region and including a spacer filled with air. | 2014-09-04 |
20140246725 | Integrated Circuit Memory Devices Including Parallel Patterns in Adjacent Regions - An integrated circuit memory device includes a substrate having a sense amplifier region or a word line driver region comprising circuits configured to operate a memory cell array. The substrate further includes a conjunction region adjacent the sense amplifier region or word line driver region and defining a boundary therebetween. A plurality of gate patterns extends on the substrate. The gate patterns include peripheral gate patterns extending in the sense amplifier region or word line driver region, and conjunction gate patterns extending in the conjunction region. Ones of the conjunction gate patterns and ones of the peripheral gate patterns proximate the boundary extend substantially parallel along the boundary between the conjunction region and the sense amplifier region or word line driver region. | 2014-09-04 |
20140246726 | METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES - A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper. | 2014-09-04 |
20140246727 | WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 2014-09-04 |
20140246728 | SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 2014-09-04 |
20140246729 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern. | 2014-09-04 |
20140246730 | EMBEDDED RESISTOR - An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench. | 2014-09-04 |
20140246731 | Voids in STI Regions for Forming Bulk FinFETs - An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric. | 2014-09-04 |
20140246732 | Circuit Incorporating Multiple Gate Stack Compositions - An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. | 2014-09-04 |
20140246733 | Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section - A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing. | 2014-09-04 |
20140246734 | REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS - A semiconductor comprising a multilayer structure which prevents oxidization of the titanium nitride layer that protects a high-K dielectric layer is provided. Replacement metal gates are over the multilayer structure. A sacrificial polysilicon gate structure is deposited first. The sacrificial polysilicon gate structure is then removed, and the various layers of the replacement metal gate structure are deposited in the space previously occupied by the sacrificial polysilicon gate structure. | 2014-09-04 |
20140246735 | METAL GATE STRUCTURE FOR SEMICONDUCTOR DEVICES - Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum. | 2014-09-04 |
20140246736 | High-K Film Apparatus and Method - Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied. | 2014-09-04 |
20140246737 | MEMS VIBRATOR, METHOD OF MANUFACTURING MEMS VIBRATOR, ELECTRONIC DEVICE, AND MOVING OBJECT - A MEMS vibrator includes an insulating portion, a first electrode provided on one surface of the insulating portion, a fixed portion, and a function portion, a second electrode provided so that at least a portion thereof overlaps the first electrode at a distance therefrom. The second electrode comes into contact with the function portion and extends from the fixed portion. | 2014-09-04 |
20140246738 | Top Port MEMS Cavity Package and Method of Manufacture Thereof - A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded said to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture. | 2014-09-04 |
20140246739 | Top Port MEMS Cavity Package and Method of Manufacture Thereof - A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture. | 2014-09-04 |
20140246740 | IMPLANTATION OF GASEOUS CHEMICALS INTO CAVITIES FORMED IN INTERMEDIATE DIELECTRICS LAYERS FOR SUBSEQUENT THERMAL DIFFUSION RELEASE - The present invention generally relates to methods for increasing the lifetime of MEMS devices by reducing the landing velocity on switching by introducing gas into the cavity surrounding the switching element of the MEMS device. The gas is introduced using ion implantation into a cavity close to the cavity housing the switching element and connected to that cavity by a channel through which the gas can flow from one cavity to the other. The implantation energy is chosen to implant many of the atoms close to the inside roof and floor of the cavity so that on annealing those atoms diffuse into the cavity. The gas provides gas damping which reduces the kinetic energy of the switching MEMS device which then should have a longer lifetime. | 2014-09-04 |
20140246741 | MAGNETORESISTIVE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. The first terminal, a bit line, is connected to the top magnetic reference layer, and the second terminal is located at the middle recording layer which is connected to the underneath select CMOS transistor through a VIA and the third one, a digital line, is a voltage gate with a narrow pillar underneath the memory layer across an insulating functional layer which is used to reduce the write current by manipulating the perpendicular anisotropy of the recording layer. The fabrication includes formation of a bottom electrode, formation of digital line, formation of memory cell & VIA connection and formation of the top bit line. Photolithography patterning and hard mask etch are used to form the digital line pillar and small memory pillar. Ion implantation is used to convert a buried dielectric layer outside the center memory pillar into an electric conductive path between middle recording layer and underneath CMOS transistor. | 2014-09-04 |
20140246742 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first free layer having a magnetic direction that changes according to a direction and an amount of a first current, a first tunnel insulating layer arranged on the first free layer, a pinned layer, arranged on the first tunnel insulating layer, having a magnetic direction set to a first direction, a second tunnel insulating layer arranged on the pinned layer, and a second free layer, arranged on the second tunnel insulating layer, having a magnetic direction that changes according to a direction and an amount of a second current. | 2014-09-04 |
20140246743 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, SIGNAL TRANSMISSION/RECEPTION METHOD USING SUCH SEMICONDUCTOR DEVICE, AND TESTER APPARATUS - A semiconductor device includes a substrate, an internal circuit including a plurality of transistors provided over the substrate, an insulating film provided over the substrate, a bonding pad provided over the insulating film, an inductor being formed in the insulating film, the inductor carrying out a signal transmission/reception to/from an external device in a non-contact manner by an electromagnetic induction and being electrically coupled to the internal circuit. The inductor includes a first conducting layer, and the bonding pad includes a second conducting layer. The first conducting layer includes a lower level layer than the second conducting layer in a thickness direction of the substrate. Ina plan view, the inductor includes a first portion overlapping the bonding pad and a second portion not overlapping the bonding pad. | 2014-09-04 |
20140246744 | METHOD OF MANUFACTURING RADIATION DETECTOR AND RADIATION DETECTOR - A graphite substrate is accommodated into a chamber where vacuum drawing is performed via a pump. Thereafter, carbon is heated under vacuum, whereby impurities in the carbon are evaporated causing the carbon to be purified. The carbon in the graphite substrate is purified, achieving suppression of the impurities as donor/acceptor elements and also metallic elements in the semiconductor layer of 0.1 ppm or less, the impurities being contained in the carbon in the graphite substrate. As a result, occurrence of leak current or an abnormal leak point enables to be suppressed, and thus abnormal crystal growth in the semiconductor layer enables to be suppressed. | 2014-09-04 |
20140246745 | CHIP SIZE PACKAGE (CSP) - A chip size package (CSP) includes an antenna for wireless communication, used in signal transmission and reception with external substrates, the antenna being formed as a wiring of a rewiring layer, the rewiring layer being disposed between a silicon layer and solder bumps. | 2014-09-04 |
20140246746 | OPTICAL-TO-ELECTRICAL CONVERTER UNIT AND SEMICONDUCTOR LIGHT-RECEIVING DEVICE - An optical-to-electrical converter unit includes a substrate having front and back surfaces; an optical waveguide unit; and an optical-to-electrical converter. The optical-to-electrical converter includes a light-receiving element optically coupled to the optical waveguide unit; a capacitance element including first and second conductive layers and an insulating layer disposed between the first and second conducive layers; an electrode pad electrically connected to the light-receiving element; a back electrode formed on the back surface of the substrate; and a via electrode extending from the front surface to the back surface of the substrate. The optical waveguide unit, the light-receiving element, the capacitance element, and the electrode pad are formed on the front surface. The first conductive layer of the capacitance element is electrically connected to the light-receiving element and the electrode pad. The second conductive layer of the capacitance element is electrically connected to the back electrode through the via electrode. | 2014-09-04 |
20140246747 | POLYMERIC BINDERS INCORPORATING LIGHT-DETECTING ELEMENTS AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder. | 2014-09-04 |
20140246748 | IMAGE SENSORS WITH SMALL PIXELS HAVING HIGH WELL CAPACITY - An image sensor having small pixels with high charge storage capacity, low dark current, no image lag, and good blooming control may be provided. The high charge storage capacity is achieved by placing a p+ type doped layer under the pixel charge storage region with an opening in it for allowing photo-generated charge carriers to flow from the silicon hulk to the charge storage well located near the surface of the photodiode. A compensating n-type doped implant may be formed in the opening. Image lag is prevented by placing a p− type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. Blooming control is achieved by adjusting the length of the transfer gate in the pixel and thereby adjusting the punch-through potential under the gate. | 2014-09-04 |
20140246749 | INFRARED DETECTOR AND INFRARED IMAGE SENSOR INCLUDING THE SAME - An infrared detector includes at least one infrared absorber provided on a substrate and a plurality of thermocouples. The at least one infrared absorber may include one of a plasmonic resonator and a metamaterial resonator. The plurality of thermocouples may be configured to generate electromotive forces in response to thermal energy generated by the at least one infrared absorber. | 2014-09-04 |
20140246750 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n | 2014-09-04 |
20140246751 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer. | 2014-09-04 |
20140246752 | SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF - Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure. | 2014-09-04 |
20140246753 | HIGH QUALITY FACTOR INDUCTOR IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) - Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls. | 2014-09-04 |
20140246754 | METAL-OXIDE-METAL CAPACITOR - Provided is a capacitor of a semiconductor device. The capacitor can includes a plurality of parallel lower conductive lines in parallel and a plurality of upper conductive lines on the lower conductive lines. Each lower conductive line can have a line width that is different than that of the upper conductive line adjacent to it. | 2014-09-04 |
20140246755 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Hydrogen atoms and crystal defects are introduced into an n− semiconductor substrate by proton implantation. The crystal defects are generated in the n− semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current. | 2014-09-04 |
20140246756 | LITHOGRAPHY METHOD AND DEVICE - Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps. | 2014-09-04 |
20140246757 | THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS - Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure. | 2014-09-04 |
20140246758 | NITROGEN-CONTAINING OXIDE FILM AND METHOD OF FORMING THE SAME - A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %). | 2014-09-04 |
20140246759 | SEMICONDUCTOR DEVICE STRUCTURES COMPRISING A POLYMER BONDED TO A BASE MATERIAL AND METHODS OF FABRICATION - Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures. | 2014-09-04 |
20140246760 | Charge Protection for III-Nitride Devices - A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride. | 2014-09-04 |
20140246761 | FAST RECOVERY SWITCHING DIODE WITH CARRIER STORAGE AREA - A power device (such as a power diode) has a peripheral die area and a central area. The main PN junction of the device is formed by a P+ type region that extends down into an N− type layer. The central portion of the P+ type region has a plurality of openings so mesa structures of the underlying N− type material extend up to the semiconductor surface through the openings. Due to the mesa structures being located in the central portion of the die, there are vertically extending extensions of the PN junction in the central portion of the die. Minority carrier charge storage is more uniform per unit area across the surface of the die. Due to the form of the P+ type region and the mesa structures, the reverse recovery of the PN junction exhibits a soft characteristic. | 2014-09-04 |
20140246762 | SEMICONDUCTOR DEVICE HAVING DEEP WELLS AND FABRICATION METHOD THEREOF - Semiconductor devices and methods of fabricating the same are provided. An insulating film can be disposed on a semiconductor substrate, and insulating film patterns can be formed opening a plurality of areas with predetermined widths by patterning the insulating film. A plurality of ion implantation areas having a first conductivity type can be formed by implanting impurities into the plurality of open areas, and an oxide film pattern can be formed on each of the ion implantation areas. The insulating film patterns can be removed, and ion implantation areas having a second conductivity type can be formed by implanting impurities using the oxide film pattern as a mask. The semiconductor substrate can be annealed at a high temperature to form deep wells. | 2014-09-04 |
20140246763 | SYSTEMS AND METHODS FOR TESTING AND PACKAGING A SUPERCONDUCTING CHIP - Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously. | 2014-09-04 |
20140246764 | ROLLED-UP TRANSMISSION LINE STRUCTURE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT (RFIC) - A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure. | 2014-09-04 |
20140246765 | PRINTED WIRING BOARD - A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer. | 2014-09-04 |
20140246766 | Semiconductor Chip Package - The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements. | 2014-09-04 |
20140246767 | SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME - A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process. | 2014-09-04 |
20140246768 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the front surface of the circuit substrate. The enclosing case is a resin case in which semiconductor elements are installed. The metal part, included inside the enclosing case, includes a first mounting portion, a second mounting portion, and a bus bar. The first mounting portion mounts the circuit substrate on the enclosing case, and is connected to a ground pattern of the circuit substrate when mounting. The second mounting portion mounts an external instrument on the enclosing case, and is grounded when mounting. The bus bar connects the first mounting portion and second mounting portion. | 2014-09-04 |
20140246769 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes an insulating substrate having a semiconductor element mounted thereon; an outer case accommodating the insulating substrate; and a metallic terminal bar disposed above the insulating substrate and fixed to side walls of the outer case at both ends thereof. Each of both ends of the terminal bar at a position close to the side wall of the outer case at a surface on an opposite side to a surface facing the insulating substrate is provided with a pressed groove. | 2014-09-04 |
20140246770 | COPPER NANOROD-BASED THERMAL INTERFACE MATERIAL (TIM) - A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters. | 2014-09-04 |
20140246771 | PACKAGE SUBSTRATE, METHOD OF MANUFACTURING THE PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE PACKAGE SUBSTRATE - A package substrate may include an insulating substrate, a first land array, a second land array, a first plating line and a second plating line. The first land array may be arranged on a first surface of the insulating substrate. The second land array may be arranged on a second surface of the insulating substrate opposite to the first surface. The second land array may be electrically connected to the first land array. The second land array may include outer lands and inner lands. The first plating line may be connected to the outer lands. The second plating line may be connected between the outer lands and the inner lands. The second plating line may have a width narrower than that of the first plating line. The second plating line may be removed by applying a removing current to the first plating line prior to the first plating line. | 2014-09-04 |
20140246772 | Passivation Scheme - An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation layer is disposed over the first passivation layer. A stress buffer layer is disposed over the second passivation layer. A conductive interconnect layer is over and coupled to the conductive pad and over the stress buffer layer with the conductive interconnect layer adjoining sidewalls of the first passivation layer and the stress buffer layer. | 2014-09-04 |
20140246773 | Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate - An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required. | 2014-09-04 |
20140246774 | SEMICONDUCTOR DEVICE HAVING A BUFFER LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same are provided. A metal pad can be electrically connected to metal interconnections in a lower portion of the device. A passivation layer can be provided and can exposes a portion of the metal pad, and a buffer layer can be formed on lateral sides of the passivation layer. | 2014-09-04 |
20140246775 | METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer. | 2014-09-04 |
20140246776 | DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING - A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer. | 2014-09-04 |
20140246777 | CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING - Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer. | 2014-09-04 |
20140246778 | SEMICONDUCTOR DEVICE, WIRELESS DEVICE, AND STORAGE DEVICE - According to one embodiment, a semiconductor device includes a substrate, a first semiconductor chip, a second semiconductor chip, and a discrete element part. The first semiconductor chip is arranged on the substrate and includes a first electrode group. The second semiconductor chip is arranged on the substrate and includes a second electrode group, at least one of electrodes included in the second electrode group being connected to at least one of electrodes included in the first electrode group via at least one bonding wire. The discrete element part is arranged on the substrate and under the at least one bonding wire. | 2014-09-04 |
20140246779 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 2014-09-04 |
20140246780 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PATTERN - A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern. | 2014-09-04 |
20140246781 | SEMICONDUCTOR DEVICE, METHOD OF FORMING A PACKAGED CHIP DEVICE AND CHIP PACKAGE - According to one embodiment, the semiconductor device is of the multi-chip type. The semiconductor device has a embedded-chip-package-in-substrate, a wiring layer, and plural second chips. The embedded-chip-package-in-substrate has the first chip accommodated in it. The wiring layer is formed on the top surface of the embedded-chip-package-in-substrate. Plural second chips are stacked on the wiring layer. | 2014-09-04 |
20140246782 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact. | 2014-09-04 |
20140246783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L | 2014-09-04 |
20140246784 | SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS - Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines. | 2014-09-04 |
20140246785 | Package on Package Structure - A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit. | 2014-09-04 |
20140246786 | STACKED PACKAGES HAVING THROUGH HOLE VIAS - Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs. | 2014-09-04 |
20140246787 | SEMICONDUCTOR APPARATUS - According to one embodiment, a semiconductor apparatus includes a substrate, a first semiconductor chip, a second semiconductor chip and a first converter. The first semiconductor chip includes a first surface and a second surface and is mounted on the substrate, the first surface is opposed to the substrate, the second surface is opposed to the first surface. The second semiconductor chip includes a first area and is stacked on the second surface. The first converter is arranged in the first area, the first converter is configured to perform at least one of analog-to-digital conversion and digital-to-analog conversion and arranged in the first area. A part of the first area does not overlap the first semiconductor chip when viewed from a direction perpendicular to the second surface. | 2014-09-04 |
20140246788 | STACK-TYPE SEMICONDUCTOR PACKAGE - Provided is a stack-type semiconductor package comprising a first semiconductor package with a first package substrate and a logic chip mounted thereon, a second semiconductor package including a second package substrate disposed on the first semiconductor package and first and second memory chips stacked on the second package substrate, and connection pads disposed between the first and second package substrates to connect the first and second semiconductor packages electrically to each other. The first package substrate has first and second edges that are substantially perpendicular to each other. The first package substrate may include first DQ connection pads electrically connected to the first memory chip, and second DQ connection pads electrically connected to the second memory chip. The first DQ connection pads may be arranged adjacent to the first edge and the second DQ connection pads may be arranged adjacent to the second edge. | 2014-09-04 |
20140246789 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER - A semiconductor device ( | 2014-09-04 |
20140246790 | FLOATING BOND PAD FOR POWER SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size. | 2014-09-04 |
20140246791 | 14 LPM CONTACT POWER RAIL - A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches. | 2014-09-04 |
20140246792 | POWER TRANSFER AND GENERATION USING PRESSURIZED FLUIDS - The invention captures harvestable mechanical energy, e.g., in the form of wind or moving water, and uses it for electrical generation or other work. In various embodiments a turbine is used to pressurize a fluid, and the pressurized fluid is then optionally stored and then used to drive an electric generator. Because the pressurized fluid can be stored in a pressurized state indefinitely, the invention provides a straightforward way to accumulate the mechanical energy until it is needed. Additionally, the invention allows portions of the system, e.g., a pressure vessel or generator, to be located away from the turbine, reducing the costs of deploying and maintaining the system. | 2014-09-04 |
20140246793 | FILL PACK ASSEMBLY AND METHOD WITH BONDED SHEET PAIRS - A fill pack assembly and method for assembling a fill pack from individual sheets utilizes integrally bonded sheet pairs. Each sheet pair is a pair of two individual adjacent fill sheets which have been bonded together via any suitable bonding method. A plurality of the thus formed sheet pairs can then be attached together to form an entire fill pack or portion of a fill pack. Such fill packs are useful in heat exchange devices such as industrial cooling towers. | 2014-09-04 |
20140246794 | WINE AERATOR - A device for aerating a liquid, such as wine, includes a cup portion with a cavity that receives an amount of liquid therein, the cavity extending between a proximal opening and a distal opening. A neck portion of the device defines an aeration section in fluid communication with the cavity. Passages in the aeration section extend laterally to an outer surface of the neck portion through which air is drawn into the aeration section. A central passage through the neck portion is in fluid communication with the aeration section and extends to a distal opening of the device. A diffuser element between the cavity and the aeration section has arms that are configured to contact the liquid as it flows from the cavity to inhibit a swirling flow of the liquid so that the liquid passes into the aeration section in a generally vertical and linear manner. | 2014-09-04 |
20140246795 | HEAT EXCHANGER FOR REMOVAL OF CONDENSATE FROM A STEAM DISPERSION SYSTEM - A steam dispersion apparatus includes a steam chamber communicating in an open-loop arrangement with a first steam source for supplying steam to the steam chamber. The steam chamber includes a steam dispersion location at which steam exits therefrom at generally atmospheric pressure. A heat exchanger communicates in a closed-loop arrangement with a second steam source for supplying steam to the heat exchanger at a pressure generally higher than atmospheric pressure. The heat exchanger is located at a location that is not directly exposed to the air to be humidified, the heat exchanger being in fluid communication with the steam chamber so as to contact condensate from the steam chamber. The heat exchanger converts condensate formed by the steam chamber back to steam when the condensate contacts the heat exchanger. | 2014-09-04 |
20140246796 | LENS MOLD AND METHOD FOR MANUFACTURING LENSES UTILIZING THE LENS MOLD - A lens mold includes a bottom mold and a top mold joining with the bottom mold. The bottom mold defines a first through hole. The top mold defines a second through hole. The lens mold further includes a bottom mold core and a top mold core. The bottom mold core is detachably received in the first through hole of the bottom mold. The top mold core is detachably received in the second through hole of the top mold. A plurality of microstructures is formed on a top surface of the bottom mold core near the top mold core to form a plurality of microstructures on a bottom surface of a lens formed by the lens mold. A method for manufacturing the lens with the lens mold is also provided. The lens is used as a secondary optical element for an LED. | 2014-09-04 |
20140246797 | TRANSFER MOLD AND MANUFACTURING METHOD FOR STRUCTURE - A transfer mold includes a body, a first layer, and a second layer. The body has a projecting-and-recessed surface. The first layer contains an inorganic material and is disposed on the projecting-and-recessed surface of the body. The second layer contains fluorine and is disposed on a surface of the first layer. The average of hardness values of the projecting-and-recessed surface on which the first and second layers are disposed is 30 Hv or higher. | 2014-09-04 |
20140246798 | BLOOD VESSEL MODEL - A blood vessel model which imitates a human blood vessel including an aqueous gel made from polyvinyl alcohol having an average polymerization degree of 300 to 3500 and a saponification degree of 90% by mole or more, and silica particles; and a method for producing a blood vessel model which imitates a human blood vessel, including filling a mixed solution containing polyvinyl alcohol having an average polymerization degree of 300 to 3500 and a saponification degree of 90% by mole or more, silica particles and water in a mold for forming a blood vessel model, and freezing the mixture at a temperature of −10° C. or lower, followed by thawing. The blood vessel model can be suitably used as a blood vessel model for practicing insertion of a stent graft into an aneurysm, a blood vessel model for practicing resection or ligation surgery of a blood vessel, and the like. | 2014-09-04 |
20140246799 | IMPRINT APPARATUS AND ARTICLE MANUFACTURING METHOD - The imprint apparatus of the present invention includes a holding unit configured to hold a mold; a particle inspection unit configured to inspect whether or not particle is present on an imprint area, in which the resin pattern is formed, of the substrate; a dispenser configured to apply an uncured resin to the imprint area; a movable unit configured to move the imprint area with respect to the holding unit; and a controller. The movable unit is capable of moving the imprint area to each of an inspection position by means of the inspection unit, an application position by means of the dispenser, and a contacting position by means of the holding unit. Also, the controller causes the inspection unit to perform inspection of the imprint area in association with the movement of the imprint area by means of the movable unit. | 2014-09-04 |
20140246800 | LOW COST ELECTRICAL MOTOR COMPONENTS MANUFACTURED FROM CONDUCTIVE LOADED RESIN-BASED MATERIALS - Electric motor components are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is between about 20% and 50% of the weight of the conductive loaded resin-based material. The micron conductive powders are metals or conductive non-metals or metal plated non-metals. The micron conductive fibers may be metal fiber or metal plated fiber. Further, the metal plated fiber may be formed by plating metal onto a metal fiber or by plating metal onto a non-metal fiber. Any platable fiber may be used as the core for a non-metal fiber. Superconductor metals may also be used as micron conductive fibers and/or as metal plating onto fibers in the present invention. | 2014-09-04 |
20140246801 | METHOD FOR MANUFACTURING MICROFLUIDIC CHIPS, DEVICE FOR FUNCTIONALIZING MICROFLUIDIC CHIPS, MICROFLUIDIC CHIP AND DEVICE FOR HOLDING A MICROFLUIDIC CHIP - The invention relates to a method for manufacturing microfluidic chips having at least one capillary for through-flow of a fluid, comprising the steps of:
| 2014-09-04 |
20140246802 | Polyhydroxyalkanoate Medical Textiles and Fibers - Absorbable polyester fibers, braids, and surgical meshes with prolonged strength retention have been developed. These devices are preferably derived from biocompatible copolymers or nomopolymers of 4-hydroxybutyrate. These devices provide a wider range of in vivo strength retention properties than are currently available, and could offer additional benefits such as anti-adhesion properties, reduced risks of infection or other post-operative problems resulting from absorption and eventual elimination of the device, and competitive cost. The devices may also be particularly suitable for use in pediatric populations where their absorption should not hinder growth, and provide in all patient populations wound healing with long-term mechanical stability. The devices may additionally he combined with autologous, allogenic and/or xenogenic tissues to provide implants with improved mechanical, biological and handling properties. | 2014-09-04 |
20140246803 | METHOD FOR PRODUCING A FRAME FOR AN ENGINE COOLING FAN OF A MOTOR VEHICLE - Equipping engine cooling fans with flaps, in particular ram-air flaps, which are opened by the relative wind and can close again by means of gravity at a vehicle standstill, is known. Until know, it has been common to install such ram-air flaps manually on a frame of the engine cooling fan. However, all of said embodiment concepts require complex motion guidance during the installation in/on the frame. The invention relates to a method for producing a frame ( | 2014-09-04 |
20140246804 | METHOD OF FORMING MIDSOLE OF TWO MATERIALS - A first portion of a midsole formed of a first material has a recess in a top surface thereof, and a first aperture positioned within the recess and extending therethrough. The first portion is placed in a recess in a bottom plate of a second mold assembly. A middle plate with a second aperture extending therethrough is placed in contact with the bottom plate. A second material is inserted through the second aperture such that it fills the recess and the first aperture in the first portion to form a second portion of the midsole. A top plate of the second mold assembly is positioned in contact with the middle plate so as to close the second mold assembly. The second mold assembly is subjected to heat and pressure such that the second portion cures and bonds to the first portion of the midsole. | 2014-09-04 |
20140246805 | PROCESS FOR MANUFACTURING GOLF BALLS HAVING A MULTI-LAYERED COVERS - Process for making golf ball having multi-layered cover having a very thin outermost cover layer comprising: providing first and second substantially hemispherical half shells comprising a thermoplastic composition; dispensing uncured liquid thermoset composition into a hemispherical cavity of first half shell; inserting first half of a core subassembly into hemispherical cavity and displacing an amount of the uncured liquid thermoset composition such that the uncured liquid thermoset composition forms an inner cover layer; dispensing the uncured liquid thermoset composition into hemispherical cavity of second half shell; inserting second half of core subassembly into hemispherical cavity of second half shell and displacing an amount of the uncured liquid thermoset composition such that the uncured liquid thermoset composition forms an inner cover layer and thereby mating the first and second half shells; curing thermoset inner cover layer; and forming dimples in the outer surfaces of mated first and second half shells. | 2014-09-04 |
20140246806 | METHOD FOR MAKING AND DECORATING A TRANSPARENT TIMEPIECE COMPONENT - A method for making and decorating top and bottom surfaces of a transparent timepiece component, the method including: depositing a first decoration on a male pattern; moving the male pattern, covered or not covered by a preform, into an injection chamber and injecting a transparent material therein to coat the male pattern to obtain a compound including the top face with the first decoration, on the bottom face; polymerizing the first compound in the injection chamber and then removing therefrom; depositing another material and/or second decoration in a cavity and held by gravity, and deposited on the top surface via a relative motion in the direction of gravity, to obtain a second compound. | 2014-09-04 |
20140246807 | Method for Forming a Melt-Resistant Glass Fiber Product, and Associated Apparatus - A method is provided for forming a melt-resistant glass fiber product, by applying an insulating material to a glass fiber product comprised of filiform glass fibers so as to substantially coat each of the filiform glass fibers therewith, such that the coated filiform glass fibers render the glass fiber product resistant to heat. In one aspect, such a method comprises forming a wetted mixture including filiform glass fibers and insulating material comprising a fire-retarding solution, wherein the wetted mixture has a solids content of the fire-retarding solution substantially uniformly and thoroughly dispersed therethrough. An associated apparatus is also provided. | 2014-09-04 |
20140246808 | PATTERN FORMATION METHOD AND PATTERN FORMATION DEVICE - According to one embodiment, a pattern formation method is disclosed. The method is configured to transfer a shape of a pattern to a plurality of shot regions of an object using a mold including a first pattern region and a second pattern region aligned with the first pattern region. The method can include transferring the shape of the pattern to each of the plurality of shot regions sequentially in a first direction from the first pattern region toward the second pattern region when the shape of the pattern is transferred using the first pattern region. The method can include transferring the shape of the pattern to each of the plurality of shot regions sequentially in a second direction from the second pattern region toward the first pattern region when the shape of the pattern is transferred using the second pattern region. | 2014-09-04 |
20140246809 | SYSTEMS AND METHODS IMPLEMENTING ADDITIVE MANUFACTURING PROCESSES THAT UTILIZE MULTIPLE BUILD HEADS - Systems and methods in accordance with embodiments implement additive manufacturing processes that utilize multiple build heads. In one embodiment, an additive manufacturing apparatus includes: a plurality of build heads, each of which being adapted to cause the formation of a structure onto a surface; a substrate; and a translation system, where the translation system is associated with at least one of the plurality of build heads and the substrate, such that the spatial relationship between the plurality of build heads and the substrate can be controlled. | 2014-09-04 |
20140246810 | MOLDING METHOD AND APPARATUS THEREFOR - In a molding method and an apparatus for the method, a base material is placed on mounting portions of bottom support pins, which protrude from a first inner surface of a lower mold in an open state. Pressing portions of top support pins, which protrude from a second inner surface of an upper mold, are brought into contact with the base material. Consequently, the base material is sandwiched between the mounting portions and the pressing portions. Thereafter, pre-forming preferably is carried out. For example, the bottom support pins and the top support pins are lowered toward the lower mold, such that the base material is brought into contact with the first inner surface. Then, the lower mold and the upper mold are closed, and the base material is molded into a molded article. | 2014-09-04 |
20140246811 | METHOD FOR MAKING NANOWIRE STRUCTURE - The disclosure related to a method for making a nanowire structure. First, a free-standing carbon nanotube structure is suspended. Second, a metal layer is coated on a surface of the carbon nanotube structure. The metal layer is oxidized to grow metal oxide nanowires. | 2014-09-04 |
20140246812 | PROCESS FOR PRODUCING POLYMERIC STRUCTURES THAT HAVE ACTIVATED SURFACES AND ACTIVATED POLYMERIC STRUCTURES - The present invention relates to a process for producing polymeric structures that have activated surfaces. The process proved to be simple, quick, with high production capacity and low operating costs. The process occurs by depositing a polymer solution, which is assisted by a high electric field, on a conductive liquid surface to produce particles and/or filaments that have an activated surface. More particularly, the process of the present invention has the ability to produce particles and/or filaments that have chemically activated surfaces, in a single process. | 2014-09-04 |
20140246813 | APPARATUS AND METHOD FOR THE SEPARATION OF A FOIL FROM A MATERIAL LAYER - An apparatus and method for additive fabrication which helps to prevent the newly hardened layer from being separated from the previously formed layer of the object while the foil is peeled from the newly hardened layer is provided. In one embodiment, use of a peel angle helps prevent the newly hardened layer from being separated from the previously formed layer during peeling by distributing the peeling force so that less of the z-direction component of the peeling force is applied to the newly hardened layer. In another embodiment, the object can be oriented to initiate the peel at an area, of the object which results in a lesser initial peeling force applied to the newly hardened layer. | 2014-09-04 |
20140246814 | Method for Producing Air Ducts from Plastic Material, and Mould Used - Method and mould for producing air ducts (P) from plastic material, especially soft plastic material, with a hardness of between Shore 5 and Shore 65, of the type comprising a hollow main body (P | 2014-09-04 |
20140246815 | BLAST FURNACE INSTALLATION - A blast furnace installation includes a blast furnace and a chute transmission gearbox; the blast furnace having a top cone with a top cone ring arranged thereon for receiving a connection flange of the chute transmission gearbox. The connection flange is directly fixed onto the top cone ring by fixing means for establishing a firm connection between the top cone ring and the connection flange. According to an aspect of the present invention, the connection flange is fixed to the top cone ring in three separated fixation regions ( | 2014-09-04 |