| 36th week of 2008 patent applcation highlights part 63 |
| Patent application number | Title | Published |
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| 20080215824 | CACHE MEMORY, PROCESSING UNIT, DATA PROCESSING SYSTEM AND METHOD FOR FILTERING SNOOPED OPERATIONS - A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory. | 2008-09-04 |
| 20080215825 | Memory Share by a Plurality of Processors - A method and an apparatus for having a memory shared by a plurality of processors are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a memory, a main processor connected to one side of the memory through a first memory bus, and application processors in a quantity of n connected parallel to the other side of the memory through a second memory bus. Each application processor performs at least one predetermined function. The main processor is connected parallel to the n application processors through a control bus, and delivers a control signal to at least one application processor through the control bus. With the present invention, the structure of a digital processing apparatus can be simplified, and the cost and size of a digital processing apparatus can be minimized. | 2008-09-04 |
| 20080215826 | DETERMINISTIC MEMORY MANAGEMENT IN A COMPUTING ENVIRONMENT - Systems and methods for memory management in a computing environment are provided. The method comprises uniquely identifying a first object associated with a first task for an application executed in a computing environment, wherein a first area of memory is allocated to the first object; determining a first execution scope for the first task according to a first execution context associated with the first task, wherein the first context defines a first life expectancy for the first task within the execution environment hierarchy; determining a change in execution scope of the first task, in response to monitoring the first execution context; and deallocating the first area of memory, in response to determining that the first task is no longer executed within the first execution scope. | 2008-09-04 |
| 20080215827 | SELECTING STORAGE CLUSTERS TO USE TO ACCESS STORAGE - Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available. | 2008-09-04 |
| 20080215828 | System for Reading and Writing Data - A system for writing and reading data includes a controller accessible to at least one or more computing systems, a plurality of microprocessor units accessible to the controller, and a plurality of memory device configurations each having one dedicated bus connection to individual ones or multiples of the microprocessor units. The controller receives write and read requests from the one or more computing systems and selects which of the plurality of microprocessor units will write or read data associated with the requests. | 2008-09-04 |
| 20080215829 | OPTICAL DISC RECORDER AND BUFFER MANAGEMENT METHOD THEREOF - A buffer management method is provided. A host issues a read command requesting access for a read data block and a write command requesting recording of a write data block. A write buffer is dedicated to store the write data block. A read buffer is dedicated to store the read data block. The method comprises entering the optical disc recorder into a write loop. During the write loop, the optical disc recorder triggering a write command handling procedure in response to the write command; triggering a read command handling procedure in response to the read command; and triggering a pre-recording procedure to prepare the write data block in the write buffer for recording. Wherein contents between the write buffer and read buffer are exchangeable during the write handling procedure, the read handling procedure or the pre-recording procedure. | 2008-09-04 |
| 20080215830 | EMPLOYING A DATA STRUCTURE OF READILY ACCESSIBLE UNITS OF MEMORY TO FACILITATE MEMORY ACCESS - A data structure of readily accessible units of memory is provided. The data structure includes designations of one or more units of memory that while represented in the data structure do not need expensive address translation, other tests or special handling in order to access the units of memory. By employing such a data structure, memory access and system performance are enhanced. | 2008-09-04 |
| 20080215831 | Interleaver With Linear Feedback Shift Register - An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output. | 2008-09-04 |
| 20080215832 | DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE - A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict. | 2008-09-04 |
| 20080215833 | INFORMATION STORAGE DEVICE AND STORED DATA PROCESSING METHOD - An information storage device includes one or more semiconductor memories storing management data accompanying content data and being configured to erase data in units of one block, and a controller setting up, in the one or more semiconductor memories, a working area to temporarily store the management data and a storage area to retain all or part of the management data stored in the working area, writing the management data to the working area while monitoring the free space of the working area, moving the management data stored in the working area to the storage area when the free space of the working area falls below a prescribed value, and erasing the management data stored in the working area after the movement of the management data to the storage area. | 2008-09-04 |
| 20080215834 | FAST BLOCK DEVICE AND METHODOLOGY - A device, method and system is directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address. | 2008-09-04 |
| 20080215835 | Storage system and data processing system - A storage system comprises a data set storage region for storing a data set containing data and update information for managing this data, and a control section. The data set storage region is divided into a plurality of storage regions including a first storage region and a second storage region. The control section generates a first data set containing first data and first update data which is update data for same, stores at least the first data of this first data set in the first storage region, generates a second data set containing second data and second update data which is update data for same, and stores at least the second data of this second data set in the second storage region, which is separate from the first storage region. | 2008-09-04 |
| 20080215836 | Method of managing time-based differential snapshot - Provided is a method of managing differential snapshots in a storage system, the storage system having a disk drive and a disk controller, the differential snapshot management method including the steps of: providing a storage area of the disk drive as a plurality of logical volumes including an operational volume and a differential volume; storing a time of update for each block in the operational volume; and judging, upon reception of a request to write in a block included in the operational volume, whether to copy data of the block in which requested data is to be written in accordance with the received write request to the differential volume, based on the time of update of the block in which requested data is to be written and a time of creation of the differential snapshot. Accordingly, it is possible to manage the differential snapshot without using a bitmap. | 2008-09-04 |
| 20080215837 | Storage System With Multiple Copy Targeting and Disk Failure Protection - An apparatus is disclosed in which a storage controller cooperable with a host and a plurality of controlled storage is provided to localize an impact of a failure to a target disk in an affected segment. The storage controller includes a host write component to write a data object to a source image storage; a first copy component responsive to a first metadata state to control copying of the data object to a first target storage; a second copy component responsive to a second metadata state to perform either: copying the data object to a second target or causing the first copy component to copy the second target to the first target; and a third copy component to control cascaded copying of the data object to a third target storage. Either the second or the third copy component controls cascaded copying of a delimited data image subsequence responsive to a metadata state indicating currency of a data grain in either the second or the third target. | 2008-09-04 |
| 20080215838 | Providing Storage Control in a Network of Storage Controllers - An apparatus for providing storage control in a network of storage controllers is disclosed. The apparatus includes an owner storage controller; an I/O performing component, an ownership assignment component, a lock manager and a messaging component. The ownership assignment component assigns ownership of metadata for data to an owner storage controller. The lock manager controls the locking of metadata during I/O. The messaging component passes messages among storage controllers to request metadata state, to grant locks, to request release of locks, and to signal lock release. The I/O is performed on data whose metadata is owned by an owner storage controller, subject to compliance with metadata lock protocols controlled by the owner storage controller, and any copy of the data held from time to time is maintained in a coherency relation with the data. | 2008-09-04 |
| 20080215839 | Providing Storage Control in a Network of Storage Controllers - An apparatus for providing storage control in a network of storage controllers is disclosed. The apparatus includes an owner storage controller; an I/O performing component, an ownership assignment component, a lock manager and a messaging component. The ownership assignment component assigns ownership of metadata for data to an owner storage controller. The lock manager controls the locking of metadata during I/O. The messaging component passes messages among storage controllers to request metadata state, to grant locks, to request release of locks, and to signal lock release. The I/O is performed on data whose metadata is owned by an owner storage controller, subject to compliance with metadata lock protocols controlled by the owner storage controller, and any copy of the data held from time to time is maintained in a coherency relation with the data. | 2008-09-04 |
| 20080215840 | ELECTRONIC FILE SYSTEM, OPERATING DEVICE, APPROVAL DEVICE, AND COMPUTER PROGRAM - An electronic file system includes an operating device for receiving an input for performance of an operation on an electronic file and an approval device used for approving of the operation on the electronic file. The electronic file includes an operation file on which an operation is to be performed and a restriction file indicating a restriction condition (policy) for restricting an operation performable on the operation file and a request destination for approval of the restricted operation. The operating device includes determination means for determining whether the operation to be performed on the operation file is permitted in accordance with the restriction condition described in the restriction file and means for, when it is determined that the operation corresponds to the restriction condition, transmitting to the approval device described as the request destination in the restriction file an approval request for requesting approval of the operation. | 2008-09-04 |
| 20080215841 | Memory Lock System - A memory lock system ( | 2008-09-04 |
| 20080215842 | DISTANCE-PRESERVING ANONYMIZATION OF DATA - An embodiment includes a system with a processing unit and a communication unit. The processing unit is configured: to compute a first reference point of a data point that represents a private data item and has a first distance value to the data point, wherein the first distance value is less than a threshold value, to compute a second reference point of the data point different from the first reference point with a second distance value to the data point, wherein the second distance value is less than the threshold value, and to generate hidden reference points from the reference points. The communication unit is configured to send the hidden reference points and distance values to a system. | 2008-09-04 |
| 20080215843 | STORAGE AREA MANAGEMENT METHOD FOR A STORAGE SYSTEM - The load of managing a storage system is lessened. In a storage system where multiple logical volumes are included in a logical volume group and a copy of the logical volume group is made in a pool area different from the one to which the logical volume group belongs, a management computer adds to the pool area capacity when the capacity of a pool area exceeds a predetermined threshold. When the pool area includes multiple logical volume groups, the management computer requests the storage system to create a pool area for each of the logical volume groups and to create the logical volume groups respectively for the created pool areas. When the pool area includes one logical volume group, the management computer requests the storage system to make the capacity of the pool area coincide with the capacity of a pool area to which the logical volume group is copied. | 2008-09-04 |
| 20080215844 | AUTOMATIC MAINTENANCE OF CONFIGURATION INFORMATION IN A REPLACEABLE ELECTRONIC MODULE - The present invention provides methods and systems to automatically manage hardware and software capabilities of replaceable electronic modules as the modules are replaced or reassigned to different tasks. Each such module stores configuration information in a persistent memory. This configuration information enables the module to use only selected hardware and to execute only selected software. A replaceable electronic module manager stores copies of each module's configure information in a separate persistent memory. When a module is replaced, a copy of the configuration information is fetched from the module manager's persistent memory and sent to a replacement module, thereby making the replacement module functionally equivalent (from a point of view of which hardware can be used by the module or which software can be executed by the module) to the replaced module. In addition, when a module is assigned to a different task, appropriate configuration information can be sent to the module, so the module can appropriately perform the assigned task, such as use selected hardware or execute selected software. | 2008-09-04 |
| 20080215845 | Methods, Systems, and Media for Managing Dynamic Storage - Methods, systems, and media for managing dynamic memory are disclosed. Embodiments may disclose identifying nodes with having memory for dynamic storage, and reserving a portion of the memory from the identified nodes for a heap pool. After generating a heap pool, embodiments may allocate dynamic storage from the heap pool to tasks received that are associated with one of the identified nodes. More specifically, embodiments identify the node or home node associated with the task, the amount of dynamic storage requested by the task, and create a heap object in the node associated with the task to provide the requested dynamic storage. Some embodiments involve de-allocating the dynamic storage assigned to the task upon receipt of an indication that the task is complete and the dynamic storage is no longer needed for the task. Several of such embodiments return the de-allocated dynamic storage to the heap pool for reuse. | 2008-09-04 |
| 20080215846 | METHOD AND APPARATUS FOR MANAGING CENTRAL PROCESSING UNIT RESOURCES OF A LOGICALLY PARTITIONED COMPUTING ENVIRONMENT WITHOUT SHARED MEMORY ACCESS - A method and apparatus for managing CPU resources of a logically partitioned computing environment without shared memory access. A logical partition needing additional resources sends a message requesting such resources to a central domain manager, which sends messages to other partitions in the same group requesting that they assess their ability to donate resources to the requesting partition. Upon receiving such assessment request, each logical partition assesses its ability to donate resources to the requesting partition and responds accordingly to the domain manager. If at least one partition responds that it can donate resources to the requesting partition, the domain manager sends a message to a selected donor partition requesting that it reconfigure itself to donate resources to the requesting partition. Upon receiving a notification from the donor partition that it has successfully reconfigured itself, the domain manager notifies the requesting partition, which reconfigures itself to accept the donated resources. | 2008-09-04 |
| 20080215847 | SECURE YET FLEXIBLE SYSTEM ARCHITECTURE FOR SECURE DEVICES WITH FLASH MASS STORAGE MEMORY - A device with mass storage capability that uses a readily available non secure memory for the mass storage but has firmware (and hardware) that provides security against unauthorized copying of data. This is true even though the firmware itself is stored in the non secure mass storage memory, and therefore potentially vulnerable to hacking. An indication of the authenticity of the firmware must be present before it will be executed by the device. This protects the device contents from unauthorized duplication or tampering. Additional functionality can be added to the device with additional firmware applications, and the authenticity of those additional applications will also be verified before they will be executed. This further prevents unauthorized copying or tampering of secure content through any mechanisms that may be unscrupulously introduced. Any data within the mass storage memory may also be encrypted. | 2008-09-04 |
| 20080215848 | Method and System For Caching Address Translations From Multiple Address Spaces In Virtual Machines - A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors. | 2008-09-04 |
| 20080215849 | HASH TABLE OPERATIONS WITH IMPROVED CACHE UTILIZATION - Method and apparatus for building large memory-resident hash tables on general purpose processors. The hash table is broken into bands that are small enough to fit within the processor cache. A log is associated with each band and updates to the hash table are written to the appropriate memory-resident log rather than being directly applied to the hash table. When a log is sufficiently full, updates from the log are applied to the hash table insuring good cache reuse by virtue of false sharing of cache lines. Despite the increased overhead in writing and reading the logs, overall performance is improved due to improved cache line reuse. | 2008-09-04 |
| 20080215850 | SYSTEMS, METHODS AND APPARATUS FOR LOCAL PROGRAMMING OF QUANTUM PROCESSOR ELEMENTS - Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices. | 2008-09-04 |
| 20080215851 | Method and arrangement for the power-efficient control of processors - A method is provided for the functional control of program and/or data flows in digital signal processors and processors, which have respective closed and separated modules for program and data flow control, working in parallel with computers. The method enables a power-efficient adaptation of the signal processing with the applied SIMD command-type in the individual paths and minimizes the emergence of the appearance of NOP-commands with which the VLIW-architecture of the processor must be supplied. The adaptation of the signal processing is achieved by individually controlling the parallel signal processing of the processor in the data paths (DP) which respectively belong to a first and second slice. For this purpose, a single slice halt outputted from an SSM register bank switches the register clockline according to state-dependent signal processing. | 2008-09-04 |
| 20080215852 | System and Device Architecture For Single-Chip Multi-Core Processor Having On-Board Display Aggregator and I/O Device Selector Control - System, device, device architecture, and method for operating a multi-core processor providing application level file isolation and providing display frame buffer aggregator or selector to provide a user with the experience of multiple simultaneous application execution within a single processor while actually providing separate concurrent but isolated processing sessions. | 2008-09-04 |
| 20080215853 | System and Method for Line Rate Frame Processing Engine Using a Generic Instruction Set - A system comprises a frame parser and lookup engine operable to receive an incoming data frame, extract control data from payload data in the data frame, and using the control data to access a memory to fetch a plurality of instructions, a destination and tag management module operable to receive the fetched instructions and execute the instructions to transform the data frame control data, and an assemble module operable to assemble the transformed control data and the payload data. | 2008-09-04 |
| 20080215854 | System and Method for Adaptive Run-Time Reconfiguration for a Reconfigurable Instruction Set Co-Processor Architecture - A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed. | 2008-09-04 |
| 20080215855 | Execution unit for performing shuffle and other operations - In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed. | 2008-09-04 |
| 20080215856 | METHODS FOR GENERATING CODE FOR AN ARCHITECTURE ENCODING AN EXTENDED REGISTER SPECIFICATION - There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier. | 2008-09-04 |
| 20080215857 | Method For Latest Producer Tracking In An Out-Of-Order Processor, And Applications Thereof - Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location specified by the first instruction, (3) writing a producer tracking status value at a producer tracking map location specified by the physical register identification value, and (4) modifying, upon graduation of the first instruction, the first in-register status value only if the producer tracking map location stores the producer tracking status value written in step (3). Other methods are also presented. | 2008-09-04 |
| 20080215858 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group. | 2008-09-04 |
| 20080215859 | Computer with high-speed context switching - A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end. | 2008-09-04 |
| 20080215860 | Software Protection Using Code Overlapping - Apparatus and methods for implementing software protection using code overlapping are disclosed. In one implementation, a combination block comprising a first sub-block of instructions with one or more interspersed obfuscation instructions is received. The obfuscation instructions interspersed among sequentially executable instructions of the first sub-block of instructions can include instructions from other sub-blocks as well as control instructions configured to guide a processor to execute all of the instructions in first sub-block of instructions in sequence. The obfuscation instructions are replaced with one or more replacement instructions. The replacement instructions can be of a same bit-length as the replaced obfuscation instructions. Moreover, the replacement instructions can include integrity checks configured to check for tampering with instructions and/or runtime program state in the first sub-block and/or the combination block. | 2008-09-04 |
| 20080215861 | METHOD AND APPARATUS FOR EFFICIENT RESOURCE UTILIZATION FOR PRESCIENT INSTRUCTION PREFETCH - Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread. | 2008-09-04 |
| 20080215862 | Program Creation Device, Program Test Device, Program Execution Device, Information Processing System - The present invention comprises a program generation apparatus for generating an obfuscated program difficult to analyze from outside and a program execution apparatus for executing the program. The program generation apparatus comprises: an acquisition unit operable to acquire a 1 | 2008-09-04 |
| 20080215863 | Method and Apparatus for Autonomically Initiating Measurement of Secondary Metrics Based on Hardware Counter Values for Primary Metrics - A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality may be provided in the performance monitoring application for initiating the measurement of secondary metrics with regard to identified instructions, data addresses, ranges of identified instructions, or ranges of identified data addresses, based on counter values for primary metrics. Thus, for example, when a primary metric counter, or a combination of primary metric counters, meets or exceeds a predetermined threshold value, an interrupt may be generated. In response to receiving the interrupt, counters associated with the measuring of secondary metrics of a range of instructions/data addresses may be initiated. | 2008-09-04 |
| 20080215864 | Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor - A simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again. | 2008-09-04 |
| 20080215865 | DATA PROCESSOR AND MEMORY READ ACTIVE CONTROL METHOD - Instruction cache memory having a plurality of memory (for example, cache WAY), means | 2008-09-04 |
| 20080215866 | BRANCH PREDICTION APPARATUS, SYSTEMS, AND METHODS - An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system context, using a second strategy. In some embodiments, apparatus and systems may comprise one or more first storage locations to store branch history information associated with a first operating context, and one ore more second storage locations to store branch history information associated with a second operating context. | 2008-09-04 |
| 20080215867 | METHOD AND SYSTEM FOR AUTOMATICALLY TRANSITIONING OF CONFIGURATION SETTINGS AMONG COMPUTER SYSTEMS - A method and system for automatically transiting configuration settings among computer systems. Multiple configuration settings comprising a computer “personality” are located on a source computing system using multiple transition rules from a personality object. The computer personality includes customization choices, data files, electronic mail, system preferences, application customization choices, the network environment, browser information, etc. The configuration settings are extracted from multiple locations on the source computing system. The multiple extracted configuration settings are stored in a pre-determined transition format. The multiple extracted configuration settings are manipulated. A transition package is created from the multiple manipulated configuration settings. The transition package includes the multiple manipulated configuration settings. The transition package is sent to a target computing system. The transition package is infused on the target computing system to automatically transition configuration settings from the source computing system to the target computing system. The method and system may vastly reduce transition, configuration and deployment times for service providers, corporations, and end-users when a new computing system is deployed. | 2008-09-04 |
| 20080215868 | BIOS MANAGEMENT DEVICE AND METHOD FOR MANGING BIOS SETTING VALUE - The invention provides a BIOS management device and a method for managing a BIOS setting value. The invention determines whether to shut down a computer and to restore the BIOS setting value to a default state by detecting whether a restoring event occurs. In addition, the computer is shut down and the BIOS setting value is restored to the default state when the restoring event occurs. Therefore, the fault caused by the improper setting of the BIOS is eliminated. | 2008-09-04 |
| 20080215869 | MANAGING CONFIGURATION OF COMPUTER SYSTEMS ON A COMPUTER NETWORK - A system configuration manager provides a graphical user interface that allows a system administrator to easily administer configuration settings for different computer systems and platforms on a computer network. The system configuration manager allows identifying one system configuration or a settings profile as a “model system”. Once the model system is defined, other computer systems may be compared to the model system. Differences between the selected computer systems and the model system are then displayed, and the system configuration manager may be used to update the selected computer systems with configuration settings specified in the model system. Cross-platform support is provided by a configuration mapping mechanism that maps configuration information from one platform to corresponding configuration information for another platform. The configuration mapping mechanism effectively hides the differences between platforms by translating the configuration information from a selected platform to corresponding configuration information for the model system. | 2008-09-04 |
| 20080215870 | Method and apparatus for loading boot code - Apparatus for loading boot code including a non-volatile memory for the storage of the boot code, a micro-control unit for the storage of a small boot code, a microprocessor, and a volatile memory; and wherein the microprocessor copies the boot code from the non-volatile memory into the volatile memory using the small boot code. A corresponding method is also disclosed. | 2008-09-04 |
| 20080215871 | Swapping "Fixed System" Hard Disk - Method for ‘Cool-Swap’, ‘Warm-Swap’ and ‘Hot-Swap’ of ‘Fixed’ ‘System’ hard disk(s) in and out of the computer and for re-cycling the computer between ‘diskly’ state to ‘diskless’ state by combining the following features in one way or the other: separating the power supply of the ‘Fixed’ ‘System’ hard disk(s) from the internal power supply that is supplying power to other components of the computer, in particular the motherboard; taking the operating system, capable of being taken to run as ramdisk-based operating system, in control of the computer to run as ramdisk-based operating system; putting the computer into different power management states; and issuing commands or instructions for logical disconnection and/or re-connection of hard disk(s). | 2008-09-04 |
| 20080215872 | METHOD OF BOOTING ELECTRONIC DEVICE AND METHOD OF AUTHENTICATING BOOT OF ELECTRONIC DEVICE - Provided is a method of booting an electronic device including a host central processing unit (CPU) and a security module. The method includes: the host CPU starting to boot a system by using boot information in response to a reset or power on event of the electronic device; and when an authentication start instruction is not received by the security module from the host CPU until a first predetermined period elapses after an occurrence of the reset or power on event of the electronic device, controlling an operation of the host CPU by the security module. According to the method, when the authentication start instruction is received before the first predetermined period elapses, the security module authenticates the boot information and controls the operation of the host CPU based on an authentication result. A method of authenticating a boot of the electronic device in the security module is also provided. | 2008-09-04 |
| 20080215873 | SYSTEM AND METHOD FOR PRESENTING COPY PROTECTED CONTENT TO A USER FROM A PORTABLE STORAGE DEVICE - A device for presenting content to a user is utilized in combination with a general purpose computer. The computer has a processor, a computer communications interface, a computer memory and an operating system. The operating system has one or more file management tools. The device has a housing, a device communications interface and a device memory. The device memory comprises a boot partition which includes boot software. The boot software is copied from the device into the computer memory and is executed from the computer memory by the processor. The device memory also comprises a secure partition inaccessible by the file management tools and having content stored thereon. The device memory also comprises content delivery software, which is copied to the computer memory, and when executed by the processor from the computer memory can access the content from the secure partition and present it to the user as sensory data. | 2008-09-04 |
| 20080215874 | System and Method for Masking a Boot Sequence by Providing a Dummy Processor - A system and method for masking a boot sequence by providing a dummy processor are provided. With the system and method, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The execution of the masking code on the non-boot processors preferably generates electromagnetic and/or thermal signatures that approximate the signatures of the actual boot code execution on the boot processor. One of the non-boot processors is selected to execute masking code that is different from the other masking code sequence to thereby generate a electromagnetic and/or thermal signature that appears to be unique from an external monitoring perspective. | 2008-09-04 |
| 20080215875 | Method and apparatus for establishing safe processor operating points - A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information. | 2008-09-04 |
| 20080215876 | COMPUTER AND BIOS CLEAR BUTTON THEREOF - A computer and a BIOS clear button thereof are provided. The BIOS clear button is adapted to be electrically connected with a motherboard of the computer. The BIOS clear button includes a body, a key, and a connecting part. The body has a recessed portion and a plurality of protrusion portions disposed beside the recessed portion, wherein the protrusion portions protrude from the recessed portion. The key is disposed on the recessed portion, and the connecting part is connected to the body and is electrically connected with the motherboard. | 2008-09-04 |
| 20080215877 | Offload Processing for Secure Data Transfer - Improvements in security processing are disclosed which enable security processing to be transparent to the application. Security processing (such as Secure Sockets Layer, or “SSL”, or Transport Layer Security, or “TLS”) is performed in (or controlled by) the stack. A decision to enable security processing on a connection can be based on configuration data or security policy, and can also be controlled using explicit enablement directives. Directives may also be provided for allowing applications to communicate with the security processing in the stack for other purposes. Functions within the protocol stack that need access to clear text can now be supported without loss of security processing capability. No modifications to application code, or in some cases only minor modifications (such as inclusion of code to invoke directives), are required to provide this security processing. Improved offloading of security processing is also disclosed, which provides processing efficiencies over prior art offloading techniques. Offload components can be controlled from the kernel, an SSL layer or an application. | 2008-09-04 |
| 20080215878 | Service Management System and Method - The delivery of services is managed by a system that includes a portable device and a management apparatus which receives and decrypts a first identifier generated and encrypted by the portable device. One of the devices also digitally signs a second identifier, which is validated at the other device. | 2008-09-04 |
| 20080215879 | METHOD AND SYSTEM FOR AUTHENTICATING A WIDGET - A system and computer implemented method for providing a widget are described. The widget is portable, embeddable and for dynamically displaying multimedia content. The method and system include receiving a request corresponding to the widget and performing an authentication corresponding to the request. The method and system also include fulfilling the request if the authentication is successful. | 2008-09-04 |
| 20080215880 | MULTI-DOMAIN DYNAMIC GROUP VIRTUAL PRIVATE NETWORKS - Systems and/or methods of secure communication of information between multi-domain virtual private networks (VPNs) are presented. A dynamic group VPN (DGVPN) can reside in one domain and a disparate DGVPN can reside in a disparate domain. An administrative security authority (ASA) can be employed in each domain. Each ASA can generate and exchange respective keying material and crypto-policy information to be used for inter-domain communications when routing data from a member in one DGVPN to a member(s) in the disparate DGVPN, such that an ASA in one domain can facilitate encryption of data in accordance with the policy of the other domain before the data is sent to the other domain. Each ASA can establish a key server to generate the keying material and crypto-policy information associated with its local DGVPN, and such material and information can be propagated to intra-domain members. | 2008-09-04 |
| 20080215881 | Method Of Encrypting/Decrypting The Document And A Safety Management Storage Device And System Method Of Its Safety Management - A method of encrypting/decrypting the document and a safety management storage device and system method of its safety management, using for the safety management of electronic documents, the said system comprising a PC or mainframe installed with common reading software and a storage device of safety management connected to the said PC/mainframe through hot-plug; when connected to the mainframe, the said storage device is enumerated as a USB CDROM device at least. The user owns the said storage device can encrypt the electronic documents by using the encryption keys to generate an encrypted document with the same file type, also can open the encrypted document by using common reading software, and then use the document according to the predetermined operation authority. By using present invention, the users and the range of using the documents will be limited through the control of the distribution of the said storage devices, thus, a document safety management system with high security and easy-use will be established, and with the advantage of easy control, low cost of investment and maintenance. | 2008-09-04 |
| 20080215882 | Assigning Security Levels to a Shared Component - Security levels are assigned to a shared component. A workflow manager receives a workflow request that corresponds to a plurality of workflow steps. For each workflow step, the workflow manager determines whether the workflow step uses a shared component or an unshared component for execution. If the workflow step uses a shared component, the workflow manager invokes the step, and stores the step and its corresponding security level in a security tracking table. When the workflow manager encounters a shared component, the workflow manager uses the security tracking table entries in order to determine a security level to assign the shared component. The workflow manager assigns the determined security level to the shared component, and invokes the shared component to execute the corresponding process step. | 2008-09-04 |
| 20080215883 | PROVIDING SECURE INTER-APPLICATION COMMUNICATION FOR A MOBILE OPERATING ENVIRONMENT - Providing for secure and efficient communication for mobile applications executed in a mobile operating environment is described herein. As an example, a primary mobile application can initiate a handshake that includes a unique identifier of the primary application and a random number for signing and/or certifying responsive requests. A recipient application can reference the unique identifier with a list of certified primary applications to verify the primary application. If verified, the recipient responds with the random number and a second random number that can sign and/or certify data requests sent by the primary application. According to some embodiments, random numbers can be hashed and/or truncated to provide low power encryption for such numbers. Further, round-trip policies can be enforced to provide reliable transmission of data. Accordingly, reliable, secure and low power synchronous communication can be conducted in a mobile environment. | 2008-09-04 |
| 20080215884 | Communication Terminal and Communication Method Thereof - A communication terminal capable of helping make communication with the other end more active and of enabling even elder people or the like, who are unaccustomed to operating information devices, to have telephone conversation, while readily displaying various video information through simple operation, thereby furthering warm communication. In this apparatus, an information storage processing part ( | 2008-09-04 |
| 20080215885 | SYSTEM AND METHOD FOR GUARANTEEING SOFTWARE INTEGRITY VIA COMBINED HARDWARE AND SOFTWARE AUTHENTICATION - A system, method, and computer program product enabling individual user devices to authenticate and validate a digital message sent by a distribution center, without requiring transmissions to the distribution center. The center transmits the message with an appended modulus that is the product of two specially selected primes. The transmission also includes an appended authentication value that is based on an original message hash value, a new message hash value, and the modulus. The new message hash value is designed to be the center's public RSA key; a corresponding private RSA key is also computed. Individual user devices combine a digital signet, a public modulus, preferably unique hardware-based numbers, and an original message hash to compute a unique integrity value K. Subsequent messages are similarly processed to determine new integrity values K′, which equal K if and only if new messages originated from the center and have not been corrupted. | 2008-09-04 |
| 20080215886 | FUNCTION LICENSE AUTHENTICATION METHOD AND FUNCTION LICENSE AUTHENTICATION SYSTEM - There is provided a function license authentication method and system capable of preventing the illegal creation of a license key. | 2008-09-04 |
| 20080215887 | CARD AUTHENTICATION SYSTEM - A card authentication system. In one embodiment, the invention relates to a method for authenticating a data card having an intrinsic magnetic characteristic and recorded data on the data card, the method including reading information from the data card, the data card information including the intrinsic magnetic characteristic and the recorded data on the data card, encrypting the data card information, sending the encrypted data card information, receiving the encrypted data card information, decrypting a portion of the encrypted data card information, the portion including the intrinsic magnetic characteristic, generating a score indicative of a degree of correlation between the intrinsic magnetic characteristic of the data card information and a stored value, and determining an authenticity of the data card based at least in part on the score. | 2008-09-04 |
| 20080215888 | Method and Arrangement For Authentication and Privacy - The present invention improves privacy protection and authentication over prior art GAA/GBA system specifying a Bootstrap Server Function (BSF) that creates an Authentication Voucher asserting to a network application function NAF authentication of a. BSF generates keys Ks and Ks NAF with corresponding key identifiers B_TID and B_TID_NAF. In order to prevent tracking of user by collusion between several NAF entities B_TID_NAF and the Voucher can be unique for each NAF. The interface Ua is further protected by encryption using key Ks and the Ub interface is further protected against man-in-the-middle attacks by using signatures with key Ks and provision of freshness. | 2008-09-04 |
| 20080215889 | Efficient Watermark Detection - A system and a method of effectively detecting watermarks in a significant amount of data signals. The method, in overview, consists in pre-filtering the significant amount of data signals in order to eliminate from the final watermark detection the segments of the data signals which have no significant relevance to the owner of the copyrights of the watermark under investigation, and then performing the actual watermark detection over the remaining segments of data signals relevant to the investigation. The pre-filtering feature being implemented by a definition of one or more goal descriptors, extraction of one or more descriptors from the data signals and its content and a comparison between goal descriptors and extracted descriptors. | 2008-09-04 |
| 20080215890 | System and method for secure remote biometric authentication - Systems and methods for secure remote biometric authentication are provided. A network-based biometric authentication platform stores biometric templates for individuals which have been securely enrolled with the authentication platform. A plurality of sensor platforms separately establishes secure communications with the biometric authentication platform. The sensor platform can perform a biometric scan of an individual and generate a biometric authentication template. The sensor platform then requests biometric authentication of the individual by the biometric authentication platform via the established secure communications. The biometric authentication platform compares the generated biometric template to one or more of the enrolled biometric templates stored in memory at the biometric authentication platform. The result of the authentication is then communicated to the requesting sensor platform via the established secure communications. | 2008-09-04 |
| 20080215891 | Systems and Methods for Watermarking Software and Other Media - Systems and methods are disclosed for embedding information in software and/or other electronic content such that the information is difficult for an unauthorized party to detect, remove, insert, forge, and/or corrupt. The embedded information can be used to protect electronic content by identifying the content's source, thus enabling unauthorized copies or derivatives to be reliably traced, and thus facilitating effective legal recourse by the content owner. Systems and methods are also disclosed for protecting, detecting, removing, and decoding information embedded in electronic content, and for using the embedded information to protect software or other media from unauthorized analysis, attack, and/or modification. | 2008-09-04 |
| 20080215892 | Data Transmission Between Modules - In a method for transferring data (D) between a first module ( | 2008-09-04 |
| 20080215893 | Multiple levels of guided scrambling - Multiple levels of guided scrambling. Selective scrambling is performed on user data (or any information) that is to be output. The selection of which scrambling is to be employed can be based on whether or not a baseline error constraint and/or randomness constraint is met. The writing of the scrambled user data can be performed in parallel with, during the same time period, and/or simultaneously with the determination of whether or not a baseline error constraint and/or randomness constraint is met. If the constraint is not met, the outputting and/or writing of the scrambled user data can be aborted mid-process. | 2008-09-04 |
| 20080215894 | Method, System and Devices For Digital Content Protection - This invention relates to a system (and a corresponding method and devices) of digital content protection the system comprising a first digital content protection system ( | 2008-09-04 |
| 20080215895 | Electronic book secure communication with home subsystem - The invention, an electronic book selection and delivery system, is a new way to distribute books and other textual information to bookstores, libraries and consumers. The primary components of the system are a subsystem for placing text in a video signal format and a subsystem for receiving and selecting text that is placed in the video signal format. The system configuration for consumer use contains additional components and optional features that enhance the system, namely: (1) an operation center, (2) a video distribution system, (3) a home subsystem, including reception, selection, viewing, transacting and transmission capabilities, and (4) a billing and collection system. The operation center and/or video distribution points perform the functions of manipulation of text data, security and coding of text, cataloging of books, messaging center, and uplink functions. The home subsystem performs the functions of connecting to a video distribution system, menu selecting text, storing text, and transacting through phone or cable communicating mechanisms. A portable book-shaped viewing device is used for viewing the textual material delivered. The billing and collection system performs the transaction, management, authorization, collection and publisher payments automatically utilizing the telephone system. | 2008-09-04 |
| 20080215896 | Issuing a Publisher Use License Off-Line in a Digital Rights Management (DRM) System - A publishing user publishes digital content and issues to itself a corresponding digital publisher license to allow itself to render the published digital content. The publishing user is supplied with a publishing certificate from a digital rights management (DRM) server, where the publishing certificate allows the publishing user to so publish the digital content and to so issue the publisher license. | 2008-09-04 |
| 20080215897 | Security Containers for Document Components - Methods, systems, computer program products, and methods of doing business whereby document components are secured or controlled using “security containers” which encapsulate the components (and other component metadata). A “security container” encapsulates the component (i.e., content) that is to be controlled within a higher-level construct such as a compound document. The security container also contains rules for interacting with the encapsulated component, and one or more encryption keys usable for decrypting the component and rules for authorized requesters. | 2008-09-04 |
| 20080215898 | Computer device having display device capable of being automatically turned off or turned on according to switch motion of host - An exemplary computer device ( | 2008-09-04 |
| 20080215899 | METHOD AND APPARATUS FOR NEGOTIATING POWER BETWEEN POWER SOURCING EQUIPMENT AND POWERABLE DEVICES - The present invention provides a power negotiation protocol that enables PDs and PSEs to negotiate the amount of inline power that a PD consumes and the corresponding PSE provides. This power negotiation allows the PDs provide fine-grained power consumption level to PSEs, and the PSEs are able to manage inline power efficiently using the negotiation protocol of the present invention. The PDs can ask the PSEs for more power when needed rather than having to constantly reserve the maximum amount of power they can consume at all times. Similarly, the PDs can release reservation of excess power when their respective power requirements decrease. The PSEs can limit the amount of power that can be consumed by the PD, thereby providing the ability for an administrator to control how much power a given PD can consume. | 2008-09-04 |
| 20080215900 | Power-Managed Server and Method for Managing Power Consumption - A power-managed server and method for managing power consumption is disclosed. According to one embodiment, a power-managed server data processing system is provided among a plurality of server data processing systems which comprises a power management communication port to communicatively couple the power-managed server data processing system to a power management server data processing system of the plurality of server data processing systems. The power-managed server data processing system of the described embodiment further comprises a system management processor coupled to the power management communication port which comprises power-managed logic configured to transmit power management data to the power management server data processing system and to receive a power management command utilizing the power management communication port. Moreover, the power management command is generated utilizing the power management data, and the power management data comprises power management capability data. | 2008-09-04 |
| 20080215901 | BATTERY POWERED DEVICE WITH DYNAMIC AND PERFORMANCE MANAGEMENT - A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a variable frequency generator, a variable voltage power supply and voltage supply level and clocking frequency management circuitry. The variable frequency generator is coupled to the processor and delivers a clock signal to the processor. The variable voltage power supply is coupled to the processor and delivers voltage to the processor. The voltage supply level and clocking frequency management circuitry adjust both the voltage provided by the variable voltage power supply and the frequency of the signal provided by the variable frequency generator. The computing device includes a temperature sensor that provides signals indicative of the temperature of the processor and the voltage supply level and clocking frequency management circuitry adjusts the voltage and/or the clocking frequency provided by the variable voltage power supply. The computing device may also include a fan controlled by the voltage supply level and clocking frequency management circuitry, the fan adjusting the temperature of the processor when activated. In cold weather applications, the computing device may further include a heater controlled by the voltage supply level and clocking frequency management circuitry that raises the temperature of the processor when activated. | 2008-09-04 |
| 20080215902 | METHOD AND APPARATUS FOR NEGOTIATING POWER BETWEEN POWER SOURCING EQUIPMENT AND POWERABLE DEVICES - The present invention provides a power negotiation protocol that enables PDs and PSEs to negotiate the amount of inline power that a PD consumes and the corresponding PSE provides. This power negotiation allows the PDs provide fine-grained power consumption level to PSEs, and the PSEs are able to manage inline power efficiently using the negotiation protocol of the present invention. The PDs can ask the PSEs for more power when needed rather than having to constantly reserve the maximum amount of power they can consume at all times. Similarly, the PDs can release reservation of excess power when their respective power requirements decrease. The PSEs can limit the amount of power that can be consumed by the PD, thereby providing the ability for an administrator to control how much power a given PD can consume. | 2008-09-04 |
| 20080215903 | POWER MANAGEMENT OF NON-VOLATILE MEMORY SYSTEMS - Methods and apparatus for placing a non-volatile memory systems in one of a number of power-down modes in response to events being monitored are useful in reducing power consumption of the non-volatile memory system. The power-down modes provide for successively less functionality, thus providing for successively less power consumption. A non-volatile memory system thus can respond to the events to place the system in a mode that permits the desired operation or a desired response time for subsequent operations while seeking to minimize power consumption. | 2008-09-04 |
| 20080215904 | INTERFACE CIRCUIT - An interface circuit is disclosed. | 2008-09-04 |
| 20080215905 | Interface Device, Circuit Module, Circuit System, Device for Data Communications and Method for Calculating a Circuit Module - An interface device allows data communication between a controller and a plurality of circuit units. The interface device has a first interface for a connection to the controller, a second interface for a connection to a second circuit unit, and a third interface for a connection to a second circuit unit. An interface calibrating unit is coupled to the second and third interfaces and a non-volatile calibrating parameter memory is arranged in the interface calibrating unit or coupled to the calibrating unit. The memory is adapted to store calibrating parameters for the second and third interfaces. | 2008-09-04 |
| 20080215906 | Method for Fault Tolerant Time Synchronization Mechanism in a Large Scaleable Multi-Processor Computer - Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips. | 2008-09-04 |
| 20080215907 | Method and apparatus for the generation and control of clock signals - Methods and apparatuses for the dynamic configuring of profiles used for the control of the frequency of clock signals. At least one embodiment of the present invention provides a means of dynamically generating, storing, updating and using spread spectrum profiles in a clock circuit to provide spread spectrum modulated clock signals and to slew clock frequency. | 2008-09-04 |
| 20080215908 | Sleep Watchdog Circuit For Asynchronous Digital Circuits - The sleep watchdog circuit for asynchronous circuits of the present invention contains clock means, counting means with multiple trigger input function and a digital supply. When the circuit is in the normal operation state, a periodic reset or activity signal is present that will reset the watchdog counter. As a result the clock means will keep on running, and the digital supply is operating in “normal” mode. When the circuit is put into the “sleep/standby” state, the “activity” signal becomes inactive, and if no wakeup events occur before the counter is finished the clock means will be put to a halt and the digital supply changes into a low power mode. | 2008-09-04 |
| 20080215909 | APPARATUS, SYSTEM, AND METHOD FOR TRANSACTIONAL PEER RECOVERY IN A DATA SHARING CLUSTERING COMPUTER SYSTEM - The invention provides an apparatus, system, and method for cluster-wide peer recovery in the event of a computer failure. A failure of a first computer is detected and a recovery module is registered as the first computer. In one embodiment, the recovery module is a peer computer. The recovery module retrieves a privately held undo log data through the authorized assumption of the failure identity associated with the failed first computer, backs out in-flight transaction updates of the first computer, and frees up data resources locked by the first computer. | 2008-09-04 |
| 20080215910 | High-Availability Networking with Intelligent Failover - Methods and systems for maintaining high-availability in a computer network using intelligent failover are presented. In a network switch running an OSI model layer-2 or higher protocol on its external links, the protocol state information is monitored to determine failover status of the link to avoid identifying external link failures due to link flapping. One such protocol is the spanning tree protocol. Additionally, flexibility in failover is provided using configurable triggers to define external failure events. The triggers initiate a link drop of one or more internal links of the network switch in response to an external failure event. The link drops, in turn, initiate failover of an attached computing device to a redundant link through a network interface teaming/failover arrangement whereby the computing device switches to an alternative network interface accessing the network through a redundant path. Failover can be selective depending upon VLAN and trunking configurations. | 2008-09-04 |
| 20080215911 | Storage device capable of meeting the reliability and a building and data writing method thereof - A storage device capable of meeting the reliability has a storage capacity and the reliability of the storage device is defined. The storage device includes at least one first storage unit, at least one second storage unit, and a control unit. The first storage unit forms the storage capacity of the storage device. The second storage unit is allocated to form a spare capacity according to the storage capacity and the reliability. The second storage unit replaces the bad blocks in the first storage unit. The control unit controls the first storage unit and the second storage unit to transmit and convert the data with an application system. Thereby, by allocating the spare capacity of the second storage unit, the different reliability requirement is met, and the storage capacity of the first storage unit is unaffected. | 2008-09-04 |
| 20080215912 | System and Method for Raid Recovery Arbitration in Shared Disk Applications - A RAID controller is provided for each host sharing a RAID. Each RAID controller can determine whether another host is sharing the RAID and assume a master or slave status with respect to rebuild operations for the shared disk. The master controller may then manage any rebuild operations on rebuild disks within the RAID. | 2008-09-04 |
| 20080215913 | Information Processing System and Information Processing Method - An anomaly detector detects anomaly of a first device. A second device reset part, in case that anomaly has been detected by the anomaly detector, resets a second device. A first device reset part, in case that anomaly has been detected by the anomaly detector, resets a first device. Further, a collating part collates data generated by the first device with data generated by the second device, and judges anomaly when these data are in disagreement with each other. A reset part, in case that the anomaly has been judged by the collating part, resets the second device. | 2008-09-04 |
| 20080215914 | Self-reparable semiconductor and method thereof - A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually. | 2008-09-04 |
| 20080215915 | Mechanism to Change Firmware in a High Availability Single Processor System - A “high availability” system comprises multiple switches under the control of a control processor (“CP”). The firmware executing on the processor can be changed when desired. Consistent with the high availability nature of the system (i.e., minimal down time), a single CP system implements a firmware change by loading new firmware onto the system, saving state information pertaining to the old firmware, preventing the old firmware from communicating with the switches, bringing the new firmware to an active state and applying the saved state information to the new firmware. | 2008-09-04 |
| 20080215916 | TEMPLATE BASED PARALLEL CHECKPOINTING IN A MASSIVELY PARALLEL COMPUTER SYSTEM - A method and apparatus for a template based parallel checkpoint save for a massively parallel super computer system using a parallel variation of the rsync protocol, and network broadcast. In preferred embodiments, the checkpoint data for each node is compared to a template checkpoint file that resides in the storage and that was previously produced. Embodiments herein greatly decrease the amount of data that must be transmitted and stored for faster checkpointing and increased efficiency of the computer system. Embodiments are directed to a parallel computer system with nodes arranged in a cluster with a high speed interconnect that can perform broadcast communication. The checkpoint contains a set of actual small data blocks with their corresponding checksums from all nodes in the system. The data blocks may be compressed using conventional non-lossy data compression algorithms to further reduce the overall checkpoint size. | 2008-09-04 |
| 20080215917 | Synchronizing Cross Checked Processors During Initialization by Miscompare - A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user. | 2008-09-04 |
| 20080215918 | METHOD FOR MONITORING SERVER SUB-SYSTEM HEALTH - A server self health monitor (SHM) system monitors the health of the server it resides on. The health of a server is determined by the health of all of a server's sub-systems and deployed applications. The SHM may make health check inquiries to server sub-systems periodically or based on external trigger events. The sub-systems perform self health checks on themselves and provide sub-system health information to requesting entities such as the SHM. Sub-systems self health updates may be based on internal events such as counters or changes in status or based on external entity requests. Corrective action may be performed upon sub-systems by the SHM depending on their health status or the health status of the server. Corrective action may also be performed by a sub-system upon itself. | 2008-09-04 |
| 20080215919 | Method and System for Verifying Information Handling System Hardware Component Failure Diagnosis - Hardware component failure diagnosis of an information handling system is verified with a hardware diagnostics code generated by a diagnostics module integrated with an information handling system and sent from the information handling system to a diagnostics engine of a service center. The hardware diagnostics code includes a unique identifier for the information handling system and a hardware component failure code that identifies the type of hardware and type of failure. The diagnostics engine analyzes the hardware diagnostics code to confirm that diagnostics were run on the information handling system and, for authentic hardware failures, automatically initiates the sending of a replacement hardware component to the information handling system. | 2008-09-04 |
| 20080215920 | PROGRAM CODE TRACE SIGNATURE - A processor generates a signature value indicating a sequence of executed instructions, and the signature value is compared to signature values calculated for two or more possible sequences of executed instructions to determine which instruction sequence was executed. The signature is generated via a signature generator during program execution, and is provided external to the processor via a signature message. | 2008-09-04 |
| 20080215921 | Method, System and Computer Program for Performing Regression Tests Based on Test Case Effectiveness | 2008-09-04 |
| 20080215922 | Method and System for Diagnosing an Application - A system, method and program enabling users to diagnose applications easily without affecting the operating performance of the application server, optimizing the log mechanism based on the integrated development environment. The method includes running the application in a main running environment and at least one shadow environment, the shadow environment obtained by duplicating the main running environment; and the main running environment interacting with the shadow environment with respect to the fault of the application. The method includes performing the steps of the main running environment: monitoring the exceptions in the system and sending system exception information to the shadow environment in the event of finding exceptions in the system. The shadow environment: receives the system exception information, opens diagnostic log/trace functions to obtain diagnosis log/trace files related to the system exceptions, and analyzes the diagnosis result based on the obtained diagnosis log/trace files. | 2008-09-04 |
| 20080215923 | DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TRIGGER) - Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events. | 2008-09-04 |
