| 36th week of 2008 patent applcation highlights part 44 |
| Patent application number | Title | Published |
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| 20080213918 | Polynucleotides encoding two novel human G-protein coupled receptors, HGPRBMY28 and HGPRBMY29, and splice variants thereof - The present invention provides novel polynucleotides encoding HGPRBMY28 and HGPRBMY29 polypeptides, fragments and homologues thereof. The present invention also provides polynucleotides encoding splice variants of HGPRBMY29 polypeptides, HGPRBMY29v1 and HGPRBMY29v2. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to diagnostic and therapeutic methods for applying these novel HGPRBMY28, HGPRBMY29, HGPRBMY29v1, and HGPRBMY29v2 polypeptides to the diagnosis, treatment, and/or prevention of various diseases and/or disorders related to these polypeptides. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention. | 2008-09-04 |
| 20080213919 | Functionalized fluorescent nanocrystals, and methods for their preparation and use - Functionalized fluorescent nanocrystal compositions and methods for making and using these compositions are disclosed. The compositions are fluorescent nanocrystals coated with at least one material. The coating material has chemical compounds or ligands with functional groups or moieties with conjugated electrons and moieties for imparting solubility to coated fluorescent nanocrystals in aqueous solutions. The coating material provides for functionalized fluorescent nanocrystal compositions which are water soluble, chemically stable, and emit light with a high quantum yield and/or luminescence efficiency when excited with light. The coating material may also have chemical compounds or ligands with moieties for bonding to target molecules and cells as well as moieties for cross-linking the coating. In the presence of reagents suitable for reacting to form capping layers, the compounds in the coating may form a capping layer on the fluorescent nanocrystal with the coating compounds operably bonded to the capping layer. | 2008-09-04 |
| 20080213920 | DIAGNOSTIC DETECTION DEVICE - The invention comprises a device for detecting an analyte in a liquid sample deposited on a first portion of the device for transport to a second portion of the device that is in fluid contact with the first portion. In specific embodiments, the device comprises a labeled conjugate comprising a binding member reactive with a first epitope of the analyte and a label comprising a gold colloid, preferably having a mean particle size of 50 nm to 100 nm. In further embodiments, the device comprises a capture component comprising polymerized streptavidin. The diagnostic device is particularly useful in the preparation of pregnancy test kits. | 2008-09-04 |
| 20080213921 | Immunoassay Methods - The invention generally relates to the field of diagnostic or prognostic assays and in particular relates to assays for the detection of antibodies in a sample comprising patient bodily fluid, wherein such antibodies are used as biological markers of a disease state or disease susceptibility. The assay is based on cross-titration of both the patient bodily fluid to be tested for the antibody and an antigen used to detect the antibody by specific binding. | 2008-09-04 |
| 20080213922 | Method And System For Identification Of Antigen - There is provided a method for the identification of antigens recognized by a given antibody. In particular the method provides for characterization of the epitope recognized by the antibody and for purification based on the physico-chemical properties of the antigen. The characterization facilitates subsequent analysis of the antigen for identification purposes. | 2008-09-04 |
| 20080213923 | DNA-Based Memory Device and Method of Reading and Writing Same - The present invention is directed to a memory device having very high storage density capability. In general, the memory device includes an array of individual memory cells which store information that is assigned a value based on the molecular contents of the memory cell. In a preferred embodiment, the molecules utilized for storing information in the memory cells may be single-strand polynucleotides, for instance single-strand oligonucleotides of between about 5 and about 20 monomer units. The present invention is also directed to methods and systems useful for writing and reading the molecular-based memory devices. In particular, the devices may be written and read via modified atomic force microscopy processes. | 2008-09-04 |
| 20080213924 | Ferroelectric memory device and method of manufacturing the same - A method of manufacturing a ferroelectric memory device includes: forming a hydrogen barrier film which covers a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, wherein a thickness of an area of the hydrogen barrier film provided on the upper electrode is made greater than a thickness of an area of the hydrogen barrier film provided on a sidewall of the ferroelectric capacitor by forming the area of the hydrogen barrier film provided on the upper electrode in a plurality of layers. | 2008-09-04 |
| 20080213925 | PHOTOMETRICALLY MODULATED DELIVERY OF REAGENTS - A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the sampling region, based on its interaction with the infrared radiation; and process control means arranged to receive the output of the infrared photometric monitor and to responsively control one or more process conditions in and/or affecting the process system. | 2008-09-04 |
| 20080213926 | METHOD FOR EVALUATING A SEMICONDUCTOR SUBSTRATE - A method for evaluating a semiconductor substrate is provided that can evaluate even a thin semiconductor substrate or a substrate with untreated surfaces, can evaluate a large quantity of semiconductor substrates for solar cells in a short time and can be used as in-line inspection in a production process of solar cells or the like. The method for evaluating a semiconductor substrate comprises a step of immersing a semiconductor substrate in an etching solution filled in a container, a step of irradiating the substrate being immersed in the etching solution with light via the etching solution to cause the substrate to emit photoluminescence, and a step of observing the emitted photoluminescence. | 2008-09-04 |
| 20080213927 | METHOD FOR MANUFACTURING AN IMPROVED RESISTIVE STRUCTURE - Provided, in one embodiment, is a method for manufacturing a resistive structure. This method, without limitation, includes forming a substrate, and forming a tantalum-aluminum-nitride resistive layer over the substrate. Moreover, a bulk resistivity of the tantalum-aluminum-nitride resistive layer may be adjusted by varying at least one deposition condition selected from the group consisting of a flow rate ratio of nitrogen to argon, power, pressure, temperature and radio frequency (RF) bias voltage. | 2008-09-04 |
| 20080213928 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method for manufacturing a semiconductor light emitting device can result in a device that includes a housing having a cavity, a light emitting element on a bottom face of the cavity, and a wavelength conversion layer provided within the cavity. The wavelength conversion layer can include particles of a wavelength conversion material. The method includes forming the wavelength conversion layer within the cavity, which can include applying and hardening a first material to form a first wavelength conversion layer on the light emitting element, and applying and hardening a second material to substantially fill the remainder of the entire cavity, thereby forming a second wavelength conversion layer. The semiconductor light emitting device manufactured by the inventive method can achieve uniform light emitting characteristics without substantially any uneven color and can include high heat dissipation efficiency. | 2008-09-04 |
| 20080213929 | Light Emitting Device - An objective is to increase the reliability of a light emitting device structured by combining TFTs and organic light emitting elements. A TFT ( | 2008-09-04 |
| 20080213930 | Dual panel-type organic electroluminescent display device and method of fabricating the same - A dual panel-type organic electroluminescent display device includes first and second substrates facing and spaced apart from each other, an array element layer disposed along an inner surface of the first substrate, the array element including a thin film transistor, a connection pattern disposed on the array element layer and electrically connected to the thin film transistor, a color filter layer disposed along an inner surface of the second substrate, the color filter layer including red, green, and blue color filters, an overcoat layer disposed on the color filter layer, the overcoat layer including a hygroscopic material, an organic electroluminescent diode disposed on the overcoat layer and connected to the connection pattern, the organic electroluminescent diode including a first electrode, an organic light-emitting layer, and a second electrode sequentially formed on the overcoat layer, and the organic light-emitting layer emits substantially monochromatic light, and a seal pattern along peripheral portions between the first and second substrates. | 2008-09-04 |
| 20080213931 | LIGHT EMITTING DEVICE - A light emitting device includes a laminate of a lower electrode layer, an organic light-emitting layer, and an upper transparent electrode layer. In the light emitting device, an auxiliary electrode layer is formed of colloidal nano-sized particles of a conductive metal between the lower electrode layer and the organic light-emitting layer. The auxiliary electrode layer causes the lower electrode layer to be flat and the light emitting efficient to be improved. A light emitting device having a structure in which a transparent electrode layer is formed as the lower electrode layer, and an organic light-emitting layer, an auxiliary electrode layer, and an upper electrode layer are sequentially formed thereon has the same effects. When glass is produced by a sol-gel method using metal alkoxide and the light emitting device is sealed by the glass, it is possible to extend the light emitting period. | 2008-09-04 |
| 20080213932 | METHOD OF IMPROVING THE FLATNESS OF A MICRODISPLAY SURFACE AND METHOD OF MANUFACTURING LIQUID CRYSTAL ON SILICON (LCOS) DISPLAY PANEL THE SAME - A method of improving the flatness of a microdisplay surface is disclosed. A reflective mirror layer and a raised layer are formed in order on substrate. The raised layer may comprise a buffer layer and a stop layer, and pixel electrode areas are defined therefrom and gaps are consequently formed among the pixel electrode areas. A dielectric layer is deposited on the pixel electrode areas and fills the gaps. A dielectric layer is partially removed such that the portion on the raised layer is completely removed and the portion filling the gaps are partially removed, thereby the remaining dielectric layer in the gaps has a height not lower than the top of the mirror layer. Thereafter, the raised layer is entirely or partially removed. A transparent conductive layer may be further combined onto the semiconductor substrate and a liquid crystal filling process is performed to form an LCoS display panel. | 2008-09-04 |
| 20080213933 | METHODS OF FABRICATING A LARGE AREA TRANSDUCER ARRAY - Methods of fabricating a tiled transducer array are disclosed. Embodiments of the methods include fabricating a wafer comprising a plurality of transducers, dicing the wafer to form individual transducers, testing the individual transducers to identify a plurality of known good transducers, preparing a substrate having a front side and a backside wherein the backside of the substrate comprises a plurality of connectors, positioning the plurality of known good transducers on the front side of the substrate and aligning the plurality of transducers in a horizontal direction and a vertical direction to form a transducer array, and electrically coupling the connectors on the substrate to the plurality of known good transducers, wherein the connectors are arranged such that each of the plurality of known good transducers may be electrically coupled to an electronic device disposed on the backside of the substrate, through a respective one or more of the plurality of connectors. | 2008-09-04 |
| 20080213934 | INTEGRATED DEVICE MANUFACTURING PROCESS - A process for manufacturing an integrated device includes the steps of: providing a silicon substrate on which a silicon dioxide structure is arranged; and forming a trench having first and second essentially vertical walls relative to the substrate in the structure by means of anisotropic-type etching. A concavity having a sloped wall relative to the substrate is formed by isotropic-type etching which removes the second wall so that the concavity is open to the trench and the sloped wall faces the first wall. | 2008-09-04 |
| 20080213935 | Manufacturing Method of Solid-State Imaging Device - Provided is a manufacturing method of a CCD solid-state imaging device having such an impurity concentration distribution with which shading is reduced and formation of a buried channel endowed with a large saturation signal charge amount is made possible. The manufacturing method includes: an oxide layer forming step of forming an oxide layer ( | 2008-09-04 |
| 20080213936 | Alignment mark forming method, alignment method, semiconductor device manufacturing method, and solid-state image capturing apparatus manufacturing method - An alignment mark forming method according to the present invention includes: an alignment mark forming step of using an impurity implantation region as an alignment target layer and using, as a mask, the same resist film used for forming the impurity implantation region to form an alignment mark that is used when a patterning is performed in at least one of a subsequent impurity implantation step and a subsequent process layer forming step. | 2008-09-04 |
| 20080213937 | METHOD OF FABRICATING OPTICAL DEVICE CAPS - A wafer having a plurality of through holes is provided, and a glass wafer is disposed on the wafer. A plate having a plurality of concave cavities is disposed on the glass wafer, wherein the concave cavities corresponding to the through holes of the wafer so that a part of the plate corresponding to the through holes is not in contact with the glass wafer. A voltage source is provided, and two electrodes thereof respectively have electrical connections to the wafer and the plate. The wafer and the glass wafer are bonded to each other by the anodic bonding method so that a plurality of optical device caps are formed. | 2008-09-04 |
| 20080213938 | METHOD FOR FABRICATING A CMOS IMAGE SENSOR - A method for fabricating a CMOS image sensor is disclosed. First, a substrate having a sensor array region and a peripheral region is provided. A contact pad is formed on the substrate of the peripheral region, and a dielectric layer is disposed on the substrate for exposing the surface of the contact pad. A cap layer is disposed on the dielectric layer and the contact pad, in which the cap layer is patterned to form an optical shielding layer on the dielectric layer of the peripheral region and a passivation layer on the contact pad. Subsequently, a plurality of color filters, a planarizing layer, and a plurality of microlenses are disposed on the dielectric layer. | 2008-09-04 |
| 20080213939 | Solid-state imaging device and method for producing the same - In a solid-state imaging device, a light-shielding film | 2008-09-04 |
| 20080213940 | Methods of forming metal oxide layers, methods of forming gate structures using the same, and methods of forming capacitors using the same - Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NR | 2008-09-04 |
| 20080213941 | Bump-on-Lead Flip Chip Interconnection - A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process. | 2008-09-04 |
| 20080213942 | Method for fabricating semiconductor device and carrier applied therein - This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions. The inspection aperture is inspected with a naked eye to determine whether the gap is completely filled with the adhesive, thereby reducing inspection costs and increasing yields of products with no additional packaging costs. | 2008-09-04 |
| 20080213943 | THERMOSETTING DIE BONDING FILM - The thermosetting die bonding film of the invention is a thermosetting die bonding film used to produce a semiconductor device, which contains, as main components, 5 to 15% by weight of a thermoplastic resin component and 45 to 55% by weight of a thermosetting resin component, and has a melt viscosity of 400 Pa·s or more and 2500 Pa·s or less at 100° C. before the film is thermally set. | 2008-09-04 |
| 20080213944 | STRUCTURE COMBINING AN IC INTEGRATED SUBSTRATE AND A CARRIER, AND METHOD OF MANUFACTURING SUCH STRUCTURE - The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure. | 2008-09-04 |
| 20080213945 | Semiconductor device and fabrication process thereof - A semiconductor device includes a mount substrate and a semiconductor chip mounted upon the mount substrate via a metal bump, wherein metal bump includes an inner part joined to the semiconductor chip and an outer part covering the inner part, the outer part having an increased hardness as compared with the inner part. | 2008-09-04 |
| 20080213946 | SUBSTRATE BASED UNMOLDED PACKAGE - A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes. | 2008-09-04 |
| 20080213947 | Resin encapsulation molding method for semiconductor device - According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the device-mounted substrate is set in one mold part. A release film is thereafter provided between the device-mounted substrate and the other mold part opposite to that one mold part. The one and other mold parts are then closed to press the release film against the portion of the semiconductor device. The device-mounted substrate has a projection enclosing the portion of the semiconductor device for preventing resin flash from being formed. When the mold parts are closed, the release film is pressed against the projection to allow the projection to dig into the release film. | 2008-09-04 |
| 20080213948 | DUAL WIRED INTEGRATED CIRCUIT CHIPS - A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts. | 2008-09-04 |
| 20080213949 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE - A method for manufacturing a substrate for a flat panel display device is disclosed. The present method uses photolithography with four masks to manufacture a TFT-LCD. After the third half-tone mask is used, the manufacturing of the TFTs and the defining of the pixel area of the substrate can be completed. The present method can avoid the alignment deviation and the generation of parasitic capacitance happened on the substrate made through the conventional photolithography with five masks. Therefore, the present method can reduce the costs and increase the yield. Moreover, the substrate for the TFT-LCD made by the present method can define a channel region in the semiconductor layer after the second half-tone mask. Hence, the subsequent manufacturing for forming a transparent conductive layer, a source, and a drain can be achieved by wet etching to effectively reduce the non-homogeneous etching for the channel region in the semiconductor layer. | 2008-09-04 |
| 20080213950 | Array substrate for a liquid crystal display and method for fabricating thereof - An array substrate for a liquid crystal display device includes a substrate, a plurality of thin film transistors formed on the substrate, each thin film transistor includes a gate electrode, a first gate insulation layer, a second gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode, a plurality of gate lines, a plurality of data lines disposed orthogonal to the plurality of gate lines, a plurality of pixel electrodes disposed at pixel regions defined by intersections of the plurality of gate lines and the plurality of data lines, each pixel electrode electrically contacting each drain electrode of the plurality of thin film transistors, and a plurality of storage capacitors each including a portion of each gate line as a first capacitor electrode, the first gate insulation layer as a dielectric layer, and a capacitor electrode electrically communicating with each pixel electrode and functioning as a second capacitor electrode with a portion of each pixel electrode. | 2008-09-04 |
| 20080213951 | Method of fabricating pixel structure - A method of fabricating a pixel structure including the following procedures is provided. First, a substrate having an active device thereon is provided. A patterned passivation layer is formed on the substrate and the active device, and the patterned passivation layer exposes a portion of the active device. Then, a conductive layer is formed over the patterned passivation layer, and the conductive layer is electrically connected to the active device. A mask exposing a portion of the conductive layer is provided above the conductive layer. A laser is used to irradiate the conductive layer via the mask to remove the portion of the conductive layer exposed by the mask. As a result, the remained portion of the conductive layer constitutes a pixel electrode, and the pixel electrode is electrically connected to the active device. The method simplifies the fabrication process of a pixel structure, and thus reduces the fabrication cost. | 2008-09-04 |
| 20080213952 | SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION - A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer. | 2008-09-04 |
| 20080213953 | Method of manufacturing a semiconductor device - There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained. | 2008-09-04 |
| 20080213954 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film. | 2008-09-04 |
| 20080213955 | Schottky Diode With Minimal Vertical Current Flow - A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region. | 2008-09-04 |
| 20080213956 | FIELD EFFECT TRANSISTOR DEVICE INCLUDING AN ARRAY OF CHANNEL ELEMENTS - The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel. | 2008-09-04 |
| 20080213957 | Integrated circuit with multi-length output transistor segments - A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the semiconductor die, the L-shaped area having first and second inner sides that are respectively disposed adjacent first and second sides of the control circuit. At least one of the first and second output transistors is coupled to the control circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2008-09-04 |
| 20080213958 | Capacitor structure and fabricating method thereof - Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts. | 2008-09-04 |
| 20080213959 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield - An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced. | 2008-09-04 |
| 20080213960 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING A TRENCH-STUFFED LAYER - A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer. A first conductivity type source region is produced in the second conductivity type base region, and both a gate insulating layer and a gate electrode layer are produced so as to be associated with the first conductivity type source region and the first conductivity type drift layer such that an inversion region is defined in the second conductivity type base region in the vicinity of both the gate insulating layer and the gate electrode layer. | 2008-09-04 |
| 20080213961 | PROCESS FOR MANUFACTURING A TFT DEVICE WITH SOURCE AND DRAIN REGIONS HAVING GRADUAL DOPANT PROFILE - Process for realizing TFT devices on a substrate which comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device. | 2008-09-04 |
| 20080213962 | STRAINED SILICON WITH ELASTIC EDGE RELAXATION - A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations. | 2008-09-04 |
| 20080213963 | Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same - A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described. | 2008-09-04 |
| 20080213964 | FIELD EFFECT TRANSISTOR WITH THIN GATE ELECTRODE AND METHOD OF FABRICATING SAME - A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness. | 2008-09-04 |
| 20080213965 | METHOD FOR MANUFACTURING DMOS DEVICE - A method for manufacturing a semiconductor device is provided. The semiconductor device may be a drain extended metal-oxide-semiconductor (DMOS) device. The method includes: forming a gate insulating film on a semiconductor substrate having an active region; forming a gate on the gate insulating film; forming a low-concentration source region and a low-concentration drain region over the semiconductor substrate by implanting low-concentration impurity ions using the gate as a mask; forming a spacer on sides of the gate; forming a silicide area block (SAB) pattern over the semiconductor substrate, covering a portion of the gate and the low-concentration drain region; and forming a high-concentration source region and a high-concentration drain region over the semiconductor substrate by implanting high-concentration impurity ions using the SAB pattern as a mask. | 2008-09-04 |
| 20080213966 | INDUCTOR EMBEDDED IN SUBSTRATE, MANUFACTURING METHOD THEREOF, MICRO DEVICE PACKAGE, AND MANUFACTURING METHOD OF CAP FOR MICRO DEVICE PACKAGE - An inductor embedded in a substrate, including a substrate, a coil electrode formed by filling a metal in a spiral hole formed on the substrate, an insulation layer formed on the substrate, and an external connection pad formed on the insulation layer to be connected to the coil electrode. The inductor-embedded substrate can be used as a cap for a micro device package by forming a cavity on its bottom surface. | 2008-09-04 |
| 20080213967 | TRENCH CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - Method of manufacturing a trench capacitor includes providing a substrate having a memory array region and a logic region, performing a shallow trench isolation (STI) process for forming at least a STI in the substrate within each of the memory array regions and the logic regions, forming a patterned hard mask and the hard mask exposing a portion of the STI and a portion of the substrate surrounding the STI on the substrate, performing a first etching process to form first deep trenches through the patterned hard mask, performing a second etching process to form second deep trenches extending downwardly from the first deep trenches respectively, and forming a capacitor structure in each of the first deep trenches and the second deep trenches. | 2008-09-04 |
| 20080213968 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes firstly providing a substrate. A doped first dielectric layer and an undoped second dielectric layer are then formed on the substrate sequentially. Next, many trenches are formed in the first and the second dielectric layers. Afterwards, an ion implantation process is performed in the largest space between the adjacent trenches to form an ion-implanted region in a portion of the second dielectric layer in upper parts of the trenches. A wet etching process is then performed to remove a portion of the second dielectric layer in the ion-implanted region and a portion of the first dielectric layer at bottoms of the trenches. Thereafter, a first conductive layer and a capacitor dielectric layer are formed sequentially on surfaces of the trenches. Finally, a second conductive layer is formed in the trenches. | 2008-09-04 |
| 20080213969 | METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - The present invention is related to a method of forming an isolation layer in a semiconductor device and comprises the steps of forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, the width of an upper portion of the conductive layer patterns being narrower than that of a lower portion; forming a trench between the conductive layer patterns on the semiconductor substrate; forming an insulating layer to fill a portion of the trench with the insulating layer; and performing an etching process to remove an overhang of the insulating layer formed at an upper edge of the conductive layer patterns. Here, the step of forming the insulating layer and the step of performing the etching process are repeatedly performed until a space between the conductive layer patterns and the trench are filled with the insulating layer. | 2008-09-04 |
| 20080213970 | PROCESS FOR THE FORMATION OF DIELECTRIC ISOLATION STRUCTURES IN SEMICONDUCTOR DEVICES - A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material. | 2008-09-04 |
| 20080213971 | Semiconductor device having dual-STI and manufacturing method thereof - A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. | 2008-09-04 |
| 20080213972 | Processes for forming isolation structures for integrated circuit devices - Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 2008-09-04 |
| 20080213973 | METHOD OF FABRICATING A SUBSTRATE FOR A PLANAR, DOUBLE-GATED, TRANSISTOR PROCESS - A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN. | 2008-09-04 |
| 20080213974 | Method of manufacturing bonded wafer - The present invention provides a method of manufacturing a bonded wafer. The method comprises an oxidation step in which an oxide film is formed on at least one surface of a base wafer, a bonding step in which the base wafer on which the oxide film has been formed is bonded to a top wafer to form a bonded wafer, and a thinning step in which the top wafer included in the bonded wafer is thinned. The oxidation step comprises heating the base wafer to a heating temperature ranging from 800 to 1300° C. at a rate of temperature increase ranging from 1 to 300° C./second in an oxidizing atmosphere, and the bonding step is carried out so as to position the oxide film formed in the oxidation step at an interface of the top wafer and the base wafer. | 2008-09-04 |
| 20080213975 | Supply Mechanism For the Chuck of an Integrated Circuit Dicing Device - A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table ( | 2008-09-04 |
| 20080213976 | METHODS FOR FABRICATING SEMICONDUCTOR COMPONENTS AND PACKAGED SEMICONDUCTOR COMPONENTS - Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall. | 2008-09-04 |
| 20080213977 | Vacuum expansion of integrated circuits at sort - A frame and vacuum expansion chuck are used in combination for stretching a tape carrying a plurality of singulated devices to facilitate removal of the devices with reduced risk of contact between a device being removed from the tape and an adjacent device on the tape. The combination includes a frame for holding edges of a tape carrying a plurality of singulated devices, and a vacuum chuck having upper surfaces for contacting an underside of a tape carrying a plurality of singulated devices. The vacuum chuck extends along a perimeter circumscribing the singulated devices, and at least one groove is defined in the upper surface of the vacuum chuck. Conduit for providing fluid communication between the groove and a vacuum source are provided. Upon evacuation of the volume defined between the groove and the tape, the tape is drawn down into the groove and stretched, thereby increasing the separation or gap between adjacent dice and reducing the risk of damage upon removal of the dice. | 2008-09-04 |
| 20080213978 | Debris management for wafer singulation - The present invention discloses methods and apparatuses for substrate singulation. Embodiments of the present invention comprise cryogenic-assist scribing or cutting mechanism for debris reduction, preferably cryogenic-assist laser scribe or cutting; controlling mechanism for debris flow and redeposition during laser process; and integrated, dry debris removal scribing process with breaking mechanism. An exemplary embodiment comprises an integrated housing for aligning a laser beam with the cryogenic cleaning beam. The integrated housing is preferably made of low thermal conductivity material to provide a high temperature gradient between the low temperature of the cryogenic fluid and the ambient temperature, preventing condensation of the moisture. The entire areas, or the critical areas of the apparatus can also be purged with flowing “dry” inert gases to further reduce the condensation moisture. Reactive gas can be introduced to react with debris, converting into gaseous form for ease of removal. | 2008-09-04 |
| 20080213979 | METHOD AND APPARATUS FOR BREAKING SEMICONDUCTOR SUBSTRATE, METHOD FOR BREAKING SOLAR CELL AND METHOD FOR FABRICATION OF SOLAR CELL MODULE - A method and apparatus for breaking a semiconductor substrate along a predetermined area over which a split groove is formed. The breaking apparatus includes a table for placing a portion of the semiconductor substrate inside the predetermined area and a breaking blade being operable to move downward from a position above the semiconductor substrate placed on the table to thereby compress a portion of the semiconductor substrate outside the predetermined area so that the semiconductor substrate is broken along the split groove. The predetermined area of the semiconductor substrate has at least a neighboring pair of sides intersecting at an angle of less than 180 degrees, and the breaking blade has a projection which, when the semiconductor substrate is broken, compresses a portion of the semiconductor substrate outside the one side so that the one side is compressed ahead of the other side. | 2008-09-04 |
| 20080213980 | Process Applied to Semiconductor - A process applied to grinding, dicing, and/or stacking semiconductors is disclosed. One of its features is that after transparent material is stuck on its active surface, a semiconductor is ground from another surface thereof to become thinner, then take advantage of transparency of the transparent material to cut the transparent material and the semiconductor, to obtain at least one smaller semiconductor unit such as die or chip. Another feature is that the transparent material remains sticking to the active surface of the die by an adhesion layer until the die is attached to a carrier or another die, and then the transparent material and the adhesion layer are removed by taking advantage of a function of the adhesion layer: receiving a ray to lose adhesion between it and the active surface. Preferably the ray reaches the adhesion layer via the transparent material stuck on the active surface of the die. | 2008-09-04 |
| 20080213981 | Method of Fabricating a Silicon-On-Insulator Structure - In the field of sensor fabrication, it is known to form a silicon-on-insulator starting structure from which fabrication of the sensor based. The present invention provides a method of forming a silicon-on-insulator structure comprising a substrate having an insulating layer patterned thereon. A silicon oxide layer is then deposited over the patterned insulating layer before silicon is grown over both an exposed surface of the substrate as well as the silicon oxide layer, mono-crystalline silicon forming on the exposed parts of the substrate and polysilicon forming on the silicon oxide layer. After depositing a capping layer over the structure, the wafer is heated, whereby the polysilicon re-crystallises to form mono-crystalline silicon, resulting in the insulating layer being buried beneath mono-crystalline silicon. | 2008-09-04 |
| 20080213982 | METHOD OF FABRICATING SEMICONDUCTOR WAFER - Provided is a method of fabricating a semiconductor wafer. The method includes preparing a substrate wafer having a non-single-crystalline thin layer; disposing at least one single crystalline pattern adjacent to the non-single-crystalline thin layer on the substrate wafer; and forming a material layer contacting the single crystalline pattern on the non-single-crystalline thin layer. | 2008-09-04 |
| 20080213983 | Method for manufacturing semiconductor device - Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate. | 2008-09-04 |
| 20080213984 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A cap film is formed over semiconductor films formed over an insulating substrate; the semiconductor films are irradiated with a laser beam which is capable of completely melting the semiconductor film in a film-thickness direction to completely melt the semiconductor film. By controlling the laser beam, a crystalline semiconductor films are formed over the substrate, in each of which orientations of crystal planes are controlled. In addition, an n-channel thin film transistor is formed using a crystalline region in which crystal planes are oriented along {001} and a p-channel thin film transistor is formed using a crystalline region in which crystal planes are oriented along {211} or {101}. | 2008-09-04 |
| 20080213985 | METHOD OF FORMING POLYCRYSTALLINE SILICON THIN FILM AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE METHOD - Provided is a method of forming a polycrystalline silicon thin film with improved electrical characteristics. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion of the amorphous silicon thin film by irradiating the portion of the amorphous silicon thin film with a laser beam having a low energy density, forming polycrystalline silicon grains with a predetermined crystalline arrangement by crystallizing the partially molten portion of the amorphous silicon thin film, completely melting a portion of the polycrystalline silicon grains and a portion of the amorphous silicon thin film by irradiation of a laser beam having a high energy density while repeatedly moving the substrate by a predetermined distance, and growing the polycrystalline silicon grains by crystallizing the completely molten silicon homogeneously with the predetermined crystalline arrangement. | 2008-09-04 |
| 20080213986 | LASER ANNEALING METHOD AND LASER ANNEALING DEVICE - In order to promote an effect of laser annealing in respect of a semiconductor film, moisture is intentionally included in an atmosphere in irradiating laser beam to the semiconductor film by which a temperature holding layer comprising water vapor is formed on the surface of the semiconductor film in irradiating the laser beam and the laser annealing operation can be performed effectively. | 2008-09-04 |
| 20080213987 | Method of Fabricating a Sige Semiconductor Structure - A method of fabricating an integrated circuit includes providing a substrate and creating base-windows in a layer. The method also includes forming a monocrystalline SiGe base layer in each of the base layers, and polycrystalline SiGe elsewhere. Additionally, the method also includes forming a monocrystalline silicon layer over selectively exposed portions of the surface of the substrate. The integrated circuit beneficially includes silicon-based elements such as a lateral pnp transistor, a varactor, and a polysilicon transistor, which are formed on a common substrate with an npn SiGe bipolar transistor. | 2008-09-04 |
| 20080213988 | SUBSTRATE HEATING APPARATUS AND SEMICONDUCTOR FABRICATION METHOD - A substrate heating apparatus having a heating unit for heating a substrate placed in a process chamber which can be evacuated includes a suscepter which is installed between the heating unit and a substrate, and on which the substrate is mounted, and a heat receiving member which is installed to oppose the suscepter with the substrate being sandwiched between them, and receives heat from the heating unit via the suscepter. A ventilating portion which allows a space formed between the heat receiving member and substrate to communicate with a space in the process chamber is formed. | 2008-09-04 |
| 20080213989 | SILICON WAFER FOR MANUFACTURING SOI WAFER, SOI WAFER, AND METHOD FOR MANUFACTURING SOI WAFER - A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer. | 2008-09-04 |
| 20080213990 | METHOD FOR FORMING GATE ELECTRODE IN SEMICONDUCTOR DEVICE - A method for forming a gate electrode in a semiconductor device includes providing a substrate, forming a gate insulation layer over the substrate, forming first and second conductive layers over the gate insulation layer, forming a hard mask pattern over the second conductive layer, etching the second conductive layer using the hard mask pattern as an etch mask, performing an oxidation process to form an anti-oxidation layer on a sidewall of the etched second conductive layer, and etching the first conductive layer using the hard mask as an etch mask. | 2008-09-04 |
| 20080213991 | Method of forming plugs - The present invention is a method of forming plugs for engaging with a socket on a substrate having pads thereon. The method including the steps of forming an insulation layer on the substrate, patterning the insulation layer to form openings for exposing the pads by a wet etching, respectively, forming conductive plugs in the openings to electrically connect with the pads, and partially removing the insulation layer. | 2008-09-04 |
| 20080213992 | SEMICONDUCTOR PACKAGE HAVING ENHANCED HEAT DISSIPATION AND METHOD OF FABRICATING THE SAME - A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided. | 2008-09-04 |
| 20080213993 | Method and Apparatus of Stress Relief in Semiconductor Structures - A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer. | 2008-09-04 |
| 20080213994 | Treating a liner layer to reduce surface oxides - In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed. | 2008-09-04 |
| 20080213995 | Ultrasonic electropolishing of conductive material - In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while ultrasonically agitating the semiconductor wafer until a predetermined amount of the conductive layer remains over the barrier layer. Other embodiments are described and claimed. | 2008-09-04 |
| 20080213996 | Designs and methods for conductive bumps - Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer. | 2008-09-04 |
| 20080213997 | SELECTIVE COPPER-SILICON-NITRIDE LAYER FORMATION FOR AN IMPROVED DIELECTRIC FILM/COPPER LINE INTERFACE - A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer. | 2008-09-04 |
| 20080213998 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM FOR EXECUTING THE METHOD - The semiconductor device manufacturing method includes forming an alloy film of copper and an additive metal along a wall surface of a recess portion of an interlayer insulating film in a surface of a substrate; forming a barrier layer made of a compound of the additive metal and a constituent element of the interlayer insulating film; heating the substrate under an atmosphere containing an organic acid, an organic acid anhydride, or ketones to precipitate surplus additive metal onto a surface of the alloy film; and burying copper in the recess portion after heating the substrate. Since the organic acid, the organic acid anhydride, and the ketones have a reducing power for Cu, an oxidation of Cu in the alloy film is suppressed while a barrier layer made of a compound of the additive metal and a constituent element of the insulating film is formed. | 2008-09-04 |
| 20080213999 | Compositions and methods for forming and depositing metal films on semiconductor substrates using supercritical solvents - Compositions and methods for depositing elemental metal M(0) films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing a metal precursor, an excess amount of neutral labile ligands, and a supercritical solvent; exposing the metal precursor to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; reducing the metal precursor to the elemental metal M(0) by using the reducing agent and/or the thermal energy; and depositing the elemental metal M( | 2008-09-04 |
| 20080214000 | POLISHING COMPOSITION AND POLISHING METHOD USING THE SAME - The present invention relates to a polishing composition more suitable for application in polishing semiconductor devices. The polishing composition consists of a liquid component including water and water-soluble amine. The water-soluble amine includes at least one of triethylenetetramine (TETA) and tetraethylenepentamine (TEPA) and is dissolved in the water. | 2008-09-04 |
| 20080214001 | Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same - The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing compounds are homoleptic complexes that include unsymmetrical β-diketiminate ligands. In other embodiments, the metal-containing compounds are heteroleptic complexes including at least one β-diketiminate ligand. The compounds can be used to deposit metal-containing layers using vapor deposition methods. Vapor deposition systems including the compounds are also provided. Sources for β-diketiminate ligands are also provided. | 2008-09-04 |
| 20080214002 | Cleaning solution and manufacturing method for semiconductor device - A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %. | 2008-09-04 |
| 20080214003 | METHODS FOR FORMING A RUTHENIUM-BASED FILM ON A SUBSTRATE - Methods for forming a film on a substrate in a semiconductor manufacturing process A reaction chamber a substrate in the chamber are provided. A ruthenium based precursor, which includes ruthenium tetroxide dissolved in a mixture of at least two non-flammable fluorinated solvents, is provided and a ruthenium containing film is produced on the substrate. | 2008-09-04 |
| 20080214004 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate. | 2008-09-04 |
| 20080214005 | Chemical solution feeding apparatus and method for preparing slurry - An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device with the slurry. A pump sends the chemical solution in the preparation tank to the circulation pipe and the feeding pipe. A concentration detector is arranged downstream to the pump to detect the concentration of the slurry. A controller controls the concentration of the chemical solution in the preparation tank in accordance with the detection value of the concentration detector and controls the feeding of the chemical solution. | 2008-09-04 |
| 20080214006 | METHODS OF USING CORROSION-INHIBITING CLEANING COMPOSITIONS FOR METAL LAYERS AND PATTERNS ON SEMICONDUCTOR SUBSTRATES - Provided herein are methods for using corrosion-inhibiting cleaning compositions for semiconductor wafer processing that include an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant. | 2008-09-04 |
| 20080214007 | METHOD FOR REMOVING DIAMOND LIKE CARBON RESIDUE FROM A DEPOSITION/ETCH CHAMBER USING A PLASMA CLEAN - Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon residue to a plasma clean in the presence of fluorine containing gas and oxygen containing gas. The method may further include purging the deposition chamber having been subjected to the plasma clean with an inert gas, and pumping the deposition chamber having been subjected to the plasma clean. | 2008-09-04 |
| 20080214008 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a plurality of structures are formed on a substrate, and a coating film is formed over a whole surface of the substrate to cover the plurality of structures. A photoresist layer is formed to have an opening portion above a target structure of the plurality of structures, and the coating film on a side of the opening is etched to expose a part of the target structure by using the photoresist layer as a mask while maintaining the substrate in a state covered with the coating film. Also, a target portion as at least a portion of the target structure is etched while leaving the coating film, and the photoresist layer and the coating film are removed. | 2008-09-04 |
| 20080214009 | Methods of Forming a Recess Structure and Methods of Manufacturing a Semiconductor Device Having a Recessed-Gate Structure - Methods of forming a recess structure having a gentle curvature are provided. Such methods include forming a hard mask on a substrate, forming a first preliminary recess on the substrate using the hard mask as an etching mask and forming a spacer on a sidewall of the first preliminary recess. Methods may include forming a second preliminary recess from the first preliminary recess using the spacer as an etching mask and forming the recess structure having an enlarged lower portion from the second preliminary recess using the spacer as an etching mask. | 2008-09-04 |
| 20080214010 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND PATTERN FORMATION MOLD - According to the present invention, there is provided a semiconductor device fabrication method comprising, bringing a mold having a predetermined pattern into contact with at least a portion of an imprinting material formed on a substrate to be processed, and forming the pattern on the substrate to be processed by sequentially transferring the pattern for each shot, wherein one of a dicing region and a monitor pattern formation region of the substrate to be processed is coated with the imprinting material. | 2008-09-04 |
| 20080214011 | Method for Fabricating Dual Damascene Structures - A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers to form a multi-tiered structure in the photo-resist layers. | 2008-09-04 |
| 20080214012 | Apparatus and method for fabricating semiconductor devices and substrates - An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads. | 2008-09-04 |
| 20080214013 | Method for Removal of Bulk Metal Contamination from III-V Semiconductor Substrates - The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 μm×2 μm) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device. | 2008-09-04 |
| 20080214014 | ABSORBER LAYER CANDIDATES AND TECHNIQUES FOR APPLICATION - The present invention generally provides an absorber layer using carbon based materials with increased and stabled thermal absorption coefficient and economical methods to produce such an absorber layer. One embodiment of the present invention provides a method for processing a substrate comprising depositing an absorber layer on a top surface of the substrate, wherein the substrate is maintained under a first temperature, annealing the substrate in a thermal processing chamber, wherein the substrate is heated to a second temperature, and the second temperature is higher than the first temperature, and removing the absorber layer from the substrate. | 2008-09-04 |
| 20080214015 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a semiconductor device includes providing a workpiece, and forming a dielectric material over the workpiece. Forming the dielectric material includes forming a first layer of a first material and forming a second layer of a second material. The first material includes AO | 2008-09-04 |
| 20080214016 | PROCESS FOR REACTIVE ION ETCHING A LAYER OF DIAMOND LIKE CARBON - Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon. | 2008-09-04 |
| 20080214017 | Forming Method and Forming System for Insulation Film - A gate insulation film ( | 2008-09-04 |
