| 36th week of 2008 patent applcation highlights part 28 |
| Patent application number | Title | Published |
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| 20080212315 | Illumination System for Illumination Display Devices, and Display Device Provided with Such an Illumination System - The invention relates to an illumination system for illuminating display devices, comprising at least one light source, and a light guide for guiding light generated by the at least one light source in the direction of a display device. The invention also relates to a display device provided with such an illumination system. | 2008-09-04 |
| 20080212316 | Sealed Light Fixture - A method and apparatus are disclosed for providing illumination. The apparatus includes a lamp housing defining a cavity, a plurality of light emitting diodes disposed within the cavity and sealing means comprising at least a first glass sheet for sealing the cavity. | 2008-09-04 |
| 20080212317 | GARAGE LIGHT LUMINAIRE WITH CIRCULAR COMPACT FLUORESCENT EMERGENCY LIGHTING OPTICS - The present invention relates to a round garage light assembly having a housing with a lamp mounting surface wherein a main HID lamp and an auxiliary circular high output fluorescent lamp are mounted. The auxiliary lamp is mounted centrally within the assembly and above the photometric center of the high intensity discharge lamp so that the light pattern emitted from the auxiliary lamp is symmetrical and the auxiliary lamp does not shadow the light emitted from the HID lamp. | 2008-09-04 |
| 20080212318 | Light Source Device for Components Inspection - The present invention discloses a LED light source device for components inspection. The device has a white annular lamp and a blue annular lamp installed on a fixed blue-lamp ring, a green annular lamp installed on a fixed green-lamp ring and a red annular lamp installed on a fixed red-lamp ring. The fixed blue-lamp, green-lamp and red-lamp ring are being arranged from bottom to top respectively, and the white annular lamp is being positioned at the bottommost. In addition, a heat-dissipation ring is installed on the outskirt of the green annular lamp, along with heat-dissipation electric fans and a fixed light-source ring positioned on the top of the light source device. The present invention not only has the advantages of using four different light sources, including: a red light source, a green light source, a blue light source and a white light source, to illuminate inspected objects from different angles which allow camera to capture more information, but also increase the convenience for component inspection which in term provides higher assurance for components quality. | 2008-09-04 |
| 20080212319 | LED lamps including LED work lights - Work light has LEDs that may require heatsink. Desired radiation pattern achieved by using optical components designed to produce beam or LEDs may have beams in different directions. Radiation pattern of LEDs may be changed by refractive-reflective optics or by convex lenses. Convex lenses may be hemispheres, other planoconvex shapes, concavo-convex shapes, or other shapes. Curved surfaces on any lenses may be spherical or aspheric. Ballast to operate the LEDs from line voltage AC or low voltage DC. Work light may contain batteries. The work light may be mounted on a stand. May have accessory mount. May have charging station. May have a paging transmitter to activate a paging receiver in work light. May have openings for heat transfer from heatsink to ambient air external to light. | 2008-09-04 |
| 20080212320 | Producing Distinguishable Light in the Presence of Ambient Light - A process and apparatus for producing distinguishable light, in the presence of ambient light is disclosed. The process involves admitting light in a first wavelength band through a first light admission port into a first optical cavity at least partially defined by a first reflector operably configured to reflect light out of the first optical cavity. The process also involves filtering ambient light reflected into the first optical cavity and entering and exiting a first space defined about the first light admission port such that ambient light outside the first wavelength band is attenuated on entry and exit from the first space. | 2008-09-04 |
| 20080212321 | Diffuser Having Optical Structures - A diffuser used in a backlight module including a plurality of light sources is disclosed. The diffuser according to the present invention makes a uniform light output. The diffuser includes a transparent substrate and a plurality of optical structures. The transparent substrate has an entrance surface and an exit surface. The plurality of optical structures is disposed on the exit surface, each optical structure is dented from the exit surface to the interior of the transparent substrate and forms a refractive convex within the transparent substrate, and each refractive convex corresponds to one of the plurality of the light sources. The maximum value of the included angle between the tangent to the refractive convex edge and the normal to the exit surface is smaller than 30 degrees, such that an incident light ray from the light sources refracts and deviates from the normal to the refractive convex through the refractive convex. | 2008-09-04 |
| 20080212322 | Illumination arrangement, multiple light module, luminaire and use thereof - An illumination arrangement comprising a plurality of light-emitting semiconductor components ( | 2008-09-04 |
| 20080212323 | LED track light device - The LED track light device has plurality of LED-units fit within track means. At least one of LED element(s) are fit within the LED-units geometric construction and element(s) electric poles are connected with conductive mean, resilient conductive means, contact means, bus means to build the electric signal(s) deliver from the preferred AC or DC power source, circuit means, switch means, sensor means, timer means, control means to the said element(s) to make desired light function for illumination of area. The said LED-units have geometric construction and space to allow element(s) fix on position or incorporated with reflector means to make the said reflector means can be rotating, swivel, tilt by rotating means. Hanging means or other electric device also can add on the said LED track light device or said LED-unit to add more practical extra function. | 2008-09-04 |
| 20080212324 | LED TABLE LAMP - A light emitting diode (LED) table lamp including a base, a support arm, a pivot, and a light emitting device is provided. One end of the support arm is connected to the base, and the pivot is provided at the other end of the support arm. The light emitting device includes a lampshade, a LED light assembly provided at the lampshade, and at least a heat pipe. The lampshade is pivotally connected to the support arm by the pivot, and the heat pipe is provided at the LED light assembly. In addition, an end of the heat pipe is tightly fitted with the pivot. | 2008-09-04 |
| 20080212325 | LED LAMP WITH HEAT DISSIPATION MECHANISM AND MULTIPLE LIGHT EMITTING FACES - An LED lamp with heat dissipation mechanism having double heat pipe and tridimensional LEDs arrangement is disclosed. The lamp is composed of a heat-dissipation unit, a heat pipe whose one end is mounted on the heat-dissipation unit, a plurality of LED units mounted on an outer surface of the heat pipe, a fin module encompassing the heat-dissipation unit and a reflector mounted on a bottom of the heat-dissipation unit. The heat-dissipation unit has two basin-like casings. The LED units on the heat pipe are towards the reflector. Thus the reflector concentrates the light from the LED units. | 2008-09-04 |
| 20080212326 | Lighting Apparatus - The present invention relates to a lighting apparatus, and more particularly to a lighting apparatus including a frame in which a connector is installed, a lampshade in which a reflector, whose first and second anodized aluminum reflectors are integrally connected to each other and connected to the front side of the frame, is fixed to the inner circumference, and a lamp connected to the connector through a socket and having a cover to which the socket is connected and a luminous element connected to the inside of the cover, whereby illuminance is enhanced, the reflector is easily assembled, lifespan of a lamp is prevented from being shorter due to re-reflected light, reflectivity of the reflector is increased, and heating value is effectively reduced. | 2008-09-04 |
| 20080212327 | Illumination System of a Microlithographic Exposure Apparatus - An illumination system of a microlithographic exposure apparatus has an optical axis and a beam transforming device. This device includes a first mirror with a first reflective surface having a shape that is defined by rotating a straight line, which is inclined with respect to the optical axis, around the optical axis. The device further includes a second mirror with a second reflective surface having a shape that is defined by rotating a curved line around the optical axis. At least one of the mirrors has a central aperture containing the optical axis. This device may form a zoom-collimator for an EUV illumination system that transforms a diverging light bundle into a collimated light bundle of variable shape and/or diameter. | 2008-09-04 |
| 20080212328 | ETENDUE-SQUEEZING ILLUMINATION OPTICS - In some embodiments, an apparatus for use generating illumination is provided that comprises a reflective base, a first light source positioned proximate the reflective base, and a reimaging reflector positioned partially about the first light source, where a percentage of light emitted from the first light source is reflected from the reimaging reflector to the reflective base adjacent the first light source establishing a first real image. The reimaging reflector can further comprise a first sector of a first ellipsoid and a second sector of a second ellipsoid, where the first and second sectors establish the first and a second real image. Further embodiments provide a lens that includes a reimaging reflector that receives light and reflects the light establishing a first real image. The reimaging reflector can further comprise a plurality of sectors that reflect light to establish first and second real images. | 2008-09-04 |
| 20080212329 | Assembly of Light Emitting Diodes for Lighting Applications - An assembly of light emitting diodes for a streetlight or the likes comprises a first board having a first matrix of light emitting diodes (LEDs) mounted thereon defining a first light projection plane and at least another board having a second matrix of LEDs mounted thereon defining a second light projection plane. The other boards are mounted to the first board so as to define an angle therebetween. The LEDs can be mounted to the boards so as to independently define and angle therewith. They can also be oriented towards privileged directions. The present assembly allows providing a more uniform light distribution. | 2008-09-04 |
| 20080212330 | Light fixture - A light fixture for flush mounting against a ceiling wall includes a housing for securement in a wall hole and a light transmitting lens. The lens is flush with the wall and covers the entirety of the housing so that the housing is not viewable when installed. The outer edge of the lens is out of line of sight relation with the light source, but provides illumination through radial transmission of light outwardly from a central portion of the lens. Movable tongues supported at opposing sides of the housing and grooves formed in a skirt of the lens removably join the lens to the housing. | 2008-09-04 |
| 20080212331 | OPTICAL MEMBER, METHOD OF FABRICATING THE SAME AND LIQUID CRYSTAL DISPLAY APPARATUS HAVING THE SAME - In an LCD apparatus having an optical member, the optical member has a base body having a light incident surface and a light emitting surface faced the light incident surface. A first resin layer is formed on the light emitting surface and a light diffusing pattern is uniformly formed on the first resin layer so as to diffuse a first light and emit a second light. Accordingly, the LCD apparatus can improve display quality and can be fabricated in low-cost manufacture. Also, since the light diffusing pattern is formed with a curable material, the light diffusing pattern can have various shapes and superior reproducibility. | 2008-09-04 |
| 20080212332 | LED cooling system - The invention relates to a LED cooling system that effects cooling of the LED's during use, and helps the LED's have a longer operating function, and uses less electricity for the LED's to operate. The use of cooling also provides a steadier light and has greater efficiency. | 2008-09-04 |
| 20080212333 | Heat radiating device for lamp - The present invention relates to an improved heat radiating device for lamp, comprising an exhaust space configured around the periphery of lamp stand, an exhaust fan disposed at the top of exhaust space, and simultaneously a radiator and a plurality of heat conductors at the back of the printed circuit board of a light emitting diode (LED) lamp set where the heat conductors extend to the peripheral inner wall of lamp stand in the exhaust space. Through such a radiating device, high heat generated by the LED lamp set can be dissipated through the radiator and through the plurality of heat conductors to the periphery of lamp stand in the exhaust space, thereby enlarging the heat dissipation area. In addition, through the exhaust fan disposed at the top of the exhaust space, ventilation can take place continuously to let the heat in the exhaust space be vented rapidly, thereby achieving fast heat dissipation and prolonging the service life of LED lamp. | 2008-09-04 |
| 20080212334 | Vehicle wheel solar powered lighting system - A vehicle wheel lighting system powered by the sun including light emitting devices attached to the front of a wheel in an aesthetic array. The light emitting devices are powered by rechargeable batteries that are recharged by solar panels. The light emitting devices are activated by light sensors that sense ambient light for automatically energizing the light emitting devices in darkness. In addition to the vehicle lighting system's aesthetics, it also provides automatic lighting for the vehicle, which from the safety standpoint is beneficial when a vehicle is parked or stopped or moving. | 2008-09-04 |
| 20080212335 | Vehicle Lamp Collapsible Closeout - A collapsible closeout for a gap between a vehicle lamp and closure, and particularly well suited for a gap between a headlamp and a hood, is disclosed. The closeout may include a base mounted to a lamp housing, a closeout wall extending from the base, and a contact flange extending under the hood and having a free end extending toward a headlamp lens. The closeout may also include first support ribs extending from the closeout wall toward the headlamp and opposed second support ribs extending from the closeout wall. | 2008-09-04 |
| 20080212336 | Light emitting diode light source - Provided is an LED light source including a frame having a V-shaped groove formed in the upper portion thereof and a heat sink formed to extend from the lower portion thereof, the V-shaped groove having a planar bottom surface on which a circuit pattern is formed; a plurality of LEDs disposed on the bottom surface of the V-shaped groove; a diffuser plate coupled to the upper end of the frame so as to diffuse light emitted from the plurality of LEDs; a pair of plugs coupled to both side ends of the frame and receiving alternating-current (AC) power from outside; and a power converter fixed and coupled to the lower portion of the frame and electrically connected to the plugs and the plurality of LEDs, the power converter converting the AC power applied from the plugs into direct-current (DC) power and supplying the DC power to the LEDs. | 2008-09-04 |
| 20080212337 | Multifunctional Floor Pods - An ambient lighting system for a hospital operating room environment and a method of using said system is described. An apparatus comprising the combination of a translucent sheet and a backlight LED panel or colored light source (colored lamp(s) or LED(s) in an alcove) provides a diffuse light when light from said panel, alcove, or other source is presented to the translucent sheet, is scattered, and represented as unfocused light on the exposed surface of the translucent sheet. Usage of the apparatus in an operating room provides a calming environment. The method and apparatus may be adapted to include wireless control over the intensity, color, and on/off state of the light. Further, usage of known translucent materials provides a sterile and safe surface. | 2008-09-04 |
| 20080212338 | PRISM SHEET, A BACK-LIGHT UNIT USING SAID PRISM SHEET, AND A TRANSMISSION TYPE LIQUID CRYSTAL DISPLAY DEVICE - [Objective] Providing a prism sheet, a back-light unit using the prism sheet, and a transmission type liquid crystal display device.
| 2008-09-04 |
| 20080212339 | Light-guiding plate, lighting device and display device - A light-guiding plate, an optical source device and an electronic device. The light-guiding plate including an incident surface, and an emission surface substantially perpendicular to the incident surface. The incident surface has a surface substantially perpendicular to the incident surface, and has projections or depressions extending substantially parallel to the emission surface. The incident surface has flat planes among the projections or depressions. | 2008-09-04 |
| 20080212340 | Method For Operating A Power Converter In A Soft-Switching Range - For converting a first DC voltage to a second DC voltage, a first bridge circuit comprised in a power converter is controlled to convert the first DC voltage to a first AC voltage. The first AC voltage is transformed to a second and possibly further AC voltage. The second and each possibly further AC voltage is converted to a DC voltage by respective bridge circuits. To increase efficiency of the power converter switches of the power converter are controlled to operate in soft switching. Thereto a duty cycle of each AC voltage is controlled. In an embodiment, a half-cycle voltage-time integral of each AC voltage is controlled to be substantially equal. | 2008-09-04 |
| 20080212341 | DC-DC CONVERTER AND TRANSFORMER - A DC-DC converter using a plurality of transformers capable of decreasing the loss, preventing heat generation of transformers, and improving the heat transfer property of the core, and an integrated type transformer used in this DC-DC converter. A terminal T | 2008-09-04 |
| 20080212342 | Control Method for Direct-Current Transmission - In a method for controlling a rectifier and an inverter, which are connected together by a direct current circuit, a measuring direct current voltage and respectively, a measuring direct current are measured at at least one measuring point of the direct current circuit and are transmitted to a direct current control for controlling the rectifier and/or an inverter control for controlling the inverter. The direct current control controls the rectifier in such a manner that a total of a difference direct current voltage and a differential direct current is minimal and the inverter control of the inverter is controlled in such a manner that the difference between the differential direct current of the differential direct current voltage is minimal. The method is reliable and is economical. Accordingly, the desired flow of the direct current control and the desired flow of the inverter control are identical. | 2008-09-04 |
| 20080212343 | INVERTER BASED STORAGE IN DYNAMIC DISTRIBUTION SYSTEMS INCLUDING DISTRIBUTED ENERGY RESOURCES - A microsource is provided, which includes an inverter, an energy storage device, and a controller. The controller calculates a maximum frequency change for the inverter based on a first comparison between a first power set point and a measured power from the inverter. The first power set point is defined based on a charge level of the energy storage device. A minimum frequency change for the inverter is calculated based on a second comparison between a second power set point and the measured power from the inverter. An operating frequency for the inverter is calculated based on a third comparison between a power set point and a measured power flow. A requested frequency for the inverter is calculated by combining the maximum frequency change, the minimum frequency change, and the operating frequency. The requested frequency is integrated to determine a phase angle of a voltage of the inverter to control a frequency of an output power of the inverter. | 2008-09-04 |
| 20080212344 | Methods for Managing Electrical Power - Certain exemplary embodiments comprise a system comprising a plurality of Active Front End units adapted to be electrically coupled to a direct current (DC) bus. Each of the plurality of Active Front End units can be adapted to be electrically coupled to a separate winding of a transformer of a plurality of transformers. Each of the plurality of Active Front End units can be adapted to convert alternating current (AC) voltage to a DC voltage. Each of the plurality of Active Front End units can be adapted to supply the DC voltage to the DC bus. The DC bus can be adapted to be electrically coupled to a plurality of inverters. | 2008-09-04 |
| 20080212345 | DC-DC CONVERTER SYSTEM - A DC-DC converter system is provided to improve switching control operation of a battery charging DC-DC converter ( | 2008-09-04 |
| 20080212346 | ANTENNA IMPEDANCE MODULATION METHOD - A method for modulating the impedance of an antenna circuit supplying pump signals to a charge pump comprising at least one first pump stage and one last pump stage, the last pump stage supplying a continuous voltage. The output of the first pump stage is short-circuited by means of a switch and the last pump stage goes on pumping electric charges and supplying the continuous voltage. Application in particular to RFID passive transponders. | 2008-09-04 |
| 20080212347 | SWITCHED-CAPACITOR REGULATORS - A switched-capacitor regulator is provided for regulating the output voltage of a voltage supply. The switched-capacitor regulator includes a supply input terminal capable of receiving a supply voltage, two or more flying capacitors, a regulation switch located between each flying capacitor and the supply input terminal, and a voltage control circuit. The activity of the regulation switches is controlled by the voltage control circuit. In one embodiment of the invention, the voltage control circuit includes a feedback resistance area having one or more feedback resistors located between the output of the flying capacitors and a ground terminal, a first gain stage connected to the feedback resistance area, and two or more second switchable gain stages, which are each connected to a regulation switch and the first gain stage. The switched-capacitor regulator operates in pseudo-continuous regulator mode using three-stage switchable operational amplifiers with time-multiplexed pole-splitting compensation. | 2008-09-04 |
| 20080212348 | Method for Operating an Inverter and Arrangement for Executing the Method - There is described a method for operating an electronically controlled inverter. The inverter is controlled during the positive half-wave of the output alternating voltage in such a way that it operates as a SEPIC converter, and during the negative half-wave of the output alternating voltage in such a way that it operates as a CUK converter. | 2008-09-04 |
| 20080212349 | Power converter - A power converter of the present invention is connected between a direct current power source and controls power to a load by switching equipment. The converter is equipped with a first conductor for connecting a negative pole of the power converter and the switching equipment, and a second conductor for connecting a housing of the power converter and the negative pole of the power converter to the first conductor through a resistor. | 2008-09-04 |
| 20080212350 | CAM Asynchronous Search-Line Switching - This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements | 2008-09-04 |
| 20080212351 | Pin configuration changing circuit, base chip and system in package including the same - A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB). | 2008-09-04 |
| 20080212352 | MULTI-LAYER SEMICONDUCTOR MEMORY DEVICE COMPRISING ERROR CHECKING AND CORRECTION (ECC) ENGINE AND RELATED ECC METHOD - Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer. | 2008-09-04 |
| 20080212353 | SRAM design with separated VSS - An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other. | 2008-09-04 |
| 20080212354 | BIASED SENSING MODULE - A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics. | 2008-09-04 |
| 20080212355 | Compact Virtual Ground Diffusion Programmable ROM Array Architecture, System and Method - A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line. | 2008-09-04 |
| 20080212356 | Random Access Memory Featuring Reduced Leakage Current, and Method for Writing the Same - The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell. | 2008-09-04 |
| 20080212357 | Simultaneous read circuit for multiple memory cells - A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing state. | 2008-09-04 |
| 20080212358 | METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE AND FERROELECTRIC MEMORY DEVICE - A method for manufacturing a ferroelectric memory device includes: forming a conductive base layer above a substrate; and laminating above the base layer a first electrode, a ferroelectric layer and a second electrode, wherein, prior to the step of forming the base layer, the method includes forming an active element in the substrate, forming an interlayer dielectric film on the substrate, and forming a contact plug in the interlayer dielectric film, and wherein the step of forming the base layer includes: forming a first conductive layer composed of a conductive material having a self-orienting property on the interlayer dielectric film including the contact plug; planarizing the first conductive layer by a chemical mechanical polishing method thereby forming a planarized first conductive layer that covers the interlayer dielectric film including the contact plug; applying an ammonia plasma process to a surface of the planarized first conductive layer; forming a titanium layer on the planarized first conductive layer treated with the ammonia plasma process; and heat-treating the titanium layer in a nitrogen atmosphere thereby changing the titanium layer to a titanium nitride layer which forms a second conductive layer. | 2008-09-04 |
| 20080212359 | Memory Device and Semiconductor Integrated Circuit - First electrode layer includes a plurality of first electrode lines (W | 2008-09-04 |
| 20080212360 | PERSISTENT VOLATILE MEMORY CELL - A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point when an erase signal has an active value, a switch for triggering the charge of the memory point when a write signal has an active value, and a sense-amplifier circuit having an input receiving the persistent voltage, and an output supplying the binary datum. The memory cell can be applied to the management of an inventory flag in a contactless integrated circuit. | 2008-09-04 |
| 20080212361 | NONVOLATILE NANOTUBE DIODES AND NONVOLATILE NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING SAME - Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell. | 2008-09-04 |
| 20080212362 | Control of set/reset pulse in response to peripheral temperature in pram device - A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature. | 2008-09-04 |
| 20080212363 | METHOD FOR PROGRAMMING PHASE-CHANGE MEMORY AND METHOD FOR READING DATE FROM THE SAME - When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat. | 2008-09-04 |
| 20080212364 | Magnetic Memory Cell and Method of Fabricating Same - A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media. | 2008-09-04 |
| 20080212365 | Scalable Magnetic Random Access Memory Device - A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one spacer layer, and a third free magnetic layer separated from the second free magnetic layer by at least one anti-parallel coupling layer. A magnetic moment of the first free magnetic layer is greater than both a magnetic moment of the second free magnetic layer and a magnetic moment of the third free magnetic layer. The magnetic memory cell may be used in conjunction with a magnetic random access memory device. | 2008-09-04 |
| 20080212366 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory device comprising Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction. | 2008-09-04 |
| 20080212367 | METHOD OF OPERATING A FLASH MEMORY DEVICE - In a method of operating a flash memory device including a memory cell array having a Multi-Level Cell (MLC) for storing plural bit data, a first memory block included in the MLC is selected. First to M | 2008-09-04 |
| 20080212368 | DATA VERIFICATION METHOD AND SEMICONDUCTOR MEMORY - A semiconductor memory device storing multi-bit write data and a related method of verifying data programmed to a memory cell are disclosed. The method compares a write data reference bit selected from the write data with a corresponding external data bit indicative of an intended write data bit value, and verifies a target bit selected from the write data only upon a positive comparison between the write data reference bit and the corresponding external data bit. | 2008-09-04 |
| 20080212369 | METHOD OF MANAGING A MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS - A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells. | 2008-09-04 |
| 20080212370 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside. | 2008-09-04 |
| 20080212371 | NON-VOLATILE MEMORY COPY BACK - Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory controller for data repair operations by the controller. | 2008-09-04 |
| 20080212372 | Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same - A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of memory cells and the additional block of virtual memory cells may be read independently to provide a total of three blocks of read data. | 2008-09-04 |
| 20080212373 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE - A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness. | 2008-09-04 |
| 20080212374 | Novel Multi-State Memory - Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data. | 2008-09-04 |
| 20080212375 | METHOD OF PROGRAMMING AND ERASING A P-CHANNEL BE-SONOS NAND FLASH MEMORY - A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state. | 2008-09-04 |
| 20080212376 | METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME - Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous. | 2008-09-04 |
| 20080212377 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the bit lines, and transmitting the data of the memory cells; transfer gates connected between the bit lines and the sense nodes; a latch circuit latching a first high level potential to one of the pair of sense nodes, and latching a low level potential to the other sense node of the pair of sense nodes; and a level shifter applying a second high level potential higher than the first high level potential to one of the pair of bit lines according to the potentials latched to the pair of sense nodes during a data write operation or a data write-back operation. | 2008-09-04 |
| 20080212378 | DATA LATCH CONTROLLER OF SYNCHRONOUS MEMORY DEVICE - Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the control signals being synchronized with rising and falling edges of the divided signal; and a latch unit for latching data corresponding to the bits by means of the control signals, and outputting the data for the detection and amplification of the data. The data input circuit may include a first delay unit for delaying the data in order to match setup-hold time, a second delay unit for performing delay for adjusting the data outputted from the latch unit, and a third delay unit for performing delay for adjusting the write strobe signal outputted from the latch unit. | 2008-09-04 |
| 20080212379 | Semiconductor Memory Device - When writing 16-bit write data to the memory array | 2008-09-04 |
| 20080212380 | Self-refresh control circuit for detecting current flowing from current generator and semiconductor device including same - A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle. | 2008-09-04 |
| 20080212381 | Voltage generating circuits for semiconductor memory devices and methods for the same - In a voltage generating circuit for a semiconductor memory device, each of a plurality of reset signal generators individually generates a reset signal in response to one of a plurality of external source voltages. The plurality of external source voltages have different voltage levels. An output voltage generator generates a plurality of output voltages by independently driving each of the plurality of external source voltages in response to a corresponding one of the plurality of reset signals. The output voltage generator outputs the plurality of output voltages through a common output terminal. | 2008-09-04 |
| 20080212382 | Crossbar waveform driver circuit - A driving waveform circuit includes a crossbar array having input columns and output rows wherein the crossbar array is configured to store data in the form of high or low resistance states, delay timing circuitry electrically connecting an input signal to the input columns of the crossbar array and configured to provide a relative delay timing between the input signal and each input column, and summation circuitry electrically connected to the output rows of the crossbar array for generating one or more output signals based on the stored resistance state data and the input signal. The driving waveform circuit is taught to be applied as inkjet printing drivers, micromirror drivers, robotic actuators, display device drivers, audio device drivers, computational device drivers, and counters. | 2008-09-04 |
| 20080212383 | Circuit and method for parallel test of memory device - A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal. | 2008-09-04 |
| 20080212384 | SENSE AMP CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A differential input circuit receives differential input signals at a pair of differential input terminals and produces a pair of first differential output signals. A sensing circuit senses at least one of the pair of first differential output signals reaching a certain voltage and provides an activation signal. A latch-type amplifier provides a pair of second differential output signals when activated in accordance with the activation signal. A cutoff circuit establishes connection between the differential input circuit and the latch-type amplifier and breaks connection between the differential input circuit and the latch-type amplifier in accordance with the activation signal. | 2008-09-04 |
| 20080212385 | Output driver - According to one embodiment a semiconductor device is provided. The device includes a first compensator to generate a first compensated signal and a first limiter to control operation of the first compensator. Furthermore, a second compensator to generate a second compensated signal and a second limiter to control operation of the second compensator is provided. An output device is adapted to receive the first compensated signal and the second compensated signal to drive an output. | 2008-09-04 |
| 20080212386 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND REFRESH CONTROL METHOD - A semiconductor memory device comprises: a memory cell array in which memory cells are divided into banks; cache memories each for storing data of a word line selected by a row address; a setting register for setting a data holding capacity so that a holding area where data is held during a self refresh period and a non-holding area where data is not held during the self refresh period are commonly included in each bank; a refresh controller for outputting a row address to be refreshed at predetermined intervals during the self refresh period and for performing a refresh operation for a selected word line corresponding to the row address in an activated bank; and a bank controller for activating all banks when the selected word line is included in the holding area and inactivating all banks when the selected word Line is included in the non-holding area. | 2008-09-04 |
| 20080212387 | INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses. | 2008-09-04 |
| 20080212388 | INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses. | 2008-09-04 |
| 20080212389 | SDRAM with Reset Function - A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRS | 2008-09-04 |
| 20080212390 | Bulk bias voltage level detector in semiconductor memory device - There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage. | 2008-09-04 |
| 20080212391 | LOW POWER MULTI-CHIP SEMICONDUCTOR MEMORY DEVICE AND CHIP ENABLE METHOD THEREOF - A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals. | 2008-09-04 |
| 20080212392 | MULTIPLE PORT MUGFET SRAM - A circuit includes a multi gate field effect transistor based static random access memory device having a cross coupled inverter cell. A first set of multi gate field effect transistor access devices are coupled to the memory device to provide a first port. A second set of multi gate field effect transistor access devices are coupled to the memory device to provide a second port. Further ports may be provided in further embodiments. | 2008-09-04 |
| 20080212393 | Semiconductor memory device - A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits of the word line driver unit, and outputting the latched first address to the word line driver unit; and an address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the word line driver unit, and outputting a latched second address to the word line driver unit. | 2008-09-04 |
| 20080212394 | WRITE DRIVING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A write driving circuit includes a plurality of driving units that write data corresponding to detection signals on memory banks, and at least one detecting unit that detects data input from the outside, and outputs the detection signals to two or more driving units among the plurality of driving units. | 2008-09-04 |
| 20080212395 | Driver, and a semiconductor, memory device having the same - A driver may include a driving unit and/or a boosting unit. The driving unit may be configured to provide a driving signal to at least one load. The boosting unit may be configured to boost the driving signal based on transition time points of the driving signal to reduce a distortion of the driving signal. The transition time points may be time points during a transition of the driving signal from a first level to a second level. | 2008-09-04 |
| 20080212396 | Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays - A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w | 2008-09-04 |
| 20080212397 | Method and Apparatus to Optimize the Mixing Process - The invention discloses a system for mixing a liquid material and a solid material, said system comprising: i) a base unit ( | 2008-09-04 |
| 20080212398 | HYDRAULIC ACTUATED CAVITATION CHAMBER WITH INTEGRATED FLUID ROTATION SYSTEM - A method for initiating cavitation within the fluid within a cavitation chamber is provided. In the cavitation preparatory steps, a hydraulically actuated piston is fully retracted and then the cavitation chamber is isolated. The hydraulic piston is then fully extended after which the chamber is partially opened until a predetermined cavitation piston position is obtained. After the chamber is once again isolated, cavities are formed and imploded by retracting and then extending the cavitation piston. At least one impeller, located within the cavitation chamber, is rotated in order to stabilize the cavities. | 2008-09-04 |
| 20080212399 | Double-Chamber Mixing Device For Viscous Pharmaceutical Substances - The invention concerns a double-chamber device for mixing at least two viscous substances, comprising: cylindrical and coaxial first and second communicating vessels, each hermetically sealed at one end by a mobile piston, and provided at its second end with a slightly conical bottom end, the two vessels being arranged, preferably vertically, in mirror symmetry relative to a meridian plane perpendicular to their common axis; a central mixing element connecting the two vessels at the two slightly conical bottom ends; and a high pressure hydraulic device for automatically activating the pistons in a coordinated reciprocating movement. | 2008-09-04 |
| 20080212400 | System for Agitating the Fluid Contents of A Container - An automated analyzer for performing multiple diagnostic assays simultaneously includes multiple stations, or modules, in which discrete aspects of the assay are performed on fluid samples contained in reaction receptacles. The analyzer includes stations for automatically preparing a specimen sample, incubating the sample at prescribed temperatures for prescribed periods, preforming an analyte isolation procedure, and ascertaining the presence of a target analyte. An automated receptacle transporting system moves the reaction receptacles from one station to the next. The analyzer further includes devices for carrying a plurality of specimen tubes and disposable pipette tips in a machine-accessible manner, a device for agitating containers of target capture reagents comprising suspensions of solid support material and for presenting the containers for machine access thereto, and a device for holding containers of reagents in a temperature controlled environment and presenting the containers for machine access thereto. A method for performing an automated diagnostic assay includes an automated process for isolating and amplifying a target analyte. The process is performed by automatically moving each of a plurality of reaction receptacles containing a solid support material and a fluid sample between stations for incubating the contents of the reaction receptacle and for separating the target analyte bound to the solid support from the fluid sample. An amplification reagent is added to the separated analyte after the analyte separation step and before a final incubation step. | 2008-09-04 |
| 20080212401 | Modular Dye Meter - A modular dye meter ( | 2008-09-04 |
| 20080212402 | Process for the controlled production of organic particles - A process for the production of a microparticle or a nanoparticle of a chemical compound comprising the steps of providing a solution of said chemical compound in a first liquid; providing a second liquid in which said chemical compound is insoluble or substantially insoluble; combining said liquids in a region of high shear thereby causing formation of said particles; and isolating said particles of said compound. The processing time of a coacervation style process can be reduced and the yield can be substantially increased both by control of the precipitation step which allows for the desolvation step to be dispensed with leading to significant process time reduction. The invention also provides a molecular mixing unit comprising an outer body defining a mixing zone; a shear means to provide shear liquid in said mixing zone; at least one fluid inlet means for a first liquid; at least one fluid inlet means for a second liquid and a fluid outlet means. | 2008-09-04 |
| 20080212403 | BLENDER HAVING AN INVERTABLE JAR - The blender includes a motor housing that has an outer surface surrounding an electric motor. The motor housing has a first end and a second end. The outer surface has a first mounting member. The motor housing includes a control electrically connected to the motor. A jar has an open end and a blending end and an interior surface. The jar includes a blade assembly proximate to the blending end. The jar is removably mountable to the first end of the motor housing in a operable position. The interior surface of the jar has a second mounting member. The second mounting member is in releasable registry with the first mounting member when the open end of the jar is placed over the first end of the motor housing in a storage position such that the motor housing is at least partially contained within the jar. | 2008-09-04 |
| 20080212404 | APPARATUS FOR CONTINUOUS BLENDING - The present invention provides a continuous blender having a drive unit assembly with a shell assembly mounting assembly and a shell assembly structured to be removably coupled to the shell assembly mounting assembly by one or more clamps. The drive unit assembly may be coupled to shell assemblies having different lengths and diameters. Thus, by changing the shell assembly coupled to the drive unit assembly, the output of the continuous blender may be dramatically changed. | 2008-09-04 |
| 20080212405 | Mixing Apparatus - A mixing apparatus comprising: a) a mixing well characterized by an internal volume not exceeding 100 ml.; b) a drive mechanism including a stationary circumferential gear on an inner surface of the mixing well; and c) a planetary mixing element driven by a mixing element gear which engages the stationary circumferential gear. | 2008-09-04 |
| 20080212406 | METHOD FOR LATERALLY STEERING STREAMER CABLES - A device and a method for laterally steering a streamer cable towed underwater behind a seismic survey vessel. The device includes a cable-steering assembly rotatably attached to a streamer cable. The assembly includes a body to which one or more wings are mounted. The wings are arranged to pivot about pivot axes. The assembly is ballasted so that the pivot axes of the wings are largely in a vertical plane. A conventional cable-leveling bird is converted to one version of a cable-steering device by ballasting to maintain the pivot axes of the bird's wings largely vertical. With an orientation sensor for sensing the orientation of the wings, the cable-steering device adjusts the angle of the wings to provide a sideward component of force to steer the streamer. | 2008-09-04 |
| 20080212407 | Surface Micromechanical Process For Manufacturing Micromachined Capacitive Ultra-Acoustic Transducers and Relevant Micromachined Capacitive Ultra-Acoustic Transducer - The invention concerns a manufacturing process, and the related micromachined capacitive ultra-acoustic transducer, that uses commercial silicon wafer | 2008-09-04 |
| 20080212408 | Ultrasonic Rod Transducer - An ultrasonic rod transducer having a heat transfer element for more efficient thermal coupling to a piezoelectric transducer. The heat transfer element enables reduced thermal resistance to the surrounding atmosphere or to the housing, and thus to the bath in the case of immersed rod transducers. | 2008-09-04 |
| 20080212409 | Membrane For a Mems Condenser Microphone - A membrane ( | 2008-09-04 |
| 20080212410 | DISMISS ALL EVENT REMINDERS - A mobile electronic device that includes a controller including at least one processor, for controlling operation of the mobile device; a display coupled to the controller; a user input device coupled to the controller; and a storage coupled to the controller, the storage storing event reminder information identifying event reminders for different types of events, times at which the event reminders are scheduled to be released for display on the display. The controller is operative to: maintain a list of pending event reminders that have been released for display; display on the display a first event reminder window corresponding to one of the pending event reminders, the first event reminder window including a first user selectable option to dismiss the event reminder corresponding thereto, and a second user selectable option to dismiss a plurality of the pending event reminders that are for the same type of event as represented in the first event reminder window; upon detecting selection of the first user selectable option, remove the first event reminder window from the display and display on the display a further event reminder window corresponding to a further one of the pending event reminders; and upon detecting selection of the second user selectable option, remove the first event reminder window from the display and remove from the list of pending event reminders pending event reminders that are for the same type of event as represented in the first event reminder window. | 2008-09-04 |
| 20080212411 | PROGRAMMABLE TIME SIGNAL RECEIVER, METHOD FOR PROGRAMMING A TIME SIGNAL RECEIVER, AND PROGRAMMING DEVICE FOR TIME SIGNAL RECEIVERS - A programmable time signal receiver, method for programming a time signal receiver, and programming device for time signal receivers, is provided. The programmable time signal receiver has receiver for receiving an electromagnetic time signal and a programming signal, as well as processor, configured to process the time signal and the programming signal, whereby the receiver and/or the processor are assigned a memory, configured for temporary storage of programming instructions and for supplying the programming instructions to the receiver and/or to the processor. The programmable time signal receiver also has a controller, which are configured to supply a programming control signal supplied by the receiver and/or by the processor and/or by the memory. | 2008-09-04 |
| 20080212412 | WIRELESS SYNCHRONOUS TIME SYSTEM - A wireless synchronous time keeping system includes a primary device and a secondary device. The primary device includes a receiving unit to receive a first signal, a processor coupled to the receiving unit and operable to process the first signal to produce a processed time component, an internal clock to store and increment the component to produce a first internal time, and a transmitting unit to transmit a second signal having the first internal time and an event having an instruction and a time element. The secondary device includes a receiving unit to receive the second signal, an internal clock to store and increment the first internal time to produce a second internal time, a memory operable to store one or more messages, a display operable to display the messages, and an event switch operable to execute the instruction when the second internal time matches the time element. | 2008-09-04 |
| 20080212413 | WIRELESS SYNCHRONOUS TIME SYSTEM - A method of synchronizing an event system. The method includes receiving a first signal at a primary device. The first signal includes a time component. The method also includes processing the first signal to produce a second signal. The second signal includes the processed time component and an instruction. The method further includes wirelessly transmitting the second signal to a repeating device, wirelessly receiving the second signal at the repeating device, wirelessly transmitting a third signal from the repeating device, wirelessly receiving the third signal at a secondary device, and executing an event with the third signal. | 2008-09-04 |
| 20080212414 | Systems and methods for use with traffic ticket printing parking meters - Certain example embodiments of this invention relate to systems and methods for use with traffic ticket printing parking meters. According to certain example embodiments, a parking meter is provided. A payment acceptor may be operable to accept payment. A display may be operable to display a validated period during which the meter is valid, with the validated period being based on an amount of payment inserted into the payment acceptor. Vehicle identifying programmed logic circuitry may be operable to identify a vehicle parking in, parked in, and/or leaving a parking spot associated with the parking meter. A printer may be operable to print a parking ticket when a parking violation occurs, with the parking ticket including vehicle identification information from the vehicle identifying programmed logic circuitry and/or parking violation information. | 2008-09-04 |
