| 36th week of 2008 patent applcation highlights part 20 |
| Patent application number | Title | Published |
|---|
| 20080211515 | Method and Apparatus for Measuring Scattering Coefficient of Device Under Test - A measuring method and measuring apparatus for vector-measuring a scattering coefficient of a device under test substantially using a scalar measuring instrument while enabling a reduction in the size of the measuring instrument and the cost. The measurement system includes a signal source that applies a signal to a device under test, a scalar measuring instrument that measures a reflected wave reflected from the device under test or a transmitted wave transmitted through the device under test as a scalar value, and a superimposing signal system that superimposes three different vector signals whose relation values are specified in advance on the reflected wave or the transmitted wave of the device under test. The three vector signals are superimposed on the reflected wave or the transmitted wave of the device under test, and the superimposed signals are each measured as a scalar value by the electric-power measuring instrument. The three measured scalar values are converted into a single vector value using the specified relation values of the three vector signals, thereby obtaining a transmission coefficient of the device under test. | 2008-09-04 |
| 20080211516 | Method and Measuring Instrument for Measuring Water Content - For measuring the water content of a web in the wire section of a paper machine, at least one radiofrequency-operated resonator sensor forms an electric near field, in which a web affects the resonance frequency of each resonator sensor. The water content of the web is measured as a function of the resonance frequency of each resonator sensor in a measuring unit. | 2008-09-04 |
| 20080211517 | Measurement Arrangement for Determining the Characteristic Line Parameters by Measuring Scattering Parameters - The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetrically to a reference ground (RG) in the layer at all ends. | 2008-09-04 |
| 20080211518 | Method and Apparatus for Measuring Electrical Conductivity - An apparatus ( | 2008-09-04 |
| 20080211519 | CAPACITANCE SENSOR - A code-type sensor for detecting a change in capacitance includes a plurality of detection electrodes for detecting a change in capacitance, a shield electrode surrounding the plurality of detection electrodes so as to restrict a detection range of the capacitance and having an opening in a direction of detection, and a contact detecting electrode for detecting contact disposed along a longitudinal direction of the sensor. The detection electrodes are disposed at a position close to the opening in the shield electrode and at a position far from the opening in the shield electrode. The contact detecting electrode is disposed on a back side in the direction of detection of the shield electrode. The respective detection electrodes are integrally connected to each other in such a way as to be held in a separate state, the detection electrodes and the shield electrode are integrally connected to each other in such a way as to be held in a separate state, and the shield electrode and the contact detecting electrode are kept in such a way as to be held in a separate state across a clearance in a natural state and are brought into contact with each other when the sensor is pressed in the direction of detection by contact of an object. | 2008-09-04 |
| 20080211520 | Semiconducting nanowire fluid sensor - Nanowire fluid sensors are provided. The fluid sensors comprise a first electrode, a second electrode, and at least one nanowire between the first electrode and the second electrode. Each nanowire is connected at a first end to the first electrode and at a second end to the second electrode. Methods of fabricating and operating the fluid sensor are also provided. | 2008-09-04 |
| 20080211521 | Moisture Content Sensor and Related Methods - A moisture content sensor comprising a signal source ( | 2008-09-04 |
| 20080211522 | SENSOR FOR DETECTING THE POSITION OF A MOVABLE MAGNETIC OBJECT AND A CONVEYING DEVICE HAVING THE SENSOR - The sensor according to the invention for detecting the position of a movable magnetic object includes a resistance track and a contact electrode arranged thereon. Moreover the sensor includes a magnetic position transmitter, which is developed in such a way that it can follow the magnetic object, that it can be moved along the contact electrode and through which the contact electrode can be brought into contact with the resistance track. | 2008-09-04 |
| 20080211523 | Inspection contact structure and probe card - In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them. | 2008-09-04 |
| 20080211524 | Electrochemically Fabricated Microprobes - Multilayer probe structures for testing semiconductor die are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. In some embodiments the structures may include generally helical shaped configurations, helical shape configurations with narrowing radius as the probe extends outward from a substrate, bellows-like configurations, and the like. In some embodiments arrays of multiple probes are provided. | 2008-09-04 |
| 20080211525 | Probe card assembly and method of forming same - A probe card assembly has a probe contactor substrate having a plurality of probe contactor tips thereon and a probe card wiring board with an interposer disposed between the two. Support posts contacting the probe contactor substrate are vertically adjustable until secured by a locking mechanism which is coupled to the probe card wiring board. When the posts are secured in a fixed position, the position is one in which the plane of the plurality of probe contactor substrates is substantially parallel to a predetermined reference plane. | 2008-09-04 |
| 20080211526 | Wafer holder, heater unit used for wafer prober and having wafer holder, and wafer prober - By wafer holder including a chuck top for mounting a wafer and a supporter supporting the chuck top and having flatness of at most 0.1 mm, a heater unit for a wafer prober and the wafer prober using the wafer holder, a wafer holder and a wafer prober apparatus hardly deformable even under high load and capable of effectively preventing contact failure, and capable of preventing temperature increase in a driving system when a semiconductor wafer having semiconductor chips with minute circuitry that requires high accuracy is heated can be provided. In the wafer holder of the present invention, the flatness of the supporter is preferably at most 0.05 mm, and more preferably at most 0.01 mm. | 2008-09-04 |
| 20080211527 | Heat-resistant lens kit - A heat-resistant lens kit configured within the pogo tower of the wafer tester is disclosed. The heat-resistant lens kit has two parallel lenses and a main body with a through hole. The main body and two parallel lenses enclose a vacuum room within the through hole. | 2008-09-04 |
| 20080211528 | Inspection contact structure and probe card - In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them. | 2008-09-04 |
| 20080211529 | INTEGRATED CIRCUIT FOR BEING APPLIED TO ELECTRONIC DEVICE, AND ASSOCIATED TESTING SYSTEM - An integrated circuit (IC) for being applied to an electronic device includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to another IC for testing. A testing system includes at least one testing device and a plurality of ICs that are tested by the testing device. The ICs are coupled to the testing device. Each IC of the ICs is for being applied to an electronic device and includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to one of the other IC(s) for testing. | 2008-09-04 |
| 20080211530 | INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION - Methods for testing a semiconductor circuit ( | 2008-09-04 |
| 20080211531 | INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION - Methods for testing a semiconductor circuit ( | 2008-09-04 |
| 20080211532 | Circuit with control function and test method thereof - There is provided a circuit with control function including a circuit to be controlled so as to be operated only if a predetermined environment meets a specific condition and being arranged to detect, in any predetermined environment, whether or not the circuit with control function is normally operated, and a test method thereof. The circuit with control function includes a controller (microcomputer) for operating the circuit to be controlled (a heater) only if a predetermined environment (ambient temperature) detected by a sensor (a first temperature sensor) meets a specific condition (0° or below). The controller includes a self-diagnosis device for diagnosing whether or not the circuit with control function is normally operated (step S | 2008-09-04 |
| 20080211533 | IMPEDANCE MATCHING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - An impedance matching circuit includes a code generating unit for generating a calibration code in response to a reference voltage and a voltage on a node, a calibration resistance unit for supplying a power supply voltage to the node, being calibrated to an external resistor, wherein the calibration resistance unit includes a switching unit for turning on/off a plurality of resistors connected in parallel in response to the calibration code, a termination pull-up resistance unit provided at an output node for receiving the calibration code, wherein the termination pull-up resistance unit has a switching unit which is identical to that of the calibration resistance unit, and a termination pull-down resistance unit at the output node, for receiving the calibration code, wherein the termination pull-down resistance unit has a switching unit which is identical to that of the calibration resistance unit. | 2008-09-04 |
| 20080211534 | IMPEDANCE MATCHING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values. | 2008-09-04 |
| 20080211535 | Pseudo-differential output driver with high immunity to noise and jitter - Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output driver consumes little circuit area and has low output capacitance. | 2008-09-04 |
| 20080211536 | Driver calibration methods and circuits - Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals. | 2008-09-04 |
| 20080211537 | Open drain output circuit - The transition time of an output is sometimes changed by a certain supply voltage connected to an output terminal of an output circuit. An output circuit to address this problem includes: a level detection circuit which detects a pull-up supply voltage applied to an output terminal OUT; and an open drain buffer circuit which can switch its driving ability on the basis of the detection result of the level detection circuit. Even if the output circuit is connected to a circuit whose supply voltage is different, it is made possible to produce an output while stabilizing the transition time of the output. | 2008-09-04 |
| 20080211538 | FLEXIBLE WRAPPER ARCHITECTURE FOR TILED NETWORKS ON A CHIP - A wrapper organization and architecture for networks on a chip employing an optimized switch arrangement with virtual output queuing and a backpressure mechanism for congestion control. | 2008-09-04 |
| 20080211539 | Programmable matrix array with phase-change material - A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated. | 2008-09-04 |
| 20080211540 | PROGRAMMABLE ANTI-FUSE BASED ON, E.G., ZNCDS MEMORY DEVICES FOR FPGA AND OTHER APPLICATIONS - According to some embodiments, an “excess-current programming method” on ZnCdS memory devices for FPGA applications is disclosed. an “excess-current programming method” can also be employed within a variety of other applications, including other memory devices having low On-resistance, such as, e.g., metal-oxide memory like Ti-oxide, Ni-oxide, W-oxide, Cu-oxide and so on. Embodiments of ZnCdS based devices (e.g., memory devices), FPGA elements incorporating the same and methods thereof for reconfigurable circuits can reduce area overhead, power overhead and/or latency (e.g., of FPGA), address a disturbance problem during logic operation, decrease an ON-resistance characteristic and/or obtain increased data retention. | 2008-09-04 |
| 20080211541 | Precision voltage level shifter based on thin gate oxide transistors - A precision voltage level shifter based on thin gate oxide transistors is disclosed. A method of a voltage level shifter includes serially connecting thin n-channel gate oxide semiconductor FETs to think n-channel gate oxide semiconductor FETs to enable the voltage level shifter with a low input voltage. The method further includes permanently turning on a thick p-channel gate oxide semiconductor FET through grounding a gate of the thick p-channel gate oxide semiconductor FET to enable the voltage level shifter with an input voltage close to the I/O voltage of the voltage level shifter. | 2008-09-04 |
| 20080211542 | Input buffer with wide input voltage range - The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage. | 2008-09-04 |
| 20080211543 | 4-Level Logic Decoder - The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit, which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL. | 2008-09-04 |
| 20080211544 | Peak voltage detector circuit and binarizing circuit including the same circuit - A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal. | 2008-09-04 |
| 20080211545 | SAMPLE-AND-HOLD APPARATUS AND OPERATING METHOD THEREOF - A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively. | 2008-09-04 |
| 20080211546 | INTEGRATED DRIVER CIRCUIT FOR A LIN BUS - An integrated driver circuit is provided for a LIN bus comprises a first input terminal, a second input terminal, and an output terminal, which is to be connected to a bus line of the LIN bus and at which an output data signal, dependent on an input data signal, is output, whereby the output data signal is output according to a first or according to at least one second LIN bus specification depending on whether the input data signal is applied at the first input terminal or the at least second input terminal. | 2008-09-04 |
| 20080211547 | Inverter citcuit - An inverter circuit includes an IGBT ( | 2008-09-04 |
| 20080211548 | Semiconductor integrated circuit controlling output impedance and slew rate - The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on. | 2008-09-04 |
| 20080211549 | Fast Pulse Generator - A pulse generator including a pulsed switch ( | 2008-09-04 |
| 20080211550 | Noise reduced PWM driver - A PWM driver for driving an electric device by a PWM signal includes an ECU that provides a command signal, first circuit that provides a carrier signal of a triangular shape having a preset frequency, a second circuit that forms a PWM signal having a duty ratio formed based on the carrier signal and the command signal and an output circuit that drives an output device. The second circuit includes a duty ratio limiting circuit that limits the duty ratio of the PWM signal to a range between a first duty ratio and a second duty ratio to prevent the wave shape of the PWM signal from becoming a shape of an impulse. | 2008-09-04 |
| 20080211551 | Semiconductor memory device - A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry. | 2008-09-04 |
| 20080211552 | Controllable synchronous rectifier - The present controllable synchronous rectifier employs a Lus semiconductor to set synchronous rectification action in quadrant 1 of output characteristics of the conventional power MOSFETs. By controlling the voltage level of the gate-source voltage, the drain current can be controlled in the synchronous rectifier. Further, in combination with a protect opposite circuit to transfer a sinusoidal wave power supply or pulse power supply to a direct current power output, the synchronous rectifier is an indispensable high efficiency rectifier in the industry. | 2008-09-04 |
| 20080211553 | Delay locked loop in semiconductor memory device and method for generating divided clock therein - Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock. | 2008-09-04 |
| 20080211554 | Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays - A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation. | 2008-09-04 |
| 20080211555 | Delay locked loop in semiconductor memory device - A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively comparing a phase of a delayed feedback signal and a phase of the feedback signal with a phase of the external clock signal; a clock selecting block for selecting one of the first and second internal clock signals based on one comparison result to thereby generate a selected internal clock signal; a stuck checking block for determining a delay value based on the other comparison result; a delay line block for delaying the selected internal clock signal by the delay value; and an output buffer for buffering an outputted signal from the delay line block to thereby generating a DLL clock signal. | 2008-09-04 |
| 20080211556 | SEMICONDUCTOR INTEGRATED CIRCUIT - A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing charge competition for a given period of time in transition of the input to the component. The delay clock control circuit includes a P-type transistor disposed, for example, between a power line and the connection node for receiving the output of the second inverter at the gate thereof. | 2008-09-04 |
| 20080211557 | SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS - The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree. | 2008-09-04 |
| 20080211558 | Structure for Radiation Hardened Programmable Phase Frequency Divider Circuit - A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. | 2008-09-04 |
| 20080211559 | DATA HOLDING CIRCUIT AND SIGNAL PROCESSING CIRCUIT - A data holding circuit is capable of latching an input signal at both a rising edge and a falling edge of a clock signal. Several flip-flops and exclusive OR circuits cooperate to achieve this function. | 2008-09-04 |
| 20080211560 | CLOCK GENERATOR AND ASSOCIATED SELF-TEST AND SWITCHING-CONTROL METHOD - A clock generator with extended tuning range and associated method is provided. The associated self-test and switching-control method includes steps of generating a primary clock signal by a phase-locked loop circuit; determining a frequency limit of the primary clock signal; and determining a frequency-dividing condition of the frequency-dividing module according to the frequency limit and the target frequency. | 2008-09-04 |
| 20080211561 | Clock Signal Generation Circuit and Semiconductor Device - The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal. | 2008-09-04 |
| 20080211562 | METHOD AND DEVICE FOR GENERATING A CLOCK SIGNAL - A method and device for generating a clock signal, the method including measuring, using a first clock signal, a characteristic of a reference event in a received signal, determining, using the first clock signal, a variation of a characteristic of a second event in a received signal, correcting the measurement according to the variation of the characteristic of the second event, and generating a second clock signal using the first clock signal according to the corrected measurement. | 2008-09-04 |
| 20080211563 | Interface Circuit, Power Conversion Device, and Vehicle-Mounted Electric Machinery System - An interface circuit capable of reliably transmitting signal even when there is fluctuation in the potential difference in reference potentials between circuits between which signal transmission is carried out. An interface circuit | 2008-09-04 |
| 20080211564 | Signal Input Circuit - A circuit for breaking a signal path has not only a switching means but also a low-pass or bandpass filter whose frequency characteristic is switchable or bypassable. The insulation between the input and the output when the switching means is open, which decreases with frequency in the case of ordinary switching means, is compensated for by the filter which is then connected. In one embodiment of the circuit, an out-of-band signal is applied to the circuit in addition to the useful signal. The out-of-band signal is intended to be supplied permanently to an evaluation circuit, regardless of the switching position of the switching means. To this end, the out-of-band signal is tapped off downstream of the filter, and the filter is designed such that the out-of-band signal can pass through the filter In the case of a circuit for selecting one of two inputs, at least one of the inputs is provided with switchable or bypassable filter, and the switching means is a selection means. Even when the input is not selected, an out-of-band signal is forwarded to an evaluation circuit. To this end, the out-of-band signal, as described above, is tapped off downstream of the filter and upstream of the selection means. | 2008-09-04 |
| 20080211565 | Mute Circuit - AnNchMOS transistor ( | 2008-09-04 |
| 20080211566 | Apparatus for Driving a Load - An apparatus for driving a load that may include, for instance, a semiconductor chip, comprising a first switch, and a fracture sensor. The apparatus may further include, for instance, a circuit disposed outside the semiconductor chip and comprising a second switch coupled in series with the first switch, and configured such that an on/off state of the second switch is set in accordance with a state of the fracture sensor. | 2008-09-04 |
| 20080211567 | BIDIRECTIONAL SWITCH AND METHOD FOR DRIVING THE SAME - A bidirectional switch includes a field-effect transistor having a first ohmic electrode, a second ohmic electrode and a gate electrode, and a control circuit for controlling between a conduction state and a cut-off state by applying a bias voltage to the gate electrode. The control circuit applies the bias voltage from the first ohmic electrode as a reference when a potential of the second ohmic electrode is higher than the potential of the first ohmic electrode, and applies the bias voltage from the second ohmic electrode as a reference when the potential of the second electrode is lower than the potential of the first ohmic electrode. | 2008-09-04 |
| 20080211568 | MuGFET POWER SWITCH - A multi-gate field effect transistor power switch is used to selectively couple a circuit to a supply voltage. In various embodiments, both n and p-type multi-gate field effect transistor power switches may be used to couple sub-circuits of varying granularity to different voltage supplies. | 2008-09-04 |
| 20080211569 | Higher voltage switch based on a standard process - A higher voltage switching circuit based on a standard process limits the lowest applied voltage to an intermediate voltage between the higher voltage and ground, instead of ground. In this way, the maximum electric field across the gate dielectric is greatly reduced. In additional the use of p-type triple well also reduces junction breakdown in some embodiments. This concept is also valid in the case where the high voltage is negative, in which case the intermediate voltage is also negative. | 2008-09-04 |
| 20080211570 | Systems, Methods, and Integrated Circuits with Inrush-Limited Power Islands - A new approach for managing turn-on of power islands uses a precharge phase to begin the process of bringing up the island's internal supply voltage, while minimizing transients and associated power-control-logic instability. | 2008-09-04 |
| 20080211571 | Device For Passive Stabilization of Supply Voltages of a Semiconductor Element - In a device for passive stabilization of voltage supplies of a semiconductor element, regions made of a second conductivity type are embedded in a first layer of a first conductivity type within lateral regions, which are used for the wiring of standard cells of components. Barrier layers whose capacitances are used for supporting supply voltages are formed on the boundary surfaces. For this purpose, the regions of the second conductivity type are connected either to first substrate of the same conductivity type or to troughs within standard cells, which have the second conductivity type. | 2008-09-04 |
| 20080211572 | REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation. | 2008-09-04 |
| 20080211573 | Tunable balanced loss compensation in an electronic filter - The invention provides a system for providing tunable balanced loss compensation in an electronic filter. Tunable balanced loss compensation is provided by using cross-connected balanced transconductors and self-connected balanced transconductors. The cross-connected balanced transconductors and the self-connected transconductors compensate the unbalanced loss across the electronic filter. The self-connected balanced transconductors compensate the balanced loss across the electronic filter. Further, the cross-connected and the self-connected balanced transconductors are tunable by adjusting the values of their transconductances, thereby providing tunable balanced loss compensation. | 2008-09-04 |
| 20080211574 | CHOPPER-STABILIZED INSTRUMENTATION AMPLIFIER - This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal. | 2008-09-04 |
| 20080211575 | Loop Gain Equalizer For Rf Power Amplifier - The output power of an RF power amplifier is controlled using a feedback loop including a differential integrator for controlling the amplifier's bias voltage. The gain of integration in the differential integrator is varied so as to compensate for variations in the derivative of the power amplifier output power versus the bias voltage. | 2008-09-04 |
| 20080211576 | Linearization of RF Power Amplifiers Using an Adaptive Subband Predistorter - Predistorting an input signal prior to amplification in an RF power amplifier ( | 2008-09-04 |
| 20080211577 | AUDIO POWER AMPLIFIER USING VIRTUAL GROUND AND METHOD OF PROCESSING SIGNAL IN THE AUDIO POWER AMPLIFIER - An audio power amplifier provides a virtual ground to reduce power on/off noise and a method for processing a signal in the audio power amplifier. The audio power amplifier includes a switching amplifier to amplify a small output pulse width modulation (PWM) signal so as to generate a large output PWM signal, a pulse generating unit to generate a pulse signal having the same level as that of the PWM signal level, a first low pass filter to allow the large output PWM signal amplified by the switching amplifier to be low-pass filtered so as to restore the PWM signal to an audio signal, and a second low pass filter to allow the pulse signal generated by the pulse signal generating unit to be low-pass filtered so as to convert the pulse signal into a virtual ground voltage with respect to the restored audio signal. | 2008-09-04 |
| 20080211578 | Delta Sigma-Type AD converter, class-D amplifier, and DC-DC converter - A ΔΣ-type AD converter includes a subtractor which receives an analogue input signal and a feedback signal and which outputs a signal pertaining to a difference between the signals, an integrator which integrates a signal output from the subtractor, a comparator which binarizes a signal output from the integrator by comparing with a predetermined threshold value, a counter which measures respective pulse widths of a signal output from the comparator, and a PWM circuit which outputs a pulse signal of a predetermined period having a duty cycle responsive to a count value output from the counter and which feeds back the pulse signal as the feedback signal to the subtractor. The counter measures the respective pulse widths in each PWM frame period in synchronism with the PWM circuit, and the PWM circuit feeds back to the subtractor a pulse signal whose duty cycle is set in accordance with a value of the measured pulse width in a next PWM frame. A count value output from the counter is extracted as a converted digital output value. | 2008-09-04 |
| 20080211579 | METHOD AND APPARATUS FOR OPTIMIZING POWER DISSIPATION IN A LOW NOISE AMPLIFIER - A method and a low noise amplifier are provided such that the low noise amplifier has a power dissipation that is adaptive to the noise interference levels. The low noise amplifer includes (i) first, second and third differential amplifiers connected in series each having a terminal for receiving a power supply current; and (ii) first and second switches responsive to a control signal, the first and second switches configured such that, (a) when the control signal is in a first state, the first switch and the second switch enable independent currents to flow in the terminals for receiving a power supply current; and (b) otherwise, the first switch and the second switch enable the terminal for receiving a power supply current of the second differential amplifier to reuse a current provided to the terminal for receiving a power supply current of the third differential amplifier. The control signal is provided by a radio frequency noise power detector, which senses an output signal of the low noise amplifier. | 2008-09-04 |
| 20080211580 | LOW NOISE AC DIFFERENTIAL AMPLIFIER WITH REDUCED LOW CORNER FREQUENCY AND CURRENT CONSUMPTION - An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop. | 2008-09-04 |
| 20080211581 | Amplifier circuit with internal zeros - An amplifier circuit with internal zeros provides a second pole in addition to a first pole and two zeros such that the second pole can prevent excessive gain at high frequency, so as to have high-frequency noise under control. | 2008-09-04 |
| 20080211582 | WIDE-BAND ADJUSTABLE GAIN LOW-NOISE AMPLIFIER - A wide-band adjustable gain low-noise amplifier (LNA) is disclosed. In various embodiments, the LNA includes a first sub-circuit and a second sub-circuit coupled in parallel. In various embodiments, the first sub-circuit includes an amplifier configured to receive power when a logical signal is asserted and de-powered otherwise. In various embodiments, the second sub-circuit includes an amplifier configured to shunt an input node to a reference node using a resistor when the logical signal is de-asserted. Methods according to various embodiments of the invention are also disclosed. | 2008-09-04 |
| 20080211583 | SYSTEM AND METHOD FOR DYNAMIC DRAIN VOLTAGE ADJUSTMENT TO CONTROL LINEARITY, OUTPUT POWER, AND EFFICIENCY IN RF POWER AMPLIFIERS - A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency. | 2008-09-04 |
| 20080211584 | Cross-differential amplifier - A cross-differential amplifier is provided. The cross-differential amplifier includes an inductor connected to a direct current power source at a first terminal. A first and second switch, such as transistors, are connected to the inductor at a second terminal. A first and second amplifier are connected at their supply terminals to the first and second switch. The first and second switches are operated to commutate the inductor between the amplifiers so as to provide an amplified signal while limiting the ripple voltage on the inductor and thus limiting the maximum voltage imposed across the amplifiers and switches. | 2008-09-04 |
| 20080211585 | Adaptive Protection Circuit For a Power Amplifier - A radio frequency device comprises a radio frequency (RF) power amplifier (PA) operably coupled to a protection circuit for minimising voltage standing wave ratio effects, wherein the protection circuit comprises a current limiter indexed to a power supplied to the RF PA. | 2008-09-04 |
| 20080211586 | DUAL INPUT LOW NOISE AMPLIFIER FOR MULTI-BAND OPERATION - A dual input low noise amplifier (LNA) for multi-band frequency operation is disclosed. The dual input LNA ( | 2008-09-04 |
| 20080211587 | Method and Apparatus for Increasing the Efficiency of Low Power Amplifier - The present invention is directed to a method for reducing the current consumption and increasing the efficiency of an RF power amplifier (PA), while maintaining the output power. The desired output power of the PA is determined and for each level of the desired output power, the load that is connected to the output stage of the PA is tuned to essentially match the output impedance of the output stage to provide maximal gain. By doing so, the dynamic RF load line has a slope that causes it to intersect with the drain-source (or emitter-collector, in case of a bipolar transistor) voltage, across the output stage, at a value that corresponds to the voltage swing required to provide the desired output power. | 2008-09-04 |
| 20080211588 | Phase Error Cancellation - A noise cancellation signal is generated for a fractional-N phase-locked loop ( | 2008-09-04 |
| 20080211589 | Phase locked loop circuit including digital voltage-controlled oscillator, ring oscillator and selector - A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks. | 2008-09-04 |
| 20080211590 | METHOD AND SYSTEM FOR A VARACTOR-TUNED VOLTAGE-CONTROLLED RING OSCILLATOR WITH FREQUENCY AND AMPLITUDE CALIBRATION - Aspects of a method and system for a varactor-tuned voltage-controlled ring oscillator with frequency and amplitude calibration may include generating in a voltage controlled ring oscillator, an oscillating signal using delay cells, wherein each delay cell may comprise varactors and variable resistors. The frequency of the generated oscillating signal may be variable and may be calibrated by calibrating a delay associated with the delay cells. The amplitude of the generated oscillating signal may be calibrated by adjusting variable resistors and current sources within the delay cells. The frequency of the generated oscillating signal may be varied by varying the delay of at least one delay cell through changing the capacitance of its varactors. Changing a control voltage may change the varactor capacitance. The gain of the ring oscillator may be reduced by adjusting the varactors, and the generated oscillating signal may be a square wave signal. | 2008-09-04 |
| 20080211591 | OSCILLATORY SIGNAL OUTPUT CIRCUIT FOR CAPACITIVE COUPLING AN OSCILLATING SIGNAL WITH BIAS VOLTAGE APPLIED - Oscillatory signal output circuitry includes a bias circuit generating a bias voltage, which is applied to an amplifier and an oscillatory circuit to generate an oscillatory signal. The oscillatory signal is capacitively coupled and level-shifted up by the bias voltage to produce output signals. The produced output signals are operatively applied to PMOS and NMOS transistors of an output part. When the voltages of the output signals decrease at the same time, the drain current of the NMOS transistor decreases to output a high level. When the voltages of the output signals increase at the same time, the drain current of the NMOS transistor increases to output a low level. Therefore, the output part attains its large gain, and is ensured to operate to develop the output signal. A variation in threshold voltage would cause the bias voltages to change accordingly, thus being ensured to output the output signal. | 2008-09-04 |
| 20080211592 | Drive Circuit for a Voltage Controlled Differential Oscillator - A drive circuit for a voltage controlled differential oscillator using a negative resistance circuit for driving the resonator circuit of the voltage controlled differential oscillator. Opposite sides of the resonator circuit are connected to the negative resistance circuit with respective coupling capacitors so as to provide DC isolation between the resonator circuit and the negative resistance circuit. The negative resistance circuit includes an amplifier having a gain greater than unity so as to compensate for degradation in negative resistance resulting from the coupling capacitors. | 2008-09-04 |
| 20080211593 | Oscillation circuit - Provided is an oscillation circuit capable of obtaining a plurality of oscillation frequencies using a single oscillation resonator. The oscillation circuit includes the oscillation resonator, an oscillation inverter, a dumping resister connected between an output of the oscillation inverter and an output terminal, a feedback resistor connected with input and output of the oscillation inverter, and a feedback resistor switch for varying a feedback resistance value or an oscillation inverter switch for varying a mutual conductance value of the oscillation inverter. When the feedback resistance value or the mutual conductance value of the oscillation inverter is varied by the feedback resistor switch or the oscillation inverter switch, a frequency band of the oscillation circuit is adjusted to select a harmonic component of the oscillation resonator. Therefore, an oscillation frequency can be switched, so it is possible to obtain a plurality of oscillation frequencies using a single oscillation resonator. | 2008-09-04 |
| 20080211594 | Multi-Channel Pulse Modulator System - The present invention relates to a multi-channel pulse modulator system comprising a pulse modulator circuit, wherein said pulse modulator circuit comprises an N-channel, wherein the modulator output is output from the pulse modulator circuit by means of L output connections of the pulse modulator circuit and where L is less than the number of modulator channels N. The invention further relates to a method of converting an N-channel pulse modulated signal into an M-channel signal, where M is less than N. | 2008-09-04 |
| 20080211595 | CIRCUIT ARRANGEMENT FOR FREQUENCY MODULATION - A circuit arrangement for frequency modulation is provided, which includes a voltage-controlled oscillator having at least one varactor diode that is driven by a drive signal, wherein a capacitance of the varactor diode depends on the drive signal, includes a modulating unit that creates a modulation signal for frequency modulation of the voltage-controlled oscillator, and includes a drive unit that generates the drive signal for the at least one varactor diode from the modulation signal, wherein the drive unit generates the drive signal from the modulation signal in such a manner that a linear relationship results between the modulation signal and the capacitance of the varactor diode. | 2008-09-04 |
| 20080211596 | FREQUENCY MODULATION CIRCUIT - Provided is a frequency modulation circuit | 2008-09-04 |
| 20080211597 | Filter Circuit - A filter circuit including first and second real filters of a zero-IF scheme. The first and second real filters receive an I component and a Q component separated from a reception signal, respectively; and a switch section for producing a complex filter by switchably connecting the first and second real filters through interconnection elements. The switch section further receiving a switching signal for connecting the first and second real filters, thereby switching from the zero-IF scheme to a low-IF scheme. | 2008-09-04 |
| 20080211598 | ON-CHIP IMPEDANCE MATCHING USING A VARIABLE CAPACITOR - A system and a method for on-chip impedance matching, of at least two ports: an output source and an input load. The system includes an on-chip integrated impedance matching circuit (IMC) that comprises: at least one variable capacitor; a control unit that enables tuning of the variable capacitor, receiving and transmitting of signals and processing of signals; and at least one peak detector that enables detection of signal peaks (SP). Control unit enables determining of a substantially optimal signal peak and tuning of the variable capacitor to a substantially optimal capacitance that is corresponding to the said optimal signal peak. The highest signal peak provides the substantially optimal impedance matching between the ports. | 2008-09-04 |
| 20080211599 | Method for Determining Cable Termination Resistances in Communication Networks and a Corresponding Communication Network - The invention relates in general to a method for determining cable termination resistances in communication networks and a corresponding communication network, and is applicable especially to high-speed communication networks in automobiles, which uses dual-wire harnesses like FlexRay e.g. For this purpose a method for determining cable termination resistances in communication networks is proposed, where a termination resistance is assigned to at least a part of the cable ends of the network in accordance with the following steps determining for each cable end the cable length to any other cable end, assigning a weight value to each length where lengths with greater values are combined with higher weights than lengths with smaller values, for all cable ends: summing up the weights assigned to all lengths starting from a specific cable end and assigning this sum to the respective cable end as the weight of this cable end, determining the termination resistance of a specific cable end by multiplying the cable impedance Z with a constant of proportionality and the sum of the weights of all cable ends divided by the weight of the specific cable end. | 2008-09-04 |
| 20080211600 | Broad Band Mechanical Phase Shifter - Mechanical phase shifter which from an external feed signal obtains several signals out of phase with each other, each one of which is applied to an antenna of an array, so that the result of the interference of the radiated fields provides a radiation pattern. The object of the invention is to obtain a greater range of pointing angles, achieved by protrusions or screws that act as capacitors or short-circuits that allow suppressing the higher modes generated in the phase shifter, as well as preventing part of the mutual coupling between the phase shifter L-lines. In addition, due to the greater length of the L-lines, these are reinforced by a protrusion perpendicular to the greater length of the line located on the outer edge of each L-line, and in addition they are provided with supporting means for the L-lines which minimise the vibrations, sag and deformations. The L-lines also increase the frequency at which higher modes appear. | 2008-09-04 |
| 20080211601 | Discrete Voltage Tunable Resonator Made of Dielectric Material - A voltage tunable resonator is provided, including a dielectric base made of a dielectric material having at least one of a voltage dependent dielectric constant and piezoelectric characteristics. A metal contact having a predetermined area is provided on an outer surface of the dielectric base at a predetermined location to provide a predetermined loaded Q for the resonator, and a metal ground coating is provided on the remaining exposed surfaces of the dielectric base, and an isolation region having a sufficient area to prevent significant coupling between the metal contact and the metal ground coating. A control voltage applied between the metal contact and the metal ground coating provides at least one of (i) a variable electric field to control the dielectric constant and a resonant frequency of the resonator and (ii) a piezoelectric response causing a dimensional change in the resonator to control the resonant frequency of the resonator. | 2008-09-04 |
| 20080211602 | High-Frequency Acoustic Wave Device - An acoustic wave device comprising a piezoelectric layer on an omnidirectional acoustic mirror and excitation and/or reception means on a surface of said piezoelectric layer, capable of exciting waves in a band gap of the acoustic mirror. | 2008-09-04 |
| 20080211603 | Filter Coupled by Conductive Plates Having Curved Surface - Provided is a resonator filter using conductive plates having a curved surface to connect an input/output coaxial connector to a resonator. The resonator filter includes: a plurality of resonators for resonating; an input/output coaxial connector; an input/output supporting unit formed between the input coaxial connector and one of the resonators and/or between an output supporting unit formed between the output coaxial connector and other resonator for electrically and mechanically supporting the input/output coupling; and a connecting unit for connecting the input/output supporting unit and the input/output coaxial connector, wherein the input/output supporting unit is a conductive plate with a curved surface having a center axis similar to the resonators. | 2008-09-04 |
| 20080211604 | High frequency circuit board converting a transmission mode for mounting a semiconductor device - A microstrip line includes a signal strip conductor and a ground conductor. A coplanar line includes two regions. A first region includes a signal strip conductor which is connected to the signal strip conductor of the microstrip line via a wire or the like and a ground strip conductor which continues to the ground conductor. A second region is formed with a ground strip conductor formed above the ground strip conductor via a through hole. A transmission mode changes itself in the microstrip line, the first region of the coplanar line, and the second region of the coplanar line in the sequence as described. This enables converting the transmission mode efficiently from the microstrip line to the coplanar line. | 2008-09-04 |
| 20080211605 | Coupling Lines For a Yig Filter or Yig Oscillator and Method For Producing the Coupling Lines - A coupling conductor for a YIG filter or YIG oscillator, which may be produced from a metallic foil by eroding, laser cutting and/or etching of a metallic foil. The coupling conductor includes at least one curved section, which at least partially surrounds a YIG element and at least one conductor section. | 2008-09-04 |
| 20080211606 | TEMPERATURE COMPENSATION ATTENUATOR - A temperature compensation attenuator comprises a base, a serial film thermistor and a parallel film resistor on the base, an input terminal and an output terminal which are connected to the serial film thermistor The serial film resistor is at least partially a film thermistor and the parallel film resistor is not a thermistor. The attenuators can be applied in various circuits and systems utilizing high frequency waves or microwaves, and more particularly, are suitable for use in mobile communication systems, satellite communication systems, satellite navigational systems, and radar systems which require strict temperature characteristics. | 2008-09-04 |
| 20080211607 | Ground fault circuit interrupter device - A ground fault circuit interrupter device is described. | 2008-09-04 |
| 20080211608 | Electromagnetic relay - An electromagnetic relay includes an electromagnetic unit operable so as to generate a magnetic field perpendicular to a bottom wall of a housing when excited such that an actuating plate pivots from a releasing position to a pushing position, where a magnetically-attractable end portion of the actuating plate is attracted by the electromagnetic unit and where an actuating end portion of the actuating plate moves toward a first conductive plate, thereby driving a pushing block to move a resilient end portion of the first conductive plate toward a second conductive plate. Hence, first and second contacts on the first conductive plate contact electrically and respectively third and fourth contacts on the second conductive plate. | 2008-09-04 |
| 20080211609 | LEVER SWITCH - First rotator ( | 2008-09-04 |
| 20080211610 | Magnet Assembly - A magnet assembly ( | 2008-09-04 |
| 20080211611 | Transformer with Electrical Shield - A transformer, in particular an entirely cast resin transformer, includes at least one lower voltage winding and at least one upper voltage winding. The application of an electrical shielding around the upper voltage winding makes it possible to prevent a voltage disruptive discharge in such a way that the outer wall of the transformer can be touched by a person and also provides the transformer with electromagnetic shielding. The transformer is provided with bushings for internal electric connections and for that reason, it can be placed in media affected by dirty surroundings and in open air. | 2008-09-04 |
| 20080211612 | Hybrid Coils Having an Improved Heat Transfer Capability - A hybrid coil ( | 2008-09-04 |
| 20080211613 | TRANSFORMER - A transformer is provided. The transformer includes a first electrical conductor, a second electrical conductor, a circuit board and a core set. The first electrical conductor has a through hole and the second electrical conductor is electromagnetically coupled with the first electrical conductor and includes a plurality of spiral coils formed by winding a single conductive wire, each spiral coil having a through hole. The circuit board has a through hole. The core set penetrates the through hole of the first electrical conductor, the through hole of the circuit board, and the through holes of the plurality of spiral coils of the second electrical conductor, and covers at least one portion of the first electrical conductor and the second electrical conductor. | 2008-09-04 |
| 20080211614 | Inductive Rotary Transfer Device - There is described a device for the contactless transfer of energy and data. Said device comprises a primary coil assembly, which is located in a fixed manner on a first support and a secondary coil assembly, which is located in a fixed manner on a second support, the first and second supports being rotatable in relation to one another and the primary and secondary coil assemblies having a respective energy coil for the inductive transfer of electric energy. To achieve a least possible interference of the data transfer caused by the energy transfer, the primary and secondary coil assemblies comprise at least one respective data coil for an inductive data transfer and at least one data winging of said data coil surrounds at least one energy winding of the energy coil in such a way that a first section of the data winding is wound in the wound direction of the energy coil and a second section of the data winding is wound in the opposite direction to the wound direction of said energy coil. | 2008-09-04 |
