| 36th week of 2008 patent applcation highlights part 15 |
| Patent application number | Title | Published |
|---|
| 20080211013 | SEMICONDUCTOR MEMORY DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions. | 2008-09-04 |
| 20080211014 | ULTRA DENSE TRENCH-GATED POWER DEVICE WITH THE REDUCED DRAIN-SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE - The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate. | 2008-09-04 |
| 20080211015 | METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE - A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers. | 2008-09-04 |
| 20080211016 | TRENCH MOSGATED DEVICE WITH DEEP TRENCH BETWEEN GATE TRENCHES - A trench gated MOSFET especially for operation in high radiation environments has a deep auxiliary trench located between the gate trenches. A boron implant is formed in the walls of the deep trench (in an N channel device); a thick oxide is formed in the bottom of the trench, and boron doped polysilicon which is connected to the source electrode fills the trench. The structure has reduced capacitance and improved resistance to single event rupture and single event breakdown and improved resistance to parasitic bipolar action. | 2008-09-04 |
| 20080211017 | Semiconductor Device - A semiconductor substrate is formed with trenches, and each of the trenches includes: a gate electrode portion in which a gate electrode is arranged; and a gate lead portion which is brought into contact with an interconnect for electrically connecting the gate electrode to the outside. In the gate lead portion for electrically connecting the gate electrode to the outside, an end of each of the trenches has a greater width than a portion of the trench other than the end. | 2008-09-04 |
| 20080211018 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device includes a trench gate transistor including a groove formed on a semiconductor, a gate electrode formed in the groove via a gate insulating film, and a source and a drain disposed near the gate electrode on the semiconductor substrate via the gate insulating film. The gate electrode extends from an inner side of the groove to an outer side of the groove. The gate electrode has a misalignment portion in a width direction from the inner side of the groove to the outer side of the groove. The misalignment portion of the gate electrode is formed at a side higher than an opening edge of the groove. A height from the opening edge of the groove to the misalignment portion is larger than a thickness of the gate insulating film. | 2008-09-04 |
| 20080211019 | FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING A FIELD-EFFECT TRANSISTOR - A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer. The field-effect transistor includes a drain electrode at a side of the substrate facing away from the surface. An additional electrode is implemented between the gate electrode and the trench bottom and electrically insulated from the substrate and an electrical connection between the additional electrode and the gate electrode, wherein the electrical connection has a predetermined ohmic resistance value. | 2008-09-04 |
| 20080211020 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a lateral direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer; and a sixth first-conductivity-type semiconductor layer provided on the major surface of the first first-conductivity-type semiconductor layer in a termination section outside the periodic array structure. The second first-conductivity-type semiconductor layer has an impurity concentration varying in the lateral direction and the impurity concentration is minimized at a center in the lateral direction. An impurity concentration in the sixth first-conductivity-type semiconductor layer is not higher than the impurity concentration at the center of the second first-conductivity-type semiconductor layer. | 2008-09-04 |
| 20080211021 | Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture - According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region. | 2008-09-04 |
| 20080211022 | Semiconductor device having a triple gate transistor and method for manufacturing the same - In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer. | 2008-09-04 |
| 20080211023 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a first semiconductor layer and a second semiconductor layer facing each other across a back gate insulation film, a first conductive type plate provided in the first semiconductor layer, a gate insulation film provided on a surface of the second semiconductor layer so as to be in contact with a second surface opposite to a first surface in contact with the back gate insulation film, a gate electrode provided so as to be in contact with the gate insulation film, a first conductive type body region provided in the region facing the gate electrode across the gate insulation film in the second semiconductor layer, a second conductive type source layer and a second conductive type drain layer provided to sandwich the body region in the second semiconductor layer and a second conductive type diffusion layer provided in a surface region of the first semiconductor layer facing the source layer and the drain layer across the back gate insulation film, wherein the body region is in an electrically floating state and stores data by accumulating or discharging charges. | 2008-09-04 |
| 20080211024 | Memory Device and Manufacturing Method of the Same - An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film. | 2008-09-04 |
| 20080211025 | SOI field effect transistor and corresponding field effect transistor - A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile. | 2008-09-04 |
| 20080211026 | Coupling well structure for improving HVMOS performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 2008-09-04 |
| 20080211027 | ESD structure without ballasting resistors - An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor. | 2008-09-04 |
| 20080211028 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRO-STATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode. | 2008-09-04 |
| 20080211029 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced. | 2008-09-04 |
| 20080211030 | Semiconductor device and method of manufacturing thereof - A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the second conductive layer. An interlayer insulator has a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on the first layered film. The interlayer insulator is formed covering the first conductive layer and the second conductive layer. | 2008-09-04 |
| 20080211031 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A device isolation film is formed in a semiconductor substrate at a border portion between a first region and a second region for defining a first active region in the first region and a second active region in the second region. A gate insulating film and a gate electrode is formed over the semiconductor substrate in the first region. A first photoresist film covering the second region and having an opening exposing the first active region and having an edge on the border portion of the opening positioned nearer the second active region than a middle of the device isolation film is formed over the semiconductor substrate with the gate electrode. Impurity ions are implanted from a direction tilted from a normal direction of the semiconductor substrate with the first photoresist film and the gate electrode as a mask to form pocket regions in the semiconductor substrate on both sides of the gate electrodes. | 2008-09-04 |
| 20080211032 | Semiconduct Device and Method of Manufacturing Such a Semiconductor Device - The invention relates to a CMOS device ( | 2008-09-04 |
| 20080211033 | Reducing oxidation under a high K gate dielectric - A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier. | 2008-09-04 |
| 20080211034 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source region and the first drain region; and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first nickel silicide layer having a Ni/Si composition ratio of 1 or greater, and a silicide layer formed on the first nickel silicide layer. The silicide layer contains a metal having a larger absolute value of oxide formation energy than that of Si, and a composition ratio of the metal to Si is smaller than the Ni/Si composition ratio. | 2008-09-04 |
| 20080211035 | Semiconductor memory device and method of manufacturing the same - A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell. | 2008-09-04 |
| 20080211036 | Bipolar Resistive Memory Device Having Tunneling Layer - A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive layer and the tunneling layer may support transition between first and second resistance states responsive to first and second voltages applied across the first and second electrodes. The first and second voltages may have opposite polarities. | 2008-09-04 |
| 20080211037 | Semiconductor Device and Method of Forming Isolation Layer Thereof - A method of forming an isolation layer of a semiconductor device includes the steps of forming a gate insulating layer and a conductive layer on an active area of a semiconductor substrate; forming a spacer layer on side walls of the conductive layer; forming a trench on the semiconductor substrate between the spacer layer-covered side walls; removing the spacer layer to form a step on an upper edge of the trench; and forming a liner insulating layer on the trench. The method makes it possible to solve problems caused by impurities present in material with which the trench is gap-filled or present in etchants used in an etch-back process. | 2008-09-04 |
| 20080211038 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode. | 2008-09-04 |
| 20080211039 | Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals - A nonvolatile memory device includes a semiconductor substrate. A charge storage insulating film containing metal silicide nanocrystals is on the substrate. A gate electrode is on the charge storage insulating film. Related methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices including metal silicide nanocrystals, are also disclosed. | 2008-09-04 |
| 20080211040 | NANOSENSORS - Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described. | 2008-09-04 |
| 20080211041 | Micro electrical mechanical system device - A micro electrical mechanical system device includes a frame portion having an upper surface with a rectangular shape; a functional element; a beam portion extending from one of sides of the frame portion toward an opposite one and having a first side surface, a second side surface opposite to the first side surface, and upper and lower surfaces between the first and second side surfaces; and a movable portion supported on the beam portion inside the frame portion to be movable. The beam portion includes a constricted portion formed in the first side surface and the second side surface along the functional element, and having a main surface and two side surfaces facing each other. The movable portion includes a center portion having four corner portions and protruding portions extending from the corner portions and away from the frame portion and the beam portion. | 2008-09-04 |
| 20080211042 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - To provide a method for manufacturing a semiconductor device and a semiconductor device manufactured by the method. In the method, a movable portion formed on a semiconductor substrate can be released by etching an insulation layer in a shorter time and more readily controlling the etching amount in a section direction of the insulation layer. | 2008-09-04 |
| 20080211043 | METHOD AND SYSTEM FOR FLIP CHIP PACKAGING OF MICRO-MIRROR DEVICES - A package for a micro-electromechanical device includes a substrate adapted to support the micro-electromechanical device. The micro-electromechanical device is electrically coupled to a plurality of electrodes. The package also includes a thermally conductive structure coupled to the substrate, an electrical contact layer having a plurality of traces in electrical communication with the plurality of electrodes, and an interposer structure coupled to the substrate. The interposer structure includes a continuous annular region defining a recessed region bounded by a bond surface. The package further includes a transparent cover coupled to the interposer structure and sealing the micro-electromechanical device in the recessed region to isolate the micro-electromechanical device in a controlled environment. | 2008-09-04 |
| 20080211044 | Micro-electro-mechanical systems device - According to an aspect of an embodiment, a micro-electro-mechanical systems (MEMS) device comprises a substrate, a MEMS and a movable absorber. | 2008-09-04 |
| 20080211045 | Module for optical apparatus and method of producing module for optical apparatus - An electric wiring of a module for an optical apparatus includes: a first through electrode passing through the solid-state image sensor; a first rewiring layer being formed in such a way as to be re-wired to a necessary area in the rear surface of the solid-state image sensor, and being electrically connected to the first through electrode; a second rewiring layer being formed in such a way as to be re-wired to a necessary area in the rear surface of the image processing apparatus, and being electrically connected to the first rewiring layer; a second through electrode passing through the image processing apparatus and being electrically connected to the second rewiring layer; and a third rewiring layer being formed in such a way as to be re-wired to a necessary area in a front surface of the image processing apparatus, and being electrically connected to the second through electrode. The image processing apparatus includes an external connection terminal electrically connected to the third rewiring layer. With the foregoing structure, a small and light module for an optical apparatus and a production method of such module are realized without giving a constraint on the structure of the module. | 2008-09-04 |
| 20080211046 | SEMICONDUCTOR DEVICE FOR IMAGE SENSOR - Embodiments relate to a semiconductor device for an image sensor method of fabricating a semiconductor device for an image sensor having a micro lens. According to embodiments, the method may include forming a lower insulating film having cavities on a substrate, forming an upper insulating film having cavities on the lower insulating film, forming a protective insulating film having metal films on the upper insulating film, forming a number of color filters having a specified pattern on the protective insulating film, forming a planarization layer having a specified curvature on the color filters to bury the color filters in the planarization layer, and forming a number of micro lenses on the planarization layer at respective positions corresponding to the color filters. | 2008-09-04 |
| 20080211047 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS USING THE SAME - A solid-state imaging device includes a semiconductor substrate, a first pixel with a green color filter, a second pixel with a blue color filter and a third pixel with a red color filter. The first pixel includes a first area for generating an electric signal by photoelectric conversion, disposed in a first trench that is formed on a surface of the semiconductor substrate, and a first transistor area that outputs the electric signal obtained from the first area. The second pixel includes a second area formed in a flat shape on the surface of the semiconductor substrate, and a second transistor area that outputs the electric signal obtained from the second area. The third pixel includes a third area formed in a flat shape on the surface of the semiconductor substrate, and a third transistor area that outputs the electric signal obtained from the third area. | 2008-09-04 |
| 20080211048 | Encapsulated Optical Package - A method for providing an encapsulated optoelectronic chip is provided. The optoelectronic chip is secured on a substrate. A translucent coating substance is then applied on said optoelectronic chip and the translucent coating substance is then polished away to enable an optical coupling. | 2008-09-04 |
| 20080211049 | METHOD AND DEVICE FOR INTEGRATING AN ILLUMINATION SOURCE AND DETECTOR INTO THE SAME IC PACKAGE THAT ALLOWS ANGULAR ILLUMINATION WITH A COMMON PLANAR LEADFRAME - An optical navigation device includes an integrated package. The integrated package includes a planar leadframe, a light source die mounted on the leadframe, and a sensor die mounted on the leadframe to be coplanar with the light source die. The integrated package may be mounted at an angle or parallel to a navigation surface. The sensor die may be mounted at a distance from the light source die to detect specular or scattered reflection. The optical navigation device may be devoid of any optical element used to manipulate light generated by the light source die. | 2008-09-04 |
| 20080211050 | Image sensor with inter-pixel isolation - An image sensor with a plurality of photodiodes that each have a first region constructed from a first type of material and a second region constructed from a second type of material. The photodiodes also have an insulating region between the first and second regions. The photodiodes are arranged in an array. In corner regions of the array, the second regions are offset relative to the insulating regions to capture more photons of incoming light. | 2008-09-04 |
| 20080211051 | Component with a Semiconductor Junction and Method for the Production Thereof - A component comprising a semiconductor junction (HU) is proposed which is formed from crystalline doped semiconductor layers. A semiconductor circuit (IC) is formed on the surface of the component, and a diode is formed internally and directly below the circuit. Integrated circuit and diode are connected to one another and formed and integrated diode component, in particular a photodiode array. | 2008-09-04 |
| 20080211052 | FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid. | 2008-09-04 |
| 20080211053 | Superjunction Semiconductor Device - In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region. | 2008-09-04 |
| 20080211054 | METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS - A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer. | 2008-09-04 |
| 20080211055 | Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit - Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization. | 2008-09-04 |
| 20080211056 | Semiconductor device and a method of manufacturing the same and designing the same - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 2008-09-04 |
| 20080211057 | Semiconductor having buried word line cell structure and method of fabricating the same - Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer. | 2008-09-04 |
| 20080211058 | Semiconductor device and method of manufacturing same - A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode lead subjected to trimming comprises a diffusion layer formed in an uppermost layer of the silicon substrate. The diffusion layer is covered with a protection film made of doped polysilicon and is directly formed on the silicon substrate. | 2008-09-04 |
| 20080211059 | ELECTRONIC FUSE HAVING HEAT SPREADING STRUCTURE - A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented. | 2008-09-04 |
| 20080211060 | ANTI-FUSE WHICH WILL NOT GENERATE A NON-LINEAR CURRENT AFTER BEING BLOWN AND OTP MEMORY CELL UTILIZING THE ANTI-FUSE - An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly. | 2008-09-04 |
| 20080211061 | Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates - A method of making a virtual substrate includes providing a device substrate of a first material containing a device layer of a second material different from the first material located over a first side of the device substrate, implanting ions into the device substrate such that a damaged region is formed in the device substrate below the device layer, bonding the device layer to a handle substrate, and separating at least a portion of the device substrate from the device layer bonded to the handle substrate along the damaged region to form a virtual substrate comprising the device layer bonded to the handle substrate. | 2008-09-04 |
| 20080211062 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type GaN substrate ( | 2008-09-04 |
| 20080211063 | Semiconductor wafer and manufacturing method of semiconductor device - A semiconductor wafer includes a semiconductor substrate, a semiconductor layer, and an oxide layer. The semiconductor layer is disposed on a surface of the semiconductor substrate and has a crystal structure similar to a crystal structure of the semiconductor substrate. The semiconductor layer includes an element section and a scribe section. The scribe section is disposed to divide the element section into a plurality of portions and is configurated to be used as a cutting allowance for dicing. Each of the portions includes a column structure in which columns having different conductivity types are arranged alternately. The oxide layer is disposed on a surface of the scribe section to be exposed to an outside of the semiconductor device. | 2008-09-04 |
| 20080211064 | DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH - A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region. | 2008-09-04 |
| 20080211065 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a material layer of a semiconductor device includes providing a workpiece, and forming a ZrO | 2008-09-04 |
| 20080211066 | BARRIER FILM AND METHOD OF PRODUCING BARRIER FILM - A barrier film formed on top of a substrate, a barrier film formed so as to cover a functional element region fabricated on top of a substrate, or a barrier film formed on both a substrate and a functional element region, wherein the barrier film includes at least one layer of a silicon nitride film formed by laminating two or more silicon nitride layers having different Si/N composition ratios. | 2008-09-04 |
| 20080211067 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect. | 2008-09-04 |
| 20080211068 | METHOD FOR MANUFACTURING LEADFRAME, PACKAGING METHOD FOR USING THE LEADFRAME AND SEMICONDUCTOR PACKAGE PRODUCT - A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads. | 2008-09-04 |
| 20080211069 | SEMICONDUCTOR PACKAGE CONFIGURATION WITH IMPROVED LEAD PORTION ARRANGEMENT - A semiconductor device with improved reliability is provided. The semiconductor device in a QFN package configuration has a semiconductor chip mounted on a tab, leads which are alternately arranged around the tab and electrically connected to the electrodes of the semiconductor chip via bonding wires, and an encapsulating resin portion for encapsulating therein the semiconductor chip and the bonding wires. The lower exposed surfaces of the leads are exposed at the outer peripheral portion of the back surface of the encapsulating resin portion to form external terminals. The lower exposed surfaces of the leads are exposed at the portion of the back surface of the encapsulating resin portion which is located inwardly of the lower exposed surface of the leads to also form external terminals. The cut surfaces of the leads are exposed at the cut surfaces of the encapsulating resin portion, while the upper exposed surfaces of the leads are exposed from the portion of the encapsulating resin portion which is proximate to the cut surfaces thereof. Each of the upper exposed surfaces of the leads has a width smaller than the width of each of the lower exposed surfaces thereof. | 2008-09-04 |
| 20080211070 | Flip chip contact (FCC) power package - This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames. | 2008-09-04 |
| 20080211071 | Memory IC Package Assembly Having Stair Step Metal Layer and Apertures - Disclosed is a low cost memory IC package assembly having a first metal layer bonded to the die and a dielectric insulating layer with circuits and with apertures to expose the first metal layer bonded thereto. | 2008-09-04 |
| 20080211072 | Testing and burn-in using a strip socket - A method and apparatus are provided for using a strip socket in testing or burn-in of semiconductor devices in a strip. In one example of the method, processing of semiconductor devices involves assembling the semiconductor devices into a strip, isolating a portion of each of the semiconductor devices of the strip, and performing operations on the strip using a strip socket, wherein the strip socket is designed to make electrical contact substantially simultaneously with each semiconductor device in the strip. | 2008-09-04 |
| 20080211073 | AIRTIGHT PACKAGE - An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit. | 2008-09-04 |
| 20080211074 | IC CARD AND METHOD OF MANUFACTURING THE SAME - An IC body is loaded to a case | 2008-09-04 |
| 20080211075 | IMAGE SENSOR CHIP SCALE PACKAGE HAVING INTER-ADHESION WITH GAP AND METHOD OF THE SAME - A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes; a multiple rings (dam bar) formed over the substrate, the RDL, and the bonding pads area except the sensor area; an adhesive glues fill into the space of the multiple ring except the sensor area; and a transparency material bonded on the top of the multiple ring and the adhesive glues, wherein the adhesive glues adhesion between the transparency material and the multiple rings. | 2008-09-04 |
| 20080211076 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of elevating a yield rate of products to improve the productivity and also ensuring high reliability in production and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a semiconductor substrate | 2008-09-04 |
| 20080211077 | Low profile chip scale stacking system and method - The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material. | 2008-09-04 |
| 20080211078 | SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked semiconductor packages provides a simple manufacturing process. The stacked semiconductor package embodying these principles preferably includes a base substrate, one or more lower semiconductor packages, one or more upper semiconductor packages, and an external sealing agent. Each lower semiconductor package can include a first inner substrate, one or more first semiconductor chips electrically connected to and mounted on the first inner substrate, a first inner sealing agent sealing the first semiconductor chips, and a first contact portion. Each lower semiconductor package is preferably mounted on a portion of an upper surface of the base substrate and is electrically connected to the base substrate via the first contact portion. Each upper semiconductor package can include a second inner substrate, one or more second semiconductor chips electrically connected to and mounted on the second inner substrate, a second inner sealing agent sealing the second semiconductor chips, and a second contact portion which preferably does not contact the lower semiconductor package. Each upper semiconductor package is preferably mounted on and electrically connected to an upper surface of the base substrate via the second contact portion. One or more of the upper semiconductor packages can cover one or more of the lower semiconductor packages. The external sealing agent can cover the upper surface of the base substrate and seal the lower semiconductor package and the upper semiconductor package. A third contact portion can be formed on a lower surface of the base substrate to electrically connect the base substrate to the outside. Use of stacked semiconductor packages constructed according to these principles leads to low defect rates and high mechanical stability. | 2008-09-04 |
| 20080211079 | Heat dissipation methods and structures for semiconductor device - A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip. | 2008-09-04 |
| 20080211080 | Package structure to improve the reliability for WLP - The present invention provides a package structure to improve the reliability for WLP (Wafer Level Package). The package structure includes at least two areas. One area is harder than another. The hard area sustains more shears resulting from board drop test than the soft area in order to disperse the shear in the soft area to avoid the peeling of the buffer layers within the soft area. | 2008-09-04 |
| 20080211081 | PLANAR MULTI SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate. | 2008-09-04 |
| 20080211082 | Semiconductor device and a method of manufacturing the same - A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET ( | 2008-09-04 |
| 20080211083 | Electronic package and manufacturing method thereof - An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being formed in the other surface of the second chip; encapsulating the second chip by coating the other surface of the PCB with an insulation material; and processing a first via by punching a hole on the insulation material, the first via being electrically interconnected to the pad, can perform stable handling in a process of mounting a semiconductor chip, make it unnecessary to add a process for chip encapsulation and realize a system in package having high density and high reliability. | 2008-09-04 |
| 20080211084 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER - An integrated circuit package system includes: providing a mountable integrated circuit system having an encapsulation with a cavity therein and a first interposer exposed by the cavity; mounting a second interposer over the first interposer for only stacking a discrete device thereover, and with the second interposer over the encapsulation and the cavity; and mounting an electrical component over the second interposer. | 2008-09-04 |
| 20080211085 | Semiconductor package having insulating substrate - A semiconductor package having an insulating substrate includes a dielectric layer, a set of metal layers, a set of supporting elements, and an electronic component. The set of metal layers includes a first metal layer and a second metal layer respectively located on the upper surface and the lower surface of the dielectric layer. The set of supporting elements includes a first supporting element and a second supporting element respectively located on the first metal layer and the second metal layer. The electronic component is electrically connected with the first supporting element. The dielectric layer and the set of metal layers form an insulating substrate. Furthermore, a package resin is disposed on the second supporting element to package the dielectric layer, the set of metal layers, the first supporting element, and the electronic component into one piece and fasten it on to the second supporting element. | 2008-09-04 |
| 20080211086 | Mounting method of electronic components, manufacturing method of electronic component-embedded substrate, and electronic component-embedded substrate - There is disclosed a fixing method of an electronic component or the like in which when the electronic component and a resin layer are fixed, warp and bend of the electronic component can be inhibited. During manufacturing of a semiconductor-embedded substrate | 2008-09-04 |
| 20080211087 | CHIP MODULE AND METHOD FOR PRODUCING A CHIP MODULE - A chip module comprises a substrate, a chip arranged on one side of the substrate and conductor structures arranged on at least one side of the substrate and conductively connected to the chip. At least one stiffening element is arranged on one side of the substrate and a moulding cap encapsulates at least the chip. For producing the chip module, provision is made for providing a substrate and applying conductor structures to at least one side of the substrate. At least one stiffening element is mounted onto one side of the substrate. Furthermore, a chip is mounted onto one side of the substrate and connected to the conductor structures. A moulding compound is applied on the substrate, such that the chip is covered. | 2008-09-04 |
| 20080211088 | SEMICONDUCTOR DEVICE - The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink. | 2008-09-04 |
| 20080211089 | Interposer for die stacking in semiconductor packages and the method of making the same - Methods and apparatus for improved electrical, mechanical and thermal performance of stacked IC packages are described. An IC package comprises a substrate, a first die, a second die, and an interposer with an opening in a first surface of the interposer configured to accommodate the first die. The first IC die is attached a first surface of the substrate. The interposer is mounted on the first surface of the substrate such that the first IC die is placed within the opening in the interposer. The second die is mounted on a second surface of the interposer. Wire bonds couple bond pads on the first surfaces of IC die are coupled to the first surface of the substrate. A mold compound encapsulates the first IC die, the second IC die, the interposer and the wire bonds. | 2008-09-04 |
| 20080211090 | Packed Semiconductor Sensor Chip For Use In Liquids - The present invention provides a packed semiconductor sensor chip ( | 2008-09-04 |
| 20080211091 | Power Semiconductor Module and Method for Producing the Same - A method for producing a power semiconductor module including forming a contact between a contact region and a contact element as an ultrasonic welding contact via a sonotrode. The ultrasonic welding operation also being used for joining the contact regions with the contact ends and consequently for joining the contacts and the foot regions. | 2008-09-04 |
| 20080211092 | ELECTRONIC ASSEMBLY HAVING A MULTILAYER ADHESIVE STRUCTURE - An electronic assembly comprising a first substrate, a number of bonds on the first substrate, a second substrate spaced apart from the first substrate, a number of bumps on the second substrate, each of the bumps including an insulating body and a conductive portion, the conductive portion extending from a top surface of the insulating body via at least one sidewall of the insulating body toward the second substrate, and an adhesive between the first substrate and the second substrate, the adhesive including an insulating layer and a conductive layer, the insulating layer and the conductive layer being laminated with respect to each other, wherein the insulating layer is positioned closer to the first substrate than the conductive layer. | 2008-09-04 |
| 20080211093 | Semiconductor device having conductive bumps and fabrication method thereof - A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers. | 2008-09-04 |
| 20080211094 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an electrode pad formed on a pad forming surface of a semiconductor integrated circuit chip, and a step formed on the pad forming surface to surround the electrode pad. A method of manufacturing the semiconductor device is also disclosed. | 2008-09-04 |
| 20080211095 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive adhesive contains a conductive filler including silver (Ag); and the second conductive adhesive contains a conductive filler including a metal selected from a group consisting of tin (Sn), zinc (Zn), cobalt (Co), iron (Fe), palladium (Pd), and platinum (Pt). | 2008-09-04 |
| 20080211096 | Switching Element and Reconfigurable Logic Integrated Circuit - A switching element is of a configuration that includes: an ion conduction layer ( | 2008-09-04 |
| 20080211097 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes an insulating interlayer formed above a silicon substrate and provided with a concave portion in a certain location, a barrier metal film covering an inner wall of the insulating interlayer, a lower layer copper interconnect provided so as to be in contact with the barrier metal film and buried in the interior of the concave portion, and a protective film provided so as to be in contact with the lower layer copper interconnect and also provided on substantially the entire top surface of the lower layer copper interconnect. An upper surface of the lower layer copper interconnect is provided so as to be retracted to be closer to the substrate than an upper surface of barrier metal film on the side wall of the concave portion. The protective film contains Co or Ni as constituent element, and Co concentration or Ni concentration in the protective film in vicinity of the side wall of the barrier metal film is higher than Co concentration or Ni concentration in the barrier metal film in the central region of the concave portion. | 2008-09-04 |
| 20080211098 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed. | 2008-09-04 |
| 20080211099 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 2008-09-04 |
| 20080211100 | METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION - A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy). | 2008-09-04 |
| 20080211101 | Interlayer wiring of semiconductor device using carbon nanotube and method of manufacturing the same - Provided is an interlayer wiring structure of a semiconductor device using carbon nanotubes, and a method of manufacturing the interlayer wiring structure. The interlayer wiring structure is a carbon nanotube bundle that connects a first electrode to a second electrode. The carbon nanotube bundle includes a plurality of carbon nanotubes grown from a catalyst layer that is formed on a first electrode. The carbon nanotube bundle is made in a manner that a portion of the carbon nanotube bundle close to the second electrode has higher density of carbon nanotubes than another portion of the carbon nanotube bundle close to the first electrode. The carbon nanotube bundle is surrounded by an interlayer dielectric. In one embodiment of a method of manufacturing the carbon nanotube interlayer wire, liquid droplets are distributed between the carbon nanotubes to induce surface tension between the carbon nanotubes. The surface tension makes the carbon nanotube bundle maintain higher density of carbon nanotubes in a portion close to the second electrode. | 2008-09-04 |
| 20080211102 | LATERALLY GROWN NANOTUBES AND METHOD OF FORMATION - A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts. | 2008-09-04 |
| 20080211103 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse. | 2008-09-04 |
| 20080211104 | High Temperature, Stable SiC Device Interconnects and Packages Having Low Thermal Resistance - A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling. | 2008-09-04 |
| 20080211105 | Method of assembling chips - A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material. | 2008-09-04 |
| 20080211106 | VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF - A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer. | 2008-09-04 |
| 20080211107 | Via hole structure and manufacturing method thereof - A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout. | 2008-09-04 |
| 20080211108 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 2008-09-04 |
| 20080211109 | SEMICONDUCTOR DEVICE AND METHOD OF VISUAL INSPECTION AND APPARATUS FOR VISUAL INSPECTION - A semiconductor device having the structure, which is adopted for the highly precise visual inspection with a lower cost, is achieved. A semiconductor device is a semiconductor device having a region for forming an electric circuit, and includes seal rings provided in an interconnect layer and surrounding the region for forming an electric circuit, and a dummy metal via provided in the interconnect layer and located outside of the seal rings. In a cross section perpendicular to an elongating direction of the seal ring, the width of the dummy metal via is smaller than the width of the seal ring. | 2008-09-04 |
| 20080211110 | SEMICONDUCTOR APPARATUS AND MOBILE APPARATUS - A semiconductor apparatus includes: a wiring board; a first semiconductor device mounted on the wiring board; a second semiconductor device which is stacked on the first semiconductor device and a projection part projects from the outer edge of the first semiconductor device; and a sealing resin layer which seals each semiconductor device. And the second semiconductor device has thereon a first analog cell, and a second analog cell which reaches a higher temperature than the first analog cell, and the second analog cell is arranged so as to include the projection part of the second semiconductor device. | 2008-09-04 |
| 20080211111 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDERFILL - An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device. | 2008-09-04 |
| 20080211112 | Carbon Nanotube Bond Pad Structure and Method Therefor - A bond pad structure ( | 2008-09-04 |
