| 36th week of 2008 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20080210913 | Modified electroconductive polymer material and polymer film - Disclosed is a modified electroconductive polymer material, which comprises a metal filled in a space between the chains of an electroconductive polymer. The metal is oxidized (partially formed as a hydroxide) through a chemical reaction between three substances consisting of the metal, a cation radical/dication, and absorbed water. The metal has a work function less than that of the electroconductive polymer. The contact between the metal and the electroconductive polymer is kept in the state of coexistence between three substances consisting of the metal, the cation radical/dication and the absorbed water. This allows an electroconductive polymer material to have enhanced durability against oxidation/reduction, and controlled conductivity. | 2008-09-04 |
| 20080210914 | Flame-retardant, curable moulding materials - The invention relates to a halogen-free flameproofing agent for curable moulding materials, the use of such flameproofing agents for the flame-retardant treatment of curable moulding materials, a process for the preparation of halogen-free, flame-retardant curable moulding materials, and halogen-free, flame-retardant curable moulding materials. | 2008-09-04 |
| 20080210915 | Jack bar with extendable tubes and fixturing mechanism - A jack bar includes an outer tube, an inner tube and a positioner tube coaxially located. The positioner tube is extendable to adjust a length to the jack bar in use while enabling the jack bar to be retracted for storage. The jack bar further includes a clamp configured to receive tubes of various shapes. The clamp is further configured to prevent twisting or turning of clamped tubes. | 2008-09-04 |
| 20080210916 | TOOL FOR SEPARATING LADDER SECTIONS - A separating tool includes a lever component and a linear-output component pivotally secured to the lever component. Each of the lever component and the linear-output component includes a rung-engagement member. The lever component and the linear-output component are configured so that when the rung-engagement members are engaging rungs of respective ladder sections, pivoting the lever component toward the linear output member imparts a linear force through the rung-engagement members that separates the ladder sections. | 2008-09-04 |
| 20080210917 | Wedge-Formed Lifting Cushion - The invention relates to a lifting cushion ( | 2008-09-04 |
| 20080210918 | MODULAR PERIMETER ELECTRONIC SECURITY SYSTEM - A modular array for a security fence system includes a tension module with a plurality of tension devices, a tensioning compensation module with a plurality of tensioning compensation devices, and a plurality of conductors each extending between a tension device and a tensioning compensation device. The modular arrays may be stacked for increased fence height. A conductor support module individually supports each conductor. An angular deviation module accommodates right, obtuse or acute angles. The tension devices automatically set the tension in the conductors to a predetermined tension. The tensioning compensation devices automatically accommodate expansion or contraction of the conductors due to temperature changes. All of the components of the modular array may be shipped in a standard pallet. | 2008-09-04 |
| 20080210919 | Freestanding fence - A freestanding fence constructed of square tubing and a few connectors. The fence is supported on footed x-shaped posts that sit on top of the ground. A horizontal member extends between adjacent x-shaped posts and a footed vertical support member is provided on each horizontal member approximately midway between the adjacent x-shaped posts. Several fence wires extend horizontally and connect to adjacent x-shaped posts along the length of the fence via electrical insulators and non-conductive fasteners so that the fence can be electrified. The horizontal members attach to the posts by means of couplings that allow for both vertical and horizontal adjustment. The fence is constructed of easily transported and assembled pieces that can be disassembled, moved, and then reassembled as often as needed. | 2008-09-04 |
| 20080210920 | BARRIER SAFETY SYSTEM - A barrier safety system ( | 2008-09-04 |
| 20080210921 | Silver selenide film stoichiometry and morphology control in sputter deposition - A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr. | 2008-09-04 |
| 20080210922 | Storage nodes and methods of manufacturing and operating the same, phase change memory devices and methods of manufacturing and operating the same - In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory device. The storage node may further include a phase change layer on top of a bottom diode and a top electrode on a top surface of a phase change layer. | 2008-09-04 |
| 20080210923 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device including a heater electrode formed in a contact hole formed in an interlayer insulation film to expose a lower electrode, the heater electrode includes at least three heater electrode layers which are successively laminated and successively increased in specific resistivity in a direction from the lower electrode towards a phase change film in this order. The interlayer insulation film is formed on a semiconductor substrate to cover the lower electrode. The phase change film is formed in contact with an upper surface of the heater electrode. An upper electrode is formed on an upper surface of the phase change film. | 2008-09-04 |
| 20080210924 | Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same - A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown on the lower electrode. | 2008-09-04 |
| 20080210925 | THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration. | 2008-09-04 |
| 20080210926 | Three-dimensional phase-change memory array - A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements. | 2008-09-04 |
| 20080210927 | Buffer architecture formed on a semiconductor wafer - In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed. | 2008-09-04 |
| 20080210928 | Semiconductor Device - The present invention provides a semiconductor device which has a storage element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers and a manufacturing method of such a semiconductor device. With this characteristic, a semiconductor device having a storage circuit which is nonvolatile, additionally recordable, and easily manufactured and a manufacturing method of such a semiconductor device are provided. A semiconductor device according to the present invention has a plurality of field-effect transistors provided over an insulating layer and a plurality of storage elements provided over the plurality of field-effect transistors. Each of the plurality of field-effect transistors uses a single-crystal semiconductor layer as a channel portion and each of the plurality of storage elements is an element in which a first conductive layer, an organic compound layer, and a second conductive layer are stacked in order. | 2008-09-04 |
| 20080210929 | Organic Thin Film Transistor - An organic thin film transistor is formed using an organic semiconducting polymer that contains electrically conductive micro scale or nanoscale metallic plates, particulates, or rods dispersed in the polymer at a concentration less than the percolation threshold to form a semiconducting matrix. The electrically conductive particulates are dispersed to provide a multidimensional micro scale network so that the materials do not provide electrical conductivity between themselves but only between an individual particulate and the organic semiconductor. The transconductance value of the semiconducting matrix is at least one order of magnitude greater than the transconductance value of the neat organic semiconductor, providing a switching speed from an ‘off’ state to an ‘on’ state at least one order of magnitude greater than a switching speed of the neat organic semiconductor. | 2008-09-04 |
| 20080210930 | Metal Complex, Light-Emitting Device, and Image Display Apparatus - To provide a novel metal complex suitable as a compound for an organic EL device. A metal complex including a partial structure represented by the following general formula ( | 2008-09-04 |
| 20080210931 | METHODS FOR FORMING AN UNDERCUT REGION AND ELECTRONIC DEVICES INCORPORATING THE SAME - An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the patterned protective layer. An opening within the substrate structure overlies an exposed portion of the substrate structure. The method further includes removing the exposed portion of the patterned protective layer, thereby exposing a portion of the first electrode and forming an undercut region of the substrate structure. The method still further includes depositing a liquid over the first electrode after removing the exposed portion of the patterned protective layer, and solidifying the liquid to form a solid layer. | 2008-09-04 |
| 20080210932 | Memory Element, Memory Device, and Semiconductor Device - On object of the invention is to provide a non-volatile memory device, in which data can be added to the memory device after a manufacturing process and forgery and the like by rewriting can be prevented, and a semiconductor device including the memory device. Another object of the invention is to provide a highly-reliable, inexpensive, and nonvolatile memory device and a semiconductor device including the memory device. A memory element includes a first conductive layer, a second conductive layer, a first insulating layer with a thickness of 0.1 nm or more and 4 nm or less being in contact with the first conductive layer, and an organic compound layer interposed between the first conductive layer, the first insulating layer, and the second conductive layer. | 2008-09-04 |
| 20080210933 | SUBSTITUTED ANTHRACENES AND ELECTRONIC DEVICES CONTAINING THE SUBSTITUTED ANTHRACENES - Substituted anthracene compounds and electronic devices containing the substituted anthracene compounds are provided. | 2008-09-04 |
| 20080210934 | Semiconductor Device Using Titanium Dioxide as Active Layer and Method for Producing Semiconductor Device - Object: To provide a semiconductor device using titanium dioxide as an active layer and a method for producing thereof. | 2008-09-04 |
| 20080210935 | Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method - A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal. The probing pad is configured to be contacted with a probe wire. The pad connection wiring is configured to electrically connect the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined distance from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area. | 2008-09-04 |
| 20080210936 | Hetero-Crystalline Semiconductor Device and Method of Making Same - A hetero-crystalline semiconductor device and a method of making the same include a non-single crystalline semiconductor layer and a nanostructure layer that comprises a single crystalline semiconductor nanostructure integral to a crystallite of the non-single crystalline semiconductor layer. | 2008-09-04 |
| 20080210937 | Hetero-Crystalline Structure and Method of Making Same - A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth. | 2008-09-04 |
| 20080210938 | SEMICONDUCTOR DEVICE - A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure. | 2008-09-04 |
| 20080210939 | Method for Fabricating an Image Sensor Device with Reduced Pixel Cross-Talk - A method of fabricating an image sensor device ( | 2008-09-04 |
| 20080210940 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE THEREFOR - The invention relates to a thin film transistor substrate and a display device including the same, and provides a thin film transistor substrate and a display device including the same, which can prevent damage of elements due to static electricity by forming, in each unit pixel region where a pair of first and second pixel electrodes, a pair of first and second drain electrode plates that are connected to the first and second pixel electrodes and to connected to drain terminals of thin film transistors, and can obtain a dot inversion driving effect through line inversion driving by connecting the first drain electrode in one pixel region to the first drain electrode plate, connecting the second drain electrode in the one unit pixel region to the second drain electrode plate, connecting a first drain electrode in another unit pixel region neighboring the one unit pixel region to the second drain electrode plate, and connecting a second drain electrode in another unit pixel region to the first drain electrode plate. | 2008-09-04 |
| 20080210941 | Dispaly device - The present invention provides a display device which can obviate the occurrence of a leak current in a thin film transistor. In a display device including a substrate, and gate signal lines, an insulation film, semiconductor layers and conductor layers which are sequentially stacked on the substrate, the conductor layer forms at least a drain electrode which is connected to a drain signal line and a source electrode which is connected to a pixel electrode, and the semiconductor layer is formed in a pattern in which the semiconductor layer has a protruding portion which protrudes outwardly from the conductor layer at a portion thereof except for a distal end of the drain electrode as viewed in a plan view. | 2008-09-04 |
| 20080210942 | Array substrate for liquid crystal display device and method of fabricating the same - An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively. | 2008-09-04 |
| 20080210943 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode. | 2008-09-04 |
| 20080210944 | Ejecting method and ejecting apparatus - In an ink jet apparatus for manufacturing a color filter | 2008-09-04 |
| 20080210945 | Thin film transistor, manufacturing method thereof, and semiconductor device - By a laser crystallization method, a crystalline semiconductor film in which grain boundaries are all in one direction is provided as well as a manufacturing method thereof. In crystallizing a semiconductor film formed over a substrate with linear laser light, a phase-shift mask in which trenches are formed in a stripe form is used. The stripe-form trenches formed in the phase-shift mask are formed so as to make a nearly perpendicular angle with a major axis direction of the linear laser light. CW laser light is used as the laser light, and a scanning direction of the laser light is nearly parallel to a direction of the stripe-form trenches (grooves). By changing luminance of the laser light periodically in the major axis direction, a crystal nucleation position in a semiconductor that is completely melted can be controlled. | 2008-09-04 |
| 20080210946 | IMAGE DETECTOR AND RADIATION DETECTING SYSTEM - The invention provides an image detector capable of improving the quality of detected images by reducing electronic noise, the image detector comprising, a plurality of scan lines disposed in parallel, a plurality of data lines provided so as to cross with the scan lines, thin film transistors connected with the scan and data lines and provided in matrix, sensor sections connected to the thin film transistor and provided in a matrix and a plurality of common lines disposed so as to apply bias voltage commonly to the sensor sections provided in matrix. Each of the scan lines, data lines and common lines are formed by metal layers different from each other and provided with insulating film(s) disposed therebetween. | 2008-09-04 |
| 20080210947 | Solid-state imaging device - A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential. | 2008-09-04 |
| 20080210948 | High-Heat-Resistive Semiconductor Device - The outer surface of a wide-gap semiconductor device is coated with a synthetic polymer compound containing one or more silicon-containing polymer having a bridged structure formed by a siloxane (Si—O—Si bond structure). The synthetic polymer compound may include, for example, a silicon-containing polymer which has one or more reactive groups (A′) selected from Si—R | 2008-09-04 |
| 20080210949 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor substrate includes: an AlN layer provided on a silicon substrate; an AlGaN layer that is provided on the AlN layer and has an Al composition ratio of 0.3 to 0.6; and a GaN layer provided on the AlGaN layer. | 2008-09-04 |
| 20080210950 | Diamond-like carbon electronic devices and methods of manufacture - Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp | 2008-09-04 |
| 20080210951 | Method For Fabricating High-Quality Semiconductor Light-Emitting Devices On Silicon Substrates - One embodiment of the present invention provides a semiconductor light-emitting device which includes: (1) a silicon (Si) substrate; (2) a silver (Ag) transition layer which is formed on a surface of the Si substrate, wherein the Ag transition layer covers the Si substrate surface; and (3) an InGaAlN, ZnMgCdO, or ZnBeCdO-based semiconductor light-emitting structure which is fabricated on the Ag-coated Si substrate. Note that the Ag transition layer prevents the Si substrate surface from forming an amorphous overcoat with reactant gases used for growing the semiconductor light-emitting structure. | 2008-09-04 |
| 20080210952 | PHOTO INTERRUPTER, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT USING THE SAME - A photo interrupter has a lead frame assembly that has a lead frame having connector terminals for external connection, a light-emitting mold, a light-receiving mold, and a connector mold. The photo interrupter also has an outer case having a connection section. The connector terminals are adapted to be accommodated in the connector section when the lead frame assembly is accommodated in the outer case. At least one of the outer case or the connector mold is provided with a latching section for latching the connector mold to the outer case. Resin for forming the connector mold may be same as or different from light permeable resin for forming the light-emitting mold and the light-receiving mold. | 2008-09-04 |
| 20080210953 | Luminaire with a Plurality of Light-Emitting Diodes in Decentralized Arrangement - A luminaire with a plurality of light-emitting diodes in a decentralized arrangement. To improve the light emission pattern issued by the luminaire, the emission region defined by the light guide emission ends is smaller than the arrangement region defined by the totality of the light-emitting diodes. | 2008-09-04 |
| 20080210954 | Alternating Current Light Emitting Device - The present invention relates to a light emitting device in which light emitting cells of a first light emitting cell block are connected in parallel to light emitting cells of a second light emitting cell block corresponding thereto. A light emitting device of the present invention comprises a substrate, and first and second light emitting cell blocks formed on the substrate and having a plurality of light emitting cells electrically connected in series to one another, respectively. Each of the light emitting cells has an N-electrode and a P-electrode. A P-electrode at one end of the first light emitting cell block is connected to an N-electrode at one end of the second light emitting cell block, and an N-electrode at the other end of the first light emitting cell block is connected to a P-electrode at the other end of the second light emitting cell block. The P-electrode of each of the light emitting cells of the first light emitting cell block and the P-electrode of each of the light emitting cells of the second light emitting cell block corresponding thereto, or the N-electrode of each of the light emitting cells of the first light emitting cell block and the N-electrode of each of the light emitting cells of the second light emitting cell block corresponding thereto are electrically connected to each other. In the light emitting device of the present invention, the light emitting cells of the first light emitting cell block and the light emitting cells of the second light emitting cell block corresponding thereto are respectively connected in parallel so that a current can cross the light emitting cells of the first and second light emitting cell blocks. Thus, even though a leakage current occurs in some of light emitting cells, the current is allowed to cross light emitting cells connected in another direction, thereby preventing overload on some of the light emitting cells due to the leakage current and ensuring uniform light emission and prolonged life span in the AC light emitting device. | 2008-09-04 |
| 20080210955 | Group III-V semiconductor device and method for producing the same - An object of the invention is to prevent short circuit at a side surface of a semiconductor device in the method for producing semiconductor devices including a laser lift-off step. The production method of the invention includes forming, on a sapphire substrate, a group III nitride semiconductor layer containing a plurality of semiconductor devices isolated from one another by a groove which reaches the substrate; forming a protective film for preventing short circuit on the top surface and side surfaces of the semiconductor layer and on the top surface of the sapphire substrate; forming a resin layer in the groove; bonding the semiconductor layer to a support substrate via a low-melting-point metal layer; and removing the sapphire substrate through the laser lift-off process. The resin layer functions as a support for the protective film, to thereby prevent cracking or chipping of the protective film. As a result, current leakage or short circuit, which would otherwise be caused by cracking or chipping of the protective film, can be prevented. | 2008-09-04 |
| 20080210956 | Light Emitting Diode Employing an Array of Nanorods and Method of Fabricating the Same - Disclosed are a light emitting diode employing an array of nanorods and a method of fabricating the same. The light emitting diode comprises an array of semiconductor nanorods positioned on a substrate. An upper electrode layer is deposited on the array of the nanorods such that an empty space remains between adjacent ones of the nanorods. Since the space between adjacent ones of the nanorods is not filled with an insulating material, the light extraction efficiency of a light emitting diode can be improved and a method of fabricating the light emitting diode can be simplified. | 2008-09-04 |
| 20080210957 | LIGHT EMITTING DIODE, METHOD FOR MANUFACTURING LIGHT EMITTING DIODE, INTEGRATED LIGHT EMITTING DIODE, METHOD FOR MANUFACTURING INTEGRATED LIGHT EMITTING DIODE, LIGHT EMITTING DIODE BACKLIGHT, LIGHT EMITTING DIODE ILLUMINATION DEVICE, LIGHT EMITTING DIODE DISPLAY, ELECTRONIC APPARATUS, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - Disclosed herein is a light emitting diode includes: a first semiconductor layer of a first conductivity type; an active layer on the first semiconductor layer; a second semiconductor layer of a second conductivity type on the active layer; a first electrode configured to be electrically coupled to the first semiconductor layer; and a second electrode configured to be provided on the second semiconductor layer and be electrically coupled to the second semiconductor layer, the second electrode including a first metal film that has a predetermined shape and is composed mainly of silver and a second metal film that covers the first metal film and is composed mainly of palladium and/or platinum. | 2008-09-04 |
| 20080210958 | Semiconductor white light emitting device and method for manufacturing the same - A semiconductor white light emitting device including: a semiconductor light emitting element having green and blue light emitting layers containing In; and a phosphor capable of emitting red light. | 2008-09-04 |
| 20080210959 | Light emitting apparatus - In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 Ω·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface. | 2008-09-04 |
| 20080210960 | Display device - In one embodiment, a display device includes: a first electrode; a hole transfer layer which is formed on the first electrode, the hole transfer layer comprising a first host used as a hole transfer material and a first dopant used as an electron accepting material; an emitting material layer which is formed on the hole transfer layer, the emitting material layer comprising red, blue and green light material layers stacked in sequence; an electron transfer layer which is formed on the emitting material layer, the electron transfer layer comprising a second host used as an electron transfer material and a second dopant used as an electron donating material; and a second electrode which is formed on the electron transfer layer. | 2008-09-04 |
| 20080210961 | Light emitting device - A light emitting device includes: a die-mounting base having a mounting surface; a light emitting diode mounted on the mounting surface of the die-mounting base and having a top surface facing in a normal direction normal to the mounting surface of the die-mounting base; a first wavelength-converting layer of a first wavelength-converting material formed on the mounting surface of the die-mounting base, enclosing the light emitting diode, and having a top surface; and a second wavelength-converting layer of a second wavelength-converting material formed on the top surface of the first wavelength-converting layer and having a top surface that is aligned with the top surface of the light emitting diode in the normal direction, and that has an area smaller than the top surface of the first wavelength-converting layer and not smaller than the top surface of the light emitting diode. | 2008-09-04 |
| 20080210962 | Illumination Device - An illumination device is specified which comprises an optoelectronic component having a housing body and at least one semiconductor chip provided for generating radiation, and a separate optical element, which is provided for fixing at the optoelectronic component and has an optical axis, the optical element having a radiation exit area and the radiation exit area having a concavely curved partial region and a convexly curved partial region, which at least partly surrounds the concavely curved partial region at a distance from the optical axis, the optical axis running through the concavely curved partial region. | 2008-09-04 |
| 20080210963 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME - A light emitting diode package structure has a silicon substrate, a plurality of cup-structures on the silicon substrate, a plurality of conductive patterns disposed on the silicon substrate, one of a plurality of light emitting diodes respectively disposed on each cup-structure and a plurality of wires electrically connected to the light emitting diodes and the conductive patterns. The light emitting diodes are electrically connected in series through the conductive wires and the conductive patterns. | 2008-09-04 |
| 20080210964 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes: a base substrate which has a concave portion; a light-emitting element which is provided in the concave portion, and which emits light; a prevention member which is provided to the base substrate in a manner of covering a side surface of the concave portion, and which prevents the light emitted by the light-emitting element from being incident on the side surface of the concave portion; and a translucent member which is provided in the concave portion, and which seals the light-emitting element. | 2008-09-04 |
| 20080210965 | Light-emitting diode incorporation the packing nano particules with high refractive index - Light-emitting diode packages with very high light extraction efficiency are disclosed. The packages utilize the intrinsically optically transparent nano particles with high refractive index, by the correct way of homogeneous packing, or adding additional transparent substance in the interspaces among the nano particles furthermore, to form a nano light-extracting layer with high refractivity which contacts optically with the diode surface to extract the light. By this method, because the refractive index difference between the light-extracting layer and the diode crystal turns to be small, the critical internal total reflection angle of the light on the interface increases much, it means large reduction on the internal total reflection of the light. Then the light extraction efficiency of the package can be increased significantly. | 2008-09-04 |
| 20080210966 | Light Emitting Device - A light emitting device is configured to prevent leakage of light but can be reduced in thickness as compared with conventional devices, and can effectively prevent degradation in luminous flux (luminous flux drop). The light emitting device can include a light emitting element, an optically transparent sealing resin having a pair of faces opposed to each other with an axis of light emitting direction of the light emitting device interposed therebetween. The sealing resin can cover the light emitting element and be mixed with a wavelength converting material. A reflective film can be provided on at least one of the pair of opposed faces of the sealing resin. The reflective film can be a white coating containing a white pigment in a concentration of 23 wt % to 54 wt % and formed to be 14 μm to 50 μm in thickness. | 2008-09-04 |
| 20080210967 | LIGHT EMITTING DIODE AND METHOD FOR MAKING THE SAME - A light emitting diode includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a light-converting pattern of a phosphor material formed on the second semiconductor layer; and a reflective layer of a metallic material formed on the second semiconductor layer and enclosing the light-converting pattern. | 2008-09-04 |
| 20080210968 | LIGHT-EMITTING DIODE - A light-emitting diode includes: a light-transmitting substrate; a light-emitting element mounted on the upper surface of the light-transmitting substrate; and a light-transmitting resin that seals the light-emitting element. The outer surface of the light-transmitting resin is covered with a reflecting layer formed from a silver or aluminum thin film. The light emitted from the light-emitting element is reflected from the reflecting layer, and the reflected light is guided out from the lower surface of the light-transmitting substrate in an efficient manner with minimum wastage of light intensity, and thus, high luminance light can be emitted. | 2008-09-04 |
| 20080210969 | Fabrication of Semiconductor Devices for Light Emission - A semiconductor device for light emission having a plurality of epitaxial layers with an n-type layer for light emission and a p-type layer for light reflection. The p-type layer has at least one seed layer for an outer layer of a conductive metal. The at least at least one seed layer is a material for providing a buffer for differential thermal expansion of the outer layer and the light reflecting layer. | 2008-09-04 |
| 20080210970 | Fabrication of Conductive Metal Layer on Semiconductor Devices - A method for fabrication of a light emitting device on a substrate, the light emitting device having a wafer with multiple epitaxial layers and an ohmic contact layer on the epitaxial layers remote from the substrate. The method includes the steps: (a) applying to the ohmic contact layer a seed layer of a thermally conductive metal; (b) electroplating a relatively thick layer of the conductive metal on the seed layer; and (c) removing the substrate. A corresponding light emitting device is also disclosed. The light emitting device is a GaN light emitting diode or laser diode. | 2008-09-04 |
| 20080210971 | NICKEL TIN BONDING SYSTEM WITH BARRIER LAYER FOR SEMICONDUCTOR WAFERS AND DEVICES - A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer. | 2008-09-04 |
| 20080210972 | Nitride-based semiconductor light emitting diode - Provided is a nitride-based semiconductor LED including a substrate; a first conductive-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the first conductive-type nitride semiconductor layer; a second conductive-type nitride semiconductor layer formed on the active layer; a transparent electrode formed on the second conductive-type nitride semiconductor layer; a second conductive-type electrode pad formed on the transparent electrode; a plurality of second conductive-type electrodes extending from the second conductive-type electrode pad in one direction so as to be formed in a line; a first conductive-type electrode pad formed on the first conductive-type nitride semiconductor layer, where the active layer is not formed, so as to be positioned on the same side as the second conductive-type electrode pad; and a plurality of first conductive-type electrodes extending from the first conductive-type electrode pad in one direction so as to be formed in a line. | 2008-09-04 |
| 20080210973 | ZINC-OXIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - The invention discloses a zinc-oxide-based semiconductor light-emitting device and the fabrication thereof The method according to the invention, first, is to prepare a substrate. Next, by an atomic-layer-deposition-based process, a ZnO-based multi-layer structure is formed on or over the substrate where the ZnO-based multi-layer structure includes a light-emitting region. | 2008-09-04 |
| 20080210974 | High voltage LDMOS - A power semiconductor device having high avalanche capability comprises an N | 2008-09-04 |
| 20080210975 | METHOD OF FABRICATING HETEROEPITAXIAL MICROSTRUCTURES - An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method. | 2008-09-04 |
| 20080210976 | Semiconductor Device Having an Implanted Precipitate Region and a Method of Manufacture Therefor - The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device | 2008-09-04 |
| 20080210977 | Semiconductor device having a support substrate partially having metal part extending across its thickness - A semiconductor device includes a support substrate and a semiconductor layer formed on the underlying substrate. The support substrate has its metal part formed by plating and extending across its entire thickness, whilst it has the other region made of semiconductor part. In particular, the region of the support substrate lying immediately below an active region is the metal part formed by plating. The region of the support substrate lying immediately below the region other than the active region is an inactive region made of semiconductor. The semiconductor device thus suppresses warping of a substrate otherwise caused by stress in the metal part formed by plating, and heat evolved due to the current in operation of the semiconductor device may be dissipated over the shortest path through the metal part having a higher thermal conductivity. | 2008-09-04 |
| 20080210978 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts. | 2008-09-04 |
| 20080210979 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DESIGNING THE SAME - A semiconductor integrated circuit, including: a semiconductor chip; an internal integrated circuit area formed at a center side of the semiconductor chip; and an I/O area formed at a peripheral side of the semiconductor chip except where the internal integrated circuit area exists, the I/O area having a first power supply cell placed at a predetermined position therein. In a case in which an empty area adjacent to the first power supply cell exists, a second power supply cell is inserted therein and the first power supply cell and the second power supply cell are electrically connected with each other by a first wiring pattern added. | 2008-09-04 |
| 20080210980 | Isolated CMOS transistors - Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 2008-09-04 |
| 20080210981 | Integrated Circuit Having Gates and Active Regions Forming a Regular Grating - A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same. | 2008-09-04 |
| 20080210982 | Image Sensor and Method for Manufacturing the Same - An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer. | 2008-09-04 |
| 20080210983 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device including: a plurality of photodiode parts ( | 2008-09-04 |
| 20080210984 | Solid-state image capturing device and electronic information device - A device separation insulating film and a device separation semiconductor layer are provided for a device separation section for separating adjacent devices from each other, end portions of the device separation insulating film and end portions of the device separation semiconductor layer are provided to overlap each other in order to surround two sides of an outer-periphery of the voltage conversion section and also to surround a channel section of the charge transfer device and the light receiving devices and an end portion of the device separation insulating film facing an end face of the light receiving device is arranged inwardly below a control electrode with respect to an end face of the control electrode on the light receiving device side. | 2008-09-04 |
| 20080210985 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - A solid-state imaging device, includes: a substrate where a region of a first conductivity type is formed on at least a portion of a surface thereof; a region of a second conductivity type formed on at least a portion of a surface of the region of the first conductivity type; a multilayer wiring layer formed on the substrate; and a layer of the second conductivity type formed directly above the region of the second conductivity type in the multilayer wiring layer, connected to the region of the second conductivity type. A concentration of impurities in the layer of the second conductivity type is lower with decreasing proximity to the region of the second conductivity type. | 2008-09-04 |
| 20080210986 | Global shutter pixel with charge storage region - An imaging method, apparatus, and system having pixels that store charge from a photosensor in a storage diode are disclosed. Charge accumulated in the photosensor during an integration period is transferred to and stored in the storage diode prior to readout in a global shutter imager. | 2008-09-04 |
| 20080210987 | Array of Fet Transistors Having a Nanotube or Nanowire Semiconductor Element and Corresponding Electronic Device, For the Detection of Analytes - In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each end, a junction J | 2008-09-04 |
| 20080210988 | Insulated-gate field effect transistor - In a heterostructure field effect transistor (MISHFET), a source ohmic electrode | 2008-09-04 |
| 20080210989 | SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type semiconductor layer made of a compound semiconductor provided on a substrate, a compound semiconductor layer provided on the p-type semiconductor layer, active regions that are provided on the compound semiconductor layer and are adjacent to each other across an isolation region, a connecting portion that is connected to the p-type semiconductor layer in the isolation region located between the active regions or a region adjacent to another region between the active regions, and FETs respectively provided in the active regions adjacent to each other, a source electrode of at least one of the FETs being connected to a potential of the connecting portion in a region other than the active regions. | 2008-09-04 |
| 20080210990 | CMOS IMAGE SENSOR AND FABRICATING METHOD THEREOF - A CMOS image sensor and fabricating method thereof by which capacitance of a floating diffusion region (FD) can be increased. The CMOS image sensor can include an epitaxial layer formed over a semiconductor substrate; a gate electrode formed over the epitaxial layer; a gate metal formed over a floating diffusion region of the epitaxial layer; n+ type source and drain regions formed in the epitaxial layer; a gate spacer formed on both sidewalls of the gate electrode and both sidewalls of the gate metal; an insulating interlayer formed over the epitaxial layer including the gate electrode, the gate spacer and the gate metal layer, the insulating interlayer including a first contact hole extending through the insulating interlayer exposing the source region; a second contact hole extending through the insulating interlayer exposing the gate metal; a first contact plug formed in the first contact hole and connected to the source region; a second contact plug formed in the second contact hole and connected to the gate metal; and a metal line formed over the first contact plug and the second contact plug to electrically connect the source region to the gate metal. | 2008-09-04 |
| 20080210991 | CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING - A CMOS image sensor capable of preventing leakage current of a transfer transistor and a method of manufacturing thereof are disclosed. Embodiments relate to a complementary metal-oxide-silicon (CMOS) image sensor including a transfer transistor. The transfer transistor includes an epi-layer formed over a semiconductor substrate defined by a photodiode area, an active area, and a device isolation area. A device isolation film may be formed in the device isolation area. A gate electrode may be formed over the epi-layer for the transfer transistor with a gate insulating film interposed therebetween. A first dopant diffusion area may be formed by implanting first dopant ions into the epi-layer of the photodiode area. A potential well area may be formed in the first dopant diffusion area adjacent to the gate electrode. A second dopant diffusion area may be formed by implanting second dopant ions into the epi-layer of a side-surface floating diffusion area of a gate spacer. | 2008-09-04 |
| 20080210992 | CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A CMOS image sensor that can include a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer; a poly gate contacting the first shallow trench isolation layer and the second shallow trench isolation layer and formed over the predetermined region of the epitaxial layer; and a plurality of channels formed in the epitaxial layer and under the poly gate. | 2008-09-04 |
| 20080210993 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD - The invention provides a solid-state image pickup device and method for realizing a higher sensitivity and a higher S/N ratio especially in the low-luminance region while maintaining a wide dynamic range. Plural pixels are integrated in an array configuration on a semiconductor substrate with each pixel having photodiode PD, which receives light and generates and stores photoelectric charge, transfer transistor Tr | 2008-09-04 |
| 20080210994 | Solid-state imaging devices - A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from the photoelectric transducer; a transfer and retention unit that is provided between the photoelectric transducer and the floating diffusion for a purpose of controlling a transfer of the light-generated charge and has a charge-retaining region that can retain the light-generated charge generated from the photoelectric transducer; a reset unit that initializes a potential of the floating diffusion; an amplifying transistor that generates an output based on a potential of the floating diffusion; a selection transistor that selectively outputs an output of the amplifying transistor; and an excessive charge-discharging unit that discharges excessive electric charge generated from the photoelectric transducer. | 2008-09-04 |
| 20080210995 | Image sensor and method for fabricating the same - An image sensor and a method for fabricating the same are disclosed, in which an impurity implantation layer having a predetermined thickness is formed on a source diffusion layer, thereby controlling a substantial contact point between a contact plug and the source diffusion layer upward from a surface of a semiconductor substrate. As a result, it is possible to minimize a length of an open hole, which is a main channel of the contact plug, so that the open hole has the sufficiently large size, thereby inducing the improvement of the contact quality between the contact plug and the source diffusion layer. Also, in case of the CMOS image sensor, in state the impurity implantation layer having the impurity selectively implanted is formed on the source diffusion layer, the impurity implantation layer is electrically connected with the source diffusion layer. Accordingly, without the additional process such as highly-impurity implantation and formation of salicide layer, it is possible for the source diffusion layer to increase the impurity concentration of impurity therein. Eventually, in case of realizing the image sensor according to the present invention, it is possible to the greatest contact quality between the contact plug and the source diffusion layer. In case of realizing the greatest contact quality between the contact plug and the source diffusion layer with the additional formation of the impurity implantation layer, for example, the source diffusion layer normally performs the function of converting the optical charges generated by the photodiode to voltage constituents. Thus, the completed image sensor according to the present invention realizes the great image quality. | 2008-09-04 |
| 20080210996 | Frame shutter pixel with an isolated storage node - A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion. | 2008-09-04 |
| 20080210997 | Solid-state image pickup device and manufacturing method thereof - A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region | 2008-09-04 |
| 20080210998 | Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof - Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma. | 2008-09-04 |
| 20080210999 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface. | 2008-09-04 |
| 20080211000 | Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof - A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co and Ti; A is silicon and/or germanium; 0| 2008-09-04 | |
| 20080211001 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode of MIS•FET constituting the main circuit. In the main circuit region, an insulating film made of a silicon nitride film is formed to cover the gate electrode, whereby miniaturization of elements in the main circuit region is not impaired. The memory cell array has no such insulating film. This means that the upper surface of the floating gate electrode is not contiguous to the insulating film but is covered directly with an interlayer insulating film. According to such a constitution, leakage of electrons from the floating gate electrode of the memory cell array can be suppressed or prevented and the flash memory thus obtained has improved data retention characteristics. | 2008-09-04 |
| 20080211002 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device includes: a first cylinder interlayer insulating film; a second cylinder interlayer insulating film; a cylinder hole including a first cylinder hole and a second cylinder hole communicating with the first cylinder hole; and a capacitor including a lower electrode and an upper electrode. The first cylinder interlayer insulating film has an etching rate for etchant, which is two to six times as high as an etching rate for the second cylinder interlayer insulating film, a hole diameter of the first cylinder hole is larger than that of the second cylinder hole, and the hole diameter of the second cylinder hole near an interface between the first cylinder interlayer insulating film and the second cylinder interlayer insulating film increases as the second cylinder hole approaches the interface. | 2008-09-04 |
| 20080211003 | Capacitor in semiconductor device and method of manufacturing the same - The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formation of an alumina (Al | 2008-09-04 |
| 20080211004 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer. | 2008-09-04 |
| 20080211005 | SEMICONDUCTOR DEVICE - There is provided a MOSFET-type semiconductor device having a coating insulating film formed to cover the surface portions of MOS transistors formed on a semiconductor substrate. The insulating film is formed of a silicon nitride film or silicon oxynitride film and the ratio (N—H/Si—H) of the density of N—H bonds to the density of Si—H bonds in the insulating film is set to 3 or less. | 2008-09-04 |
| 20080211006 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory including a semiconductor substrate having an upper surface; a plurality of memory cell transistors formed in the semiconductor substrate, each memory cell transistor including a gate electrode having a gate insulating layer on the upper surface of the semiconductor substrate, a floating gate electrode layer on the gate insulating layer, an inter-gate insulating layer on the floating gate electrode layer, and a control gate electrode layer on the inter-gate insulating layer; a first oxide-based insulating film formed above the upper surface of the semiconductor substrate between the gate electrodes, and including an upper surface as high or higher than that of the floating gate electrode layer but lower than that of the control gate electrode layer; a nitride-based insulating film containing boron formed on the first oxide-based insulating film and the control gate layer; and a second oxide-based insulating film formed on the nitride-based insulating film. | 2008-09-04 |
| 20080211007 | Self-Aligned Trenches With Grown Dielectric For High Coupling Ratio In Semiconductor Devices - Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into the substrate to provide an oxide of greater width and depth than the trench. Storage elements for a NAND type flash memory system, for example, can be fabricated by etching the substrate to form the trench after or as part of etching to form NAND string active areas. This can ensure alignment of the NAND string active areas between isolation trenches. Because the dielectric growth process is self-limiting, an open area resulting from the etching process can be maintained between the active areas. A subsequently formed inter-gate dielectric layer and control gate layer can fill the open area to provide sidewall coupling between control gates and floating gates. | 2008-09-04 |
| 20080211008 | MANUFACTURING METHOD OF FLASH MEMORY DEVICE - Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A spacer layer may be formed as a compound insulating layer structure over the side wall of the gate pattern. A source/drain area may be formed over the semiconductor substrate at both sides of the control gate. An insulating layer located at the outermost of the spacer layer may be removed. A contact hole may be formed between the gate patterns by forming and patterning the interlayer insulating layer. A contact plug may be formed in the contact hole. | 2008-09-04 |
| 20080211009 | Process for manufacturing an electronic device integrated on semiconductor substrate comprising non volatile floating gate memories and an associated circuitry and corresponding electronic device - An embodiment of a process is described for manufacturing a non volatile memory electronic device integrated on a semiconductor substrate which comprises a matrix of non volatile memory cells, the memory cells being organized in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors and low voltage transistors, the process comprising the steps for realizing:
| 2008-09-04 |
| 20080211010 | Semiconductor device - A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G | 2008-09-04 |
| 20080211011 | NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - It is made possible to provide a nonvolatile semiconductor memory element that can be miniaturized and can store multi-level data. A nonvolatile semiconductor memory element includes a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; and a gate structure formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region. The gate structure includes a tunnel insulating layer, a resistance variable layer formed above the tunnel insulating layer and made of a metal oxide, and a first electrode formed on the resistance variable layer. | 2008-09-04 |
| 20080211012 | Structure and Method for Forming Accumulation-mode Field Effect Transistor with Improved Current Capability - An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions. | 2008-09-04 |
