36th week of 2015 patent applcation highlights part 36 |
Patent application number | Title | Published |
20150249061 | INTERPOSER PACKAGE-ON-PACKAGE STRUCTURE - An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members. | 2015-09-03 |
20150249062 | Reflow Process and Tool - Reflow processes and apparatuses are disclosed. A process includes enclosing a package workpiece in an enclosed environment of a chamber of a reflow tool; causing an oxygen content of the enclosed environment of the chamber to be less than 40 ppm; and performing a reflow process in the enclosed environment of the chamber while the oxygen content is less than 40 ppm. An apparatus includes a reflow chamber, a door to the reflow chamber, an energy source in the reflow chamber, and gas supply equipment coupled to the chamber. The door is operable to enclose an environment in the reflow chamber. The energy source is operable to increase a temperature in the environment in the reflow chamber. The gas supply equipment is operable to provide a gas to the reflow chamber. | 2015-09-03 |
20150249063 | WIRE-BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a wire-bonding apparatus ( | 2015-09-03 |
20150249064 | PREVENTION OF WARPING DURING HANDLING OF CHIP-ON-WAFER - To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased. | 2015-09-03 |
20150249065 | Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers - A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate. | 2015-09-03 |
20150249066 | METHOD OF FORMING PACKAGE ASSEMBLY - A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer. | 2015-09-03 |
20150249067 | Semiconductor Device Having Multiple Chips Mounted to a Carrier - A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier. | 2015-09-03 |
20150249068 | CHIP PACKAGE STRUCTURE - In one embodiment, a chip package structure can include: (i) a substrate; (ii) a top chip including a plurality of vias arranged through the top chip to form electrical connections between an active surface of the top chip and a back surface of the top chip; (iii) a redistribution layer arranged on the back surface of the top chip; and (iv) a plurality of wire bonds that form electrical connections between the substrate and electrodes on the redistribution layer on the back surface of the top chip. | 2015-09-03 |
20150249069 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - Provided is a low cost and high resolution display device having light-emitting elements. An LED element is provided in a region between a first substrate and a second substrate, the region being an intersection region where a first electrode and a second electrode intersect each other in a plan view, and the LED element is provided with a first element electrode connected to the first electrode and provided on a bottom surface, and a second element electrode connected to a second electrode and provided on a top surface. | 2015-09-03 |
20150249070 | Optoelectronic Semiconductor Component and Method for Producing Said Component - An optoelectronic semiconductor component and a method for making an optoelectronic semiconductor component are disclosed. In an embodiment the component includes a carrier including at least one conversion-medium body and a potting body, the potting body surrounding the conversion-medium body at least in places, as seen in plan view, electrical contact structures fitted at least indirectly to the carrier and a plurality of optoelectronic semiconductor chips fitted to a main face of the carrier, the optoelectronic semiconductor chips configured to generate radiation, wherein the conversion-medium body is shaped as a plate, wherein the semiconductor chips are directly mechanically connected to the conversion-medium body, and wherein the conversion-medium body is free of cutouts for the electrical contact structures and is not penetrated by the electrical contact structure. | 2015-09-03 |
20150249071 | METHOD AND APPARATUS FOR PROVIDING HIGH-TEMPERATURE MULTI-LAYER OPTICS - A solid-state light-emitting device (“SLD”) converting electrical energy to photon energy using a light emitter diode (“LED”) and high-temperature multi-layer optics (“HMO”) is disclosed. The SLD, in one aspect, includes a chip-on-board (“COB”), a silicone inner layer (“SIL”), and a Poly methyl methacrylate (“PMMA”) layer. The COB includes a first surface and a second surface wherein the first surface includes at least one LED. The LED converts electrical energy to optical light and the light subsequently leaves the LED becoming visible light. The SIL includes a first silicone surface and a second silicone surface wherein the second silicone surface is in contact with the first surface of COB and the second silicone surface is in contact with the PMMA layer. The operating temperature of PMMA layer is lower than the operating temperature of SIL. | 2015-09-03 |
20150249072 | Optoelectronic Component and Method for Producing an Optoelectronic Component - An optoelectronic component includes an electrically insulating connection carrier constructed in a multipartite fashion. The connection carrier has at least one ceramic layer and a silicon layer. The silicon layer has an electrically conductive layer on the top side of the silicon layer facing away from the ceramic layer. A light-emitting diode is electrically conductively and mechanically connected to the connection carrier via the electrically conductive layer. A method for producing an optoelectronic component is furthermore specified. | 2015-09-03 |
20150249073 | Optoelectronic Semiconductor Apparatus and Carrier Assembly - A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with an optoelectronic device and a further device, wherein the optoelectronic device and the further device are interconnected to one another in parallel when the semiconductor apparatus is in operation, wherein the optoelectronic device is connected to a first contact and a second contact, the first contact and the second contact being configured to externally contact the semiconductor apparatus, and wherein the further device is connected with at least one further contact of the semiconductor apparatus. | 2015-09-03 |
20150249074 | LIGHT EMITTING DEVICE PACKAGE - Embodiments provide a light emitting device package including a package body having a top-opened cavity disposed in at least a portion thereof, a first electrode layer and a second electrode layer electrically isolated from the package body with an insulating layer interposed therebetween, the first electrode layer and the second electrode layer being electrically isolated from each other at a bottom surface of the cavity, a light emitting device placed on the bottom surface of the cavity configured to emit light through the open region of the cavity, and a sensor placed on at least a portion of the package body at the outside of the cavity configured to measure output of the light emitting device. | 2015-09-03 |
20150249075 | SEMICONDUCTOR CHIPS HAVING A DUAL-LAYERED STRUCTURE, PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR CHIPS AND THE PACKAGES - Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided. | 2015-09-03 |
20150249076 | HIGH PERFORMANCE STANDARD CELL - A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage. | 2015-09-03 |
20150249077 | SEMICONDUCTOR DEVICE - A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process. | 2015-09-03 |
20150249078 | INTEGRATED CIRCUIT HAVING AN ESD PROTECTION STRUCTURE AND PHOTON SOURCE - An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than −10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons. | 2015-09-03 |
20150249079 | SEMICONDUCTOR INTEGRATED CIRCUIT - An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET designed so as to withstand ESD. A second protection element includes a second transistor configured as a P-channel MOSFET designed so as to withstand ESD. A capacitance element is connected to a second line, and forms an RC filter together with a filter resistor. The capacitance element includes at least one from among a third transistor having the same device structure as that of the first transistor and a fourth transistor having the same device structure as that of the second transistor. | 2015-09-03 |
20150249080 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION - An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor. | 2015-09-03 |
20150249081 | DIRECTIONAL FINFET CAPACITOR STRUCTURES - A method for fabricating a capacitor within a FinFET device includes patterning a first gate interconnect material having a first recess. The method also includes patterning a first trench interconnect material coupled to the first gate interconnect material at the first recess to form a first plate of a FinFET capacitive structure. | 2015-09-03 |
20150249082 | Field-Effect Semiconductor Device - According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region. | 2015-09-03 |
20150249083 | A SEMICONDUCTOR DEVICE COMPRISING AN DIODE REGION AND AN IGBT REGION - A technology for inhibiting gate interference in an RC-IGBT employing a diode structure having Schottky connections is provided. A semiconductor device includes a semiconductor substrate including a diode region and an IGBT region. In this semiconductor device, the diode region includes: a p-type anode region connected to an anode electrode by an Ohmic contact; a plurality of n-type pillar regions connected to the anode electrode by Schottky contacts; an n-type barrier region; an n-type diode drift region; and an n-type cathode region. An on-resistance of a first pillar region with respect to the anode electrode is higher than an on-resistance of a second pillar region with respect to the anode electrode. The second pillar region is located at a position close to the IGBT region. | 2015-09-03 |
20150249084 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor device includes: forming an oxide film | 2015-09-03 |
20150249085 | HIGH SPEED BIPOLAR JUNCTION TRANSISTOR FOR HIGH VOLTAGE APPLICATIONS - High speed bipolar junction transistor switches for high voltage operations. An example switch includes a bipolar junction transistor including a collector region positioned over a buried insulator region. The collector region includes dopants of a first conductivity type. A field effect transistor includes a source region also positioned over a buried insulator region. The source region electrically is coupled to the collector region such that all current passing the collector region enters the source region. | 2015-09-03 |
20150249086 | THIRD TYPE OF METAL GATE STACK FOR CMOS DEVICES - A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. | 2015-09-03 |
20150249087 | SEMICONDUCTOR FIN DEVICES AND METHOD OF FARICATING THE SEMICONDUCTOR FIN DEVICES - A semiconductor device includes a substrate, an insulating layer disposed on the substrate and having a trench exposing a surface portion of the substrate, and a channel-forming structure comprising crystalline semiconductor material. The channel-forming structure has a lower portion located in the trench and fins extending upright on the lower portion, where the fins are spaced from each other and are each narrower than an opening of the trench, and the lower portion of the channel forming structure has a higher crystal defect density than the fins of the channel forming structure. | 2015-09-03 |
20150249088 | LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 2015-09-03 |
20150249089 | Memory Cells and Methods Of Forming Memory Cells - A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed. | 2015-09-03 |
20150249090 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a TaN layer provided on the first insulating layer and containing tantalum and nitrogen, a TaSiN layer provided on the TaN layer in contact with the TaN layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the TaSiN layer in contact with the TaSiN layer and containing oxygen, and a control electrode provided on the second insulating layer. | 2015-09-03 |
20150249091 | NVM LAYOUT - A memory device can include an array of NOR memory cells, each memory cell including a floating gate, a source on a source side of the floating gate, a drain on a drain side of the floating gate, a drain contact on the drain, and a source contact on the source. The source contacts are connected to a common source line. A plurality of bit lines are connected to respective drains in a column of the memory cells. A plurality of word lines, each word line coupled to respective floating gates in a row of the memory cells. Spacing between the word lines on the drain side is greater than spacing between the word lines on the source side. | 2015-09-03 |
20150249092 | MEMORY ARRAYS WITH A MEMORY CELL ADJACENT TO A SMALLER SIZE OF A PILLAR HAVING A GREATER CHANNEL LENGTH THAN A MEMORY CELL ADJACENT TO A LARGER SIZE OF THE PILLAR AND METHODS - The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size. | 2015-09-03 |
20150249093 | SEMICONDUCTOR DEVICES - Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer. | 2015-09-03 |
20150249094 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body. | 2015-09-03 |
20150249095 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode. | 2015-09-03 |
20150249096 | THREE DIMENSION INTEGRATED CIRCUITS EMPLOYING THIN FILM TRANSISTORS - An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage. | 2015-09-03 |
20150249097 | ARRAY SUBSTRATE, DISPLAY DEVICE AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE - An array substrate, a display device comprising the array substrate and a method of manufacturing the array substrate are provided. The array substrate include a substrate ( | 2015-09-03 |
20150249098 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY APPARATUS - An array substrate is disclosed. The array substrate comprises a substrate, a plurality of common electrodes formed on the substrate, a plurality of gate signal lines formed above the common electrodes, and a plurality of common electrode signal line units corresponding to the plurality of common electrodes, respectively. The plurality of common electrode signal line units are formed on the corresponding common electrodes, respectively. Each of the common electrode signal line units comprises a first common electrode signal line perpendicular to the gate signal line and a second common electrode signal line parallel to the gate signal line. The first and second common electrode signal lines are made of metal and cross with each other and are electrically connected to each other. Two adjacent common electrode signal line units are electrically connected by a bridge line. The present disclosure also relates to a method for manufacturing the array substrate and a display apparatus. | 2015-09-03 |
20150249099 | Semiconductor Device - A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included. | 2015-09-03 |
20150249100 | Method To Form Group III-V And Si/Ge FINFET On Insulator And Integrated Circuit Fabricated Using The Method - A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed. | 2015-09-03 |
20150249101 | PIXEL CELL, METHOD FOR MANUFACTURING THE SAME AND IMAGE SENSOR COMPRISING THE SAME - A pixel cell, a method for manufacturing the same and an image sensor including the same are provided. The pixel cell includes: a substrate; a photodiode, a pass transistor and a floating diffusion structure respectively formed on the substrate, in which the pass transistor is formed between the photodiode and the floating diffusion structure; and a PINNED structure, formed on the substrate and connected with the floating diffusion structure, in which a reset voltage of the floating diffusion structure is higher than a depletion voltage of the PINNED structure. | 2015-09-03 |
20150249102 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate. The pad electrode is arranged at a position overlapping the mark-like appearance part. The coupling part couples the pad electrode and mark-like appearance part. At least a part of the pad electrode on the other main surface side of the substrate is exposed through an opening reaching the pad electrode from the other main surface side of the substrate. The mark-like appearance part and coupling part are arranged to at least partially surround the outer circumference of the opening in plan view. | 2015-09-03 |
20150249103 | SOLID-STATE IMAGE SENSING DEVICE AND METHOD OF MANUFACTURING THE SAME - By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other. | 2015-09-03 |
20150249104 | IMAGE SENSOR DEVICE - An image sensor and image sensor device include: a lighting portion extending in a main scanning direction and emitting light to the object-to-be-read; a rod lens array for imaging light from the object-to-be-read; and a light receiving portion for converting the light imaged by the rod lens array to an electric signal. The lighting portion emits a normally directed light from the normal direction of the object-to-be-read to irradiate a first irradiation region of the object-to-be-read, and an inclined light inclined by a predetermined angle from the normal direction of the object-to-be-read to irradiate a second irradiation region being apart from the first irradiation region in a sub-scanning direction. | 2015-09-03 |
20150249105 | IMAGING SYSTEMS WITH FLIP CHIP BALL GRID ARRAYS - An imaging system may include an integrated circuit package that includes an image sensor die mounted in a flip chip configuration to a package substrate. The image sensor die may be a backside illumination sensor die. The image sensor die may include an imaging device structure formed over a carrier layer. Through-silicon vias formed in the carrier layer may couple imaging device circuitry in the imaging device structure to conductive bumps on the carrier layer that are coupled to metal interconnects. A ball grid array may be formed on a surface of the package substrate that may be coupled to the conductive bumps. A glass lid may be attached to the image sensor die using attachment structures such that an air gap is formed between the glass lid and the image sensor die. Package sealing material may be deposited between the image sensor die and the package substrate. | 2015-09-03 |
20150249106 | PHOTOELECTRIC CONVERSION APPARATUS, MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION APPARATUS, AND ELECTRONIC DEVICE - A photoelectric conversion apparatus includes a TFT | 2015-09-03 |
20150249107 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - Disclosed is a semiconductor device including a first semiconductor substrate and a first atom diffusion prevention portion, the first atom diffusion prevention portion being arranged at a part on the first semiconductor substrate and configured to prevent diffusion of an atom having a dangling bond terminating effect. | 2015-09-03 |
20150249108 | ARRAY-TYPE LIGHT-RECEIVING DEVICE - An array-type light-receiving device includes a substrate including a main surface, a rear surface, and a plurality of recesses formed in the rear surface, the rear surface including an incident plane on which incident light is received; a stacked semiconductor layer disposed on the main surface of the substrate, the stacked semiconductor layer including a light-receiving layer; and a plurality of pixel regions each of which includes the light-receiving layer. The plurality of recesses are each depressed from the rear surface in a thickness direction of the substrate. In addition, each of the plurality of recesses has a bottom surface and a side surface, the bottom surface facing at least one of the plurality of pixel regions, the side surface including a tapered region inclined at a predetermined inclination angle with respect to an in-plane direction of the main surface. | 2015-09-03 |
20150249109 | METHOD OF FABRICATING A METAL GRID FOR SEMICONDUCTOR DEVICE - A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench. | 2015-09-03 |
20150249110 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer which is formed over a substrate; a contact plug which is coupled with the substrate by passing through the inter-layer dielectric layer and has a protruding portion over the inter-layer dielectric layer; a first variable resistance pattern which is formed over the contact plug; and a protective layer which covers the first variable resistance pattern and a portion of sidewalls of the contact plug in such a manner that the sidewalls of the contact plug are exposed. | 2015-09-03 |
20150249111 | ELECTRONIC DEVICE - An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction. | 2015-09-03 |
20150249112 | Vertical Thin Film Transistors In Non-Volatile Storage Systems - Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches that are filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The hard mask permits the base thickness to be defined by the deposition thickness, rather than an uncontrolled etch back. | 2015-09-03 |
20150249113 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell that is disposed at a position where the first and second wirings cross so as to be interposed between the first and second wirings. The memory cell includes a variable resistive layer and a tunnel barrier layer that is formed of an insulating film provided in contact with the variable resistive layer. The tunnel barrier layer is provided close to the first wiring to which a positive voltage with applied during set operation changing the variable resistive layer to a low-resistance state from a high-resistance state. | 2015-09-03 |
20150249114 | ORGANIC LIGHT EMITTING DISPLAY AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an organic light emitting display that has a configuration excluding a polarizing plate and exhibits improved flexibility and visibility, and a method for manufacturing the same, the organic light emitting display includes a touch electrode array facing the organic light emitting diode on the second buffer layer, the touch electrode array including first and second touch electrodes intersecting each other and an exterior light shielding layer including at least a color filter layer, an adhesive layer formed between the organic light emitting diode and the touch electrode array. | 2015-09-03 |
20150249115 | ORGANIC ELECTROLUMINESCENCE ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An organic electroluminescence array substrate, a manufacturing method thereof and a display device are provided, and the organic electroluminescence array substrate an active backplane and a color display layer formed on the active backplane, wherein the color display layer includes a plurality of pixel units; and each pixel unit includes a red sub-pixel, a green sub-pixel and a blue sub-pixel. Both an area of the red sub-pixel and an area of the green sub-pixel are less than an area of the blue sub-pixel. The organic electroluminescence array substrate has increased aperture ratio thereof. | 2015-09-03 |
20150249116 | Light-Emitting Module, Light-Emitting Panel, and Lighting Device - An object is to provide a light-emitting module in which a light-emitting element suffering a short-circuit failure does not cause wasteful electric power consumption. Another object is to provide a light-emitting panel in which a light-emitting element suffering a short-circuit failure does not allow the reliability of an adjacent light-emitting element to lower. Focusing on heat generated by a light-emitting element suffering a short-circuit failure, provided is a structure in which electric power is supplied to a light-emitting element through a positive temperature coefficient thermistor (PTC thermistor) thermally coupled with the light-emitting element. | 2015-09-03 |
20150249117 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a bank including a lower layer and an upper layer on the first electrode, the lower layer disposed on edges of the first electrode and having a first width and a first thickness, the upper layer disposed on the lower layer and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the lower layer; and a second electrode on the organic emitting layer and covering an entire surface of the display region. | 2015-09-03 |
20150249118 | ORGANIC LIGHT EMITTING DISPLAY - A method of making a display device includes forming first electrodes of organic light emitting diodes in respective pixel areas on a substrate, forming a first common layer on the first electrodes in the pixel areas, forming emission layers in the pixel areas on the first common layer, forming a second electrode of the organic light emitting diodes on the emission layer, and applying physical pressure to divide the first common layer. | 2015-09-03 |
20150249119 | ORGANIC LIGHT-EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display and a method of manufacturing an organic light-emitting display are described. According to an aspect, the organic light-emitting display includes a substrate, a photodiode on the substrate, a planarization layer covering the photodiode, a first electrode on the planarization layer, a pixel defining layer at least partially exposing the first electrode, an organic layer covering the first electrode which is exposed by the pixel defining layer and a second electrode covering the pixel defining layer and the organic layer. | 2015-09-03 |
20150249120 | OLED ARRAY SUBSTRATE, MANUFACTURING METHOD AND DISPLAY DEVICE THEREOF - An OLED array substrate and a manufacturing method thereof, and a display device provided with the OLED array substrate are disclosed. The OLED array substrate includes a plurality of thin film transistors ( | 2015-09-03 |
20150249121 | INDUCTOR STRUCTURE WITH MAGNETIC MATERIAL AND METHOD FOR FORMING THE SAME - The mechanisms for forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure also includes a first metal layer formed in the first dielectric layer and a magnetic layer formed over the first dielectric layer, and the magnetic layer has edges more than four in a cross section view. | 2015-09-03 |
20150249122 | Aluminum Nitride Substrate and Group-III Nitride Laminate - A substrate includes aluminum nitride, wherein the aluminum nitride substrate has on at least a surface thereof an aluminum nitride single-crystal layer having as a principal plane a plane that is inclined 0.05° to 0.40° in the m-axis direction from the (0001) plane of a wurzite structure. | 2015-09-03 |
20150249123 | OXIDE SEMICONDUCTOR FILM, TRANSISTOR, AND SEMICONDUCTOR DEVICE - To provide an oxide semiconductor film which has high stability and does not easily cause variation in electric characteristics of a transistor, a transistor including the oxide semiconductor film in its channel formation region, and a highly reliable semiconductor device including the transistor. The oxide semiconductor film including indium includes a crystal part whose c-axis is substantially perpendicular to a surface of the oxide semiconductor film. In the crystal part, the length of a crystal arrangement part containing indium and oxygen on a plane perpendicular to the c-axis is more than 1.5 nm. Further, the semiconductor device includes the transistor including the oxide semiconductor film in its channel formation region. | 2015-09-03 |
20150249124 | SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD - A super junction structural semiconductor device with a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region; trench gate MOSFET units in the first region comprising a plurality of trench gate regions and a first plurality of pillars; a body region between the trench gate regions and the first plurality of pillars; a second plurality of pillars in the second region extending along a corresponding side of the first region comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein in a corner part of the second region, ends of the plurality of lateral pillars and ends of the plurality of longitudinal pillars are stagger and separated apart from each other. | 2015-09-03 |
20150249125 | BURIED-CHANNEL FIELD-EFFECT TRANSISTORS - Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric. | 2015-09-03 |
20150249126 | SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n | 2015-09-03 |
20150249127 | METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND SELECTIVELY REMOVING SOME OF THE FINS BY PERFORMING A CYCLICAL FIN CUTTING PROCESS - One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed. | 2015-09-03 |
20150249128 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first MOSFET and a second MOSFET that is monolithic-integrated with the first MOSFET on a high-resistance substrate. The first MOSFET includes a first semiconductor layer formed on the high-resistance substrate and a second semiconductor layer formed above the first layer. The second semiconductor layer serves as a well layer of the first MOSFET. The second MOSFET includes a first insulating layer formed on the high-resistance substrate and having a mesa-shape in its upper part, the mesa-shape being formed by being sandwiched between two trenches filled with an oxide film formed in the first semiconductor layer. A second insulating layers formed on the mesa-shape of the first insulating layer and a third semiconductor layer is formed on the second insulating layer, the third semiconductor layer serving as a well layer of the second MOSFET. | 2015-09-03 |
20150249129 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 2015-09-03 |
20150249130 | INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME - Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses. | 2015-09-03 |
20150249131 | Epitaxial Film On Nanoscale Structure - An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein. | 2015-09-03 |
20150249132 | INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES - An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate. | 2015-09-03 |
20150249133 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT MANUFACTURING METHOD, SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE - An ohmic electrode layer is disposed on a second main surface of a silicon carbide substrate, and a metal electrode layer is disposed on the ohmic electrode layer. A notch is formed along at least one pair of sides, facing each other, of a periphery of the second main surface of the silicon carbide substrate. The cross-section of the notch orthogonal to a side of the second main surface has a corner. In the cross-section, a thickness of the silicon carbide substrate at an edge thereof under which the notch is formed is smaller than a thickness of the silicon carbide substrate in a region under which the notch is not formed, and larger than a thickness of the silicon carbide substrate in a region under which a bottom of the corner is formed. | 2015-09-03 |
20150249134 | Group III-Nitride-Based Enhancement Mode Transistor - A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer. | 2015-09-03 |
20150249135 | SEMICONDUCTOR HETEROSTRUCTURE AND METHOD OF FABRICATION THEREOF - A III-V compound semiconductor heterostructure grown on a substrate is described. The heterostructure includes a first semiconductor layer, wherein the first layer semiconductor layer is a compound semiconductor layer with (III) (V), wherein (III) represents one or more group-III elements and (V) represents one or more group-V elements, an intermediate layer on the first semiconductor layer, wherein the intermediate layer is a compound semiconductor layer with (III) | 2015-09-03 |
20150249136 | DEPOSITING AN ETCH STOP LAYER BEFORE A DUMMY CAP LAYER TO IMPROVE GATE PERFORMANCE - An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure. | 2015-09-03 |
20150249137 | ELECTRONIC DEVICE, IMAGE DISPLAY DEVICE AND SENSOR, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a control electrode | 2015-09-03 |
20150249138 | FINFET AND METHOD OF FABRICATING THE SAME - A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins. | 2015-09-03 |
20150249139 | METHODS OF FORMING GERMANIUM-CONTAINING AND/OR III-V NANOWIRE GATE-ALL-AROUND TRANSISTORS - Methods of forming gate-all-around transistors which include a germanium-containing nanowire and/or an III-V compound semiconductor nanowire. Each method includes the growth of a germanium-containing material or an III-V compound semiconductor material that includes an upper portion and a lower portion within a nano-trench and on an exposed surface of a semiconductor layer. In some instances, the upper portion of the grown semiconductor material is used as the semiconductor nanowire. In other instances, the upper portion is removed and then a semiconductor etch stop layer and a nanowire template semiconductor material of a Ge-containing material or an III-V compound semiconductor material can be formed atop the lower portion. Upon subsequent processing, each nanowire template semiconductor material provides a semiconductor nanowire. | 2015-09-03 |
20150249140 | METHOD OF MAKING A LOGIC TRANSISTOR AND NON-VOLATILE MEMORY (NVM) CELL - A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal. | 2015-09-03 |
20150249141 | SEMICONDUCTOR TRANSISTOR DEVICE WITH DOPANT PROFILE - A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel. | 2015-09-03 |
20150249142 | SEMICONDUCTOR STRUCTURE HAVING A METAL GATE WITH SIDE WALL SPACERS - A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening. | 2015-09-03 |
20150249143 | Method For Forming Oxide Below Control Gate In Vertical Channel Thin Film Transistor - A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line. | 2015-09-03 |
20150249144 | High Voltage Drain-Extended MOSFET Having Extra Drain-OD Addition - An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate. | 2015-09-03 |
20150249145 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode. | 2015-09-03 |
20150249146 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers. The impurity concentration in the surface of the oxide semiconductor film is lower than or equal to 5×10 | 2015-09-03 |
20150249147 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed. | 2015-09-03 |
20150249148 | TRANSISTOR AND MANUFACTURING METHOD THEREOF - A transistor includes a semiconductor substrate comprising a first region and a second region. The transistor further includes an emitter and a base disposed on the first region, and a collector disposed on the second region. | 2015-09-03 |
20150249149 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICOUNDUCTOR DEVICE - A forward termination structure that surrounds an active region is provided between the active region and a p | 2015-09-03 |
20150249150 | TRANSISTOR HAVING NITRIDE SEMICONDUCTOR USED THEREIN AND METHOD FOR MANUFACTURING TRANSISTOR HAVING NITRIDE SEMICONDUCTOR USED THEREIN - A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode. | 2015-09-03 |
20150249151 | CIRCUIT ARRANGEMENT - A circuit arrangement with at least a source contact ( | 2015-09-03 |
20150249152 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND FINS ON FINFET DEVICES AND THE RESULTING DEVICES - One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure. | 2015-09-03 |
20150249153 | METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION - Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs. | 2015-09-03 |
20150249154 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region. | 2015-09-03 |
20150249155 | METHOD AND APPARATUS OF STRESSED FIN NMOS FINFET - A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide. | 2015-09-03 |
20150249156 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side. | 2015-09-03 |
20150249157 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC APPLIANCE INCLUDING THE SEMICONDUCTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE - A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 1×10 | 2015-09-03 |
20150249158 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure. | 2015-09-03 |
20150249159 | THIN FILM TRANSISTOR - Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm. | 2015-09-03 |
20150249160 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC APPLIANCE INCLUDING THE SEMICONDUCTOR DEVICE, THE DISPLAY DEVICE, OR THE DISPLAY MODULE - A semiconductor device including a transistor is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a third insulating film over the source electrode, and a fourth insulating film over the drain electrode. A fifth insulating film including oxygen is provided over the transistor. The third insulating film includes a first portion, the fourth insulating film includes a second portion, and the fifth insulating film includes a third portion. The amount of oxygen molecules released from each of the first portion and the second portion is smaller than the amount of oxygen molecules released from the third portion when the amounts are measured by thermal desorption spectroscopy. | 2015-09-03 |