36th week of 2015 patent applcation highlights part 35 |
Patent application number | Title | Published |
20150248961 | ELECTROMAGNETIC STABILIZER - An electromagnetic stabilizer comprises:—a first and a second plurality of electromagnets ( | 2015-09-03 |
20150248962 | FAULT CURRENT LIMITER - A fault current limiter of the type having at least one elongated core biased magnetically towards saturation by means of a surrounding magnetic field, and an AC coil surrounding the core, the fault current limiter including: an elongated core having a variable cross section along the axis of the core in the vicinity of the AC coil, providing increased saturation of the core and enhanced fault current limiting for a lower DC bias. | 2015-09-03 |
20150248963 | COMPOSITE MATERIAL, REACTOR, CONVERTER, AND POWER CONVERSION DEVICE - There is provided a composite material containing magnetic powder and a polymeric material including the powder in a dispersion state, wherein a content of the magnetic powder with respect to the whole composite material is more than 50% by volume and 75% by volume or less, a saturation magnetic flux density of the composite material is 0.6 T or more, and a relative magnetic permeability of the composite material is more than 20 and is 35 or less. It is preferable that a density ratio of the magnetic powder should be 0.38 or more and 0.65 or less. The density ratio is set to be an apparent density/a true density. Moreover, it is preferable that the magnetic powder should include a plurality of particles constituted of the same material. | 2015-09-03 |
20150248964 | TRANSFORMERS AND METHODS FOR FABRICATING TRANSFORMERS - A transformer includes multiple differential ports and first and second transformer windings. The first transformer winding includes a first transformer half-winding coupled to a first differential port of the differential ports. The first transformer winding also includes a second transformer half-winding coupled to a second differential port of the differential ports. An amplifier system that has a transformer is also provided. The amplifier system includes a first and a second stage amplifier. The first stage amplifier includes a first and a second amplifier. The second stage amplifier includes a third and a fourth amplifier. The transformer is coupled between the first stage amplifier and the second stage amplifier, where the transformer has a primary loop and a secondary loop. The primary loop of the transformer may be configured to receive differential signals of the first amplifier. A method for fabricating a transformer is also provided. | 2015-09-03 |
20150248965 | COMPOSITE TRANSFORMER WITH A LONGER CREEPAGE DISTANCE - A composite transformer with a longer creepage distance includes a primary winding rack and an insulation support rack mounted onto the primary winding rack. The insulation support rack includes a first insulation half shell and a second insulation half shell that have respectively a first encasing portion and a second encasing portion to encase the primary winding rack. The first and second encasing portions have respectively a first insulation portion and a second insulation portion, and a first isolating portion and a second isolating portion extended respectively from the first and second insulation portions. The first isolating portion has a first covering section extended towards the second isolating portion to cover the second isolating portion. The second isolating portion has a second covering section extended towards the first isolating portion to cover the first isolating portion. | 2015-09-03 |
20150248966 | SIGNAL TRANSMITTING CIRCUIT - A transmitter circuit feeds to a transmitter coil, every time transmission data changes in logical value, a current signal in pulse form having a positive or negative polarity that is alternately inverted in response to each change in logical value; and a receiver circuit inputs induction voltage signals each being double pulses having both positive and negative polarities, which have been induced in a receiver coil by the current signal fed to the transmitter coil, to demodulate the transmission data. The receiver circuit includes: an amplifier that amplifies the induction voltage signals of double pulses induced in the receiver coil; and a signal generating unit that, when detecting first single pulses in the induction voltage signals of double pulses amplified by the amplifier, sets up an insensitive period for second single pulses therein, to generate an output signal corresponding to the transmission data, based solely on the first single pulses. | 2015-09-03 |
20150248967 | MAGNETIC CORE, MAGNETIC COMPONENT AND DESIGN METHOD OF MAGNETIC CORE - A magnetic core including a winding core portion; and a flange portion provided on the axial end side of at least one of the winding core portion, wherein the flange portion is formed such that contour line OL | 2015-09-03 |
20150248968 | Method for producing neodymium-iron-boron rare earth permanent magnetic device - A method for producing neodymium-iron-boron rare earth permanent magnetic materials mainly comprises processes of: alloy smelting, coarsely pulverization, milling, magnetic compaction, sintering, machining, vacuum heat treatment, and etc. Magnetic performance of permanent magnetic devices is increased by improving technologies of hydrogen pulverization, milling by jet mill, and vacuum heat treatment, in such a manner that usage amount of rare earth is decreased. The present invention is applicable in producing rare earth permanent magnetic materials having high performance. | 2015-09-03 |
20150248969 | PHOTOELECTRIC CONVERSION ELEMENT, DYE-SENSITIZED SOLAR CELL, METAL COMPLEX DYE, DYE SOLUTION, DYE-ADSORBED ELECTRODE, AND METHOD FOR PRODUCING DYE-SENSITIZED SOLAR CELL - A photoelectric conversion element, having a photoconductor layercontaining semiconductor fine particles carrying a metal complex dye of Formula (I); a metal complex dye, a dye solution, a dye-adsorbed electrode, a dye-sensitized solar cell, and a method for producing the solar cell: | 2015-09-03 |
20150248970 | POWER STORAGE DEVICE - A power storage device that includes a first adhesive member between a first current collector and a second surface layer, and a second adhesive member between a second current collector and a first surface layer. A first electrolyte retaining layer is provided between the first adhesive member and the first current collector. A second electrolyte retaining layer is provided between the second adhesive member and the second current collector. | 2015-09-03 |
20150248971 | ELECTRODE FOR CAPACITOR AND CAPACITOR USING SAME - A capacitor electrode includes a collector, and an electrode layer disposed in contact with the collector and capable of inserting and releasing cations. The electrode layer includes first carbon material particles capable of inserting and releasing cations and second carbon material particles capable of inserting and releasing cations. The average particle diameter of primary particles of the second carbon material particles is smaller than the average particle diameter of primary particles of the first carbon material particles. In the electrode layer, the content amount of the second carbon material particles is smaller than the content amount of the first carbon material particles. | 2015-09-03 |
20150248972 | LINKED STACKS OF PARTLY REDUCED GRAPHENE, METHOD FOR PRODUCING LINKED STACKS OF PARTLY REDUCED GRAPHENE, POWDER COMPRISING LINKED STACKS OF PARTLY REDUCED GRAPHENE, FILM COMPRISING LINKED STACKS OF PARTLY REDUCED GRAPHENE, GRAPHENE ELECTRODE FILM, METHOD FOR PRODUCING GRAPHENE ELECTRODE FILM, AND GRAPHENE CAPACITOR - The object of the present invention is to provide linked stacks of reduced graphene, in which excellent electrical property on the surface of graphene may be utilized, a method for producing the same, powder comprising the same, and film comprising the same. The object may be solved by using linked stacks of partly reduced graphene | 2015-09-03 |
20150248973 | ALUMINUM ALLOY FOIL FOR ELECTRODE CHARGE COLLECTOR, AND METHOD FOR PRODUCING SAME - An object of the present invention is to provide an aluminum alloy foil for electrode current collectors having superior rolling properties, high conductivity, and high strength after the drying step following the application of the active material. According to the present invention, an aluminum alloy foil for electrode current collector, including 0.03 to 0.1% of Fe, 0.005 to 0.02% of Ti, 0 to 0.1% of Si, 0 to 0.01% of Cu, 99.85% or more of Al, with the rest being unavoidable impurities, wherein tensile strength of the aluminum alloy foil is 175 MPa or higher, and electrical conductivity of the aluminum alloy foil is 60% IACS or higher, is provided. | 2015-09-03 |
20150248974 | MULTI-PRINT FILM AND MULTI-LIGHT SWITCH FOR VEHICLE USING THE SAME - A multi-print film having a multi-layer structure in which a first recognition mark and a second recognition mark are separately displayed. The multi-print film may include a first printed layer on which the first recognition mark configured to transmit the wavelength of a first light source, but to not transmit the wavelength of a second light source is printed and a second printed layer on which the second recognition mark configured to transmit the wavelength of the second light source, but to not transmit the wavelength of the first light source is printed. | 2015-09-03 |
20150248975 | Connecting Device - A connecting device suitable for connecting a movable conducting terminal of a switching device to a stationary conducting terminal of a switchgear apparatus, includes: a pin-group suitable for being inserted into an opening obtained in a connection-region which is defined by mutually overlapping portions of the movable and stationary conducting terminals. The pin-group is movable from a releasing position to a locking-clamping-position. There is provided a locking-positioning-arrangement configured for keeping the pressing-clamping-end blocked in the locking-clamping-position and for imparting to the pressing-clamping-end, upon a movement of the pin-group from the releasing position to the locking-clamping-position, a tightening displacement so as to generate a tightening force which presses the mutually overlapping portions against to one other. The connecting device is provided with a tightening-control-arrangement configured for controlling the tightening force so as to set a desired value of tightening-contact-pressure between the mutually overlapping portions. | 2015-09-03 |
20150248976 | Contact System - An electrical switching device including at least a nominal contact arrangement, the nominal contact arrangement at least a first nominal contact with a plurality of nominal contact fingers forming a finger cage concentric with respect to a longitudinal axis (z), and at least a mating second nominal contact. An arcing contact arrangement including a first arcing contact and a mating second arcing contact. An arcing contact finger including at its free end a first impact area in which a first contacting to the second arcing contact occurs when closing, the electrical switching device. The first impact area is formed by a first planar surface arranged at an inclination angle (α) larger than zero degrees with respect to the longitudinal axis (z). | 2015-09-03 |
20150248977 | SWITCHING APPARATUS - Provided are: a vacuum valve having a fixed contact and a movable contact; a fixed side mounting plate which supports a fixed side conductor; and an operating mechanism which is coupled to a movable side conductor and performs opening and closing operation of both the contacts. The fixed side mounting plate is configured such that a plurality of plate-like members are overlapped; an exposed portion of the fixed side conductor is attached with a divided terminal which has a fitting hole to be fitted to the exposed portion and is formed with a slit in a radial direction from the fitting hole; and the divided terminal is fixed to the fixed side mounting plate and the fixed side conductor is supported by the fixed side mounting plate via the divided terminal. | 2015-09-03 |
20150248978 | VACUUM INTERRUPTER ARRANGEMENT FOR A MEDIUM VOLTAGE CIRCUIT BREAKER WITH CUP-SHAPED TMF-CONTACTS - An exemplary vacuum interrupter arrangement for a medium voltage circuit breaker includes a vacuum housing within which a pair of electrical contacts are coaxially arranged and concentrically surrounded by the cylindrical shaped vacuum housing. The electrical contacts are formed as a type of TMF-contacts, each having a slotted cup-shaped contact part which is attached to the distal end of a contact shaft and which is covered by a contact ring disposed on a rim of the cup-shaped contact part, wherein each cup-shaped contact part is provided with a vertical inward bending towards the contact ring. The outer diameter of the bottom section of the cup-shaped contact part is larger than the outer diameter of its rim section, in order to alter the Lorentz force to a respective inward direction. | 2015-09-03 |
20150248979 | ELECTRICAL PYROTECHNIC SWITCH - An electrical switch includes a first conductive terminal having a first contact portion, a second conductive terminal having a second contact portion, and a moveable body moveable from a first position, in which the first and second contact portions are electrically disconnected, to a second position, in which the first and second contact portions are electrically connected. The first and second contact surfaces are cylinders parallel to respectively the first and second contact portions, such that the second contact surface freely goes through the first contact portion, the first contact surface enters in connection with the first contact portion simultaneously to the moment when the second contact surface enters in connection with the second contact portion, and at least one of the first and second surfaces and the corresponding one of the first and second contact portions are arranged so that the moveable body is maintained in the second position. | 2015-09-03 |
20150248980 | RELAY FIXING STRUCTURE - Rib portions ( | 2015-09-03 |
20150248981 | Alternative Power Source for Network Protector Relay - A relay for control of a network protector located on a low voltage side of a transformer with a set of three phases, the relay having at least one route for power to be provided to the relay from at least one of the set of three phases taken from a transformer side of the network protector so that the relay may have power and be functional before the network protector is closed to provide power into a dead network. | 2015-09-03 |
20150248982 | GENERATION AND USE OF ELECTRIC FIELDS FROM CAPACITIVE EFFECTS OF A SOLENOID - Systems, apparatuses, and methods are provided for producing a directional electric field from an end of the solenoid in an efficient manner. For example, voltage pulses can be used to charge the turns of the coil so that the coil acts as a capacitor. The voltage pulses can be of a specified time width (e.g., 1 μs or less) so as to reduce the amount of current flowing in the coil, and thus reduce the input power used in the coil. The electric field can be used for a variety of purposes, e.g., for charging or communication. An output conductor can be positioned such that electrons can be moved in the output conductor. The motion of electrons can correspond to the communication of data or be used to operate a load (e.g., in charging a device or otherwise providing power). | 2015-09-03 |
20150248983 | SWITCHING DEVICE WITH SEVERAL REGIONS OF CONNECTION - An electromagnetic switching device, with several distinct regions ( | 2015-09-03 |
20150248984 | Actuating apparatus for a vacuum interrupter and disconnecting arrangement - An actuating device for a vacuum switching tube has a connecting element which can be connected to an electric contact of the vacuum switching tube, an electromagnetic actuating device for displacing the connecting element between a first and a second position, and a retaining yoke, relative to which the connecting element can be displaced and has a first magnetic element. The first magnetic element generates a first and a second magnetic circuit in the retaining yoke. The actuating device further has a ferromagnetic retaining anchor, which is arranged on the connecting element. The retaining anchor is located in the first position of the connecting element in the first magnetic circuit and in the second position of the connecting element in the second magnetic circuit. The connecting element is held in the first and in the second position by a respective magnetic force between the retaining yoke and the retaining anchor. | 2015-09-03 |
20150248985 | KNOB ELEMENT AND SLIDE ELEMENT OF AN ADJUSTING APPARATUS AND ADJUSTING APPARATUS AND METHOD FOR ADJUSTING A POSITION OF A THERMAL TRIPPING SHAFT - Embodiments of the present invention relate to a knob element and a slide element of an adjusting apparatus, to an adjusting apparatus, and to a method for adjusting a position of a thermal tripping shaft as well as to a thermal magnetic trip unit and an electrical switch for interrupting a current flow of an electric current in an electrical circuit in the event of the occurrence of a tripping event, having the adjusting apparatus, which has a rotatably mounted knob element and a tangentially movably mounted slide element. In at least one embodiment, the knob element and the slide element are operatively connected in such a way that the rotary movement of the knob element becomes a tangential movement of the slide element. | 2015-09-03 |
20150248986 | THERMAL TRIP DEVICE OF A THERMAL MAGNETIC CIRCUIT BREAKER HAVING A RESISTOR ELEMENT, THERMAL MAGNETIC CIRCUIT BREAKER AND SWITCHING DEVICE FOR INTERRUPTING A CURRENT FLOW AND METHOD FOR PROTECTING AN ELECTRICAL CIRCUIT FROM DAMAGE - A thermal magnetic circuit breaker is disclosed for protecting an electrical circuit from damage by overload, along with a thermal trip device and a switching device of the thermal magnetic circuit breaker and a method for protecting an electrical circuit from damage. In at least one embodiment, an electric conductive bimetal element is arranged with its first end next to a current conductive element for conducting electrical current and with its second end next to a tripping element adapted to trigger an interruption of a current flow. A resistor element is arranged between the bimetal element and the current conductive element in order to redirect the electrical current at least partially via the bimetal element, when an overload occurs. | 2015-09-03 |
20150248987 | CIRCUIT BREAKER - A circuit breaker includes a housing, wiring boards and terminals disposed within the housing, wherein the terminal comprises a screw, a press board and a wire trap provided with a incoming line hole and a wiring space; the screw passes through a threaded hole on the top end face of the wire trap to contact the press board which is able to lift up and down and is embedded in the wire trap; the wiring board traverses the wire trap, and divides the wiring space of the wire trap into two independent wiring spaces; a first line hole is provided on the housing at a position above the screw of the terminal; and the press board and the wire trap perform a relative displacement with the wiring board under the action of the screw, to compress the two independent wiring spaces so as to realize the connection between wires. In the circuit breaker, with the wiring board as a boundary, the wiring space of the wire trap is divided into two independent wiring spaces, realizing a hybrid junction of commonly used wires while realizing the hybrid junction wiring function of single-strand wires with different diameter. | 2015-09-03 |
20150248988 | PROCESS FOR REPAIRING AN ANODE FOR EMITTING X-RAYS AND REPAIRED ANODE - A process for repairing a damaged annular region of an anode configured to emit x-rays includes the step of machining the damaged annular region made of an initial target coating to a depth smaller than a thickness of the coating so as to leave behind a residual annular layer. An intermediate layer is then deposited on the residual annular layer. A repairing layer is then deposited on the intermediate layer. A heat treatment is then performed using an anneal which causes, by interdiffusion and formation of a solid solution, the material of the intermediate layer and the material of the residual annular layer to diffuse into each other and further cause the material of the intermediate layer and the material of the repairing layer diffuse into each other. As a result of this anneal the intermediate layer disappears. | 2015-09-03 |
20150248989 | ION GENERATION APPARATUS AND ELECTRIC EQUIPMENT - Each of first to fourth needle-like electrodes is arranged such that a direction of extension thereof is parallel, and generates ions by discharge. Through a space, a gas for conveying the ions generated by the first to fourth needle-like electrodes flows. Needle tips of the first needle-like electrode and the second needle-like electrode protrude from a first wall surface that forms the space, are spaced apart from each other, and are arranged in line in the space. Needle tips of the third needle-like electrode and the fourth needle-like electrode protrude from a second wall surface that forms the space and faces the first wall surface, are spaced apart from each other, and are arranged in line in the space. The first needle-like electrode and the fourth needle-like electrode generate positive ions, and the second needle-like electrode and the third needle-like electrode generate negative ions. | 2015-09-03 |
20150248990 | Energy-discrimination detection device - This invention provides a method for improving performance of a reflective type energy filter for a charged particle beam, which employs a beam-adjusting lens on an entrance side of a potential barrier of the energy filter to make the charged particle beam become a substantially parallel beam to be incident onto the potential barrier. The method makes the energy filter have both a fine energy-discrimination power over a large emission angle spread and a high uniformity of energy-discrimination powers over a large FOV. A LVSEM using this method in the energy filter can obviously improve image contrast. The invention also provides multiple energy-discrimination detection devices formed by using the advantages of the method. | 2015-09-03 |
20150248991 | Stage Device and Charged Particle Beam Apparatus Using the Stage Device - To attain the above object, in the present invention, proposed are a stage apparatus including a sample stage that mounts a sample, a first position detection device that detects a position of the sample stage, a second position detection device that detects a position of the sample stage when the sample stage is positioned in a part of a stage movement range that the first position detection device is capable of detecting, and a control device that adjusts an offset amount of the first position detection device on the basis of a position detection result obtained by the second position detection device, and a charged particle beam apparatus using the stage apparatus. | 2015-09-03 |
20150248992 | BORON-CONTAINING DOPANT COMPOSITIONS, SYSTEMS AND METHODS OF USE THEREOF FOR IMPROVING ION BEAM CURRENT AND PERFORMANCE DURING BORON ION IMPLANTATION - A novel composition, system and method thereof for improving beam current during boron ion implantation are provided. The boron ion implant process involves utilizing B2H6, BF3 and H2 at specific ranges of concentrations. The B2H6 is selected to have an ionization cross-section higher than that of the BF3 at an operating arc voltage of an ion source utilized during generation and implantation of active hydrogen ions species. The hydrogen allows higher levels of B2H6 to be introduced into the BF3 without reduction in F ion scavenging. The active boron ions produce an improved beam current characterized by maintaining or increasing the beam current level without incurring degradation of the ion source when compared to a beam current generated from conventional boron precursor materials. | 2015-09-03 |
20150248993 | COMPENSATION OF DEFECTIVE BEAMLETS IN A CHARGED-PARTICLE MULTI-BEAM EXPOSURE TOOL - An exposure pattern is computed which is used for exposing a desired pattern on a target by means of a blanking aperture array in a particle-optical lithography apparatus which has a finite number of defects, said desired pattern being composed of a multitude of image elements within an image area on the target: A list of defective blanking apertures is provided, comprising information about the type of defect of the defective blanking apertures; from the desired pattern a nominal exposure pattern is calculated as a raster graphics over the image elements disregarding the defective blanking apertures; the “compromised” image elements ( | 2015-09-03 |
20150248994 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus, comprising a processing chamber within a vacuum chamber, and a sample stage arranged within the processing chamber with a sample to be processed placed on its top surface, wherein plasma is formed in the processing chamber to perform processing of the sample, wherein the sample stage is provided with an electrostatic chuck which is provided with film electrodes to which power for attraction of the sample is supplied, and upper and lower plate-like sintered bodies joined mutually with the electrodes interposed between them from above and below, and the lower sintered body has a dielectric constant higher than that of the upper sintered body. | 2015-09-03 |
20150248995 | RADIOFREQUENCY ADJUSTMENT FOR INSTABILITY MANAGEMENT IN SEMICONDUCTOR PROCESSING - Methods, systems, and computer programs are presented for reducing chamber instability while processing a semiconductor substrate. One method includes an operation for identifying a first recipe with steps having an operating frequency equal to the nominal frequency of a radiofrequency (RF) power supply. Each step is analyzed with the nominal frequency, and the analysis determines if any step produces instability at the nominal frequency. The operating frequency is adjusted, for one or more of the steps, when the instability in the one or more steps exceeds a threshold. The adjustment acts to find an approximate minimum level of instability. A second recipe is constructed after the adjustment, such that at least one of the steps includes a respective operating frequency different from the nominal frequency. The second recipe is used to etch the one or more layers disposed over the substrate in the semiconductor processing chamber. | 2015-09-03 |
20150248996 | OXIDE SINTERED BODY AND SPUTTERING TARGET, AND METHOD FOR PRODUCING SAME - An oxide sintered body which is obtained by mixing and sintering zinc oxide, indium oxide, gallium oxide and tin oxide. The relative density of the oxide sintered body is 85% or more and the average grain size of crystal grains observed on the surface of the oxide sintered body is less than 10 μm. X-ray diffraction of the oxide sintered body shows that a Zn | 2015-09-03 |
20150248997 | MODIFIED LITHIUM COBALT OXIDE SPUTTERING TARGETS - A modified and improved lithium cobalt oxide sputtering target with reduced resistivity is described. Unique modifications to the composition of the lithium cobalt oxide target allow adjustment or fine-tuning of the resistance of the target not previously possible. Incorporation of a controlled amount of one or more conductive materials into the lithium cobalt oxide composition is described alone or in combination with altering the stoichiometric ratio of Li:Co to significantly reduce resistivity and thereby enhance conductivity of the target. The result is a modified sputtering target capable of sputtering lithium-containing thin films that does not exhibit deterioration of their properties by virtue of elevated levels of conductive containing material incorporated into the target. | 2015-09-03 |
20150248998 | Systems and Methods for Identifying Compounds from MS/MS Data without Precursor Ion Information - Systems and methods are provided for identifying a precursor ion without using any a priori precursor ion information. In one method, a sample is analyzed using a tandem mass spectrometer, producing at least one measured product ion spectrum from a precursor mass-to-charge ratio range. The at least one measured product ion spectrum are received. A subset of measured product ions is selected from the at least one measured product ion spectrum. A list of candidate compounds is created by searching a dictionary of potential compounds that includes one or more predicted product ions for each of the potential compounds using the subset of measured product ions. A candidate compound on the list is selected as the identified compound. In another method, the measured product ions are assumed to correspond to shortened forms of the peptide and a protein database is searched for shortened forms of the peptide. | 2015-09-03 |
20150248999 | Systems and Methods for Acquiring Data for Mass Spectrometry Images - Systems and methods are provided for maximizing the data acquired from a sample in a mass spectrometry imaging experiment. An ion source device is instructed to produce and transmit to a tandem mass spectrometer a plurality of ions for each location of two or more locations of a sample. A mass range is divided into two or more mass window widths. For each location of the two or more locations, the tandem mass spectrometer is instructed to fragment the plurality of ions received for each location using each mass window width of the two or more mass window widths and to analyze resulting product ions. A product ion spectrum is produced for each mass window width, and a plurality of product ion spectra are produced for each location of the two or more locations. | 2015-09-03 |
20150249000 | INSTRUMENT FOR ANALYSING COMPOUNDS - Instrument for analysing compounds, comprising an ion source, an adjacent drift tube and a mass spectrometer including an ion detector for separation and detection of product ions, wherein instrumental parameters of the instrument can be altered by actuating elements for actuating variables of at least one of the group consisting of ion source, adjacent drift tube, mass spectrometer and ion detector, characterized by a controlling unit which is connectable to a storage device, wherein the storage device comprises a specification for certain compounds, the specification for each compound comprising a set of data comprising at least two different instrumental parameters and corresponding intensity signals for product ions detected with the ion detector, wherein the controlling unit alters the actuating elements in accordance with the specification for each compound, wherein a correspondence signal is displayed on a display unit if the detected intensity signal for the product ion corresponds with the stored intensity signals. | 2015-09-03 |
20150249001 | SAMPLE COLLECTION THERMAL DESORBER - A thermal desorption apparatus is configured to detect a substance of interest in a sample, the apparatus comprising: a wand configured to support a swab and a detector comprising an analyser arranged to detect a substance of interest, wherein the wand is configured to couple to the detector such that thermal desorption of a sample from the swab provides a part of the sample to the analyser. | 2015-09-03 |
20150249002 | Ion Guide With Orthogonal Sampling - A mass spectrometer is disclosed comprising a RF ion guide wherein in a mode of operation a continuous, quasi-continuous or pulsed beam of ions is orthogonally sampled from the ion guide and wherein the continuous, quasi-continuous or pulsed beam of ions is not axially trapped or otherwise axially confined within the RF ion guide. The ion guide is maintained, in use, at a pressure selected from the group consisting of: (i) 0.0001-0.001 mbar; (ii) 0.001-0.01 mbar; (iii) 0.01-0.1 mbar; (iv) 0.1-1 mbar; (v) 1-10 mbar; (vi) 10-100 mbar; and (vii) >100 mbar. | 2015-09-03 |
20150249003 | SHORT ARC FLASH LAMP AND LIGHT SOURCE DEVICE - Disclosed herein are a short arc type flash lamp having high lamp starting performance and capable of reducing the diameter of its seal tube part, and a light source device thereof. The flash lamp has an electrode shaft of one of the main electrodes, and an electrode shaft of the other of the main electrodes and leads for starting auxiliary electrodes which are respectively led out from the second seal tube part, and an external trigger is disposed in a state in which it extends in the circumferential direction on the outer peripheral surface of one end side region of the second seal tube part. The light source device is structured by a concave reflection mirror disposed on the second seal tube part side of the flash lamp in a state in which a focal point of the concave reflection mirror coincides with a luminous point of the flash lamp. | 2015-09-03 |
20150249004 | METHOD OF FABRICATING NITRIDE FILM AND METHOD OF CONTROLLING COMPRESSIVE STRESS OF THE SAME - The present invention relates to a method of fabricating a nitride film, which may easily control compressive stress while stably maintaining the film quality using the atomic layer deposition, and the nitride film having compressive stress is formed on a substrate by performing a unit cycle at least one time, the unit cycle including: a first step of providing a source gas on the substrate to absorb at least of the source gas on the substrate; a second step of providing a first purge gas on the substrate; a third step of forming a unit deposition film on the substrate by providing the substrate with a stress controlling gas including a nitrogen gas (N | 2015-09-03 |
20150249005 | ATOMIC LAYER DEPOSITION OF ANTIMONY OXIDE FILMS - Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl | 2015-09-03 |
20150249006 | METHOD OF DEFINING POLY-SILICON GROWTH DIRECTION - The present invention relates to a method of defining poly-silicon growth direction. The method of defining poly-silicon growth direction comprises Step | 2015-09-03 |
20150249007 | Methods to Prepare Silicon-Containing Films - Described herein are methods of forming dielectric films such as non-porous dielectric films, comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer. | 2015-09-03 |
20150249008 | SEMICONDUCTOR PROCESS - A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted. | 2015-09-03 |
20150249009 | METHOD OF ENHANCING HIGH-k FILM NUCLEATION RATE AND ELECTRICAL MOBILITY IN A SEMICONDUCTOR DEVICE BY MICROWAVE PLASMA TREATMENT - A method for forming a semiconductor device is provided in several embodiments. According to one embodiment, the method includes providing a substrate in a process chamber, flowing a process gas consisting of hydrogen (H | 2015-09-03 |
20150249010 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a substrate, a first inter layer dielectric disposed on the substrate, and a second inter layer dielectric disposed on the first inter layer dielectric. Furthermore, one of the first and second inter layer dielectrics is a first insulator, and the other of the first and second inter layer dielectrics is a second insulator. In addition, the first insulator has a property capable of having a tensile stress in a case where the first insulator is annealed, and the second insulator has a property capable of having a compression stress in a case where the second insulator is annealed. | 2015-09-03 |
20150249011 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor. | 2015-09-03 |
20150249012 | RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON CONTAINING CYCLIC ORGANIC GROUP HAVING HETERO ATOM - A resist underlayer film composition for lithography, including: a silane: at least one among a hydrolyzable organosilane, a hydrolysis product thereof, and a hydrolysis-condensation product thereof, wherein the silane includes a silane having a cyclic organic group containing as atoms making up the ring, a carbon atom, a nitrogen atom, and a hetero atom other than a carbon and nitrogen atoms. The hydrolyzable organosilane may be a hydrolyzable organosilane of Formula (1), wherein, at least one group among R1, R2, and R3 is a group wherein a —Si(X)3 group bonds to C1-10 alkylene group, and other group(s) among R1, R2, and R3 is(are) a hydrogen atom, C1-10 alkyl group, or C6-40 aryl group; a cyclic organic group of 5-10 membered ring containing atoms making up the ring, a carbon atom, at least one of nitrogen, sulfur or oxygen atoms; and X is an alkoxy group, acyloxy group, or halogen atom. | 2015-09-03 |
20150249013 | CAPPED ALD FILMS FOR DOPING FIN-SHAPED CHANNEL REGIONS OF 3-D IC TRANSISTORS - Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors. | 2015-09-03 |
20150249014 | PROCESS FOR PRODUCING A DOUBLE-GATE FIELD-EFFECT DEVICE HAVING INDEPENDENT GATES - A substrate of SOI type is covered by an etching mask defining three distinct semiconductor patterns. A lateral spacer is formed around the three patterns and performs the connection between two adjacent patterns. The buried insulating layer is eliminated so as to define a cavity which suspends a part of a first pattern. The first etching mask is eliminated. A gate dielectric is formed on two opposite main surfaces of the first pattern. The resist is deposited in the cavity and on the first pattern and is then exposed to form two patterns defining the bottom and top gates. An electrically conducting material is deposited in the cavity and on the first pattern so as to form the bottom gate and the top gate on each side of the first semiconductor material pattern. | 2015-09-03 |
20150249015 | ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES - A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region. | 2015-09-03 |
20150249016 | METHOD OF PLANARIZING AN UPPER SURFACE OF A SEMICONDUCTOR SUBSTRATE IN A PLASMA ETCH CHAMBER - A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate. | 2015-09-03 |
20150249017 | SPACER MATERIAL MODIFICATION TO IMPROVE K-VALUE AND ETCH PROPERTIES - A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure. The K-value of high-K spacer materials are reduced to an acceptable range with oxidation using an oxygen plasma treatment. The etch rate of low-K spacer materials are reduced to a target range using a nitrogen plasma treatment. Integration of the spacer etch processing is selected based on impact to the other structures in the substrate. | 2015-09-03 |
20150249018 | DIFFERENTIAL SILICON OXIDE ETCH - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide. | 2015-09-03 |
20150249019 | Methods and Apparatus of Packaging with Interposers - Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost. | 2015-09-03 |
20150249020 | SEMICONDUCTOR DEVICE WITH METAL CARRIER AND MANUFACTURING METHOD - Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Al | 2015-09-03 |
20150249021 | PACKAGED LEADLESS SEMICONDUCTOR DEVICE - A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant. | 2015-09-03 |
20150249022 | METHOD FOR MANUFACTURING A FILLED CAVITY BETWEEN A FIRST AND A SECOND SURFACE - A method for manufacturing a filled cavity between a first surface and a second surface. The steps of the method include: providing a first surface and a second surface; applying on the first surface and/or the second surface a filling material that has a carrier fluid and necking particles; providing spacer elements for defining a width of a cavity between the first and second surfaces; bringing the first and second surfaces together to deform the filling material such that at least one spacer element is held between the first and second surfaces; and removing the carrier fluid such that necking particles attach in a contact region of at least one spacer element with the first surface or the second surface to form necks. | 2015-09-03 |
20150249023 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device, includes preparing a molding die for molding a resin case for a semiconductor device, the molding die having protrusions to fix each of a plurality of terminals having a leg portion in a predetermined position; conforming and holding each of the plurality of terminals to the corresponding protrusions in the molding die; and injecting resin into the molding die to integrally mold the plurality of terminals and the resin case. | 2015-09-03 |
20150249024 | METHOD AND EQUIPMENT FOR REMOVING PHOTORESIST RESIDUE AFER DRY ETCH - A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid. | 2015-09-03 |
20150249025 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - Provided is a heat treatment container having a small size and capable of efficiently performing a heat treatment on a SiC substrate. A heat treatment container is a container for a heat treatment on a SiC substrate | 2015-09-03 |
20150249026 | ROOM-TEMPERATURE BONDING APPARATUS AND ROOM-TEMPERATURE BONDING METHOD - A room-temperature bonding apparatus includes a vacuum chamber; a first holding mechanism; a second holding mechanism; a beam source; and a pressure bonding mechanism which bonds first and second substrates. At least one of the above members is formed of a first material which is difficult to be sputtered or which does not obstruct a function of a device obtained by bonding the first and second substrates even if the first material is in the bonding surfaces, or a surface of the at least one is covered with the first material. | 2015-09-03 |
20150249027 | THERMOCOMPRESSION BONDING SYSTEMS AND METHODS OF OPERATING THE SAME - A thermocompression bonding system for bonding semiconductor elements is provided. The thermocompression bonding system includes (1) a bond head assembly including a heater for heating an semiconductor element to be bonded, the bond head assembly including a fluid path configured to receive a cooling fluid; (2) a pressurized cooling fluid source; (3) a booster pump for receiving a pressurized cooling fluid from the pressurized cooling fluid source, and for increasing a pressure of the received pressurized cooling fluid; (4) a pressurized fluid reservoir for receiving pressurized cooling fluid from the booster pump; and (5) a control valve for controlling a supply of pressurized cooling fluid from the pressurized fluid reservoir to the fluid path. | 2015-09-03 |
20150249028 | WAFER POSITION CORRECTION WITH A DUAL, SIDE-BY-SIDE WAFER TRANSFER ROBOT - Methods and systems for positioning wafers using a dual side-by-side end effector robot are provided. The methods involve performing place moves using dual side-by-side end effector robots with active wafer position correction. According to various embodiments, the methods may be used for placement into a process module, loadlock or other destination by a dual wafer transfer robot. The methods provide nearly double the throughput of a single wafer transfer schemes by transferring two wafers with the same number of moves. | 2015-09-03 |
20150249029 | LOAD STATION - A substrate loading station including a frame forming a chamber configured to hold a controlled environment, a transfer robot connected to the frame and one or more substrate cassette holding locations each capable of having a substrate cassette holder disposed within the frame. Each of the one or more substrate cassette holding locations being configured to removably support a respective substrate cassette in a predetermined position for communication with the transfer robot to effect substrate transfer between a respective cassette and the transfer robot where the one or more substrate cassette holding locations are configured to effect the interchangeability of one or more substrate cassette holders with other substrate cassette holders for changing a substrate cassette holding capacity of the substrate loading station. | 2015-09-03 |
20150249030 | Electrostatic Charge Removal For Solar Cell Grippers - A manufacturing system includes a gantry module, having an end effector, for moving workpieces from a conveyor system to a working area, such as a swap module. The swap module removes a matrix of processed workpieces from a load lock and place a matrix of unprocessed workpieces in its place. The processed workpieces are then moved by the gantry module back to the conveyor. Due to the speed of operation, the end effector may build up excessive electrostatic charge. To remove this built up charge, grounded electrically-conductive brushes are strategically positioned so that, as the end effector moves during normal operation, it comes in contact with these brushes. This removes this built up charge on the end effector, without affecting throughput. In another embodiment, the end effector moves over the brushes while the swap module is moving matrix to and from the load lock. | 2015-09-03 |
20150249031 | METHOD AND APPARATUS FOR AN AUTOMATED TOOL HANDLING SYSTEM FOR A MULTILEVEL CLEANSPACE FABRICATOR - The present invention provides methods and apparatus capable of routine placement and replacement of fabricator tools in a designated tool location. The tool location can be selected from multiple tool locations arranged in a matrix with horizontal and vertical designations. The operation may be fully automated. In another aspect, the invention describes Cleanspace fabricators which use devices to routinely remove and place tooling. | 2015-09-03 |
20150249032 | Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2015-09-03 |
20150249033 | METHOD FOR MODIFYING AN INITAIL STRESS STATE OF AN ACTIVE LAYER TO A FINAL STRESS STATE - This process comprises steps of: a) providing a first substrate comprising the active layer made of a first material of Young's modulus E | 2015-09-03 |
20150249034 | GRAPHENE FILM MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a graphene film manufactures a graphene film in good state without generating wrinkles and stresses and leaving residues of the resin. The method of manufacturing a graphene film comprises forming a catalyst metal film on a substrate; synthesizing a graphene film on the catalyst metal film; and removing the metal catalyst film in an oxidation atmosphere of an oxidizer and transferring the graphene film to the substrate. | 2015-09-03 |
20150249035 | METHOD FOR MANUFACTURING SOI WAFER - The present invention is a method for manufacturing an SOI wafer, including: implanting one or more gas ion selected from a hydrogen ion and a rare gas ion into a bond wafer composed of a semiconductor single crystal substrate from a surface of the bond wafer to form an ion-implanted layer; bonding the surface from which the ion is implanted into the bond wafer and a surface of a base wafer through an oxide film; and then delaminating the bond wafer at the ion-implanted layer by performing a delamination heat treatment with a heat treatment furnace to form the SOI wafer, wherein after the delamination heat treatment, a temperature of the heat treatment furnace is decreased to 250° C. or less at temperature-decreasing rate of less than 3.0° C./min, and then the SOI wafer and the bond wafer after delamination are taken out from the heat treatment furnace. | 2015-09-03 |
20150249036 | METHODS OF FORMING DIFFERENT SPACER STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS HAVING DIFFERING GATE PITCH DIMENSIONS AND THE RESULTING PRODUCTS - One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure. | 2015-09-03 |
20150249037 | MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION - A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure. | 2015-09-03 |
20150249038 | SELECTIVE CONDUCTIVE BARRIER LAYER FORMATION - A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer. | 2015-09-03 |
20150249039 | Method of Making a FinFET Device - A method of fabricating a fin-like field-effect transistor (FinFET) device includes providing a substrate having a first region and a second region, and forming a plurality of mandrel features in the first region with a first spacing. The method further includes forming first spacers along sidewalls of the mandrel features with a targeted width A, and forming second spacers with a first width W | 2015-09-03 |
20150249040 | LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 2015-09-03 |
20150249041 | Semiconductor Chip Including Region Having Integrated Circuit Transistor Gate Electrodes Formed by Various Conductive Structures of Specified Shape and Position and Method for Manufacturing the Same - A semiconductor chip includes a region that includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type. The region includes a second CS that forms a GE of a second transistor of the first transistor type and a GE of a first transistor of a second transistor type. The region includes another CS that forms a GE of a second transistor of the second transistor type. The GE's of the first and second transistors of the first transistor type are separated by a gate pitch. The GE's of the first and second transistors of the second transistor type are separated by the gate pitch. The first CS has a total length that is greater than one-half of the total length of the second CS. The second and third CS's have at least one respective end aligned with each other. | 2015-09-03 |
20150249042 | GETTER STRUCTURE AND METHOD FOR FORMING SUCH STRUCTURE - A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites. | 2015-09-03 |
20150249043 | Method of Packaging a Semiconductor Chip Using a 3D Printing Process and Semiconductor Package Having Angled Surfaces - In one aspect, a method of packaging a semiconductor module includes providing a semiconductor module having a first surface, a second surface opposite the first surface and edge sides extending between the first surface and the second surface. A packaging assembly is formed at least partly by a 3D printing process. The packaging assembly includes the semiconductor module and a protective covering that extends over the first surface. | 2015-09-03 |
20150249044 | CIRCUIT BOARD WITH PHASE CHANGE MATERIAL - Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board. | 2015-09-03 |
20150249045 | POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units. | 2015-09-03 |
20150249046 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor element, amounting substrate which has wiring layers containing copper, and a joining layer which is provided between the semiconductor element and the wiring layer and made of an alloy containing copper and metal other than copper, and in which a melting point of the alloy is higher than a melting point of the metal. | 2015-09-03 |
20150249047 | Interposer with Programmable Matrix for Realizing Configurable Vertical Semiconductor Package Arrangements - An interposer for establishing a vertical connection between semiconductor packages includes an electrically insulating substrate having a first main side and a second main side opposite the first main side, a plurality of first electrical conductors at the first main side of the substrate, a plurality of second electrical conductors at the second main side of the substrate, and a programmable connection matrix at one or both main sides of the substrate. The programmable connection matrix includes programmable junctions configured to open or close electrical connections between different ones of the first electrical conductors and different ones of the second electrical conductors upon programming of the junctions. | 2015-09-03 |
20150249048 | STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN METAL TRACE OF INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the IC device if the vacancies migrate to the vias interconnecting the metal layers. To mitigate vacancy migration, stressor elements are formed at the metal traces to form stress effects in the metal traces that, depending on type, either serve to repel migrating vacancies from the via contact area or to trap migrating vacancies at a portion of the metal trace displaced from the contact area. The stressor elements may be formed as stress-inducing dielectric or conductive material overlying the metal traces, or formed by inducing a stress memory effect in a portion of the metal trace itself. | 2015-09-03 |
20150249049 | Through-Substrate via Formation with Improved Topography Control - A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad. | 2015-09-03 |
20150249050 | FORMING FENCE CONDUCTORS USING SPACER ETCHED TRENCHES - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 2015-09-03 |
20150249051 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 2015-09-03 |
20150249052 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention comprises: a memory cell region formed on a semiconductor substrate; peripheral circuit regions formed at the periphery of the memory cell region; embedded wiring lines formed embedded in trench portions formed in the semiconductor substrate; and upper wiring lines formed in a layer above the memory cell region and the peripheral circuit regions, and peripheral circuits in the peripheral circuit regions are connected to the upper wiring lines by way of the embedded wiring lines. | 2015-09-03 |
20150249053 | NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm. | 2015-09-03 |
20150249054 | SUBSTRATE ALIGNMENT MARK AND FABRICATING METHOD THEREOF, AND SUBSTRATE - A substrate alignment mark and a fabricating method thereof, and a substrate are provided. The substrate alignment mark includes a first alignment mark pattern and a second alignment mark pattern that are formed in a different-layer structure on a substrate, the first alignment mark pattern and the second alignment mark pattern are provided with centers thereof aligned and without overlapping portions. Therefore, because two alignment marks are formed in a different-layer structure on a substrate, when uneven film formation occurs in the process of forming one of the alignment marks, causing the alignment mark to be unidentifiable in alignment, the alignment can still be performed by identifying the other alignment mark, thus identification success rate of alignment marks is increased, and then defective rate caused by failure to identify alignment marks in manufacturing process of the substrate is noticeably decreased. | 2015-09-03 |
20150249055 | CHIP DIODE AND DIODE PACKAGE - [Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode. | 2015-09-03 |
20150249056 | SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE SUPPORT LAYER - In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The excavated region covers a majority of the signal-processing region of the integrated circuit. | 2015-09-03 |
20150249057 | Seal Ring Structure With A Metal Pad - A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided. | 2015-09-03 |
20150249058 | INTEGRATED CIRCUIT COMPONENT SHIELDING - Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed. | 2015-09-03 |
20150249059 | VERSATILE AND RELIABLE INTELLIGENT PACKAGE - A package comprises a body, and an electrically conductive pattern supported by said body. An interface portion is configured to receive a module to a removable attachment with the package. The electrically conductive pattern comprises, at least partly within said interface portion, a wireless coupling pattern that constitutes one half of a wireless coupling arrangement. | 2015-09-03 |
20150249060 | ENHANCED FLIP CHIP STRUCTURE USING COPPER COLUMN INTERCONNECT - A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening. | 2015-09-03 |