| 36th week of 2009 patent applcation highlights part 24 |
| Patent application number | Title | Published |
|---|
| 20090219739 | Range-Matching Cell and Content Addressable Memories Using the Same - A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell ( | 2009-09-03 |
| 20090219740 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs. | 2009-09-03 |
| 20090219741 | DIAGONAL CONNECTION STORAGE ARRAY - In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements. | 2009-09-03 |
| 20090219742 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-09-03 |
| 20090219743 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-09-03 |
| 20090219744 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-09-03 |
| 20090219745 | MEMORY MODULE AND MEMORY DEVICE - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 2009-09-03 |
| 20090219746 | Circuit Arrangement Comprising a Non-Volatile Memory Cell and Method - The circuit arrangement comprises a symmetrically constructed comparator ( | 2009-09-03 |
| 20090219747 | METHOD OF PROGRAMMING A MEMORY HAVING ELECTRICALLY PROGRAMMABLE FUSES - An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells comprising a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line, and a second current electrode connected to the programmable fuse. The select transistor further has a semiconductor body adjacent to which the first current electrode and the second current electrode are located. These electrodes are separated by a channel. A signal terminal that is connected to the semiconductor body receives an input signal to forward bias the channel to the first current electrode during programming of the programmable fuse to increase a programming current of the programmable fuse. | 2009-09-03 |
| 20090219748 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory includes ferroelectric capacitors including ferroelectric films between first electrodes and second electrodes; cell transistors; and a bit line contact connecting the cell transistors to a bit line, wherein the first electrode is connected to one of source and drain of the cell transistor at a first node, so that the ferroelectric capacitor and the cell transistor form a unit cell, the other of source and drain of the cell transistor for the unit cell is connected to the first node of other unit cell to serially connect the cell transistors for unit cells, so that the unit cells form a cell string, the word lines are connected to gates of the cell transistors or function as gates, the plate lines are connected to the second electrodes of the ferroelectric capacitors, and the bit line is connected to a cell transistor at an end of the cell string. | 2009-09-03 |
| 20090219749 | METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SENSING OPERATION FOR RESISTIVE MEMORY DEVICES - An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data leg, across the memory element, thereby establishing a fixed current sinking capability thereof; and a plurality of differential amplifiers, each of the differential amplifiers configured to compare a first voltage input, taken at a second node of the data leg, with a second voltage input; wherein the second voltage input for each differential amplifier comprises different reference voltages with respect to one another so as to enable each differential amplifier to detect a different resistance threshold, thereby determining a specific resistance state of the programmable resistive memory element. | 2009-09-03 |
| 20090219750 | NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A nonvolatile memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a line selector circuit operative to decode an address signal to select the first and second lines; and a control circuit operative to execute control on at least one of data erase, write and read for the memory cell connected between the first and second lines selected at the line selector circuit. The control circuit executes control based on one parameter selected among a plurality of parameters. The line selector circuit specifies the parameter based on a first address portion in the address signal and selects the first and second lines based on a second address portion in the address signal. | 2009-09-03 |
| 20090219751 | PHASE CHANGE MEMORY - A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. | 2009-09-03 |
| 20090219752 | Apparatus and Method for Improving Storage Latch Susceptibility to Single Event Upsets - An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state circuit coupled to separate data nodes within the DICE latch; and a pair of local clock circuits configured within the storage latch circuit, the pair of local clock circuits configured to generate a duplicate pair of control signals that separately control a corresponding one of the separate three-state circuits. In the event of a charge accumulation event on only one of the pair of local clock circuits so as to change the logical state of the corresponding control signal, the presence of the other of the pair of local clock circuits that remains unaffected by the charge accumulation event prevents an error in the logical state of the DICE latch. | 2009-09-03 |
| 20090219753 | MAGNETIC MEMORY DEVICE - A magnetic memory device including a plurality of word lines, a plurality of bit lines which intersect the word lines and are put into groups, a plurality of memory cells which are arranged at intersections between the bit lines and the word lines, each memory cell including a magnetic element and a transistor which are connected in series, a first decoder which sequentially selects the word lines, a second decoder which sequentially drives the bit lines of each group, a weighting adder which performs weighting addition of currents flowing on bit lines in a selected group to generate an added current signal, a current/voltage converter which converts the added current signal into a voltage signal, and an analog-to-digital converter which digitizes the voltage signal. | 2009-09-03 |
| 20090219754 | Magnetoresistive device and magnetic memory using the same - A magnetic film stack is composed of a synthetic antiferromagnet including a plurality of ferromagnetic layers, adjacent two of which are antiferromagnetically coupled through a non-magnetic layer; and a reversal inducing layer exhibiting ferromagnetism. The reversal inducing layer is ferromagnetically coupled to the synthetic antiferromagnet, and designed to have a coercive field smaller than a magnetic field at which antiferromagnetic coupling within the synthetic antiferromagnet starts to be decoupled. | 2009-09-03 |
| 20090219755 | INTEGRATED CIRCUIT INCLUDING AN ELECTRODE HAVING AN OUTER PORTION WITH GREATER RESISTIVITY - An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resistivity changing material contacting the first electrode and coupled to the second electrode. | 2009-09-03 |
| 20090219756 | Apparatus and Method for Determining a Memory State of a Resistive N-Level Memory Cell and Memory Device - A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n−1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values. | 2009-09-03 |
| 20090219757 | MAGNETIC STORAGE DEVICE - A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal. | 2009-09-03 |
| 20090219758 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 2009-09-03 |
| 20090219759 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 2009-09-03 |
| 20090219760 | MEMORY DEVICE HAVING READ CACHE - A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories. | 2009-09-03 |
| 20090219761 | CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation. | 2009-09-03 |
| 20090219762 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprise a second transistor including second gate insulation films and drive the control gate line and the source line with a boost voltage higher than the first driving voltage. | 2009-09-03 |
| 20090219763 | NON-VOLATILE MEMORY - A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. A circuit provides a first voltage to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. The circuit also provides a voltage to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range. | 2009-09-03 |
| 20090219764 | Semiconductor memory device for high-speed data input / output - Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data. | 2009-09-03 |
| 20090219765 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data to be programmed into a memory cell and changes the data held according to a verify result from the memory cell. Then, the data circuit selects one of the bit line application voltage terminals based on the data held therein and applies voltage of the selected bit line application voltage terminal to a bit line BLe or BLo. | 2009-09-03 |
| 20090219766 | APPARATUS, SYSTEM, AND METHOD FOR ADJUSTING MEMORY HOLD TIME - An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first voltage to a memory controller and at a reference voltage to the memory. The first and reference voltages are set independently. | 2009-09-03 |
| 20090219767 | PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES - A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes. | 2009-09-03 |
| 20090219768 | SEMICONDUCTOR MEMORY DEVICE HAVING SHARED BIT LINE SENSE AMPLIFIER SCHEME AND DRIVING METHOD THEREOF - A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal. | 2009-09-03 |
| 20090219769 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 2009-09-03 |
| 20090219770 | Semiconductor memory device and operation method thereof - Semiconductor memory device and operation method thereof includes an output enable signal generator configured to synchronize a read command to a data clock signal to generate an output enable signal according to a CAS latency, a sampling control signal generator configured to generate a sampling control signal that is activated during a period corresponding to an activation timing of the output enable signal and an end timing of data output, a read clock signal generator configured to sample the data clock signal in response to the sampling control signal to generate a read clock signal and a data output circuit configured to output data according to the read clock signal. | 2009-09-03 |
| 20090219771 | Adjusting a Digital Delay Function of a Data Memory Unit - An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit ( | 2009-09-03 |
| 20090219772 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-09-03 |
| 20090219773 | Integrated Circuit, Method for Acquiring Data and Measurement System - An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell. | 2009-09-03 |
| 20090219774 | SEMICONDUCTOR MEMORY DEVICE AND PARALLEL TEST METHOD OF THE SAME - Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks, compressing the read data and outputting the compressed data to the outside of a chip. | 2009-09-03 |
| 20090219775 | Semiconductor memory device - Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level. | 2009-09-03 |
| 20090219776 | NON-VOLATILE MEMORY DEVICE WITH PLURAL REFERENCE CELLS, AND METHOD OF SETTING THE REFERENCE CELLS - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 2009-09-03 |
| 20090219777 | MULTI-CHIP ASSEMBLY AND METHOD FOR DRIVING THE SAME - Disclosed are a multi-chip assembly and a method for driving the same. The multi-chip assembly includes a first chip designed with a first device driven by a first power source and a second chip designed with a second device driven by a second power source. A power applying section applies first power to the first device of the first chip and a power converting section converts the first power to second power upon receiving the first power from the power applying section and applies the second power to the second device of the second chip. It is possible to provide the multi-chip assembly in the form of a package fabricated by stacking chips designed with mutually different devices driven through a single power source. | 2009-09-03 |
| 20090219778 | BACK-GATE DECODE PERSONALIZATION - A novel methodology for the construction and operation of logical circuits and gates that makes use of and contact to a fourth (4 | 2009-09-03 |
| 20090219779 | Dual Channel Memory Architecture Having a Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals - Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals. | 2009-09-03 |
| 20090219780 | Mixing System Including a Flexible Bag, Specific Flexible Bag and Locating System for the Mixing System - Mixing system comprising: | 2009-09-03 |
| 20090219781 | MIXING DRIER HAVING A SPHERICAL MIXING VESSEL - A mixing drier in the form of a spherical mixer comprises an upper vessel shell and a lower vessel shell which can be closed together in a separation plane. A stirrer having a stirrer shaft and stirring elements is affixed to the upper vessel shell. The stirrer axis is inclined to the vertical. The separation plane is perpendicular to the stirrer axis. The stirring elements are located below the separation plane. A hinge is located in the separation plane and allows the vessel of the spherical mixer to be opened for cleaning. | 2009-09-03 |
| 20090219782 | Mixing Blade With Removable Wearing Element - The invention relates to a mixing blade ( | 2009-09-03 |
| 20090219783 | Method of Conducting a Seismic Survey - A method of conducting a seismic survey of an area including a region of high seismic velocity regimes in a shallow overburden. According to the method, a zone is identified in which the boundary of the high seismic velocity region has a substantially constant critical angle and a course is plotted through the identified zone. A zone based directional seismic source is applied sequentially, with a directivity angle equal to or close to the measured critical angle. The response is detected using receivers. | 2009-09-03 |
| 20090219784 | Method and Apparatus for Investigating a Borehole with a Caliper - Embodiments of the present invention relate to a caliper and method for mapping the dimensions and topography of a formation such as the sidewall of a borehole. Examples of formations in which embodiments of the invention can be used include, but are not limited to, an oil, gas, pile borehole or barrette that has been drilled or excavated into the earth. | 2009-09-03 |
| 20090219785 | METHOD AND SYSTEM FOR DETERMINING THE LOCATION AND/OR SPEED OF AT LEAST ONE SWIMMER - Method for determining the location and/or speed of at least one swimmer, swimming through water, comprising: —sending acoustic signals through the water, using stationary acoustic transmitter means (AT) having a stationary position, or using mobile acoustic transmitter means (AT′) being carried by said swimmer (S); —receiving the acoustic signals using mobile acoustic receiver means (AR) being carried by said swimmer (S), or using stationary acoustic receiver means (AR′) respectively; —determining the time difference between the time of sending and the time of receiving each acoustic signal; —determining a location and/or speed of said swimmer (S) with respect to said stationary transmitter means (AT) or stationary receiver means (AR′), using said time differences and a predetermined propagation speed of the acoustic signal through the water. | 2009-09-03 |
| 20090219786 | MODEM AND METHOD FOR TRANSMITTING DATA IN A MEDIUM NOTABLY SUCH AS AIR AND WATER - A method for transmitting data is disclosed having the following steps: emitting packets of at least two types: pure data (long packets) and acknowledgments of receipt (acknowledgment ) (short packets). Each packet is formed of three components: a—an acquisition preamble, (1) for presence detection and the joint determination of the initial values of the time shift and of the frequency shift, and b—the data proper, (2) and c—a set of unmodulated fixed carriers (3) making it possible to permanently estimate the frequency shift. | 2009-09-03 |
| 20090219787 | TIMER FOR BRUSHING TEETH - A timer for brushing teeth, comprising a timer having a knob, said timer capable of alerting a user after the elapse of a user-determined time period, and a toy body covering said timer having a mouth portion, said mouth portion coupled to said knob, wherein said user-determined time period is determined by the user by turning said mouth portion by a user-determined number of degrees. | 2009-09-03 |
| 20090219788 | Combination watch and cell phone foldable onto each other for use around a wrist of a user - A combination watch and cell phone foldable onto each other for use around a wrist of a user. The combination includes a watch, a cell phone, a band, and apparatus selectively maintaining the watch and the cell phone folded against each other and the band. The band is engages around the wrist of the user. The watch is operatively connected to the band so as to form a wristwatch. The cell phone is operatively connected to the band. | 2009-09-03 |
| 20090219789 | Linear Fluid Timepiece - The present invention provides a timepiece wherein the passage of time is represented by the movement of a fluid column from within an inner tube to a space between the inner tube and a concentric outer tube. In one embodiment, the timepiece includes a display mechanism adapted to adjust a fluid column height based on a capacitance proportional to the fluid column height. | 2009-09-03 |
| 20090219790 | MAGNETO OPTICAL DEVICE - In a magneto optical device is which a laser beam is shone in operation through a coil ( | 2009-09-03 |
| 20090219791 | OPTICAL DISC APPARATUS AND TRACKING CONTROL METHOD - According to one embodiment, an optical disc apparatus includes track error signal generation module for generating, on the basis of a detection result by a light detection module, a second track error signal which is used for tracking control, wherein the track error signal generation module includes module for extracting low-frequency components of signals which are detected by light-receiving units of the light detection module and performing a subtraction between the low-frequency components, thereby generating a first track error signal, extraction module for extracting high-frequency components of the signals which are detected by the light-receiving units detection module for detecting envelope signals of the high-frequency components, module for generating a compensation signal by performing an addition of the envelope signals or a subtraction between the envelope signals, and compensation module for compensating the first track error signal by using the compensation signal thereby generating the second track error signal. | 2009-09-03 |
| 20090219792 | DATA REPRODUCING DEVICE AND DATA REPRODUCING METHOD - According to one embodiment, a data reproducing device according to the invention includes a frequency difference detector, a phase comparator, a loop filter, an integrator, a first conversion part for converting a value of the integrator into a first conversion value, a second conversion part for converting the value of the integrator into a second conversion value, a first conversion table, a second conversion table, a first D/A converter (DAC), a second D/A converter (DAC), a voltage controlled oscillator (VCO), and a prediction table. The value of the integrator and the first conversion value are associated with each other and stored in the first conversion table in consideration of the characteristics of the VCO. Meanwhile, the value of the integrator and the second conversion value are associated with each other and stored in the second conversion table in consideration of the characteristics of the VCO. | 2009-09-03 |
| 20090219793 | METHOD OF SETTING WRITE STRATEGY PARAMETERS, AND RECORDING AND REPRODUCING APPARATUS FOR PERFORMING THE METHOD - A method of setting write strategy parameters includes recording predetermined data on a disk loaded in a disk drive using write strategy parameters stored in a memory; adaptively equalizing a reproduction signal obtained by reproducing the recorded predetermined data from the disk; Viterbi decoding the adaptively equalized signal using a reference level; generating an ideal reproduction signal using the predetermined data, the Viterbi decoded signal, and the reference level; detecting a difference between the adaptively equalized signal and the ideal reproduction signal; generating a selection signal using the predetermined data and the Viterbi decoded signal; processing the difference using a predetermined function to detect a write strategy feedback error; and updating the write strategy parameters stored in the memory at an address specified by the selection signal using the write strategy feedback error. | 2009-09-03 |
| 20090219794 | PICKUP APPARATUS AND DISC APPARATUS INCLUDING THE SAME - A pickup apparatus including: at least a coil constituting an actuator, a signal to be sent to the coil being obtained by calculation using an algorithm on the basis of at least one of a focus error signal and a tracking error signal. | 2009-09-03 |
| 20090219795 | Optical Head and Optical Disk Drive - An optical head reduces, upon signal reproducing from a recording layer of an optical disc ( | 2009-09-03 |
| 20090219796 | RECORD CARRIER IDENTIFICATION USING ASYMMETRY MODULATION - Record carrier identification information is stored using an asymmetry modulation. This prevents the access to this information through the regular data path of the playback device. The asymmetry information is automatically removed by the playback device because of the inherent data slicing and decoding that takes place in the play back device. A parameter of the asymmetry modulation is used to verify that the record carrier is authentic and not a duplicated record carrier. The parameter is disturbed by duplication processes and thus provides a reliable difficult to circumvent indication of authenticity of the record carrier. | 2009-09-03 |
| 20090219797 | SIGNAL REGENERATOR - Pulses that are generated from multiple analog input signals are sampled, and signal elements contained in the analog signals are extracted accurately using the said sampling pulses. Binarization circuits where analog input signals A, B, C, and D are converted into pulse signals; a logic operation circuit that generates a sampling pulse upon receiving the input of the 4 pulse signals; and a sample-and-hold circuit samples and holds an input RF signal based on the sampling pulse in order to extract accurately signal elements contained in said RF signal by means of sampling of the RF signal. | 2009-09-03 |
| 20090219798 | REPRODUCTION METHOD AND HOLOGRAM RECORDING MEDIUM - Disclosed is a reproduction method for a hologram recording medium on which information is recorded with interference fringes of signal light and reference light, including: generating, based on light from a first light source, the reference light and coherent light caused to have uniform amplitude and phase, and irradiating the hologram recording medium with the reference light and the coherent light, the hologram recording medium including a recording layer on which the information is recorded with the interference fringes of the signal light and the reference light, a first reflection film formed on a lower surface side of the recording layer, and a gap layer formed between the recording layer and the first reflection film; and receiving the coherent light and a reproduction image that corresponds to recording information and is obtained as reflection light from the hologram recording medium through light irradiation in the light irradiation step, and reproducing the information based on a result of the light received. | 2009-09-03 |
| 20090219799 | OPTICAL PICKUP DEVICE AND RECORDING/REPRODUCING DEVICE - An optical pickup device has a near-field optical system having a numerical aperture of NA>1; a first light source emitting a first light having a first wavelength; a second light source emitting a second light having a second wavelength; an optical system multiplexing the first light and second light and irradiating the multiplexed light onto an optical recording medium having at least two recording layers; a first photodetector detecting the first light returned from the recording medium a second photodetector detecting the second light returned from the recording medium; a controller obtaining a signal corresponding to distance between the near-field optical system and the recording medium based on the returned second light, and obtaining a reproducing signal and a tracking signal of the recording medium and a focus signal corresponding to the recording layer based on the returned first light; and a focus position adjustment mechanism moving a focus position of the first light under control of the focus signal. | 2009-09-03 |
| 20090219800 | Transmission Method with Optimal Power Allocation Emitted for Multicarrier Transmitter - A transmission method ( | 2009-09-03 |
| 20090219801 | TRANSMITTER IN FDMA COMMUNICATION SYSTEM AND METHOD FOR CONFIGURING PILOT CHANNEL - The present invention relates to a transmitter in a frequency division multiple access communication system. The transmitter generates a plurality of pilot symbols, and groups the plurality of pilot symbols into a plurality of groups according to a location of a subcarrier. In addition, the transmitter inverse fast Fourier transforms the pilot symbol in each group, and sequentially outputs a first pilot symbol sequence corresponding to each group. The transmitter generates a plurality of pilot blocks respectively corresponding to the plurality of groups, and converts the first pilot symbol sequence of each group into a second pilot symbol sequence of a corresponding pilot block among the plurality of pilot blocks. | 2009-09-03 |
| 20090219802 | APPARATUS AND METHOD FOR TRANSMITTING DATA USING A PLURALITY OF CARRIERS - The present invention relates to a data transceiving method in a communication system based on a plurality of carriers, and more particularly, to a method of designing a sequence in a communication system using orthogonal subcarriers. The present invention includes the steps of generating a time-domain sequence with a specific length in a time domain, generating a frequency-domain sequence by performing a DFT or FFT operation on the time-domain sequence according to a length of the generated sequence, including a DC subcarrier and a guard subcarrier in the frequency-domain sequence, and performing an IDFT or IFFT operation on the frequency-domain sequence including the DC subcarrier and the guard subcarrier. | 2009-09-03 |
| 20090219803 | ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING WIRELESS COMMUNICATION OPERABLE ON FREQUENCY SELECTIVE CHANNEL, AND CHANNEL COMPENSATION METHOD - Disclosed is an OFDM (orthogonal frequency division multiplexing) wireless communication system operable on a frequency selective channel, and a channel compensation method. An IDFT (inverse discrete Fourier transform) unit of a transmitter includes first through third N-point IDFT units, and performs IDFT on a binary information signal twice. A DFT (discrete Fourier transform) unit of a receiver includes first through third N-point DFT units, a channel predictor and interpolator, and a channel compensator, and performs DFT on the signal received from the transmitter twice. | 2009-09-03 |
| 20090219804 | ROUTING PROTOCOLS FOR ACCOMMODATING NODES WITH REDUNDANT ROUTING FACILITIES - Graceful restart in routers having redundant routing facilities may be accomplished by replicating network (state/topology) information. | 2009-09-03 |
| 20090219805 | COOPERATIVE TCP / BGP WINDOW MANAGEMENT FOR STATEFUL SWITCHOVER - A system and method for performing stateful switchover with reduced data, such as only metadata about a TCP window state. The metadata comprises a size of TCP packets used to send BGP messages, and which of those have been acknowledged by a neighbor networking device. The networking device comprises a BGP module to establish a BGP session between the networking device and a neighbor networking device. An active transport module within the networking device synchronizes with a standby transport module within the networking device by sending the metadata. A fault detector within the networking device initiates a stateful switchover from the active transport module to the standby transport module responsive to detecting a failure of a process and/or processor. The standby transport module uses the metadata to determine stateful metadata for preserving current BGP and TCP sessions of the networking device. | 2009-09-03 |
| 20090219806 | METHOD, APPARATUS, AND SYSTEM FOR PROTECTING HEAD NODE OF POINT TO MULTIPOINT LABEL SWITCHED PATH - A method for protecting the head node of a Point to Multipoint Label Switched Path (P2MP LSP) includes: a Backup Head Node (BHN) establishes a backup LSP from the BHN to all Merge Points (MPs), where the backup LSP bypasses a Master Head Node (MHN); the MHN forwards data along an LSP already established between the MHN and the MPs; when a head node switchover condition is met, the BHN is switched to a master mode to forward data along the backup LSP established between the BHN and the MPs. A system and apparatus for protecting the head node are also provided. With the head node protection solution provided by the present disclosure, the head node is well protected and the protection mechanisms for the P2MP LSP are therefore more complete. This can further promote the scale deployment of P2MP systems. | 2009-09-03 |
| 20090219807 | METHOD AND ROUTER FOR CONTROLLING GRACEFUL RESTART STATUS - A method for controlling the Grace Restart (GR) status is disclosed. The method includes: entering a GR status when a router detects that neighbor relationship with a neighbor router breaks and the router itself does not restart; receiving a neighbor relationship establishing message sent by the neighbor router; and quitting the GR status when the router detects that the message does not indicate a restart of the neighbor router. A router is also disclosed. The router includes a neighbor relationship testing module restart testing module, a relationship message receiving and processing module and a GR module. The solution is able to detect timely that a router mistakenly enters a Grace Restart status. Thus, unnecessary signaling and data interaction are reduced, and CPU resource is less occupied. In addition, a newly generated routing can be delivered to the LSP, which improves the rate of a success data transfer. | 2009-09-03 |
| 20090219808 | LAYER-2 RING NETWORK SYSTEM AND MANAGEMENT METHOD THEREFOR - Disclosed is a ring network in which ring domains are managed in ring forms, layer | 2009-09-03 |
| 20090219809 | Redundant mux cnfiguration - A system and method in accordance with the principles of the present invention prevents data from being permanently lost when external interference causes packet loss, and the interference is long enough in duration to cause adjacent packets to be lost. A data packet stream is transmitted. A redundant data packet stream also is transmitted so that any interference does not cause permanent packet loss, since either the original data packet stream or the redundant data packet stream arrives. In one embodiment, the redundant data packet stream is a delayed transmission. In another embodiment, the data packet stream is transmitted over one link and the redundant data packet stream is transmitted over another link. One implementation of the present invention includes a hybrid multiplexer and redundant communications links. When performance of one link degrades, the hybrid multiplexer switches the traffic to the other link. | 2009-09-03 |
| 20090219810 | IMPLICIT RESERVATION OF RESOURCES IN A POINT-TO-MULTIPOINT OR MULTI-POINT-TO-MULTIPOINT NETWORK - A point-to-multipoint or multipoint-to-multipoint communication network comprises at least one management center and remote traffic stations, between which radio links sharing resources allocated dynamically by the management center have been established. Each traffic station is tasked, whenever it needs additional resources to increase the useful traffic (UT) that it must transmit to the management center, with adding to the current useful traffic (UT) a first traffic (ST), known as smoothing traffic and representative of a selected margin, and a second traffic (AT), known as anticipated traffic and representative of an anticipated need for additional resources, in order to implicitly solicit the management center, then with determining whether additional resources were allocated by the management center, and, if additional resources were allocated, to increase the useful traffic (UT) by an amount corresponding as much as possible to the sum of the resources corresponding to the first traffic (ST) and allocated additional resources. | 2009-09-03 |
| 20090219811 | In-Bound mechanism that monitors end-to-end QOE of services with application awareness - A method of monitoring end-to-end QOE of services with application awareness, including one or more of the following: building an application specific service ping packet having an application identification field that identifies an application to which the application specific service ping packet corresponds; forwarding the application specific service ping packet towards a destination in a network; determining requested application-specific performance and resource metrics; collecting the requested application-specific performance and resource metrics; inserting the requested application-specific performance and resource metrics into the application specific service ping packet; and extracting the service ping packet from the network. | 2009-09-03 |
| 20090219812 | In-bound mechanism that verifies end-to-end service configuration with application awareness - A method of verifying end-to-end service configuration with application awareness, including one or more of the following: building an application specific service ping packet having an application identification field that identifies an application to which the application specific service ping packet corresponds; forwarding the application specific service ping packet towards a destination in a network; determining static configuration information regarding the application to which the application specific service ping packet corresponds at a network interface of a network element; inserting the static configuration information into the application specific service ping packet; determining at least one policy that applies to a flow including the application specific service ping packet; inserting the at least one policy into the application specific service ping packet; and extracting the service ping packet from the network. | 2009-09-03 |
| 20090219813 | Application specific service ping packet - A method of using an application specific service ping packet, and related application specific service ping packet, including one or more of the following: creating the application specific service ping packing including a special packet identification field that identifies the application specific service ping packet as a special packet, and including an application identification field that identifies an application to which the application specific service ping packet corresponds; modifying a deep packet inspection engine to recognize the application specific service ping packet; sending the application specific service ping packet through a deep packet inspection element; identifying the application specific service ping packet as a special packet; determining that the application specific service ping packet can be mapped to a specific application; identifying the specific application; setting an application for processing to the specific application; and performing known application processing based on the set specific application. | 2009-09-03 |
| 20090219814 | Methods and Apparatus for Prioritizing Message Flows in a State Machine Execution Environment - A method and apparatus are provided for prioritizing message flows in a state machine execution environment. A state machine is disclosed that employs a flow graph that provides a flow control mechanism The flow control mechanism defines a plurality of states and one or more transitions between the plurality of states, wherein one or more tokens circulate within the flow graph and execute functions during the one or more transitions between the states The disclosed state machine parses one of the tokens to extract one or more predefined information elements; and assigns a priority to the token based on the extracted information elements and a state occupancy of the token, wherein the assigned priority controls an order in which the token is processed. | 2009-09-03 |
| 20090219815 | Self-Adapting Mechanism for Managing Data Streams in a Multiple Access Shared Network - A method and a system for managing the transmission of data streams by a terminal of a multiple-access shared communications network, said data streams being structured as data frames and comprising at least one priority data stream and at least one non-priority data stream. The method comprises the steps of determining a congestion state of said multiple-access shared network, and managing the transmission by said station of said priority and non-priority data streams as a function of said congestion state. | 2009-09-03 |
| 20090219816 | ACCESS CHANNEL LOAD MANAGEMENT IN A WIRELESS COMMUNICATION SYSTEM - Techniques for managing the load of an access channel in a wireless communication system are described. In an aspect, the load of the access channel may be controlled by having each terminal regulates its use of the access channel (e.g., its rate of system access) based on a rate control algorithm (e.g., token bucket). The rate control algorithm may maintain information on past activities of a terminal and may regulate the use of the access channel by the terminal based on its past activities in order to control the access channel load and achieve fairness. The system may determine at least one parameter value for the rate control algorithm based on load conditions and may broadcast the at least one parameter value to terminals. Each terminal may regulate its use of the access channel based on the at least one parameter value received from the system. | 2009-09-03 |
| 20090219817 | METHOD AND APPARATUS FOR REDUCING FLOOD TRAFFIC IN SWITCHES - An improved method and apparatus for making forwarding decisions in a switching device. The invention reduces the flooding of frames to particular network segments connected to the switch. To insure a device sees a frame addressed to it, if a switch does not know what segment a device address is connected to for a unicast frame, the switch typically floods the frame to all segments in the broadcast domain. This invention allows segments to be identified as having a predefined maximum number of device addresses that will be associated with it. When that number of addresses is already in the forwarding table the switch will not flood unicast frames to that segment since no more devices should be connected to that segment. | 2009-09-03 |
| 20090219818 | NODE DEVICE, PACKET SWITCH DEVICE, COMMUNICATION SYSTEM AND METHOD OF COMMUNICATING PACKET DATA - A node device including a congestion detection unit which detects an occurrence and release of congestion for each class of a second communication quality classification, output to a ring-type network, when packet data for each class classified by a first communication quality classification received from a port; a class association table which stores association between each class of the second communication quality classification and each class of the first communication quality classification; a class conversion unit which converts a class of the second communication quality classification detected by the congestion detecting unit into an associated class of the first communication quality classification; and a notification unit which notifies a class of the first communication quality classification to the port as a target data for stopping read out or starting read out is provided. | 2009-09-03 |
| 20090219819 | Supporting an Access to a Destination Network Via a Wireless Access Network - For supporting an access to a destination network by a mobile device via a wireless access network, the mobile device generates a predetermined request, which is addressed to a connectivity test server in the destination network. The predetermined request is transmitted to the wireless access network. In case the predetermined request reaches the connectivity test server, it generates a predetermined response and transmits it to the mobile device via the wireless access network. The mobile device determines whether a response to the predetermined request is received from the wireless access network and whether a received response corresponds to the predetermined response. | 2009-09-03 |
| 20090219820 | Systems and methods for automatic configuration of customer premises equipments - A system for automatically configuring a device which is compatible with the Technical Report TR-069 of the DSL Forum, said system comprising a first automatic configuration server compatible with the Technical Report TR-069 of the DSL Forum, which is adapted and arranged for communicating with said device and for automatically configuring at least part of the configurable parameters of said device, said device by means of the CPE WAN Management Protocol defined in Technical Report TR-069 of the DSL Forum, wherein said system further comprises a proxy server arranged between said device and said automatic configuration server. | 2009-09-03 |
| 20090219821 | SWITCH APPARATUS AND NETWORK SYSTEM - A switch apparatus providing with a loop detection function sets a port identification to a port which activates the loop detection function, only receives the loop detection frame by a high-order port in the switch apparatus connected with a backbone network or a high-order switch apparatus on the basis of the port identification set previously, and controls an inactivation of a sending source low-order port that sent the loop detection frame, when the loop detection frame is received by the high-order port. | 2009-09-03 |
| 20090219822 | Troubleshooting Voice Over WLAN Deployments - A voice over WLAN diagnostic system. In particular implementations, a method includes simulating, in response to a triggering event, Voice over Internet Protocol (VoIP) communications with a remote diagnostics engine; gathering metric data characterizing one or more aspects of the simulated VoIP communications; and periodically transmitting diagnostic packets including the metric data to the remote diagnostics engine; wherein the simulating VoIP communications comprises transmitting diagnostic protocol packets that simulate VoIP communications to the remote diagnostic engine; and intercepting diagnostic protocol packets received from the diagnostics engine. | 2009-09-03 |
| 20090219823 | METHOD AND APPARATUS FOR AUTOMATING HUB AND SPOKE INTERNET PROTOCOL VIRTUAL PRIVATE NETWORK TROUBLE DIAGNOSTICS - A method and apparatus for automating hub and spoke network trouble diagnostics in a communication network are disclosed. For example, the method retrieves provisioning and configuration data, access interface alarm information, and network facility status data related to the communication network by a diagnostic system, and identifies at least one of: a network configuration error, an access interface error, or a configuration error associated with at least one hub router or at least one spoke router, as the root cause of the problem of the communication network. | 2009-09-03 |
| 20090219824 | SYSTEMS, METHODS AND APPARATUS FOR TESTING A DATA CONNECTION PROVIDED OVER A POWER SUPPLY LINE - Systems, methods and apparatus are described for testing a data connection provided over a power supply line. A testing apparatus is coupled to a socket of the power supply line. The AC power supply line communicatively couples the testing apparatus to a communication device or another testing apparatus. The testing apparatus identifies the signal strengths of signals received by the testing apparatus and identifies the signal strengths of signals received by the communication device. The testing apparatus outputs an indicator of the first signal strength and the second signal strength to a user and this information may be utilized to detect noise or other problems in the data connection provided over the AC power supply line. | 2009-09-03 |
| 20090219825 | Endpoint Device Configured to Permit User Reporting of Quality Problems in a Communication Network - An IP telephone or other endpoint device in a network is configured to support a reporting mode of operation that may be entered, for example, responsive to user entry of a report command via a user interface of the endpoint device. In one aspect, the endpoint device stores call information in one or more buffers. Responsive to an instruction to enter a reporting mode, the endpoint device sends contents of the buffer(s) to a report server over the network. The endpoint device may reinitialize the buffer(s) responsive to an instruction to leave the reporting mode. | 2009-09-03 |
| 20090219826 | SYSTEM AND METHOD FOR LIMITING ACCESS TO AN IP-BASED WIRELESS TELECOMMUNICATIONS NETWORK BASED ON ACCESS POINT IP ADDRESS AND/OR MAC ADDRESS - A system and method manages call connections between mobile subscribers and an EP-based wireless telecommunications network through a wireless access point. Communications between the mobile subscribers and the IP-based wireless telecommunications network are initiated by a registration request. During the registration request various identifiers (IMSI, MAC address, IP Address, etc.) are communicated to the system. The system is arranged to log the identifiers and associate those identifiers with the entry point (e.g., the wireless access point) into the IP based wireless network. Call connections from the mobile subscribers are monitored for various throughput and call quality based metrics. Call handoffs between the IP-based wireless communications network and the cellular telephony network are managed by the system based on the monitored call quality and throughput metrics on a per-access point basis using the registered identifiers. | 2009-09-03 |
| 20090219827 | REGISTERED STATE CHANGE NOTIFICATION FOR A FIBRE CHANNEL NETWORK - Disclosed herein are various aspects of a Fibre Channel (Fibre Channel) fabric having switches that employ Registered State Change Notifications (RSCNs) with enhanced payloads. Two types of RSCN message formats are provided, both including status information about the affected device(s). In one embodiment, a RSCN message format for inter-switch communication provides various information about the affected devices according to one of a plurality of predetermined formats. In another embodiment, a node device RSCN message format provides information about a port state, the identification of the affected port, along with the port and node world wide names and the FC-4 types supported by the node. | 2009-09-03 |
| 20090219828 | METHOD AND SYSTEM FOR MANAGING DATA TRANSFER - A method and a system for managing data transfer are provided. The method includes receiving a poll request for a status report on Protocol Data Units (PDUs) transmitted sequentially during the data transfer, determining a status reporting range of the PDUs to be accounted in the status report based on a sequence number in the poll request, and providing the status report with status information on a receipt or a loss of the PDUs within the status reporting range during the data transfer. | 2009-09-03 |
| 20090219829 | METHOD AND APPARATUS FOR NETWORK PACKET CAPTURE DISTRIBUTED STORAGE SYSTEM - This is invention comprises a method and apparatus for Infinite Network Packet Capture System (INPCS). The INPCS is a high performance data capture recorder capable of capturing and archiving all network traffic present on a single network or multiple networks. This device can be attached to Ethernet networks via copper or SX fiber via either a SPAN port ( | 2009-09-03 |
| 20090219830 | THIN DESKTOP LOCAL AREA NETWORK SWITCH - Methods, systems, and apparatuses for an automatically configured network switch are provided. The network switch includes a plurality of ports, a switch fabric, switch control logic, and a switch configuration module. The ports are configured to be coupled to a plurality of network communication links. The switch fabric is coupled to each of the ports, providing interconnections between the ports. The switch control logic is coupled to the switch fabric to provide data path selection and arbitration. The switch configuration module is configured to generate a request for switch configuration information to be transmitted from one or more ports of the switch, over the network, to a switch management server. The switch control logic is configured to configure one or more features of the network switch to operate according to the received configuration information. | 2009-09-03 |
| 20090219831 | Bridge port MAC address discovery mechanism in ethernet networks - Various exemplary embodiments are a method and of discovering medium access control (MAC) addresses in a network and a related access node including one or more of the following: receiving, at an access node, a diagnostic message from an operator, the diagnostic message comprising physical port information and indicating that at least a portion of a MAC address of a destination bridge port is unknown to the operator; forwarding the diagnostic message to a respective bridge port of the access node; determining whether the physical port information specified in the diagnostic message corresponds to a physical port of the respective bridge port; and sending a reply message to the operator specifying a MAC address of the respective bridge port. | 2009-09-03 |
| 20090219832 | FAST CONFIGURATION OF A DEFAULT ROUTER FOR A MOBILE NODE IN A MOBILE COMMUNICATION SYSTEM - The invention relates to a method for fast configuring of a default router for a mobile node in a mobile communication system. A default router is used by a mobile node to transmit outgoing data to. The mobile node moves from a first to a second network area, which are respectively connected to a first and second router. In order to update the default router, after changing an attachment of the mobile node to the network, the new second router is adapted to transmit a notification to the mobile node, for changing its default router to the new router. According to the invention, the second router may also transmit a message to inform the mobile node about an expiration of the old first router. The new router may also send a message, including an indication about a new rust-hop router for the outgoing data of the mobile node. | 2009-09-03 |
| 20090219833 | Autonomous And Heterogeneous Network Discovery And Reuse - In some embodiments, a method is disclosed involving a mobile device discovery and use of target wireless networks which are at least partly within a coverage area of another wireless network which provides location information which includes: acquiring data from a plurality of said target wireless networks; acquiring location information from said another wireless network; mapping said data from said plurality of said target wireless networks with said location information; and selecting one of said plurality of target wireless networks based on said mapped data. | 2009-09-03 |
| 20090219834 | Dynamic Configuration of IP for a Terminal Equipment Attached to a Wireless Device - Techniques for dynamically configuring IP and providing IP connectivity for a terminal equipment attached to a wireless device are described. The wireless device obtains from a wireless network a dynamically assigned IP address, an IP gateway's IP address, a subnet mask, or none or any combination thereof. Wireless device determines a host IP address (which may be the dynamically assigned IP address), a router IP address (which may be the gateway IP address or a spoofed IP address), a server IP address (which may be the router IP address), and a subnet mask (which may be obtained from the wireless network or spoofed by the wireless device). Wireless device, acting as a DHCP server, provides IP configuration for the terminal equipment, acting as a DHCP client. Wireless device thereafter forwards IP packets exchanged between the terminal equipment and wireless network and processes DHCP packets from the terminal equipment. | 2009-09-03 |
| 20090219835 | Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes - Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights. | 2009-09-03 |
| 20090219836 | DISTRIBUTED SPANNING TREE PROTOCOL ON A MULTI CHASSIS PORT CHANNEL - In one embodiment, a technique for routing traffic in networks represented by logical topologies, such as Multi Chassis Port Channel (MCPC) or Multi Chassis Ether Channel (MCEC) topologies, is provided. By modifying a port priority vector (PPV) to include an additional “Switch ID” field that identifies a designated bridge ID or a local switch ID, depending on whether the corresponding port is used as an MCT, a routing protocol designed to avoid loops in routing paths, such as STP, may avoid blocking MCT ports. | 2009-09-03 |
| 20090219837 | SIGNAL TRANSCEIVE FOR WIRELESS COMMUNICATION DEVICE - A signal transceiver for saving the production cost of a wireless communication device includes an antenna, an antenna switch module, a radio frequency (RF) transceiver, an RF front-end circuit, a first selection unit and a second selection unit. The signal transceiver uses the RF front-end circuit unit to meet requirements of multi-band for the wireless communication device through the operation of the first selection unit and the second selection unit to greatly reduce the production cost of the wireless communication device. | 2009-09-03 |
| 20090219838 | CLOSED-LOOP MIMO SYSTEMS AND METHODS - Methods, devices and systems are provided for transmitting and receiving MIMO signals. Transmitting of the MIMO signals involves pre-coding each of at least two data symbols using a respective pre-coding codeword to preclude a corresponding plurality of pre-coded data symbols. A respective signal is transmitted from each of a plurality of antennas, the respective signal including one of the pre-coded signals and at least one pilot for use in channel estimation. The signals collectively further include at least one beacon pilot vector consisting of a respective beacon pilot per antenna, the beacon pilot vector containing contents known to a receiver for use by the receiver in determining the codeword used to pre-code the at least one data signal. Receiving of the MIMO signals involves receiving a MIMO signal containing data symbols pre-coded with a codeword. The MIMO signal includes pilots, and including at least one beacon pilot vector containing contents known to a receiver/each beacon pilot vector containing one symbol from each transmit antenna. Processing is performed on the at least one beacon pilot vector to determine which codeword was used to pre-code the data symbols. | 2009-09-03 |
