| 36th week of 2009 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20090218539 | POLYMER-BONDED MAGNETIC MATERIALS - A magnetic composition for power conversion includes a thermoplastic polymer and magnetic powders. The composition has a tensile strength of greater than 20 N/nm | 2009-09-03 |
| 20090218540 | ROTATING MACHINE, BONDED MAGNET, MAGNET ROLL, AND METHOD FOR PRODUCING SINTERED FERRITE MAGNET - A rotating machine comprising a sintered ferrite magnet having an M-type ferrite structure, comprising Ca, an R element that is at least one of rare earth elements and indispensably includes La, Ba, Fe and Co as indispensable elements, and having a composition represented by the formula: Ca | 2009-09-03 |
| 20090218541 | Deicing and Anti-Icing Compositions Comprising Renewably-Based, Biodegradable 1,3-Propanediol - Disclosed herein are deicing and anti-icing compositions comprising 1,3-propanediol, wherein the 1,3-propanediol in said deicing or anti-icing composition has a bio-based carbon content of about 1% to 100%. In addition, it is preferred that the 1,3-propanediol be biologically-derived, and wherein upon biodegradation, the biologically-derived 1,3-propanediol contributes no anthropogenic CO | 2009-09-03 |
| 20090218542 | ANISOTROPIC SILICON ETCHANT COMPOSITION - An etchant composition contains (a) an alkaline compound mixture of an organic alkaline compound and inorganic alkaline compound and (b) a silicon-containing compound. The organic alkaline compound is composed of one or more ingredients from quaternary ammonium hydroxide and ethylenediamine. The inorganic alkaline compound is composed of one or more ingredients from sodium hydroxide, potassium hydroxide, ammonia and hydrazine. The silicon-containing inorganic compound is composed of one or more ingredients from metal silicon, fumed silica, colloidal silica, silica gel, silica sol, diatomaceous earth, acid clay and activated clay, and the silicon-containing organic compound is composed of one or more ingredients from quaternary ammonium salts of alkyl silicate and quaternary ammonium salts of alkyl silicic acid. | 2009-09-03 |
| 20090218543 | CATALYTIC NANOPARTICLES FOR NERVE-AGENT DESTRUCTION - The present invention relates to compositions and methods for sorbing (e.g., adsorption and chemisorption) and destroying organophosphate chemical agents. In certain embodiments, the invention contemplates the use of finely divided, modified nanoscale metal oxide particles. In one embodiment, a suspension of magnetite (Fe | 2009-09-03 |
| 20090218544 | BLEACHING COMPOSITION COMPRISING AN ALKOXYLATED BENZOIC ACID - The present invention relates to a liquid bleaching composition comprising a hypohalite bleach, a trimethoxy benzoic acid or a salt thereof and a compound selected from the group consisting of bleach-unstable brighteners, and bleach-unstable coloring-agents and mixtures thereof. | 2009-09-03 |
| 20090218545 | Use and Method for Reduction of Corrosion - The invention relates to a use of a composition containing polyorganosiloxane S and a method of reducing corrosion on steel reinforcement in reinforced concrete constructions, and also a concrete structure which is produced using such compositions. It is highly suitable for the renovation of old concrete but also for inhibition of corrosion of reinforcing iron in fresh concrete. | 2009-09-03 |
| 20090218546 | Corrosion-Reducing Composition and Use Thereof - The invention relates to a composition which comprises at least one liquefying agent for a hydraulic composition and at least one aminoalcohol, selected from the group consisting of 2-amino-2-methyl-1-propanol and N-aminopropyl-monomethyl ethanolamine. The invention also relates to the use of said composition for reducing corrosion, especially on steel formwork in precast components or on concrete steel of concrete constructions. | 2009-09-03 |
| 20090218547 | METHODS, COMPOSITIONS, AND KITS FOR PROTEIN CRYSTALLIZATION - The present invention provides methods, compositions, and kits for protein crystallization. The present invention involves electrophoretically focusing at least a first protein species within a matrix comprising at least 2 regions of different pH, the protein being present in amount sufficient to permit crystallization within said pH gradient. | 2009-09-03 |
| 20090218548 | Electroconductive polymer material, producing method of electroconductive polymer material and electrode material - An electro-conductive polymer material of the present invention is formed by forming a at least one layer | 2009-09-03 |
| 20090218549 | Nanocarbon film and producing method thereof - A nanocarbon film that is produced in such a manner that, after a nanocarbon dispersion containing nanocarbon and a dispersant is used to form a film containing the nanocarbon and the dispersant, an external stimulus is applied to the film to at least partially decompose the dispersant contained in the film. Light irradiation is preferably applied as the external stimulus. | 2009-09-03 |
| 20090218550 | Single-Source Precursor for Semiconductor Nanocrystals - A process for preparing a single source solid precursor matrix for semiconductor nanocrystals having the steps of: mixing 0.1-1 Molar of an aqueous/non-aqueous (organic) solution containing the first component of the host matrix with 0.001-0.01 Molar of an aqueous/non-aqueous solution containing the first dopant ions, which needs in situ modification of valency state, dissolving 10-20 milligram of an inorganic salt for the in situ reduction of the first dopant ion in the solution, addition of 0.001-0.01 Molar of an aqueous/non-aqueous solution of an inorganic salt containing the dopant ions which do not need modifications of their valency state, addition of 0.1-1 Molar of an aqueous/non-aqueous solution of an inorganic salt containing the second component of the host material, addition of 5-10% by weight of an aqueous solution containing a pH modifying complexing agent, to obtain a mixture, and heating the mixture to obtain a solid layered micro-structural precursor compound. | 2009-09-03 |
| 20090218551 | BULK THERMOELECTRIC COMPOSITIONS FROM COATED NANOPARTICLES - The invention provides a dense bulk thermoelectric composition containing a plurality of nanometer-sized particles of a thermoelectric material. The bulk composition provides thermoelectric power up to 550 μV/° C. In some embodiments, the surface of each particle is coated by another thermoelectric material. The size of the particles ranges from about 5 nm to about 500 nm. The density of thermoelectric composition ranges from about 80% to about 100% of theoretical density. | 2009-09-03 |
| 20090218552 | Method of Producing Portland Cement Having Electrical Conduction and Optical Properties - A method of producing conductive and/or translucent Portland cement which has high sulphate resistance and a service life of up to 70 years under normal service conditions. Once cement has set, light can pass therethrough. Up to 70% of the final resistance of the cement is reached within 48 hours of setting. The inventive production method is characterised in that it produces a fineness of more than 3450 cm2/g and in that, upon setting, the concrete has a mechanical strength of between 26 MPa and 250 MPa, without the addition of additives, thereby enabling a reduction in the water required to obtain a determined slump. | 2009-09-03 |
| 20090218553 | Electromagnetic Wave Absorption Material for Thermoforming - The present invention is to provide an electromagnetic wave absorption (EWA) material for thermoforming having a good formability and high EWA performance. The EWA material for thermoforming contains a EWA particle covered with a thermoplastic resin layer. | 2009-09-03 |
| 20090218554 | CABLE GUARDRAIL SYSTEM AND HANGER - A hanger for a cable guardrail system is disclosed including a first portion with first and second seats on opposite sides of a post each seat capable of supporting a cable, and a second portion capable of engaging the end of the post. Also disclosed is a cable guardrail system including a plurality of posts, a plurality of hangers attached to at least a portion of the plurality of posts, and at least two cables supported by the seats on opposite sides of the post. The cable guardrail system may redirect an impacting vehicle and dissipate a portion of the impacting vehicle's energy. | 2009-09-03 |
| 20090218555 | POLYMER FENCING SECUREMENT SYSTEM - A system for securing polymer fencing to at least two fence posts or similar support structures spaced apart at defined intervals. The system includes an elongated polymer fencing member having first and second opposed ends. The polymer fencing member extends across the at least two fence posts. The system also includes a retainer for securing the first end of the polymer fencing member to one of the at least two fence posts. In use, the system prevents the application of a twisting force to the at least two fence posts when tension is applied to the polymer fencing member. A related method for securing polymer fencing to a fence post to prevent the fence post from twisting when tension is applied to the polymer fencing is also disclosed. | 2009-09-03 |
| 20090218556 | INTEGRATED CIRCUIT FABRICATED USING AN OXIDIZED POLYSILICON MASK - An integrated circuit includes a first electrode, a second electrode, and dielectric material including an opening. The opening is defined by etching the dielectric material based on an oxidized polysilicon mask formed using a keyhole process. The integrated circuit includes resistivity changing material deposited in the opening and coupled between the first electrode and the second electrode. | 2009-09-03 |
| 20090218557 | Phase change memory device and fabrication method thereof - A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer. | 2009-09-03 |
| 20090218558 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate. | 2009-09-03 |
| 20090218559 | Integrated Circuit, Memory Cell Array, Memory Module, and Method of Manufacturing an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit is provided including a plurality of magneto-resistive memory cells. Each memory cell includes a magnetic tunneling junction stack, wherein the top surfaces of the magnetic tunneling junctions stacks are electrically connected to a common continuous conductive plate. | 2009-09-03 |
| 20090218560 | METHOD FOR REVERSIBLY MOUNTING A DEVICE WAFER TO A CARRIER SUBSTRATE - New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds formed by this method are chemically and thermally resistant, but can also be softened, dissolved, or mechanically disrupted to allow the wafers to be easily separated with very low forces and at or near room temperature at the appropriate stage in the fabrication process. | 2009-09-03 |
| 20090218561 | Organic electroluminescence element - An organic electroluminescence element including at least two light-emitting layers disposed between an anode and a cathode, wherein the at least two light-emitting layers include a light-emitting layer A that contains an electron transporting light-emitting material and a hole transporting host material, wherein a concentration of the electron transporting light-emitting material gradually increases from an anode side toward a cathode side of the light-emitting layer A, and a light-emitting layer B that contains a hole transporting light-emitting material and an electron transporting host material, wherein a concentration of the hole transporting light-emitting material gradually decreases from an anode side toward a cathode side of the light-emitting layer B. An organic EL element with high light-emission efficiency and excellent durability is provided. | 2009-09-03 |
| 20090218562 | High brightness light emitting diode with a bidrectionally angled substrate - A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer, and the ( | 2009-09-03 |
| 20090218563 | NOVEL FABRICATION OF SEMICONDUCTOR QUANTUM WELL HETEROSTRUCTURE DEVICES - A device employing a quantum well structure having a pattern that is defined by a photolithographically patterned top gate electrode. By defining the active area of the quantum well structure by the patterning of the top gate electrode there is no need to pattern the quantum well structure itself, such as by etching or other processes. This advantageously allows the active are of the quantum well structure to be patterned to a very small size, without the damaging edge effects associated with the patterning of the quantum well structure itself. | 2009-09-03 |
| 20090218564 | Alternating copolymers of phenylene vinylene and biarylene vinylene, preparation method thereof, and organic thin flim transister comprising the same - Disclosed herein are an alternating copolymer of phenylene vinylene and biarylene vinylene, a preparation method thereof, and an organic thin film transistor including the same. The organic thin film transistor maintains low off-state leakage current and realizes a high on/off current ratio and high charge mobility because the organic active layer thereof is formed of an alternating copolymer of phenylene vinylene and biarylene vinylene. | 2009-09-03 |
| 20090218565 | RESISTANCE VARIABLE ELEMENT - A resistance variable element is provided, which is capable of performing bipolar operation by a specified mechanism and usable as a memory. The resistance variable element has a laminated structure including an electrode, an electrode, an oxide layer between the electrodes, and an oxide layer in contact with the oxide layer between the oxide layer and the electrode. The oxide layer is switchable from the low-resistance state to the high-resistance state by donating oxygen ions to the oxide layer, and from the high-resistance state to the low-resistance state by accepting oxygen ions from the oxide layer. The oxide layer is switchable from the low-resistance state to the high-resistance state by accepting oxygen ions from the oxide layer, and from the high-resistance state to the low-resistance state by donating oxygen ions to the oxide layer. | 2009-09-03 |
| 20090218566 | LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. | 2009-09-03 |
| 20090218567 | CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING THE SAME - A method for making a semiconductor device ( | 2009-09-03 |
| 20090218568 | THIN FILM TRANSISOTR AND DISPLAY DEVICE - To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added. | 2009-09-03 |
| 20090218569 | Display device - The present invention realizes a display device with dummy pixel portions and a frame region required for the dummy pixel portions and code notation, in which the frame region is minimized while achieving code notation in required size. | 2009-09-03 |
| 20090218570 | THIN FILM TRANSISTOR AND FLAT PANEL DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor includes a channel layer including an amorphous 12CaO.7Al | 2009-09-03 |
| 20090218571 | ACTIVE DEVICE ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF - A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode. | 2009-09-03 |
| 20090218572 | THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers. | 2009-09-03 |
| 20090218573 | Electric Device - There is provided an electric device which can prevent a deterioration in a frequency characteristic due to a large electric power external switch connected to an opposite electrode and can prevent a decrease in the number of gradations. The electric device includes a plurality of source signal lines, a plurality of gate signal lines, a plurality of power source supply lines, a plurality of power source control lines, and a plurality of pixels. Each of the plurality of pixels includes a switching TFT, an EL driving TFT, a power source controlling TFT, and an EL element, and the power source controlling TFT controls a potential difference between a cathode and an anode of the EL element. | 2009-09-03 |
| 20090218574 | Display device and manufacturing method therefor - A display device includes a thin film transistor above a substrate, in which the thin film transistor is configured to include a gate electrode, a gate insulating film formed to cover the gate electrode, a semiconductor layer formed to stride over the gate electrode on the gate insulating film, an inter-layer insulating film formed to cover the semiconductor layer, and a pair of electrodes formed to be connected to each of sides of the semiconductor layer interposing the gate electrode therebetween through contact holes formed through the inter-layer insulating film, high concentration impurity layers are formed at each connecting portion of the electrodes of the semiconductor layer, and an annular low-concentration impurity layer is formed to surround at least one of the high concentration impurity layers. | 2009-09-03 |
| 20090218575 | Display device and manufacturing method thereof - Provided is a display device including a p-type thin film transistor formed on a substrate, in which the p-type thin film transistor includes: a gate electrode; a drain electrode; a source electrode; an insulating film; a semiconductor layer formed on a top surface of the gate electrode through the insulating film; and diffusion layers of p-type impurities formed at each of an interface between the drain electrode and the semiconductor layer and an interface between the source electrode and the semiconductor layer, the drain electrode and the source electrode being formed so as to be opposed to each other with a clearance formed therebetween on a top surface of the semiconductor layer. | 2009-09-03 |
| 20090218576 | THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers. | 2009-09-03 |
| 20090218577 | HIGH THROUGHPUT CRYSTALLIZATION OF THIN FILMS - Under one aspect, a method of processing a film includes defining a plurality of spaced-apart regions to be crystallized within a film, the film being disposed on a substrate and capable of laser-induced melting; generating a sequence of laser pulses having a fluence that is sufficient to melt the film throughout its thickness in an irradiated region, each pulse forming a line beam having a length and a width; continuously scanning the film in a first scan with a sequence of laser pulses at a velocity selected such that each pulse irradiates and melts a first portion of a corresponding spaced-apart region, wherein the first portion upon cooling forms one or more laterally grown crystals; and continuously scanning the film in a second time with a sequence of laser pulses at a velocity selected such that each pulse irradiates and melts a second portion of a corresponding spaced-apart region, wherein the first and second portions in each spaced-apart region partially overlap, and wherein the second portion upon cooling forms one or more laterally grown crystals that are extended relative to the one or more laterally grown crystals of the first portion. | 2009-09-03 |
| 20090218578 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an AlN layer, a GaN layer, and an AlGaN layer sequentially formed on a semiconductor substrate. A first opening extends through said GaN layer and said AlGaN layer and exposes part of an upper surface of the AlN layer. A second opening extends through the semiconductor substrate and exposes a part of a lower surface of the AlN layer, in a location facing the first opening. A upper electrode is exposed on an upper surface of the AlN layer in the first opening; and a lower electrode is disposed on a lower surface of the AlN layer in the second opening. | 2009-09-03 |
| 20090218579 | SUBSTRATE HEATING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - In a substrate heating apparatus, thermoelectrons generated by a filament ( | 2009-09-03 |
| 20090218580 | STRUCTURE OF AC LIGHT-EMITTING DIODE DIES - A structure of light-emitting diode (LED) dies having an AC loop (a structure of AC LED dies), which is formed with at least one unit of AC LED micro-dies disposed on a chip. The unit of AC LED micro-dies comprises two LED micro-dies arranged in mutually reverse orientations and connected with each other in parallel, to which an AC power supply may be applied so that the LED unit may continuously emit light in response to a positive-half wave voltage and a negative-half wave voltage in the AC power supply. Since each AC LED micro-die is operated forwardly, the structure of AC LED dies also provides protection from electrical static charge (ESD) and may operate under a high voltage. | 2009-09-03 |
| 20090218581 | ILLUMINATION SYSTEM COMPRISING A RADIATION SOURCE AND A LUMINESCENT MATERIAL - An illumination system, comprising a radiation source ( | 2009-09-03 |
| 20090218582 | OPTICAL DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating an optical device is disclosed. The method comprises the step of forming an optical stack of laminated lenses and a phosphor film therebetween. The method further comprises the step of attaching the optical stack to an LED die. In addition, an optical device fabricated by the above method is also disclosed. | 2009-09-03 |
| 20090218583 | LIGHT-EMITTING DEVICE, ELECTRONIC APPARATUS, AND LIGHT-EMITTING DEVICE MANUFACTURING METHOD - Disclosed is a light-emitting device. The light-emitting device includes an EL layer and a heat dissipation layer. The EL layer includes a first semiconductor layer, a second semiconductor layer, and an active layer, the first semiconductor layer having a first conductivity type that is one of n type and p type, the second semiconductor layer having a second conductivity type that is opposite to the first conductivity type, the active layer being provided between the first semiconductor layer and the second semiconductor layer. The heat dissipation layer has the first conductivity type and is bonded to a side of the EL layer closer to the second semiconductor layer than the first semiconductor layer. | 2009-09-03 |
| 20090218584 | Housing for an Optoelectronic Component, Optoelectronic Component, and Method for Producing a Housing for an Optoelectronic Component - A housing for an optoelectronic component is disclosed, having a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body, wherein the plastic base body is formed from at least one first plastic component and at least one second plastic component. The second plastic component is disposed on the front side of the plastic base body, and is formed from a material that differs from the first plastic component in at least one optical property, and forms an optically functional region of the plastic base body. Further, a method for producing a housing for an optoelectronic component and a light emitting diode component is disclosed. | 2009-09-03 |
| 20090218585 | ALUMINATE PHOSPHOR CONTAINING BIVALENCE METAL ELEMENTS, ITS PREPARATION AND THE LIGHT EMITTING DEVICES INCORPORATING THE SAME - A phosphor can be excited by UV, purple or blue light LED, its production and the light emitting devices. The general formula of the phosphor is Ln | 2009-09-03 |
| 20090218586 | LED LAMP - The present invention relates to a light emitting diode (LED) lamp, and an object of the present invention is to provide an LED lamp in which an LED can be easily exchanged and external vibration can be absorbed to prevent the play thereof. To this end, an LED lamp according to the present invention comprises an LED package having a lead frame; a printed circuit board separated from the LED package and having a conductive pattern formed on a surface thereof facing the lead frame; and a pressing means for pressing the LED package toward the PCB so that the lead frame is in contact with the conductive pattern. | 2009-09-03 |
| 20090218587 | Radiation-Emitting Semiconductor Body with Carrier Substrate and Method for the Production thereof - A radiation-emitting semiconductor body with a carrier substrate and a method for producing the same. In the method, a structured connection is produced between a semiconductor layer sequence ( | 2009-09-03 |
| 20090218588 | CHIP-SCALE PACKAGED LIGHT-EMITTING DEVICES - Light-emitting devices, and related components, systems, and methods associated therewith are provided. A light-emitting device can comprise a light-emitting die comprising a light-generating region capable of generating light and an emission surface through which generated light is capable of being emitted, and a package layer at least partially disposed over at least a portion of the light-emitting die emission surface, wherein the package layer has an aperture through which light from the light-emitting die is capable of being emitted. The light-emitting device can be a chip-scale packaged device where the device area can be less than 3 times the light-emitting die emission surface area and/or the device thickness can be less than 2 times the light-emitting die thickness. | 2009-09-03 |
| 20090218589 | Semiconductor die with reduced thermal boundary resistance - Thermal boundary resistances within nitride semiconductor LEDs are reduced or eliminated by forming a thick nitride epitaxial layer, which can be separated from a growth substrate, and by reducing the number of thermal boundary layers during laser lift-off. The thermal boundary resistances within nitride semiconductor LEDs can also be reduced or eliminated by forming a plurality of thin nitride epitaxial layers. | 2009-09-03 |
| 20090218590 | METHOD OF PRODUCING THIN SEMICONDUCTOR STRUCTURES - A method of making a thin gallium-nitride (GaN)-based semiconductor structure is provided. According to one embodiment of the invention, the method includes the steps of providing a substrate; sequentially forming one or more semiconductor layers on the substrate; etching a pattern in the one or more semiconductor layers; depositing a dielectrics layer; forming a photoresist on a portion of the dielectrics layer, wherein the portion of the dielectrics layer is deposited on the one or more semiconductor layers; depositing a primer; removing the photoresist layer, wherein the primer on the photoresist is also removed; depositing a superhard material, wherein the superhard material forms in the pattern; and removing the substrate. Accordingly, the superhard material may be selectively deposited in only areas where the superhard material is desired. Vertical GaN-based light emitting devices may then be formed by cutting the semiconductor structure. | 2009-09-03 |
| 20090218591 | Method for Connecting Layers, Corresponding Component and Organic Light-Emitting Diode - A method for bonding several layers, which comprise at least one thermally bondable material, by means of a joint layer produced with the aid of thermocompression at least one of the layers comprising a semiconductor material, as well as to a correspondingly manufactured device. Also disclosed is a method for manufacturing an organic light-emitting diode and an organic light-emitting diode that is encapsulated between two cover layers with the aid of thermocompression. | 2009-09-03 |
| 20090218592 | Method of producing encapsulation resins - A process is provided for producing curable polyorganosiloxanes where noble metal oxides are used as hydrosilylation catalysts. The noble metals can be used in solid granular form or as part of a fixed bed, and do not form part of the final curable composition or cured product. The cured polyorganosiloxanes have increased stability and can be used as encapsulation resins at a temperature far lower than 300° C., have excellent light transmission properties (colorless transparency) in a wavelength region of from ultraviolet light to visible light, light resistance, heat resistance, resistance to moist heat and UV resistance, and do not generate cracks and peeling even in use over a long period of time. | 2009-09-03 |
| 20090218593 | Nitride semiconductor light emitting device and method of frabicating nitride semiconductor laser device - There is provided a nitride semiconductor light emitting device having a light emitting portion coated with a coating film, the light emitting portion being formed of a nitride semiconductor, the coating film in contact with the light emitting portion being formed of an oxynitride. There is also provided a method of fabricating a nitride semiconductor laser device having a cavity with a facet coated with a coating film, including the steps of: providing cleavage to form the facet of the cavity; and coating the facet of the cavity with a coating film formed of an oxynitride. | 2009-09-03 |
| 20090218594 | SEMICONDUCTOR LIGHT RECEIVING ELEMENT - A semiconductor photosensitive element comprises: a semiconductor substrate of a first conductivity type; a first light absorption layer, a first semiconductor layer of a second conductivity type, a first semiconductor layer of the first conductivity type, a second light absorption layer, and a second semiconductor layer of a second conductivity type, arranged in this order on the semiconductor substrate; a first electrode connected to the second semiconductor layer of the second conductivity type; a second electrode connected to the semiconductor substrate; and a third electrode electrically connecting the first semiconductor layer of the first conductivity type to the first semiconductor layer of the second conductivity type. The third electrode is located outside a light detection region for detecting optical signals. | 2009-09-03 |
| 20090218595 | SEMICONDUCTOR LIGHT RECEIVING ELEMENT - A semiconductor light detecting element comprises: a semiconductor substrate having a first major surface and a second major surface opposite each other; a first reflective layer, an absorptive layer, a phase adjusting layer, and a second reflective layer sequentially disposed, from the semiconductor substrate, on the first major surface of the semiconductor substrate; and an anti-reflection film on the second major surface of the semiconductor substrate, The first reflective layer is a multilayer reflective layer including laminated semiconductor layers having different refractive indices; the absorptive layer has a band gap energy smaller than band gap energy of the semiconductor substrate; the phase adjusting layer has a band gap energy larger than the band gap energy of the absorptive layer; and the first reflective layer contacts the absorptive layers without intervention of other layers. | 2009-09-03 |
| 20090218596 | Buffer layers for device isolation of devices grown on silicon - Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate. | 2009-09-03 |
| 20090218597 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME - A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate. | 2009-09-03 |
| 20090218598 | WARP-FREE SEMICONDUCTOR WAFER, AND DEVICES USING THE SAME - A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces. | 2009-09-03 |
| 20090218599 | POLARIZATION-INDUCED BARRIERS FOR N-FACE NITRIDE-BASED ELECTRONICS - A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient. | 2009-09-03 |
| 20090218600 | Memory Cell Layout - A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for numerous memory elements based on memory-specific parameters, and determining a layout for a front-end-of-line (FEOL) component of the integrated circuit based on electrical parameters. Once these two layouts are determined, the layouts are combined to produce a layout for a memory cell on the integrated circuit. | 2009-09-03 |
| 20090218601 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption. | 2009-09-03 |
| 20090218602 | PHOTOELECTRIC CONVERSION DEVICE, ITS MANUFACTURING METHOD, AND IMAGE PICKUP DEVICE - It is an object of the present invention to provide a manufacturing method of a photoelectric conversion device in which no plane channeling is produced even if ions are injected at a certain elevation angle into a semiconductor substrate surface made of silicon. A manufacturing method of a photoelectric conversion device including a silicon substrate and a photoelectric conversion element on one principal plane of the silicon substrate, wherein the principal plane has an off-angle forming each angle θ with at least two planes perpendicular to a reference (1 0 0) plane within a range of 3.5°≦θ≦4.5°, and an ion injecting direction for forming an semiconductor region constituting the photoelectric conversion element forms an angle φ to a direction perpendicular to the principal plane within a range of 0°<φ≦45°, and further a direction of a projection of the ion injecting direction to the principal plane forms each angle α with the two plane direction within a range of 0°<α<90°. | 2009-09-03 |
| 20090218603 | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane. | 2009-09-03 |
| 20090218604 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer. | 2009-09-03 |
| 20090218605 | Methods of Enhancing Performance of Field-Effect Transistors and Field-Effect Transistors Made Thereby - Methods of enhancing the performance of a field-effect transistor (FET) by providing a percolating network of metallic islands to the inversion layer of the FET so as to effectively reduce the channel length of the FET. The metal islands can be provided in a number of ways, including Volmer-Weber metallic film growth, breaking apart continuous metallic film, patterning metallic coating, dispersing metallic particles in a semiconducting material, applying a layer of composite particles having metallic cores and semiconducting shells and co-sputtering metallic and semiconducting materials, among others. FETs made using disclosed methods have a novel channel structures that include metallic islands spaced apart by semiconducting material. | 2009-09-03 |
| 20090218606 | VERTICALLY INTEGRATED LIGHT SENSOR AND ARRAYS - Embodiments hereof include a photosensing device, comprising an isolation layer; a photodetector layer comprising a plurality of pixels, wherein the photodetector layer is in contact with a first side of the isolation layer, wherein the photodetector layer comprises a laser-processed semiconductor material; and a semiconductor layer disposed on a second side of the isolation layer. | 2009-09-03 |
| 20090218607 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film. | 2009-09-03 |
| 20090218608 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode. | 2009-09-03 |
| 20090218609 | Semiconductor Memory Devices Including Offset Bit Lines - A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column. | 2009-09-03 |
| 20090218610 | Semiconductor Memory Devices Including Diagonal Bit Lines - A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns. | 2009-09-03 |
| 20090218611 | HIGH DENSITY STEPPED, NON-PLANAR FLASH MEMORY - A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their source/drain regions. | 2009-09-03 |
| 20090218612 | MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES - Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers. | 2009-09-03 |
| 20090218613 | SEMICONDUCTOR TIME SWITCH SUITABLE FOR EMBEDDING IN NAND FLASH MEMORY DEVICE - A semiconductor time switch includes a cell portion and an electron booster. The cell portion contains parallel linear semiconductor layers provided on a substrate as active areas, first and second linear conductor layers alternately formed on the linear semiconductor layers through a gate insulating film as control gates and extending so as to cross the linear semiconductor layers, and floating gates inserted into respective intersections of the linear semiconductor layers and the first linear conductor layers, and coupled to the first linear conductor layers through an inter-gate insulating film. The electron booster is provided on the substrate and includes a MOS transistor having a booster gate electrode connected to the second linear conductor layers. Both ends of the linear semiconductor layers are connected to first and second I/O terminals of the switch, respectively. | 2009-09-03 |
| 20090218614 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film. | 2009-09-03 |
| 20090218615 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate, a first gate insulation film formed on the substrate, a charge storage layer formed on the first gate insulation film, a second gate insulation film formed on the charge storage layer, and a gate electrode formed on the second gate insulation film, the width between side surfaces of the second gate insulation film in the bit line direction being smaller than the width between side surfaces of the gate electrode in the bit line direction. | 2009-09-03 |
| 20090218616 | TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD FOR FABRICATING THE SAME - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar. | 2009-09-03 |
| 20090218617 | SUPERJUNCTION POWER SEMICONDUCTOR DEVICE - A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device. | 2009-09-03 |
| 20090218618 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME - A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench. | 2009-09-03 |
| 20090218619 | Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method - This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt. | 2009-09-03 |
| 20090218620 | High power and high temperature semiconductor power devices protected by non-uniform ballasted sources - This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers. | 2009-09-03 |
| 20090218621 | SEMICONDUCTOR COMPONENT WITH A DRIFT REGION AND A DRIFT CONTROL REGION - A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region. | 2009-09-03 |
| 20090218622 | LDMOS TRANSISTOR - The LDMOS transistor ( | 2009-09-03 |
| 20090218623 | SOI DEVICES AND METHODS FOR FABRICATING THE SAME - Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer. | 2009-09-03 |
| 20090218624 | SOI DEVICE HAVING AN INCREASING CHARGE STORAGE CAPACITY OF TRANSISTOR BODIES AND METHOD FOR MANUFACTURING THE SAME - An SOI device includes an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate. The SOI substrate possesses grooves having a depth that extends from an upper surface of the first silicon layer to a partial depth of the buried oxide layer. An insulation layer is formed on the lower surfaces of the grooves and a second silicon layer is formed filling the grooves having the insulation layer formed thereon. Gates are formed on the second silicon layer and junction regions are formed in the first silicon layer on both sides of the gates to contact the insulation layer. | 2009-09-03 |
| 20090218625 | Modified Hybrid Orientation Technology - A semiconductor process and apparatus includes forming first and second metal gate electrodes ( | 2009-09-03 |
| 20090218626 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used. | 2009-09-03 |
| 20090218627 | FIELD EFFECT DEVICE STRUCTURE INCLUDING SELF-ALIGNED SPACER SHAPED CONTACT - A semiconductor structure and a method for fabricating the semiconductor structure include or provide a field effect device that includes a spacer shaped contact via. The spacer shaped contact via preferably comprises a spacer shaped annular contact via that is located surrounding and separated from an annular spacer shaped gate electrode at the center of which may be located a non-annular and non-spacer shaped second contact via. The annular gate electrode as well as the annular contact via and the non-annular contact via may be formed sequentially in a self-aligned fashion while using a single sacrificial mandrel layer. | 2009-09-03 |
| 20090218628 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a first silicon layer connected to a first active region of a semiconductor substrate, a second silicon layer and a relaxed silicon germanium layer formed over the first silicon layer expected to be a NMOS region, and a NMOS gate formed over the second silicon layer. | 2009-09-03 |
| 20090218629 | ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS - In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices. | 2009-09-03 |
| 20090218630 | SEMICONDUCTOR DEVICE INCLUDING MOS FIELD EFFECT TRANSISTOR HAVING OFFSET SPACERS OR GATE SIDEWALL FILMS ON EITHER SIDE OF GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME - First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode. | 2009-09-03 |
| 20090218631 | SRAM CELL HAVING ASYMMETRIC PASS GATES - Conductive stripes laterally abutting the dielectric lines are formed over a thin semiconductor layer on a gate dielectric. Angled halo ion implantation is performed to implant p-type dopants on the side of the drains of pull-down transistors and a first source/drain region of each pass gate transistor. The dielectric lines are removed and the pattern of the conductive stripes is transferred into the semiconductor layer to form gate electrodes. The resulting pass gate transistors are asymmetric transistors have a halo implantation on the side of the first source/drain regions, while the side of a second source/drain regions does not have such a halo implantation. As such, the pass gate transistors provide enhanced readability, writability, and stability. | 2009-09-03 |
| 20090218632 | CMOS STRUCTURE INCLUDING NON-PLANAR HYBRID ORIENTATION SUBSTRATE WITH PLANAR GATE ELECTRODES AND METHOD FOR FABRICATION - A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions. | 2009-09-03 |
| 20090218633 | CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS - A recessed transistor configuration may be provided selectively for one type of transistor, such as N-channel transistors, thereby enhancing strain-inducing efficiency and series resistance, while a substantially planar configuration or raised drain and source configuration may be provided for other transistors, such as P-channel transistors, which may also include a strained semiconductor alloy, while nevertheless providing a high degree of compatibility with CMOS techniques. For this purpose, an appropriate masking regime may be provided to efficiently cover the gate electrode of one transistor type during the formation of the corresponding recesses, while completely covering the other type of transistor. | 2009-09-03 |
| 20090218634 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing. | 2009-09-03 |
| 20090218635 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region | 2009-09-03 |
| 20090218636 | INTEGRATED CIRCUIT SYSTEM FOR SUPPRESSING SHORT CHANNEL EFFECTS - An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening. | 2009-09-03 |
| 20090218637 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND DEPLETION-TYPE MOS TRANSISTOR - A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. | 2009-09-03 |
| 20090218638 | NAND FLASH PERIPHERAL CIRCUITRY FIELD PLATE - A high voltage device for use in periphery circuitry of a NAND flash memory device comprising a field plate. | 2009-09-03 |
