Patents - stay tuned to the technology

Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


35th week of 2010 patent applcation highlights part 23
Patent application numberTitlePublished
20100220498SURFACE LIGHT SOURCE DEVICE AND PRISM SHEET - A surface light source device is disclosed that provides greater light condensation in the frontal direction and higher luminance in comparison to a conventional surface light source device. Disclosed is a surface light source device providing a light source, a light guide having at least one of the side surfaces thereof as an incident surface and an outgoing surface substantially perpendicular to the incident surface, and at least two prism sheets, in which the surfaces formed by the prisms of the prism sheets are arranged so as to face upward, moreover the surfaces of the sides opposing the surfaces formed by the prisms of the prism sheets are arranged substantially parallel to the outgoing surface of the light guide. Further, in this surface light source device the prisms are arranged so as to be substantially parallel to the incident surface of the light guide, the half width of emitted light distribution of the light guide is not greater than 30°, and within a cross-section of the prism of the first prism sheet substantially perpendicular to both the outgoing surface and the incident surface of the light guide, the angle θF2010-09-02
20100220499HYBRID DISTRIBUTION TRANSFORMER WITH AN INTEGRATED VOLTAGE SOURCE CONVERTER - A hybrid distribution transformer is provided that includes an electromagnetic transformer and a voltage source converter that is operable to reduce fluctuation in the output voltage of the hybrid distribution transformer in the event of an increase or decrease in the input voltage.2010-09-02
20100220500POWER CONVERTER AND METHOD FOR CONTROLLING POWER CONVERTER - The invention prevents the voltage change ratio of switching devices of a power converter from exceeding a specified maximum rating, thus avoiding damage in switching devices and an increase in conduction loss. In a power converter having a plurality of switching devices, switching means for switching a control scheme for the switching devices to a phase shift control scheme or a pulse width modulation scheme is provided, whereby the control scheme for the switching devices is switched from the phase shift control scheme to the pulse width modulation scheme in a non-load or light-load state.2010-09-02
20100220501DC/DC CONVERTER AND AC/DC CONVERTER - A DC/DC converter (2010-09-02
20100220502ISOLATING SELF-OSCILLATION FLYBACK CONVERTER - An isolating self-oscillation flyback converter includes a coupling transformer T2010-09-02
20100220503METHOD AND APPARATUS FOR CONTROLLING THE MAXIMUM OUTPUT POWER OF A POWER CONVERTER - A controller for a power converter is disclosed. An example circuit controller according to aspects of the present invention includes an input voltage sensor to be coupled to receive an input signal representative of an input voltage of the power converter. A current sensor is also included and is to be coupled to sense a current flowing in a power switch. A drive signal generator is to be coupled to drive the power switch into an on state for an on time period and an off state for an off time period. The controller is coupled to adjust a duty cycle of the power switch in response to a difference between a time it takes the current flowing in the power switch to change between two current values when the power switch is in the on state and a control time period.2010-09-02
20100220504Power supply apparatus having multiple outputs - A power supply apparatus having multiple outputs is described. The power supply apparatus having multiple outputs which comprises a transformer, a first output circuit generating a first output voltage with respect to a power transferred to a secondary side of the transformer, and a first output controller generating a first control signal for controlling a power supply provided to a primary side of the transformer, includes: a second output circuit generating a second output voltage with respect to the power transferred to the secondary side of the transformer; and a second output controller controlling an output of the second output voltage, wherein the second output circuit includes a second switch performing a switching operation on current flows of the second output circuit, and the second output controller controls the switching operation of the second switch according to the first control signal and the second output voltage. Accordingly, a plurality of output circuits are provided in the secondary side of the transformer, and an output voltage of each output circuit is individually controlled. In addition, power losses are reduced and efficiency is increased, a simple configuration can be implemented, and stable control of the output voltages of the multiple outputs can be achieved.2010-09-02
20100220505DC/DC CONVERTER - A DC/DC converter has three half-bridge-type current resonant DC/DC converters that are connected in parallel, have a phase difference of 120 degrees, and are operated at a frequency higher than a resonant frequency. Each of the three half-bridge-type current resonant DC/DC converters includes a transformer having a primary winding, a secondary winding, and a tertiary winding, a series circuit connected to both ends of a DC power source and including first and second switching elements, a series circuit connected to both ends of the first or second switching element and including a resonant reactor, the primary winding of the transformer, and a resonant capacitor, and a rectifying circuit to rectify a voltage generated by the secondary winding and output the rectified voltage to a smoothing capacitor. The tertiary windings are annularly connected to a reactor.2010-09-02
20100220506CONTROL CIRCUIT FOR SWITCHING POWER SUPPLY - A control circuit for a switching power supply (SPS) includes power input and output interfaces, a relay, a relay driving circuit, a microprocessor, and an alternating current/directing current (AC/DC) converter. The power input interface receives an external alternating current (AC) power signal, and transmits the AC power signal to the SPS via the power output interface. The AC/DC converter transforms the AC power signal into a direct current (DC) power signal to supply for the relay, the relay driving circuit, and the microprocessor. When a computer is turned on, the microprocessor sends a first control signal to control the relay driving circuit to drive the relay to connect the power input and output interfaces. When the computer is turned off, the microprocessor sends a second control signal to control the relay driving circuit to drive the relay to cut off connection between the power input and output interfaces.2010-09-02
20100220507Microcontroller operated current limited switching power supply for circuit protective devices - An AC to DC power supply for small heat sensitive electronic device. The power supply being dynamically controlled to operate symmetrically about the lowest point of the AC source voltage waveform for minimum excess heat production.2010-09-02
20100220508Photovoltaic Inverter with Option for Switching Between a Power Supply System with a Fixed Frequency and a Load Variable Frequency - A photovoltaic inverter having an inverter bridge section, a first output, a second output, and a power switch. The inverter bridge section is operable for converting DC electrical energy into AC electrical energy. The inverter bridge section has an output for outputting the AC electrical energy. The power switch is connected to the output of the inverter bridge section, the first output, and the second output. The power switch is selectively switchable between a first state in which the output of the inverter bridge section is connected to the first output via the power switch and a second state in which the output of the inverter bridge section is connected to the second output via the power switch.2010-09-02
20100220509Selective Activation of Programming Schemes in Analog Memory Cell Arrays - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.2010-09-02
20100220510Optimized Selection of Memory Chips in Multi-Chips Memory Devices - A method includes accepting a definition of a type of multi-unit memory device (2010-09-02
20100220511LOW POWER ANTIFUSE SENSING SCHEME WITH IMPROVED RELIABILITY - Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory cells is reduced by pulsing a read voltage applied to a wordline connected to the unprogrammed anti-fuse memory cells, thereby reducing the tunneling current. Further tunneling current can be reduced by decoupling the unprogrammed anti-fuse memory cells from a sense amplifier that can drive the corresponding bitline to VSS.2010-09-02
20100220512PROGRAMMABLE POWER SOURCE USING ARRAY OF RESISTIVE SENSE MEMORY CELLS - Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited to a micro-oscillator. In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input which selectively programs at least selected ones of the memory cells to a selected resistance state.2010-09-02
20100220513Bi-Directional Resistive Memory Devices and Related Memory Systems and Methods of Writing Data - A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided.2010-09-02
20100220514STORAGE DEVICES WITH SOFT PROCESSING - A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.2010-09-02
20100220515SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR - Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.2010-09-02
20100220516Reducing Source Loading Effect in Spin Torque Transfer Magnetoresisitive Random Access Memory (STT-MRAM) - Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.2010-09-02
20100220517SEMICONDUCTOR DEVICE - Data which sets up operation parameters, etc. of an internal circuit is supplied stably over a long period of time. In a cell array in which MRAM cells are arranged, read/write of test data is performed in a PROM mode. Finally, data writing is specifically performed to the memory cells in an OTP mode.2010-09-02
20100220518THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.2010-09-02
20100220519Sensing Characteristic Evaluating Apparatus for Semiconductor Device and Method Thereof - A sensing characteristic evaluating apparatus for a semiconductor device includes a test current supply unit configured to supply a test current to an input/output line during a test mode for evaluating a sensing characteristic, and a sensing amplifying circuit configured to receive the test current from the input/output line, to compare and amplify a sensing input voltage corresponding to the test current with a reference voltage, and to output an amplified voltage as a sensing output voltage.2010-09-02
20100220520Multi-bit phase change memory devices - A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three crystalline phases having different resistance values according to an increase of temperature of the phase change material.2010-09-02
20100220521PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION - A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.2010-09-02
20100220522PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING READ OPERATION THEREOF - A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is transitioned between at least two voltage stages having different voltage levels.2010-09-02
20100220523STOCHASTIC SYNAPSE MEMORY ELEMENT WITH SPIKE-TIMING DEPENDENT PLASTICITY (STDP) - An active memory element is provided. One embodiment of the invention includes a bi-polar memory two-terminal element having polarity-dependent switching. A probability of switching of the bi-polar memory element between a first state and a second state decays exponentially based on time delay and a difference between received signals at the two terminals and a switching threshold magnitude.2010-09-02
20100220524MAGNETIC BOOSTER FOR MAGNETIC RANDOM ACCESS MEMORY - Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.2010-09-02
20100220525NON-VOLATILE MEMORY DEVICE AND ERASE AND READ METHODS THEREOF - An erase method of a non-volatile memory device includes first erasing memory cells of a non-volatile memory device with a first erase voltage; in response to a judgment that the erasure of at least one of the memory cells has failed, determining an amount of voltage to add to the first erase voltage, the amount being based on a threshold voltage distribution of the first erased memory cells; and second erasing the memory cells with a second erase voltage, the second erase voltage being higher than the first erase voltage by the determined amount.2010-09-02
20100220526NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A nonvolatile memory device stores program data in a first address area, determines whether the first address area is a most significant address area and whether the program data is reliable data, and upon determining that the first address area is not a most significant address area and that the program data is reliable data, additionally stores the program data in a second address area.2010-09-02
20100220527Non-volatile FIFO with third dimension memory - A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that require non-volatile data storage can also be implemented as registers or the like using the BEOL non-volatile third dimension memory cells so that power to the FIFO can be cycled and data is retained. The BEOL non-volatile third dimension memory cells can be configured in a single layer of memory or in multiple layers of memory. An IC that includes the FIFO can also include one or more other memory types that are emulated using the BEOL non-volatile third dimension memory cells and associated FEOL circuitry configured for data operations on those memory cells.2010-09-02
20100220528NAND WITH BACK BIASED OPERATION - Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts2010-09-02
20100220529NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a sensing circuit that is configured to detect a charge of a common source line and a voltage controller that is configured to vary a level of a voltage being inputted to a word line in response to a result of the detection of the sensing circuit.2010-09-02
20100220530CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY - An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.2010-09-02
20100220531SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.2010-09-02
20100220532Readout Circuit for Rewritable Memories and Readout Method for Same - In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.2010-09-02
20100220533NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.2010-09-02
20100220534Memory Device with Reduced Buffer Current During Power-Down Mode - A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.2010-09-02
20100220535NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.2010-09-02
20100220536ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE - A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.2010-09-02
20100220537ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS - An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.2010-09-02
20100220538Integrated circuit memory power supply - An integrated circuit memory 2010-09-02
20100220539MEMORY CIRCUITS, SYSTEMS, AND OPERATING METHODS THEREOF - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBL2010-09-02
20100220540SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS - A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.2010-09-02
20100220541SWITCHED-CAPACITOR CHARGE PUMPS - A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.2010-09-02
20100220542Integrated circuit memory access mechanisms - A memory cell 2010-09-02
20100220543Circuitry and method for indicating a memory - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.2010-09-02
20100220544Device for dispensing a gas into a liquid - An aeration cartridge (2010-09-02
20100220545MIXER AND METHOD OF MIXING - A dynamic mixer in which two members (1,2) are rotated relative to each other about a predetermined axis (XX), the members having facing surfaces (2010-09-02
20100220546Apparatus for Metering and Mixing Pourable Material Components - Apparatus for dosed mixing of pourable material components, includes a mixing container, two weighing containers, each of the weighing containers including a closable discharge opening for discharging the weighing container into the mixing container; and a weighing device for weighing the content of the weighing container, and several storage containers for respective material components, each storage container including a feeding device for feeding material from the storage container to an assigned weighing container, wherein and the mixing container is arranged below the weighing containers such that the weighing containers are simultaneously dischargeable through the discharge openings into the mixing container.2010-09-02
20100220547VESSEL FOR PROCESSING A BIOPHARMACEUTICAL PRODUCT INCLUDING PROTECTION MEANS - A vessel includes: a pocket capable of assuming a folded state and an expanded state, processing element including an active inner portion; protection element including a side wall, a lower portion and an upper portion defining an inner space, the lower portion being attached to the upper portion of the pocket, the active inner portion being provided in the inner space when the pocket is in the folded state, the peripheral portion of the inner space about the processing element defining a protection chamber; at least one insertion and/or draining opening. The active inner portion is provided inside the pocket adjacent to the lower end portion thereof, the processing element and the protection element are independent in terms of their movements, and the height of the protection chamber is variable and automatically adapts itself based on respectively, the flat-folded, unfolded and expanded states or any intermediate state of the pocket.2010-09-02
20100220548METHOD AND SYSTEM FOR ADMINISTERING MICRO-INGREDIENT FEED ADDITIVES TO ANIMAL FEED RATIONS - A system and method are provided for administering micro-ingredient feed additives or supplements to feed rations. The amount of each particular micro-ingredient to be delivered to a feed ration may be determined by a bulk density measurement. Alternatively, bulk density measurement may be used in combination with existing weight measurement and volumetric metering methods for multiple micro-ingredients. Delivery by bulk density requires determination of a bulk density value along with use of a dispensing device that dispenses a calculated amount of the micro-ingredient ration. The dispensing calculation may be achieved by analysis of delivery time, pulse count, or some other quantitative measure such as magnitude. Use of bulk density as a measurement technique eliminates the requirement for use of scales in the micro-ingredient delivery system.2010-09-02
20100220549PROCESS FOR PREPARING AND APPLYING PESTICIDE OR HERBICIDE FORMULATION - Apparatus for conveying a water-soluble or water swellable particulate material to a make up unit used in the hydration or dissolution of said material comprising: a scroll conveying line (2010-09-02
20100220550Obstacle detection apparatus and method for detecting obstacle - A transmission and reception device is located at a predetermined height on a movable object and directed toward an outside. The transmission and reception device includes a transmission unit for repeatedly transmitting sensing waves at a predetermined interval and a reception unit for receiving reflective waves of the sensing waves from a detected object. A peak value detecting unit detects peak values of the received reflective waves and stores the detected peak values. A difference arithmetic unit calculates a difference in the detected peak values with movement of the movable object closer to the detected object. An object determination unit determines the detected object to be a near-road-surface obstacle, which is close to a road surface, when the difference is a negative value. The object determination unit determines the detected object to be an other obstacle than the near-road-surface obstacle when the difference is a positive value.2010-09-02
20100220551Physical object detection system - In an obstacle detection system, a wave transmitted by a transmitting element and received by receiving elements as a receiving wave includes extraneous waves, which are reflection waves from other than an obstacle, and obstacle reflection waves from an obstacle. It is determined that, an obstacle is present, if the reflection waves are detected as having an amplitude (voltage) greater than a threshold level and a reception time difference between time points at which the amplitude exceeds threshold level at the receiving elements is less than a predetermined time.2010-09-02
20100220552METHOD AND APPARATUS FOR ESTIMATING SOUND SOURCE - Sound and image are sampled simultaneously using a sound/image sampling unit incorporating a plurality of microphones and a camera. Sound pressure waveform data and image data are stored in a storage means. Then the sound pressure waveform data are extracted from the storage means, and a graph of a time-series waveform of the sound pressure level is displayed on a display screen. A time point at which to carry out a calculation to estimate sound direction is designated on the graph, and then sound direction is estimated by calculating the phase differences between the sound pressure signals of the sound sampled by the microphones, using the sound pressure waveform data for a calculation time length having the time point at the center thereof. A sound source position estimation image having a graphic indicating an estimated sound direction is created and displayed by combining the estimated sound direction and the image data sampled at the time point.2010-09-02
20100220553Method and Apparatus for Alerting a Person at Medicine Dosing Times - Disclosed are apparatus for assisting a person in the correct administration of medicine and methods for beneficially using such a device. The apparatus comprises an electronic timing mechanism which executes a dosing schedule, the dosing schedule being comprised of at least one dosing time interval. One or more annunciators are activated at the end of at least one dosing interval thereby alerting a person that it is time to take a dose of medicine. Included are attachment means, such as a pressure sensitive adhesive, for attachment to a medicine container. Construction is with materials and structures that confer to the device the flexibility required to physically conform to curved objects such as typically encountered in prescribed medications. Alerts from the device may be visible, audible, vibratory, or any combination thereof. No human readable time is displayed. At least one switch is provided for human interaction with the device. Human readable information may be visible on the device for quick dosing schedule identification. The dosing schedule may be preprogrammed and unalterable. In other embodiments the dosing schedule may be reprogrammable.2010-09-02
20100220554Apparatus for relating time to activity - An apparatus for relating time to activity is disclosed. The apparatus discloses an analog clock and a display board having one or more activities where a chosen activity begins at a time indicated by an hour indicator and a minute indicator.2010-09-02
20100220555Electronic Device and Satellite Signal Reception Method for an Electronic Device - An electronic device has a reception unit that captures positioning information satellites and receives satellite signals transmitted from the captured positioning information satellites, a solar panel, and a reception control unit that controls the reception unit. The reception control unit includes an evaluation unit that evaluates the reception environment based on power generation by the solar panel, and a mode selection unit that, based on the result from the evaluation unit, selects a time information reception mode for receiving the satellite signals and acquiring time information, or a position and time information reception mode for receiving the satellite signals and acquiring positioning information and time information, and controls operation of the reception unit in the reception mode selected by the mode selection unit.2010-09-02
20100220556Stepping motor control circuit and analog electronic watch - A stepping motor control circuit includes a rotation detecting means which detects an induced signal generated by rotation of a rotor of a stepping motor, and detects a rotation state of the stepping motor according to whether the induced signal exceeds a predetermined reference threshold voltage in a predetermined detection section, and a control means which controls driving of the stepping motor by using any one of a plurality of main driving pulses having energies different from each other or a correction driving pulse having energy higher than energy of each main driving pulse according to a detection result of the rotation detecting means. The control means allows the main driving pulse to be down when a rotation state, in which an extra driving force of the main driving pulse is small, continuously occurs by a predetermined first number of times, and allows the main driving pulse to be down even if the rotation state having a small extra driving force does not continuously occur by the predetermined first number of times when a rotation state having a large extra driving force is large has occurred under a condition in which at least the rotation state having the small extra driving force continuously occurs.2010-09-02
20100220557BRIDGE OR BOTTOM PLATE FOR A TIMEPIECE MOVEMENT - The invention relates to a timepiece movement that includes at least one bridge (2010-09-02
20100220558Real Time Clock - Various apparatuses, methods and systems for a real time clock are disclosed herein. For example, some embodiments provide a real time clock including a clock generator having a first input connected to a clock signal and a second input connected to a time set signal. The clock generator produces a time change signal at an output of the clock generator. Counters, each adapted to track a different unit of time, are connected to the time change signal. The clock generator is adapted to generate a pulse on the time change signal for each pulse of the time set signal, and to generate separate pulses on the time change signal for consecutive pulses on the clock signal and the time set signal.2010-09-02
20100220559Electromechanical Module Configuration - A wearable electronic device for conveying information using one or more display indicators, wherein the electronic device comprises a housing; a nest positioned in the housing; a plurality of independently insertable and removable modules coupled to the nest, wherein each module comprises (i) a gearing arrangement comprising at least one rotateable gear and (ii) a stepper motor, the stepper motor comprising a rotor rotateably coupled to the at least one rotateable gear; a controller operatively coupled to the stepper motor of each module, for causing the rotation of the rotor of each module; wherein each of the plurality of modules has associated therewith and mechanically coupled thereto one or more display indicators; whereby the positioning of the one or more indicators conveys information by referring to particular indicia. In a specific embodiment, the wearable electronic device is a wristwatch.2010-09-02
20100220560Watch - A bezel member rotatably mounted to a case band member is provided with an accommodating groove, a pair of passing portions continuous with the accommodating groove at positions spaced apart by approximately 180°, and a pair of escape grooves continuous with both passing portions from the center side of the bezel member and open to the exterior of the case band member. The case band member is provided with engagement grooves arranged in a ring-like fashion so as to be opposed to the accommodating groove, and a ring-like reception groove surrounded by the engagement grooves and continuous with the engagement grooves. A lock member retains the bezel member at an arbitrary rotating position. The lock member has an arcuate spring portion accommodated in the accommodating groove, a pair of pushbutton portions passing through the passing portions and to be pushed in from the outside of the bezel member, and a stopper portion engaged with the engagement grooves and adapted to be detached from the engagement grooves when the pushbutton portions are pushed into the reception groove.2010-09-02
20100220561Watch - A wristwatch is equipped with a case band, a bezel, and a guard. The case band has a circular upwardly directed protrusion to which a transparent dial cover is mounted, a surrounding wall portion forming between itself and the upwardly directed protrusion an arrangement groove extending along this protrusion, and open portions for bezel operation. The bezel having manual holding asperities facing the open portions is rotatably supported in the outer periphery of the upwardly directed protrusion, and arranged in the arrangement groove while forming between itself and the surrounding wall portion a gap extending along the surrounding wall portion. There is arranged in the gap the guard, which is engaged with a detachment preventing portion of the surrounding wall portion and moved in the peripheral direction of the bezel; the guard is movable between a use position where it closes the open portions and obstructs manual holding of the manual holding asperities and a retreated position where it opens the open portions to enable manual holding of the manual holding asperities. The guard is retained at the use position by a positioning means.2010-09-02
20100220562Portable watch - A portable watch is equipped with a watch exterior member, a crown, a crown lock button, and an urging member. In a case band with which the exterior member is equipped, there are formed a crown mounting hole and a member mounting portion communicating with this hole and vertically perpendicular thereto. The crown is arranged in the hole. The crown has a crown shaft portion passed through the hole and a crown head portion continuous therewith. The crown shaft is provided with a lock groove continuous in the peripheral direction. The lock button accommodated in the mounting portion has a button head portion (operation end portion) protruding from the mounting portion. The button is movable between a lock position where it is engaged with the groove to constrain the crown and a lock canceling position where it is detached from the groove to cancel the constraint of the crown, and is arranged at the lock canceling position through a one-touch operation of the button head portion. The watch is characterized in that the button is arranged at the lock position by an urging member accommodated in the mounting portion.2010-09-02
20100220563RECORDING CONTROL DEVICE, LASER DRIVE DEVICE, INFORMATION RECORDING DEVICE, SIGNAL TRANSMISSION METHOD, AND RECORDING/REPRODUCTION CONTROL DEVICE - An information recording device that offers high performance with an inexpensive structure is achieved without requiring a dedicated line for transmitting and receiving control data. The information recording device (2010-09-02
20100220564DISC-DRIVE APPARATUS AND METHOD - A disc drive (2010-09-02
20100220565INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD GENERATING A COPY PREVENTING STRUCTURE - User data is recorded onto a DVD by the incremental recording method and by using padding when closing a recording zone, read error data is recorded onto the DVD. The read error data is generated by making a sector error detection code or a PI/PO error correction code in the ECC block different from a correct value.2010-09-02
20100220566OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE, OPTICAL INFORMATION REPRODUCING DEVICE, AND OPTICAL INFORMATION RECORDING MEDIUM - The purpose of the present invention is to provide an optical information recording/reproducing device and the like that can suppress a decrease in a recording speed even where an optical information recording medium including multiple layers has eccentricity. The optical information recording/reproducing device records information, by treating a predefined area in a second layer corresponding to a position of a first layer at which a defect is detected, as a defect area. The optical information recording/reproducing device reproduces information, by treating a predefined area in the second layer corresponding to a position of the first layer at which a defect is registered, as a defect area. The radial distance of the defect area is preferably greater than a bonding error between the first and second layers.2010-09-02
20100220567Optical Information Recording Medium, Reproducing Device for Optical Information Recording Medium, Control Method and Control Program for the Reproducing Device, and Medium with the Control Program Recorded Therein - A super-resolution medium (2010-09-02
20100220568SIGNAL MEASUREMENT APPARATUS AND BEAM MODULATION APPARATUS USED THEREIN - An apparatus for modulating an incident beam includes a body that is non-transmissive and rotatable about an axis perpendicular to a surface of the body. The body has a first set of features including transmissive features with respect to the incident beam along a first radial path at a first radial distance from the axis and a second set of features including data storage features along a second radial path at a second radial distance from the axis. The apparatus also includes a reference sensor disposed over a first position along the second radial path. In the apparatus. the radial distances are different and the numbers of transmissive features and data storage features are relatively prime. When the body is rotating, the first set of features modulate the incident beam and the reference sensor generates a reference signal based on the data storage features traversing the first position.2010-09-02
20100220569FINAL AREA RETRIEVING APPARATUS, INFORMATION REPRODUCING APPARATUS, FINAL AREA RETRIEVING METHOD, AND FINAL AREA RETRIEVING PROGRAM - A final area retrieving apparatus, an information reproducing apparatus, a final area retrieving method, and a final area retrieving program are provided, which are capable of decreasing a period of time necessary for acquiring information necessary for reproduction of optical disc.2010-09-02
20100220570SIGNAL QUALITY EVALUATING APPARATUS AND METHOD, AND INFORMATION RECORDING MEDIUM - A signal quality evaluating method necessary for a signal quality evaluation index and a margin design is provided for an apparatus utilizing hologram recording techniques. An evaluation index is used being obtained by dividing root sum square of standard deviations of luminance value distribution of on- and off-pixels obtained from reproduced signals, by a difference between average values.2010-09-02
20100220571Optical disc medium and data recording method and apparatus - An optical disc medium and corresponding optical recording method and optical recording apparatus. The optical disc medium comprises a substrate on which a shape according to modulated information data has been formed, and a coating film formed on the substrate. Known data is recorded in a predetermined location of the information data, with the known data being rewritten as postscript information by recording a postscript portion to the coating film to alter a portion of the known data, wherein the postscript information comprises readable non-error data.2010-09-02
20100220572HARD DRIVE ERASER - Systems, apparatuses and methods for erasing hard drives. A system, which can be configured as a stand alone and portable apparatus, includes a control device configured to support an erase module. The erase module is configured to erase a hard drive such that data erased from the hard drive is forensically unrecoverable. The system further includes a user interface and at least one drive bay configured to provide communication between a hard drive and the control device.2010-09-02
20100220573OPTICAL INFORMATION RECORDING MEDIUM, OPTICAL INFORMATION REPRODUCING METHOD, AND OPTICAL INFORMATION REPRODUCING DEVICE - Provided is an optical information reproducing medium for realizing an excellent super resolution reproduction while performing a high-speed reproduction. The optical information recording medium includes a plurality of super resolution layers (2010-09-02
20100220574INFORMATION RECORDING MEDIUM AND RECORDING/REPRODUCING METHOD FOR THE SAME - The information recording medium (2010-09-02
20100220575OPTICAL PICKUP HEAD - An optical pickup head includes a first light source, a second light source, a base, a light adjusting unit, and a light guiding unit. The first light source emits a first wavelength light beam to read a first data density optical storage medium. The second light source emits a second wavelength light beam to read a second data density optical storage medium. The base includes at least a slant surface for reflecting the first wavelength light beam and the second wavelength light beam, so that the first wavelength light beam and the second wavelength light beam are parallel with each other. The light adjusting unit adjusts the first wavelength light beam and the second wavelength light beam to the same optical axis. The light guiding unit guides the first wavelength light beam and the second wavelength light beam to the first data density optical storage medium or the second data density optical storage medium.2010-09-02
20100220576OPTICAL PICKUP DEVICE AND INFORMATION RECORDING/REPRODUCTION DEVICE - The present invention makes possible a compact optical pickup device that eliminates effects due to the position where a sub beam is projected during tracking compensation, and provides for stable tracking compensation.2010-09-02
20100220577OPTICAL HEAD DEVICE, OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE, AND OPTICAL INFORMATION RECORDING/REPRODUCING METHOD - Polarization direction switching elements do not change the polarization direction of incoming light, in the case where a disc is an optical recording medium conforming to the HD DVD standards. At this time, light outputted from a semiconducted laser is collected on the disc by an objective lens, and reflection light from the disc is received by a light detector. In the case where the disc is an optical recording medium conforming to the BD standards, the polarization direction switching elements change the polarization directed of the incoming light by ninety degrees. At this time, light outputted from the semiconductor laser is collected on the disc by the objective lens, and reflection light from the disc is received by the light detector. Liquid crystal lenses correct spherical aberrations on an outgoing path and a returning path.2010-09-02
20100220578OBJECTIVE LENS, OPTICAL HEAD AND OPTICAL DISC DEVICE - Provides an objective lens, an optical head and an optical disc apparatus (drive) capable of compensating for various types of aberrations including wavelength changes for a plurality of types of optical discs including high density optical discs, DVDs and CDs with a good wavelength dispersion compensation ability and thus capable of providing good recording or reproduction characteristics.2010-09-02
20100220579INFORMATION RECORDING DEVICE AND INFORMATION RECORDING PROGRAM - It is an object to provide an information recording device capable of recording recording information with good recording property without wasting a recording region on an optical disk and capable of clearly forming visible portion. In a case where the visible portion is formed by using a recording pit supporting recording information Sr, the information recording device comprises an output unit 2010-09-02
20100220580Holding Member, Driving Apparatus, Pickup Apparatus, and Disc Apparatus - A holding member provided with a coil comprising a proximity facilitating portion capable of bringing the coil closer to a magnetic member facing the coil.2010-09-02
20100220581ELECTRONIC APPARATUS AND DISK PROTECTION METHOD - An electronic apparatus includes a body, a triaxial acceleration sensor which is built in the body and includes a long axis and a short axis, a disk device built in the body, a calculation unit that calculates a value on a basis of an acceleration value which is detected by the triaxial acceleration sensor and is output in a direction perpendicular to the long axis and to the short axis, a setting unit that sets a threshold in a state of the body in which a plane formed by the long axis and the short axis is approximately parallel to a direction of action of gravitational acceleration, and a controller that starts protection of the disk device on a basis of a result of comparison between the value calculated by the calculation unit and the threshold.2010-09-02
20100220582DISC-SHAPED INFORMATION-CARRYING MEDIUM - The present invention relates to disc-shaped information-carrying media for storage and reproduction of audio-, video- and other types of information in a digital form. The disc-shaped information-carrying medium comprises at least a substrate with a matching bore in its central area for locking said medium in a reading device, said substrate having a first side and a second side opposite thereto, on at least said first side of said substrate a first information area is provided for information storage and/or recording and reading such information using a laser beam. According to a first embodiment said substrate thickness at least within said first information area does not exceed 0.8 mm, said substrate central area is provided with N>1 ending protrusions projecting over said substrate first side and facilitating locking said medium in a reading device drive. According to a second embodiment in addition to said N protrusions on said first side, a circular recess is provided within said central area on said substrate second side, limited between the diameters of 15 mm and 22 mm. According to a third embodiment in addition to said N ending protrusions, a flat circular protrusion is provided within said central area on said substrate second side, limited between the diameters of 15 mm and 40 mm. According to a fourth embodiment said substrate comprises two flat circular protrusions provided in the general cased within the diameters of 15 mm and 40 mm, one protrusion on each substrate side. This configuration of the medium ensures its compatibility with most of modern optical media reading/recording devices, capability of storing and/or recording and/or rewriting 4.7 Gb of information and more, low birefringence and read/write error rate.2010-09-02
20100220583Optical data storage media and methods of formation - Provided are methods of forming multi-layered optical data storage media which include a high-density data layer, as well as multi-layered optical data storage media that can be formed by such methods.2010-09-02
20100220584SYSTEMS AND METHODS FOR AUTOMATICALLY GENERATING SYSTEM RESTORATION ORDER FOR NETWORK RECOVERY - Embodiments relate to systems and methods for automatically generating a system restoration order for network recovery. A set of managed machines, such as personal computers or servers, can be managed by a network management platform communicating with the machines via a secure channel. The network management platform can access a dependency map indicating a required order for restoration of machines or nodes on a network. The network management platform likewise access a reverse kickstart file for each machine to be automatically restored in order to ensure proper functioning of the network, and extract a current configuration of that machine for purposes of restoring the overall network.2010-09-02
20100220585Systems and Methods for Seamless Communications Recovery and Backup - A recovery network may provide communication recovery and backup services to an organization. The recovery network may be communicatively coupled to the existing communication infrastructure of an organization via one or more alternative communication paths. The alternative communication paths may couple the recovery network to the organization independently of a public communication network. Upon activation of recovery services, the recovery network may receive communication requests directed to the organization from the public communication network. The recovery network may service one or more of the requests using one or more of the alternative communication paths. Similarly, the recovery network may service outbound communication requests originating at the organization over an alternative communication path. Communication requests may be backed up (e.g., within a voicemail or other backup system) until an alternative path or communication network becomes available and/or may be redirected to other addresses within the public communication network.2010-09-02
20100220586ROUTE REFLECTOR FOR A COMMUNICATION SYSTEM - A method, system and apparatus for routing of data transmitted from a mobile electronic device to a first host of a plurality of hosts in a communication network using a Border Gateway Protocol (BGP) is provided. It is determined that the first host has failed via receipt of BGP rerouted data at least one network element, the BGP rerouted data originally intended for the first host. A negative acknowledgement (NACK) is transmitted to the mobile electronic device from the at least one network element, the NACK enabled to trigger the mobile electronic device to transmit data that was to be transmitted to the first host to another of the plurality of hosts and wherein the NACK is identifiable by the mobile electronic device as having been transmitted by the at least one network element.2010-09-02
20100220587SYSTEM AND METHOD PROVIDING OVERLOAD CONTROL IN NEXT GENERATION NETWORKS - A system, method and node for overload control in a network. The method includes the steps of receiving an incoming offer by a node, filtering the offer by an in-throttle to determine if the offer is permitted to be processed by the node prior to processing by the node, processing a permitted offer, and sending the processed offer to a designated target. After processing the permitted offer by the node, the offer may be further filtered prior to sending the offer to the designated target.2010-09-02
20100220588SYSTEMS AND METHODS OF PROVIDING PROXY-BASED QUALITY OF SERVICE - Systems and methods for dynamically controlling bandwidth of connections are described. In some embodiments, a proxy for one or more connections may allocate, distribute, or generate indications of network congestion via one or more connections in order to induce the senders of the connections to reduce their rates of transmission. The proxy may allocate, distribute, or generate these indications in such a way as to provide quality of service to one or more connections, or to ensure that a number of connections transmit within an accepted bandwidth limit. In other embodiments, a sender of a transport layer connection may have a method for determining a response to congestion indications which accounts for a priority of the connection. In these embodiments, a sender may reduce or increase parameters related to transmission rate at different rates according to a priority of the connection.2010-09-02
20100220589METHOD, APPARATUS, AND SYSTEM FOR PROCESSING BUFFERED DATA - A method, an apparatus, and a system for processing buffered data are disclosed. The method includes: packing data packets in a same queue; splitting the packed data packet into multiple data cells according to a predetermined cell size; and storing the split data cells in multiple memories. The preceding method, apparatus, and system improve the read and write efficiency of the memories and improve the balance of the read and write bandwidths among multiple memories, thus improving the system performance.2010-09-02
20100220590SYSTEMS AND METHODS FOR DROPPING DATA USING A DROP PROFILE - A system selectively drops data from queues. The system includes a drop table that stores drop probabilities. The system selects one of the queues to examine and generates an index into the drop table to identify one of the drop probabilities for the examined queue. The system then determines whether to drop data from the examined queue based on the identified drop probability.2010-09-02
20100220591BIAS CORRECTION FOR SCRUBBING PROVIDERS - A decision about provider quality based on a quality metric observed says little about the quality of the provider. Further, the decision may be biased by a variation in customer contributions to the quality metric observed or by a variation in a number of completed calls received by a provider. Accordingly, a method and corresponding apparatus are provided to evaluate quality and to correct bias by determining a standard that accounts for at least one source of bias, comparing an observed measure of a provider against the standard to produce an evaluation of the observed measure of the provider, and affecting a decision about the quality of the provider based on the evaluation. As a result, an unbiased decision, for example, to scrub a provider can be made and in some instances, a provider may be rescued from being scrubbed.2010-09-02
20100220592LAYERED INTERNET VIDEO ENGINEERING - Embodiments are described herein such as a method for providing media-aware congestion control for the transmission of video streams, the method comprising: estimating congestion price information for one or more network nodes; responding to the congestion price information by calculating optimal rates for one or more end hosts; adapting the sending rates of the one or more end hosts according to the calculated optimal rates; and determining an amount of FEC to be inserted into the video streams based on the congestion price information.2010-09-02
20100220593COMMUNICATION TERMINAL DEVICE AND COMMUNICATION CONTROL METHOD - Each of PLC modems 2010-09-02
20100220594EFFICIENT FLOW CONTROL IN A RADIO NETWORK CONTROLLER (RNC) - In one aspect, a mechanism is provided to resolve the Iub transport network congestion in the uplink direction by using the transmission window of the RLC to control the transfer rate of the flow. The RNC (2010-09-02
20100220595DISTRIBUTED CONGESTION AVOIDANCE IN A NETWORK SWITCHING SYSTEM - According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.2010-09-02
20100220596System and method for optimizing the routing of multimedia content - A system for optimizing the routing of data to a subscriber's device. The novel system includes a first sub-system for obtaining records on when each of a plurality of routing methods was available to the device during a predetermined period of time and a second sub-system for recommending a time and routing method to deliver data to the device based on the records. In an illustrative embodiment, the first sub-system includes an applet stored in and executed by the device adapted to monitor what routing methods are available to the device and record what routing methods were available at what times in a data file. The second sub-system includes a neural network artificial intelligence engine adapted to analyze the recorded data to predict when routing methods will be available to the device and identify an optimum time and routing method that minimizes a cost for delivering the data.2010-09-02
20100220597TIME DIVISION DUPLEXING (TDD) CONFIGURATION FOR ACCESS POINT BASE STATIONS - Systems and methodologies are described that facilitate establishing synchronization and/or mitigating interference with a time division duplexing (TDD) access point base station in a wireless communication environment. For example, a TDD configuration can be selected for the access point base station based upon received information to control interference. By way of another example, the access point base station can be synchronized with a disparate base station based upon the received information. Moreover, the received information can relate to the disparate base station, a served user equipment (UE) (e.g., served by the access point base station, . . . ), and/or a non-served UE (e.g., served by a base station other than the access point base station, . . . ). For example, the served UE can transmit a measurement related to the disparate base station to the access point base station.2010-09-02
Website © 2025 Advameg, Inc.