| 35th week of 2010 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20100219398 | BOTTOM EMISSION TYPE ORGANIC ELECTROLUMINESCENT PANEL - Provided is a bottom emission type organic EL panel capable of preventing or delaying loss of light emission from an end portion of the light emission area and reduction of the light emission area in an organic EL element. This organic electro luminescence panel includes an organic electro luminescence element having at least one organic layer between an anode and a cathode arranged on a substrate. This panel has a main light emission area emitting light with a high luminance and a non-light emission area or a low light emission area emitting light with a lower luminance than the main light emission area, arranged outside the end portion of the main light emission area. By limiting the main light emission area to a smaller size than the cathode forming area, the end portion of the cathode forming area is arranged outside the end portion of the main light emission area. | 2010-09-02 |
| 20100219399 | BLOCK COPOLYMER - A block copolymer comprising two or more of blocks of the following formula (1), wherein at least two of a plurality of m's present in the copolymer represent a number of 5 or more, Ar's in adjacent two blocks in the copolymer are mutually different, and the copolymer has two Ar's when composed of 2 blocks of the formula (1), has two or more Ar's when composed of 3 blocks of the formula (1) and has four or more Ar's when composed of 4 or more blocks of the formula (1): | 2010-09-02 |
| 20100219400 | ORGANIC ELECTROLUMINESCENT DEVICE - Provided is an organic electroluminescence device, including: an anode; a cathode; and organic thin film layers provided between the anode and the cathode, in which: the organic thin film layers have a light emitting layer, and have a hole injecting layer and a hole transporting layer, or a hole injecting/transporting layer on a side which is closer to the anode than the light emitting layer is; the hole injecting layer or the hole injecting/transporting layer contains an aromatic amine derivative having a specific substituent, and the hole transporting layer or the hole injecting/transporting layer contains an aromatic amine derivative having a specific substituent. | 2010-09-02 |
| 20100219401 | Deposition of Organic Layers - A method for depositing one or more organic layers onto a substrate, which includes: transferring the one or more layers from a depositing surface of a stamp to the substrate by bringing the layer coated depositing surface of the stamp into contact with the substrate, and the use of either or both of the steps of: (i) contacting the polymer with a plasticizer; and (ii) heating the substrate and/or stamp, in order to create favorable conditions for conformal contact and uniform layer transfer. | 2010-09-02 |
| 20100219402 | THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THE SAME - The present invention provides a method of manufacturing a thin film transistor of a top-contact structure with suppressed deterioration by a process which is easy and suitable for increase in area without damaging an organic semiconductor pattern. The organic semiconductor pattern is formed on a substrate. An electrode material film is formed on the substrate so as to cover the organic semiconductor pattern. A resist pattern is formed on the electrode material film. By wet etching using the resist pattern as a mask, the electrode material film is patterned. By the process, a source electrode and a drain electrode are formed. | 2010-09-02 |
| 20100219403 | ORGANIC LIGHT-EMITTING DIODES COMPRISING CARBENE-TRANSITION METAL COMPLEX EMITTERS, AND AT LEAST ONE COMPOUND SELECTED FROM DISILYLCARBAZOLES, DISILYLDIBENZOFURANS, DISILYLDIBENZOTHIOPHENES, DISILYLDIBENZOPHOSPHOLES, DISILYLDIBENZOTHIOPHENE S-OXIDES AND DISILYLDIBENZOTHIOPHENE S,S-DIOXIDES - The present invention relates to an organic light-emitting diode comprising an anode An and a cathode Ka and a light-emitting layer E which is arranged between the anode An and the cathode Ka and comprises at least one carbene complex and if appropriate at least one further layer, where the light-emitting layer E and/or the at least one further layer comprises at least one compound selected from disilylcarbazoles, disilyldibenzofurans, disilyldibenzothiophenes, disilyldibenzophospholes, disilyldibenzothiophene S-oxides and disilyldibenzothiophene S,S-dioxides, to a light-emitting layer comprising at least one of the aforementioned compounds and at least one carbene complex, to the use of the aforementioned compounds as matrix material, hole/exciton blocker material, electron/exciton blocker material, hole injection material, electron injection material, hole conductor material and/or electron conductor material, and to a device selected from the group consisting of stationary visual display units, mobile visual display units and illumination units comprising at least one inventive organic light-emitting diode; to selected disilylcarbazoles, disilyldibenzofurans, disilyldibenzothiophenes, disilyldibenzophospholes, disilyldibenzothiophene S-oxides and disilyldibenzothiophene S,S-dioxides, and to processes for their preparation. | 2010-09-02 |
| 20100219404 | ORGANIC EL DEVICE - An organic EL device includes: an anode, a cathode and an organic thin-film layer interposed between the anode and the cathode, in which the organic thin-film layer includes: an emitting layer containing a host material and a phosphorescent material; and a hole transporting layer provided adjacent to the anode relative to the emitting layer. The hole transporting layer includes a first hole transporting layer and a second hole transporting layer that are sequentially layered on the anode, in which the first hole transporting layer contains an amino compound substituted by an aromatic substituent represented by a formula (1) below and the second hole transporting layer contains at least one of compounds represented by formulae (2) to (5) below. | 2010-09-02 |
| 20100219405 | NOVEL ARYLAMINE POLYMER, METHOD FOR PRODUCING THE SAME, INK COMPOSITION, FILM, ELECTRONIC DEVICE, ORGANIC THIN-FILM TRANSISTOR, AND DISPLAY DEVICE - A polymer containing a repeating unit expressed by General Formula (I): General Formula (I) where Ar1 represents a substituted or unsubstituted aromatic hydrocarbon group; Ar2 and Ar3 each independently represent a divalent group of a substituted or unsubstituted aromatic hydrocarbon group; and R1 and R2 each independently represent a hydrogen atom, substituted or unsubstituted alkyl group, or substituted or unsubstituted aromatic hydrocarbon group. | 2010-09-02 |
| 20100219406 | USE OF ACRIDINE DERIVATIVES AS MATRIX MATERIALS AND/OR ELECTRON BLOCKERS IN OLEDS - The present invention relates to the use of (hetero)aryl-substituted acridine derivatives as matrix materials in a light-emitting layer of organic light-emitting diodes (OLEDs) and/or in a blocking layer for electrons in organic light-emitting diodes. The present invention further relates to a light-emitting layer which comprises at least one emitter material and at least one matrix material, wherein the matrix material used is at least one (hetero)aryl-substituted acridine derivative, and to an organic light-emitting diode which comprises at least one inventive light-emitting layer, to an organic light-emitting diode which comprises at least one acridine derivative of the formula (I) in a blocking layer for electrons, and to a device selected from stationary and mobile visual display units and illumination units which comprise at least one inventive organic light-emitting diode. | 2010-09-02 |
| 20100219407 | ORGANIC METAL COMPLEX, AND ORGANIC LIGHT EMITTING DEVICE AND DISPLAY APPARATUS USING THE SAME - Provided is an organic metal complex having a structure represented by the following general formula (1): | 2010-09-02 |
| 20100219408 | SENSOR MATRIX WITH SEMICONDUCTOR COMPONENTS - The invention relates to a sensor matrix ( | 2010-09-02 |
| 20100219409 | POLYTHIOPHENES AND DEVICES THEREOF - An electronic device containing a polythiophene | 2010-09-02 |
| 20100219410 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced. | 2010-09-02 |
| 20100219411 | SEMICONDUCTOR DEVICE HAVING A METAL OXIDE CHANNEL - A semiconductor device includes a metal oxide channel and methods for forming the same. The metal oxide channel includes indium, gallium, and zinc. | 2010-09-02 |
| 20100219412 | DISPLAY DEVICE WITH IMPROVED PIXEL LIGHT EMISSION AND MANUFACTURING METHOD OF THE SAME - A display device with pixels capable of uniform light emission and a method of making the display device are presented. A display device has a plurality of TFTs, a protection layer formed on the TFTs, and a plurality of pixel electrodes formed on the protection layer and electrically connected to the TFTs. A wall is formed around the pixel electrode and at least a portion of the wall is spaced from the pixel electrode. A light emitting layer is formed between the wall and another wall. | 2010-09-02 |
| 20100219413 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - An object is to provide a method for manufacturing a highly-reliable semiconductor device with an improved material use efficiency and with a simplified manufacturing process. The method includes the steps of forming a conductive layer over a substrate, forming a light-transmitting layer over the conductive layer, and selectively removing the conductive layer and the light-transmitting layer by irradiation with a femtosecond laser beam from above the light-transmitting layer. Note that the conductive layer and the light-transmitting layer may be removed so that an end portion of the light-transmitting layer is located on an inner side than an end portion of the conductive layer. Before the irradiation with a femtosecond laser beam, a surface of the light-transmitting layer may be subjected to liquid-repellent treatment. | 2010-09-02 |
| 20100219414 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel, according to an embodiment of the present invention, includes a first data line, a second data line neighboring the first data line, a transistor disposed in a region between the first data line and the second data line, and a pixel electrode disposed close to the second data line among the first and second data lines. An extension of the pixel electrode may cross the second data line, thereby being connected to the transistor. Accordingly, it may not be necessary to use an additional connecting member between the pixel electrode and the data line such that the process may be shortened and the structure of the wiring may be simplified. Also, the spatial utility may be increased to improve the degree of integration. | 2010-09-02 |
| 20100219415 | TRANSISTOR, FABRICATING METHOD THEREOF AND FLAT PANEL DISPLAY THEREWITH - A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other, a gate insulating layer formed on the active region, and a gate electrode formed on the gate insulating layer. | 2010-09-02 |
| 20100219416 | METHOD OF IMPROVING SURFACE MORPHOLOGY OF (GA,AL,IN,B)N THIN FILMS AND DEVICES GROWN ON NONPOLAR OR SEMIPOLAR (GA,AL,IN,B)N SUBSTRATES - A method for improving the growth morphology of (Ga,Al,In,B)N thin films on nonpolar or semipolar (Ga,Al,In,B)N substrates, wherein a (Ga,Al,In,B)N thin film is grown directly on a nonpolar or semipolar (Ga,Al,In,B)N substrate or template and a portion of the carrier gas used during growth is comprised of an inert gas. Nonpolar or semipolar nitride LEDs and diode lasers may be grown on the smooth (Ga,Al,In,B)N thin films grown by the present invention. | 2010-09-02 |
| 20100219417 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region. | 2010-09-02 |
| 20100219418 | DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 2010-09-02 |
| 20100219419 | SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor element which can suppress deterioration of element characteristics even when a semiconductor element section includes a plurality of directions having different thermal expansion coefficients within an in-plane direction. A semiconductor laser element (the semiconductor element) is provided with the semiconductor element section, which includes a direction of [1-100] and a direction of [0001] having different thermal expansion coefficients within the in-plane direction of a main surface, and a sub-mount, which includes an arrow (E) direction and an arrow (F) direction having different thermal expansion coefficients within the in-plane direction of the main surface. The semiconductor element section is bonded on the sub-mount so that the direction [1-100] of the semiconductor element section is close to the side of the arrow (E) direction than the arrow (F) direction of the sub-mount. | 2010-09-02 |
| 20100219420 | FK Module and Method for the Production Thereof - A module and method of its production in which areal electronic components are formed. The module includes (a) a cover electrode covering the electronic components; (b) a flexibly deformable substrate; (c) a base electrode formed on the substrate; and (d) an optically active layer faulted on the base electrode. The electronic components are formed on the flexibly deformable substrate by the optically active layer, the cover electrode; and the base electrode. The cover electrode projects over the optically active layer at a first side and the base electrode extends beyond the optically active layer at a second side which is oppositely disposed with regards to the first side. The components are arranged at a spacing from one another on the substrate and thereby a free substrate surface is present between components so that, on a folding in a region of the free substrate surface, the base electrode and the cover electrode are adjacent and contact one another areally and an electrically conductive touching contact is established. The electronic components are electrically connected in series with one another. | 2010-09-02 |
| 20100219421 | METHOD AND SYSTEM FOR ELECTRICALLY COUPLING A CHIP TO CHIP PACKAGE - A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds. | 2010-09-02 |
| 20100219422 | PHOTO-COUPLER - A photo-coupler is provided. The photo-coupler comprises a light emitting chip, a light-sensing chip, a light-transmissive inner encapsulant package and an outer package. Both the light emitting chip and the light-sensing chip face the same direction, while the light-sensing chip receives a light beam emitted by the light emitting chip. The light-transmissive inner encapsulant package encloses the light emitting chip and the light-sensing chip, while the outer package encloses the light-transmissive inner encapsulant package. An interface is formed between the light-transmissive inner encapsulant package and the outer package for reflecting the light beam. A reflective curve surface adjacent to the light emitting chip is formed on the interface of the light-transmissive inner encapsulant package for reflecting and converging the first portion of the light beam to the light-sensing chip. | 2010-09-02 |
| 20100219423 | Light Receiving or Light Emitting Semiconductor Module - Multiple semiconductor elements in a semiconductor module in which multiple spherical light receiving or emitting semiconductor elements are installed can easily be retrieved, reused, or repaired. In a semiconductor module | 2010-09-02 |
| 20100219424 | ORGANIC EL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An organic EL display panel is provided which includes: a substrate which includes a plurality of luminescent regions which are arranged side by side in a specific direction and run in parallel to one another; a bank formed over the substrate, the bank defining a plurality of coating regions in each of the luminescent regions, the coating regions being aligned in a row along the long axis of the luminescent region; and a pixel electrode provided in each of the coating regions, the pixel electrode having a long axis which is in parallel with the long axis of the luminescent region, wherein, in each of the luminescent regions, the coating region positioned at a lengthwise end of the luminescent region is larger in size than the coating region positioned at a lengthwise center of the luminescent region. | 2010-09-02 |
| 20100219425 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF LIGHT EMITTING CELLS CONNECTED IN SERIES AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting device having a plurality of light emitting cells connected in series and a method of fabricating the same. The light emitting device includes a buffer layer formed on a substrate. A plurality of rod-shaped light emitting cells are located on the buffer layer to be spaced apart from one another. Each of the light emitting cells has an n-layer, an active layer and a p-layer. Meanwhile, wires connect the spaced light emitting cells in series or parallel. Accordingly, arrays of the light emitting cells connected in series are connected to be driven by currents flowing in opposite directions. Thus, there is provided a light emitting device that can be directly driven by an AC power source. | 2010-09-02 |
| 20100219426 | LIGHT EMITTING DEVICE HAVING VERTICALLY STACKED LIGHT EMITTING DIODES - Disclosed is a light emitting device having vertically stacked light emitting diodes. It comprises a lower semiconductor layer of a first conductive type positioned on a substrate, a semiconductor layer of a second conductive type on the lower semiconductor layer of a first conductive type, and an upper semiconductor layer of a first conductive type on the semiconductor layer of a second conductive type. Furthermore, a lower active layer is interposed between the lower semiconductor layer of a first conductive type and the semiconductor layer of a second conductive type, and an upper active layer is interposed between the semiconductor layer of a second conductive type and the upper semiconductor layer of a first conductive type. Accordingly, there is provided a light emitting device having a structure in which a lower light emitting diode comprising the lower active layer and an upper light emitting diode comprising the upper active layer are vertically stacked. Therefore, light output per unit area of the light emitting device is enhanced as compared with a conventional light emitting device, and thus, a chip area of the light emitting device needed to obtain the same light output as the conventional light emitting device can be reduced. | 2010-09-02 |
| 20100219427 | LIGHT-EMITTING APPARATUS - Provided is a light-emitting apparatus in which light extraction efficiency of a light-emitting device is improved and viewing angle dependency of an emission color is reduced. The light-emitting apparatus includes a cavity structure and a periodic structure. When guided-wave light is diffracted by the periodic structure in a direction that forms an angle which is larger than 90° and smaller than 180° relative to a guided-wave direction of an optical waveguide in the cavity structure, a wavelength of the diffracted light becomes longer as the diffraction angle increases. | 2010-09-02 |
| 20100219428 | WARM WHITE LIGHT EMITTING APPARATUS AND BACK LIGHT MODULE COMPRISING THE SAME - A warm white light emitting apparatus includes a first light emitting diode (LED)-phosphor combination to generate a base light that is white or yellowish white and a second LED-phosphor combination to generate a Color Rendering Index (CRI) adjusting light. The base light and the CRI adjusting light together make a warm white light having a color temperature of 2500 to 4500K. | 2010-09-02 |
| 20100219429 | TOP-EMITTING OLED DEVICE WITH LIGHT-SCATTERING LAYER AND COLOR-CONVERSION - A top-emitting OLED device, comprising: one or more OLEDs formed on a substrate; a light-scattering layer formed over the one or more OLEDs; a transparent cover; one or more color filters formed on the transparent cover; a color-conversion material layer formed over the color filters, or formed over or integral with the light-scattering layer; wherein the substrate is aligned and affixed to the transparent cover so that the locations of the color filters and color conversion material correspond to the location of the OLEDs, and the color-conversion material layer, color filters, and the light-scattering layer are between the cover and substrate, and a low-index gap is formed between the light-scattering layer and the color filters, with no light-scattering layer being positioned between the color conversion material layer and the low-index gap, wherein the color-conversion material layer is formed integrally with the light-scattering layer. | 2010-09-02 |
| 20100219430 | Light emitting system, light emitting apparatus and forming method thereof - A light emitting system, a light emitting apparatus and the forming method thereof, the light emitting system comprising a plurality of light emitting units (100) and a frame for connecting the light emitting units. Each light emitting unit comprises a substrate (102), one or a plurality of chips (104) disposed on the substrate, an annular member (110) disposed on the substrate and surrounding the chips, the annular member used for adjusting the direction of the light emitted from the chips, and a protective layer (108) covering the chips, wherein the height of the protective layer is not more than that of the annular member. | 2010-09-02 |
| 20100219431 | Multi-Junction LED - A light source and method for making the same are disclosed. The light source includes a substrate and a light emitting structure that is deposited on the substrate. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first segment in series with the second segment. A first blocking diode between the light emitting structure and the substrate prevents current from flowing between the light emitting structure and the substrate when the light emitting structure is emitting light. The barrier extends through the light emitting structure into the first blocking diode. | 2010-09-02 |
| 20100219432 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a light emitting device. The light emitting device comprises a conductive substrate, an insulating layer on the conductive substrate, a plurality of light emitting device cells on the insulating layer, a connection layer electrically interconnecting the light emitting device cells, a first contact section electrically connecting the conductive substrate with at least one light emitting device cell, and a second contact section on the at least one light emitting device cell. | 2010-09-02 |
| 20100219433 | LIGHT EMITTING DEVICES - Light emitting devices conformally covered by a luminescent material layer are presented. A light emitting device includes a semiconductor light emitting die attached to a substrate. At least one bond pad is disposed on the semiconductor light emitting die. A luminescent material layer conformally covers the semiconductor light emitting die, wherein the luminescent material layer has at least one opening corresponding to and exposing the at least one bond pad. At least one wirebond is electrically connected to the at least one bond pad and a contact pad on the substrate. | 2010-09-02 |
| 20100219434 | LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device may include a reflective layer having a prescribed pattern of at least one shape having prescribed thickness, width and periodicity. The light emitting device may also include a light emitting layer formed on the reflective layer. The prescribed periodicity may be based on 0.75λ/n to 5λ/n, where λ is the wavelength of the light emitted from the light emitting layer, and n is the refractive index of the light emitting layer. | 2010-09-02 |
| 20100219435 | LIGHT EMITTING DEVICE - Provided is a light emitting device. The light emitting device comprises a body, a light emitting diode on the body, a resin layer on the light emitting diode, and a primer layer containing a metal material on the resin layer. | 2010-09-02 |
| 20100219436 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR LIGHT-EMITTING DEVICE - The present invention provides a semiconductor light-emitting device that includes a compound semiconductor layer formed by laminating a first clad layer, a light-emitting layer and a second clad layer, a plurality of first ohmic electrodes formed on the first clad layer, a plurality of second ohmic electrodes formed on the second clad layer, a transparent conductive film that is formed on the first clad layer of the compound semiconductor layer and is conductively connected to the first ohmic electrodes, a bonding electrode formed on the transparent conducting film, and a support plate that is positioned on the second clad layer side of the compound semiconductor layer and is conductively connected to the second ohmic electrodes. | 2010-09-02 |
| 20100219437 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE - A nitride semiconductor light emitting diode includes a p-type layer | 2010-09-02 |
| 20100219438 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light-emitting device comprises: a semiconductor substrate; a semiconductor layer structure on the semiconductor substrate, including an active layer and a waveguide ridge; an electrode in contact with all of a top surface of the waveguide ridge; and an insulating film coating side faces of the waveguide ridge, side faces of the electrode, and ends, but not a center portion, of an upper face of the electrode. | 2010-09-02 |
| 20100219439 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a substrate, a first semiconductor layer on substrate, an air-gap part disposed in at least portion between the substrate and the first semiconductor layer, and a plurality of compound semiconductor layers comprising a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the first semiconductor layer. | 2010-09-02 |
| 20100219440 | Inverted LED Structure with Improved Light Extraction - A light source and method for fabricating the same are disclosed. The light source includes a substrate and a light emitting structure. The substrate has a first surface and a second surface, the second surface including a curved, convex surface with respect to the first surface of the substrate. The light emitting structure includes a first layer of a material of a first conductivity type overlying the first surface, an active layer overlying the first layer, the active layer generating light when holes and electrons recombine therein, and a second layer includes a material of a second conductivity type overlying the active layer and a second surface opposite to the first surface. A mirror layer overlies the light emitting structure. | 2010-09-02 |
| 20100219441 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - An LED package structure and an LED packaging method are disclosed. The LED package structure includes a substrate, an LED unit and a transparent holding wall. The LED unit is electrically connected and located on the surface of the substrate. The transparent holding wall that corresponds to the LED unit is formed on the surface of the substrate, and has a receiving space. The LED unit is received in the receiving space. By utilizing the transparent holding wall, the colloid is controllably received in the receiving space and uniformly spread on the surface of the LED unit and around the LED unit. Thereby, the quantity of the colloid is easily controlled, and the LED package structure has a wide lighting angle due to the light emitted from the LED unit can pass through the transparent holding wall. | 2010-09-02 |
| 20100219442 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF - Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device includes a light emitting structure, an insulating substrate, a first electrode, a second electrode, and a conductive supporting substrate. The light emitting structure includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The insulating substrate is formed on the light emitting structure to include a contact groove. The first electrode is formed on the insulating substrate. The second electrode is formed under the light emitting structure. The conductive supporting substrate is formed under the second electrode. | 2010-09-02 |
| 20100219443 | LED Packaging Structure With Blind Hole Welding Device - The present invention provides a LED packaging structure, and more particularly to an innovative one designed with blind hole welding device. It at least comprises: a packaging body, which is provided with a wiring substrate; metal layers are separately arranged at both sides for coating the wiring substrate; the metal layers are divided into three portions, i.e. metal layer | 2010-09-02 |
| 20100219444 | Manufacturing method of mounting part of semiconductor light emitting element, manufacturing method of light emitting device, and semiconductor light emitting element - A manufacturing method of a mounting part of a semiconductor light emitting element comprising: preparing a semiconductor light emitting element including an electrode which has a surface, and a board which has a surface; forming a plurality of bump material bodies on at least one of the surface of the electrode and the surface of the board by shaping bump material into islands, wherein the bump material is paste in which metal particles are dispersed, a top surface and a bottom surface of the bump material bodies have different areas, and the top surface is practically flat; solidifying the bump material bodies by thermally processing the bump material bodies; and fixing the semiconductor light emitting element and the board through the bumps. | 2010-09-02 |
| 20100219445 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND LAMP - A buffer layer | 2010-09-02 |
| 20100219446 | HIGH SPEED IGBT - An IGBT with almost no tail during turning-off is formed by connection of both the base and the emitter of the BJT of the IGBT at the bottom of the chip to two regions in an area of the top surface of the chip. The two regions keep non-depleted even under a maximum voltage being applied across the collector and the base of the BJT. The current through the two regions can be controlled by a gate voltage of a place close to the active region of the MISFET of the IGBT through a surface voltage-sustaining region. The injection efficiency of minorities of the IGBT can thus be controlled. | 2010-09-02 |
| 20100219447 | SEMICONDUCTOR DEVICE | 2010-09-02 |
| 20100219448 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING PLASMA DISPLAY USING THE SEMICONDUCTOR DEVICE - The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed. | 2010-09-02 |
| 20100219449 | METHOD AND APPARATUS FOR HETEROJUNCTION BARRIER DIODE DETECTOR FOR ULTRAHIGH SENSITIVITY - The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure. | 2010-09-02 |
| 20100219450 | ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES - A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap. | 2010-09-02 |
| 20100219451 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A p-type nitride compound semiconductor layer is formed on a buffer formed on a substrate. An n-type contact region is formed by ion implantation under a source electrode and a drain electrode. An electric-field reducing layer made of an n-type nitride compound semiconductor is formed on the p-type nitride compound semiconductor layer. A career density of the electric-field reducing layer is lower than that of the n-type contact region. A first end portion of the electric-field reducing layer contacts with the n-type contact region, and a second end portion of the electric-field reducing layer overlaps with a gate electrode. | 2010-09-02 |
| 20100219452 | GaN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) STRUCTURES - A GaN HEMT structure having: a first III-N layer on GaN; a source electrode in contact with a first surface portion the first III-N layer disposed over a first region in the GaN layer; a drain electrode in contact with a second surface portion of the first III-N layer disposed over a second region in the GaN layer; a gate electrode disposed over a third surface portion of the first III-N layer, such third surface portion being disposed over a third region in the GaN layer. The GaN layer has: a fourth region therein disposed between the first region therein and the third region; and a fifth region therein disposed between the third region therein and the second region therein. A second III-N layer is disposed over the first III-N layer for generating a two-dimensional electron gas density in the GaN density in at least one of the fourth region and fifth region greater than the density in the third region of the GaN layer. | 2010-09-02 |
| 20100219453 | Nanotube Device - A device includes a nanotube source electrode located on a surface of a substrate between nanotube gate and nanotube drain electrodes. | 2010-09-02 |
| 20100219454 | FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field-effect transistor with improved moisture resistance without an increase in gate capacitance, and a method of manufacturing the field-effect transistor are provided. The field-effect transistor includes: a T-shaped gate electrode on a semiconductor layer; and a first highly moisture-resistant protective film including one of an insulating film and an organic film having high etching resistance, the first highly moisture-resistant protective film being located above the T-shaped gate electrodes over all of a region in which the T-shaped gate electrode is located. A cavity is located between the semiconductor layer and the first highly moisture-resistant protective film below a canopy of the T-shaped gate electrode. An end surface of the cavity is closed by a second highly moisture-resistant film. | 2010-09-02 |
| 20100219455 | III-NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An active layer of a first conductive-type includes a channel area. A first contact area and a second contact area of a second conductive-type are formed at positions across the channel area. A source electrode is formed on the first contact area. A drain electrode is formed on the second contact area. A gate electrode is formed above the channel area via a gate insulating layer. A reduced surface field zone of the second conductive-type is formed in the channel area at a position close to the second contact area. Thickness of the reduced surface field zone is 30 nanometers to 100 nanometers. | 2010-09-02 |
| 20100219456 | FORMING INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATE ELECTRODES - In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement. | 2010-09-02 |
| 20100219457 | SOLID-STATE IMAGING DEVICE - It is an object to provide an image sensor having a sufficiently-large ratio of a surface area of a light-receiving section to an overall surface area of one pixel. This object is achieved by a solid-state imaging device comprising: a signal line formed on a substrate; an island-shaped semiconductor arranged on the signal line; and a pixel selection line connected to a top of the island-shaped semiconductor, wherein the island-shaped semiconductor includes: a first semiconductor layer formed as a bottom portion of the island-shaped semiconductor and connected to the signal line; a second semiconductor layer formed above and adjacent to the first semiconductor layer; a gate connected to the second semiconductor layer through a dielectric film; a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; and a fourth semiconductor layer formed above and adjacent to the second and third semiconductor layers, and wherein the pixel selection line is comprised of a transparent conductive film, and a part of the gate is disposed inside a depression formed in a sidewall of the second semiconductor layer. | 2010-09-02 |
| 20100219458 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The data retention characteristics of a nonvolatile memory circuit are improved. In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an insulating film | 2010-09-02 |
| 20100219459 | METHOD FOR MANUFACTURING A NON-VOLATILE MEMORY, NON-VOLATILE MEMORY DEVICE, AND AN INTEGRATED CIRCUIT - A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure. | 2010-09-02 |
| 20100219460 | Semiconductor device and method for manufacturing the same - A semiconductor device including a semiconductor substrate, a tunnel insulation film provided on the surface of the semiconductor substrate, charge trap states at which an electron potential energy is higher than a Fermi level of the semiconductor substrate being provided at part of the tunnel insulation film at least in the vicinity of an interface with the semiconductor substrate, and at least one charge storage layer being provided on the tunnel insulation film, charges supplied from the semiconductor substrate via the tunnel insulation film being accumulated in the charge storage layer. | 2010-09-02 |
| 20100219461 | Structure With PN Clamp Regions Under Trenches - A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween. | 2010-09-02 |
| 20100219462 | MOS-Gated Power Devices, Methods, and Integrated Circuits - MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances. | 2010-09-02 |
| 20100219463 | QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer. | 2010-09-02 |
| 20100219464 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer. | 2010-09-02 |
| 20100219465 | SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section. | 2010-09-02 |
| 20100219466 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed. | 2010-09-02 |
| 20100219467 | SEMICONDUCTOR DEVICE HAVING SADDLE FIN TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a transistor having the saddle fin structure. The saddle fin transistor of the present invention has a structure in which a landing plug contact region, particularly, a landing plug contact region on an isolation layer is elevated such that the landing plug contact SAC (Self Aligned Contact) fail can be prevented. | 2010-09-02 |
| 20100219468 | POWER DEVICE STRUCTURES AND METHODS - Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling. | 2010-09-02 |
| 20100219469 | MASK ROM CELL STRUCTURE AND METHOD OF FABRICATING THE SAME - A mask read-only memory (ROM) cell structure includes buried gate electrodes, common source regions under the gate electrodes, common drain regions extending between upper portions of adjacent ones of the gate electrodes, and two vertical channel regions on opposite sides, respectively, of each of the gate electrodes. The channel regions are selectively coded such that the cell transistors are on or off depending on whether the channel region of the transistor is coded. To this end, selected ones of the channel regions of the mask ROM structure are coded by forming ion implantation regions that differentiate the threshold voltages of the thus coded channel regions from the non-coded channel regions. The coding process may thus be carried out using a shallow ion implantation process. Accordingly, a relatively thin mask for coding may be used, and the ion implantation process may be carried out at a relatively low energy level. | 2010-09-02 |
| 20100219470 | SEMICONDUCTOR DEVICE HAVING A SADDLE FIN SHAPED GATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions. | 2010-09-02 |
| 20100219471 | QUASI-RESURF LDMOS - A semiconductor device can include a drift region, at least a portion of the drift region located laterally between a drain region and a source region. The drift region can include a first layer having a first doping concentration and a second layer having a second higher doping concentration than the first layer. The second layer of the drift region be configured to allow drift current between the source region and the drain region when a depletion region is formed in at least a portion of the first layer between the source region and the drain region. | 2010-09-02 |
| 20100219472 | Semiconductor device and method of manufacturing the same - In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed. | 2010-09-02 |
| 20100219473 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region. | 2010-09-02 |
| 20100219474 | TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE - A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure. | 2010-09-02 |
| 20100219475 | INTEGRATION OF SEMICONDUCTOR ALLOYS IN PMOS AND NMOS TRANSISTORS BY USING A COMMON CAVITY ETCH PROCESS - Different strain-inducing semiconductor alloys may be incorporated into the drain and source areas of different transistors in sophisticated semiconductor devices by at least patterning the corresponding cavities in a common manufacturing sequence. Thus, the etch process may be performed on the basis of a high degree of uniformity and the subsequent epitaxial growth processes may, in some illustrative embodiments, be accomplished on the basis of only one additional lithography step. | 2010-09-02 |
| 20100219476 | ELECTROSTATIC PROTECTION DEVICE FOR SEMICONDUCTOR CIRCUIT - The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and sources and drains alternately arranged at both sides of the gates in the semiconductor substrate. A well pickup surrounding every set of the transistor fingers and extending between any two set of the fingers is formed. Metal wires are connected to at least two portions of each of the drains and are also connected to an input/output pad to which Electrostatic Discharge (ESD) excessive current is introduced. | 2010-09-02 |
| 20100219477 | METHOD FOR THE PRODUCTION OF MOS TRANSISTORS - The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents that allows for parallel logic/switching transistors. This is achieved by initially carrying out an LDD ion implantation via the edges of the gates in order to form an LDD region and subsequently removing the spacers by means of an anisotropic etching step exhibiting high selectivity in relation to the gate and substrate materials, including the covering layers thereof, or by covering the MOS transistors with an extremely low leakage currents prior to isotropic spacer production such that the spacers are formed exclusively on the edges of the gates of the logic/switching transistors, while the MOS transistors with an extremely low leakage current always remain connected solely via the LDD region, and there is no high dose implantation in the S/D regions of these MOS transistors with extremely low leakage currents. | 2010-09-02 |
| 20100219478 | MOSFET, METHOD OF FABRICATING THE SAME, CMOSFET, AND METHOD OF FABRICATING THE SAME - The present invention provides an NMOSFET including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the gate insulating film. The first gate electrode is composed of silicide of a metal M, and at least one element selected as an impurity from a group consisting of sulfur (S), fluorine (F) and chlorine (Cl). The impurity exists as an impurity layer at a surface of the first gate electrode at which the first gate electrode makes contact with the gate insulating film. | 2010-09-02 |
| 20100219479 | MOS DEVICE AND METHOD OF FABRICATING A MOS DEVICE - The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device ( | 2010-09-02 |
| 20100219480 | Field effect transistor, integrated circuit element, and method for manufacturing the same - A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region. | 2010-09-02 |
| 20100219481 | METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF - A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack. | 2010-09-02 |
| 20100219482 | SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a Loadless 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area. | 2010-09-02 |
| 20100219483 | SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area. | 2010-09-02 |
| 20100219484 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less. | 2010-09-02 |
| 20100219485 | FORMATION OF RAISED SOURCE/DRAIN STUCTURES IN NFET WITH EMBEDDED SIGE IN PFET - A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains. | 2010-09-02 |
| 20100219486 | METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY - A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide. | 2010-09-02 |
| 20100219487 | METHOD FOR MANUFACTURING A SENSOR COMPONENT AND SENSOR COMPONENT - A method for manufacturing a sensor component and a sensor component. The sensor component has a semiconductor substrate and a metal substrate. The semiconductor substrate and the metal substrate are bonded together with the aid of a low-temperature process. A bonding material containing metal particles is applied in a first step to the semiconductor substrate and/or the metal substrate and a sintering process is used in a second step for producing the bond between the semiconductor substrate and the metal substrate. | 2010-09-02 |
| 20100219488 | SILICON STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND SENSOR CHIP - A silicon structure of the present invention is provided with a silicon substrate ( | 2010-09-02 |
| 20100219489 | NANOWIRE SENSOR DEVICE - The invention concerns a sensor device, of nanowire type, comprising at least one nanowire comprising a first conductive region ( | 2010-09-02 |
| 20100219490 | SEMICONDUCTOR SENSOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor sensor has a first semiconductor layer as a base, an insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the insulating layer. A recess is formed from a bottom surface of the first semiconductor layer up to a top surface of the insulating layer. The second semiconductor layer is covered with the insulating layer in an outer circumference of a top surface of the recess. A sensitive region of the second semiconductor layer is exposed in a region except the outer circumference of the top surface of the recess. | 2010-09-02 |
| 20100219491 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material. | 2010-09-02 |
| 20100219492 | LOW SWITCHING FIELD LOW SHAPE SENSITIVITY MRAM CELL - Disclosed is a Magnetic Tunnel Junction (MTJ) stack usable in a nonvolatile magnetic memory array of MTJ stacks, the MTJ stack comprising: a) a fixed ferromagnetic layer having its magnetic moment fixed in a preferred direction in the presence of an applied magnetic field caused by a current; b) an insulating tunnel barrier layer in contact with the fixed ferromagnetic layer; and c) a free ferromagnetic layer in contact with the insulating tunnel barrier layer, the free ferromagnetic layer comprising a synthetic anti-ferromagnet (SAF) stack comprising i) at least three ferromagnetic layers arranged anti-ferromagnetically relative to the next, and ii) at least two coupling layers, wherein the at least three ferromagnetic layers are separated by the at least two coupling layers. | 2010-09-02 |
| 20100219493 | Method of Forming a Magnetic Tunnel Junction Device - A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped. | 2010-09-02 |
| 20100219494 | Sub-mm Wireless Ionizing Radiation Detector - One embodiment of a radiation sensing capacitor is presented. The radiation sensing capacitor may include a silicon layer and an insulator layer coupled to the silicon layer. The radiation sensing capacitor may also include a silicon-insulator interface region coupling the silicon layer to the insulator layer and a plurality of hole-trapping precursors formed in the insulator layer proximate to the silicon-insulator interface region. | 2010-09-02 |
| 20100219495 | Photosensitizing chip package & manufacturing method thereof - A photosensitizing chip package construction and manufacturing method thereof is comprised of photosensitizing chips constructed on one side of a wafer using a bonding layer; a color attachment array being disposed over those photosensitizing chips; a glass substrate provided with weir and covered up over the color attachment array; a proper gap being defined between the glass substrate and the color attachment array to promote permeability of stream of light by direct receiving stream of light from those photosensitizing chips constructed over the wafer. | 2010-09-02 |
| 20100219496 | WAFER ARRANGEMENT AND A METHOD FOR MANUFACTURING THE WAFER ARRANGEMENT - The wafer arrangement ( | 2010-09-02 |
| 20100219497 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - The present invention, in a photoelectric conversion device in which a pixel including a photoelectric conversion device for converting a light into a signal charge and a peripheral circuit including a circuit for processing the signal charge outside a pixel region in which the pixel are disposed on the same substrate, comprising: a first semiconductor region of a first conductivity type for forming the photoelectric region, the first semiconductor region being formed in a second semiconductor region of a second conductivity type; and a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type for forming the peripheral circuit, the third and fourth semiconductor regions being formed in the second semiconductor region; wherein in that the impurity concentration of the first semiconductor region is higher than the impurity concentration of the third semiconductor region. | 2010-09-02 |
