35th week of 2011 patent applcation highlights part 34 |
Patent application number | Title | Published |
20110212563 | Apparatus and Method of Wafer Bonding Using Compatible Alloy - A method of forming an inertial sensor provides 1) a device wafer with a two-dimensional array of inertial sensors and 2) a second wafer, and deposits an alloy of aluminum/germanium onto one or both of the wafers. The alloy is deposited and patterned to form a plurality of closed loops. The method then aligns the device wafer and the second wafer, and then positions the alloy between the wafers. Next, the method melts the alloy, and then solidifies the alloy to form a plurality of conductive hermetic seal rings about the plurality of the inertial sensors. The seal rings bond the device wafer to the second wafer. Finally, the method dices the wafers to form a plurality of individual, hermetically sealed inertial sensors. | 2011-09-01 |
20110212564 | METHOD FOR PRODUCING PHOTOVOLTAIC CELL - In a method for producing a photovoltaic cell, the improvement comprising:
| 2011-09-01 |
20110212565 | Humidity Control and Method for Thin Film Photovoltaic Materials - A method for processing a thin film photovoltaic module. The method includes providing a plurality of substrates, each of the substrates having a first electrode layer and an overlying absorber layer composed of copper indium gallium selenide (CIGS)or copper indium selenide (CIS) material. The absorber material comprises a plurality of sodium bearing species. The method maintains the plurality of substrates in a controlled environment after formation of at least the absorber layer through one or more processes up to a lamination process. The controlled environment has a relative humidity of less than 10% and a temperature ranging from about 10 degrees Celsius to about 40 degrees Celsius. The method subjects the plurality of substrates to a liquid comprising water at a temperature from about 10 degrees Celsius to about 80 degrees Celsius to process the plurality of substrates after formation of the absorber layer. The plurality of substrates having the absorber layer is subjected to an environment having a relative humidity of greater than about 10% to a time period of less then four hours. | 2011-09-01 |
20110212566 | OPTICALLY CONTROLLED ELECTRICAL-SWITCH DEVICE BASED UPON CARBON NANOTUBES AND ELECTRICAL-SWITCH SYSTEM USING THE SWITCH DEVICE - Described herein is an optically controlled electrical-switch device which includes a first current-conduction terminal and a second current-conduction terminal, and a carbon nanotube connected between the first and the second current-conduction terminals, the carbon nanotube being designed to be impinged upon by electromagnetic radiation and having an electrical conductivity that can be varied by varying the polarization of the electromagnetic radiation incident thereon. In particular, the carbon nanotube may for example, in given conditions of electrical biasing, present a high electrical conductivity when it is impinged upon by electromagnetic radiation having a given wavelength and a polarization substantially parallel to the axis of the carbon nanotube itself, and a reduced electrical conductivity when it is impinged upon by electromagnetic radiation having a given wavelength and a polarization substantially orthogonal to the axis of the carbon nanotube itself. | 2011-09-01 |
20110212567 | METHOD OF FABRICATING IMAGE SENSOR AND REWORKING METHOD THEREOF - A method of fabricating an image sensor device is provided. First, a substrate comprising a pixel array region and a pad region is provided. A patterned metal layer and a first planarization layer having an opening exposing the patterned metal layer in the pad region are sequentially formed on the substrate. A color filter array is formed on the first planarization layer in the pixel array region. A second planarization layer is formed to cover the color filter array and filled into the opening. A plurality of microlens is formed above the color filter array on the second planarization layer. A capping layer is conformally formed on the microlens and the second planarization layer. An etching step is performed to remove the capping layer and the second planarization layer in the opening so as to expose the patterned metal layer in the pad region. | 2011-09-01 |
20110212568 | Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same - A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown on the lower electrode. | 2011-09-01 |
20110212569 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified. | 2011-09-01 |
20110212570 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device, a semiconductor device with low power consumption, a semiconductor device with high productivity, and a method for manufacturing such a semiconductor device. Impurities left remaining in an oxide semiconductor layer are removed without generating oxygen deficiency, and the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after oxygen is added to the oxide semiconductor layer, heat treatment is performed on the oxide semiconductor layer to remove the impurities. In order to add oxygen, it is preferable to use a method in which oxygen having high energy is added by an ion implantation method, an ion doping method, or the like. | 2011-09-01 |
20110212571 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. | 2011-09-01 |
20110212572 | SEMICONDUCTOR DEVICE SUPPORT FOR BONDING - In one embodiment, a support structure comprises a base, a compliant layer, and a protective layer which is used to secure a semiconductor device, such as a lead-frame, to a window clamp during a bonding process. The compliant layer distributes even loading over the surface of the semiconductor device while clamped. In other embodiments, the compliant layer may be segmented into individual portions corresponding with openings in the window clamp. The window clamp may also have a compliant layer and a protective layer and may be used with or without a compliant layer on the support structure. Features on the protective layer may be included to support structures of the semiconductor device. | 2011-09-01 |
20110212573 | RIGID-BACKED, MEMBRANE-BASED CHIP TOOLING - An apparatus for use with multiple individual chips having a rigid plate, and a deformable membrane located on the plate, the deformable membrane having a thickness sufficient to allow the deformable membrane to peripherally conform to each of the individual multiple chips irrespective of any difference in height among the multiple individual chips and to prevent each of the multiple individual chips from moving in a lateral direction, the deformable membrane being configured to uniformly transfer a vertical force, applied to the rigid plate, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded during a connect and release cycle without causing damage to the individual chips or bonding surface. | 2011-09-01 |
20110212574 | PROCESSING METHOD FOR PACKAGE SUBSTRATE - A processing method for a package substrate having a base substrate partitioned by a plurality of crossing division lines to form a plurality of chip forming areas where a plurality of semiconductor chips are respectively formed and molded with resin. The package substrate has a resin surface and an electrode surface opposite to the resin surface. The processing method includes a warp correcting step of cutting the package substrate from the resin surface or the electrode surface along the division lines by using a cutting blade to form a cut groove, thereby correcting a warp of the package substrate, and a grinding step of grinding the resin surface of the package substrate in the condition where the electrode surface of the package substrate is held on a holding table after performing the warp correcting step, thereby reducing the thickness of the package substrate to a predetermined thickness. | 2011-09-01 |
20110212575 | METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved. | 2011-09-01 |
20110212576 | SEMICONDUCTOR HETEROSTRUCTURE NANOWIRE DEVICES - Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals. | 2011-09-01 |
20110212577 | SEMICONDUCTOR POWER DEVICE HAVING A STACKED DISCRETE INDUCTOR STRUCTURE - A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto. | 2011-09-01 |
20110212578 | SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME - Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer. | 2011-09-01 |
20110212579 | Fully Depleted SOI Multiple Threshold Voltage Application - An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric. | 2011-09-01 |
20110212580 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A thin film transistor (TFT) using an oxide semiconductor layer as an active layer, a method of manufacturing the TFT, and a flat panel display (FPD) including the TFT are taught. The TFT includes a gate electrode formed on a substrate, an oxide semiconductor layer electrically insulated from the gate electrode by a gate insulating layer, and the oxide semiconductor layer including a channel region, a source region, and a drain region, and a source electrode and a drain electrode respectively electrically contacting the source region and the drain region. The oxide semiconductor layer is formed of an InZnO or IZO layer (indium zinc oxide layer) including Zr. The carrier density of the IZO layer is controlled to be 1×10 | 2011-09-01 |
20110212581 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An array substrate for a liquid crystal display device comprises a substrate having a pixel region, a gate line on the substrate, and a data line crossing the gate line to define the pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, an insulating layer on the gate electrode, an active layer on the insulating layer, an ohmic contact layer on the active layer, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode. A pixel electrode connects to the drain electrode and is disposed in the pixel region. An opaque metal pattern is provided on end portions of the pixel electrode. | 2011-09-01 |
20110212582 | Method Of Manufacturing High Electron Mobility Transistor - A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate. | 2011-09-01 |
20110212583 | Method For Providing Semiconductors Having Self-Aligned Ion Implant - A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500° C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters. | 2011-09-01 |
20110212584 | Phosphorus Activated NMOS Using SiC Process | 2011-09-01 |
20110212585 | Semiconductor Device with Reliable High-Voltage Gate Oxide and Method of Manufacture Thereof - A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material. | 2011-09-01 |
20110212586 | Method for Forming Shielded Gate Field Effect Transistors - A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED. | 2011-09-01 |
20110212587 | ASYMMETRIC SOURCE AND DRAIN STRESSOR REGIONS - A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region. | 2011-09-01 |
20110212588 | Replacing Symmetric Transistors with Asymmetric Transistors - A semiconductor structure includes a symmetric metal-oxide-semiconductor (MOS) transistor comprising a first and a second asymmetric MOS transistor. The first asymmetric MOS transistor includes a first gate electrode, and a first source and a first drain adjacent the first gate electrode. The second asymmetric MOS transistor includes a second gate electrode, and a second source and a second drain adjacent the second gate electrode. The first gate electrode is connected to the second gate electrode, wherein only one of the first source and the first drain is connected to only one of the respective second source and the second drain. | 2011-09-01 |
20110212589 | Semiconductor device manufacturing method - A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; | 2011-09-01 |
20110212590 | HIGH TEMPERATURE IMPLANTATION METHOD FOR STRESSOR FORMATION - An integrated circuit device and method of fabricating the integrated circuit device is disclosed. According to one of the broader forms of the invention, a method involves providing a semiconductor substrate. A combination of a pre-amorphous implantation process, a high temperature carbon implantation process, and/or an annealing process are performed on the substrate to form a stressor region. | 2011-09-01 |
20110212591 | METHOD FOR FABRICATING TRANSISTOR OF SEMICONDUCTOR DEVICE - A method for fabricating a transistor of a semiconductor device includes: forming a gate pattern over a substrate; forming a junction region by performing an on implantation process onto the substrate at opposite sides of the gate pattern; performing a solid phase epitaxial (SPE) process on the junction region at a temperature approximately ranging from 770° C. to 850° C.; and performing a rapid thermal annealing (RTA) process on the junction region. | 2011-09-01 |
20110212592 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack. | 2011-09-01 |
20110212593 | CMP Process Flow for MEMS - The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode. | 2011-09-01 |
20110212594 | SEMICONDUCTOR DEVICE HAVING ELEMENT ISOLATION REGION - An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer. | 2011-09-01 |
20110212595 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF MAKING - A process for fabricating a semiconductor device having reduced capacitance for high frequency circuit protection is disclosed that comprises first forming an n+ buried layer in a p-type substrate by depositing n-type dopant on the top surface of the substrate and then drive in or by implanting n-type material into the substrate, and then growing an n-type epitaxial layer atop the n+ buried layer as the device layer. Trenches that surrounds the device region with depth extending from the top surface, going through the n+ buried layer and reaching down to the substrate are then formed and then an n+ layer on the sidewalls of the trenches is formed by diffusion or ion implantation. The trenches are then filled by growing a layer of thermal oxide on the sidewalls of the trenches and followed by deposition of plasma enhanced oxide, nitride, TEOS oxide CVD oxide, or polysilicon into the trenches and then planarizing the top surface by plasma etch back or polishing. Then n+ region of the device is formed by forming an oxide layer on the top surface of the device layer and then etching the oxide by photolithography, then depositing n-type dopant material and then driving in by high temperature diffusion. Finally p+ region of the device is formed by etching the oxide using photolithography, then depositing p-type dopant material by solid or gas phase deposition or ion implantation and then driving in by high temperature diffusion so that the breakdown voltage between cathode and anode of the device is set to a targeted voltage for high frequency circuit protection. | 2011-09-01 |
20110212596 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere. | 2011-09-01 |
20110212597 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Suppression of generation of a stripe pattern (unevenness) when an SOI substrate is manufactured by a glass substrate and a single crystal semiconductor substrate bonded to each other. A single crystal semiconductor substrate is irradiated with ions so that a fragile region is formed in the single crystal semiconductor substrate; a depression or a projection is formed in a region of a surface of an insulating layer provided on the single crystal semiconductor substrate, the region corresponding to the periphery of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate; thermal treatment is performed thereon to separate the single crystal semiconductor substrate at the fragile region, so that a single crystal semiconductor layer is formed over the base substrate; and the single crystal semiconductor layer in the region corresponding to the periphery is removed. | 2011-09-01 |
20110212598 | METHOD FOR MANUFACTURING BONDED WAFER - The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature. As a result, there is provided a method for manufacturing a bonded wafer having high quality, for example, mainly the reduction of defects, by forming a high bonding strength state at a lower temperature than the temperature at which the delamination is caused, in the manufacture of the bonded wafer by the Smart Cut method (registered trademark). | 2011-09-01 |
20110212599 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - Provided is a method of manufacturing a semiconductor device using a substrate processing apparatus including a reaction chamber in which a plurality of substrates are stacked at a predetermined distance; a first gas supply nozzle installed to extend to a region in which the plurality of substrates are stacked; a second gas supply nozzle installed to extend to a different position from a position at which the first gas supply nozzle is installed in the region in which the plurality of substrates are stacked; a first branch nozzle installed at the first gas supply nozzle in a direction parallel to major surfaces of the plurality of substrates, at least one line of which is branched in a direction of the second gas supply nozzle, and including at least one first gas supply port; and a second branch nozzle installed at the second gas supply nozzle in the direction parallel to the major surfaces of the plurality of substrates, at least one line of which is branched in a direction of the first gas supply nozzle, and including at least one second gas supply port; wherein the first gas supply port and the second gas supply port are installed adjacent to each other in a direction that the plurality of substrates are stacked, the method including the steps of: loading the plurality of substrates into the reaction chamber; and forming SiC films by supplying at least a silicon-containing gas and a chlorine-containing gas or a silicon/chlorine-containing gas through the first gas supply port and supplying at least a carbon-containing gas and a reduction gas through the second gas supply port. | 2011-09-01 |
20110212600 | METHOD FOR FORMING CHANNEL LAYER WITH HIGH GE CONTENT ON SUBSTRATE - A method for forming a channel layer with high Ge content on a substrate is provided. The method may comprise steps of: preparing the substrate ( | 2011-09-01 |
20110212601 | Stress-Enhanced Performance Of A Finfet Using Surface/Channel Orientations And Strained Capping Layers - Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs. | 2011-09-01 |
20110212602 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same. | 2011-09-01 |
20110212603 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 2011-09-01 |
20110212604 | METHOD OF FABRICATING TRANSISTOR - A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer. | 2011-09-01 |
20110212605 | METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND DEPOSITION APPARATUS - An object of the present invention is to provide an apparatus for successive deposition used for manufacturing a semiconductor element including an oxide semiconductor in which impurities are not included. By using the deposition apparatus capable of successive deposition of the present invention that keeps its inside in high vacuum state, and thus allows films to be deposited without being exposed to the air, the entry of impurities such as hydrogen into the oxide semiconductor layer and the layer being in contact with the oxide semiconductor layer can be prevented; as a result, a semiconductor element including a high-purity oxide semiconductor layer in which hydrogen concentration is sufficiently reduced can be manufactured. In such a semiconductor element, off-state current is low, and a semiconductor device with low power consumption can be realized. | 2011-09-01 |
20110212606 | Method of Fabricating Thin Film Transistor Structure - A method of fabricating a thin film transistor (TFT) is provided. The method comprises the steps of providing a substrate with a gate electrode formed thereon; forming an insulating layer on the substrate and covering the gate electrode; forming an intrinsic amorphous silicon layer (intrinsic a-Si layer) on the insulating layer; forming an etch-stop layer on the intrinsic amorphous silicon layer, and the etch-stop layer positioned correspondingly to the gate electrode; treating the etch-stop layer to form an oxide layer, and the oxide layer covering the etch-stop layer; forming a n+ a-Si layer above the intrinsic amorphous silicon layer, and the n+ a-Si layer covering partial surface of the etch-stop layer and the oxide layer separating a sidewall of the etch-stop layer and the n+ a-Si layer; and forming a conductive layer on the n+ a-Si layer. | 2011-09-01 |
20110212607 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns. | 2011-09-01 |
20110212608 | Sputtering-Less Ultra-Low Energy Ion Implantation - Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided. | 2011-09-01 |
20110212609 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate. | 2011-09-01 |
20110212610 | METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions. | 2011-09-01 |
20110212611 | METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions. | 2011-09-01 |
20110212612 | MEMORY DEVICES INCLUDING DIELECTRIC THIN FILM AND METHOD OF MANUFACTURING THE SAME - A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided. | 2011-09-01 |
20110212613 | SEMICONDUCTOR DEVICES HAVING A FUSE AND METHODS OF CUTTING A FUSE - A semiconductor device and methods of cutting a fuse of a semiconductor device are provided, the semiconductor device includes a semiconductor substrate that includes a fuse region, a plurality of fuse patterns disposed in the fuse region of the semiconductor substrate, and an insulating layer that insulates the fuse patterns from the semiconductor substrate. The fuse patterns each include a fuse. The fuse patterns are linked to the semiconductor substrate. | 2011-09-01 |
20110212614 | MICROELECTRONIC WORKPIECES AND METHOD FOR MANUFACTURING MICROELECTRONIC DEVICES USING SUCH WORKPIECES - Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection. In several embodiments, a microelectronic die can be coupled to the corresponding bond sites carried by the projection in a flip-chip configuration. | 2011-09-01 |
20110212615 | MANUFACTURING METHOD OF A BUMP STRUCTURE HAVING A REINFORCEMENT MEMBER - A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface. | 2011-09-01 |
20110212616 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING ROUNDED INTERCONNECTS FORMED BY HARD MASK ROUNDING - In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-aligned via trench concept. Consequently, self-aligned interconnect structures may be obtained, while at the same time providing superior fill conditions during the deposition of barrier materials and conductive fill materials. | 2011-09-01 |
20110212617 | LIQUID FOR PROTECTING COPPER WIRING SURFACE AND METHOD FOR MANUFACTURING SEMICONDUCTOR CIRCUIT ELEMENT - A copper wiring material surface protective liquid is provided that is used in production of a semiconductor circuit device containing copper wiring, and consists of an aqueous solvent and an acetylene alcohol compound containing at least 3-phenyl-2-propyn-1-ol. A method for producing a semiconductor circuit device is provided that contains: forming an insulating film and/or a diffusion preventing film on a silicon substrate; then forming a copper film by a sputtering; then forming a copper film or a copper alloy film containing 80% by mass or more of copper thereon by a plating method; and flattening the film by a chemical mechanical polishing (CMP) method, thereby providing a semiconductor substrate containing a flattened copper wiring, in which the semiconductor substrate having an exposed surface of a copper wiring material is treated by making in contact with the copper wiring material surface protective liquid. | 2011-09-01 |
20110212618 | TRENCH INTERCONNECT STRUCTURE AND FORMATION METHOD - Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I | 2011-09-01 |
20110212619 | Semiconductor Device Having Dummy Pattern and the Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern. | 2011-09-01 |
20110212620 | POST-PLANARIZATION DENSIFICATION - Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma. | 2011-09-01 |
20110212621 | ABRASIVE COMPOSITION AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention relates to a polishing composition used in a step of polishing until a barrier layer adjacent to a copper layer is exposed, in a pattern formation of polishing the copper layer provided on an insulating layer through the barrier layer thereby alternately forming a copper embedded wiring and the insulating layer, the polishing composition including: an alicyclic resin acid; a colloidal silica in which a content thereof in the polishing composition is from 0.1 to 1.5% by mass, an average primary particle size thereof is from 10 to 40 nm, an average secondary particle size thereof is from 30 to 80 nm, and (the average secondary particle size×the content) is in a range of from 10 to 40; and tetramethylammonium ion. | 2011-09-01 |
20110212622 | SURFACE TEXTURING USING A LOW QUALITY DIELECTRIC LAYER - A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation. | 2011-09-01 |
20110212623 | Substrate treatment device - It is intended to provide a substrate treatment device capable of adjusting both of a growth speed and an etching speed in a selective epitaxial growth, avoiding particle generation from nozzles, and achieving good etching characteristics. A substrate treatment device for selectively growing an epitaxial film on a surface of a substrate by alternately supplying a raw material gas containing silicon and an etching gas to a treatment chamber, the substrate treatment device being provided with a substrate support member for supporting the substrate in the treatment chamber, a heating member provided outside the treatment chamber for heating the substrate and an atmosphere of the treatment chamber, a gas supply system provided inside the treatment chamber, and a discharge port opened on the treatment chamber, wherein the gas supply system comprises first gas supply nozzles for supplying the raw material gas and second gas supply nozzles for supplying the etching gas. | 2011-09-01 |
20110212624 | SYSTEM, METHOD AND APPARATUS FOR PLASMA ETCH HAVING INDEPENDENT CONTROL OF ION GENERATION AND DISSOCIATION OF PROCESS GAS - A method of etching a semiconductor wafer including injecting a source gas mixture into a process chamber including injecting the source gas mixture into a multiple hollow cathode cavities in a top electrode of the process chamber and generating a plasma in each one of the hollow cathode cavities. Generating the plasma in the hollow cathode cavities includes applying a first biasing signal to the hollow cathode cavities. The generated plasma or activated species is output from corresponding outlets of each of the hollow cathode cavities into a wafer processing region in the process chamber. The wafer processing region is located between the outlets of the hollow cathode cavities and a surface to be etched. An etchant gas mixture is injected into the wafer processing region. A plasma can also be supported and/or generated in the wafer processing region. The etchant gas mixture is injected through multiple injection ports in the top electrode such that the etchant gas mixture mixes with the plasma output from the outlets of the hollow cathode cavities. The etchant gas mixture is substantially prevented from flowing into the outlets of the hollow cathode cavities by the plasma flowing from the outlets of hollow cathode cavities. Mixing the etchant gas mixture and the output from the hollow cathode cavities generates a desired chemical species in the wafer processing region and the surface to be etched can be etched. A system for generating an etching species is also describer herein. | 2011-09-01 |
20110212625 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate processing apparatus which is capable of improving a manufacture yield while processing a substrate with high precision, and a method of manufacturing a semiconductor device. The substrate processing apparatus includes a substrate support part provided within a process chamber and configured to support a substrate; a substrate support moving mechanism configured to move the substrate support part; a gas feeding part configured to feed a gas into the process chamber; an exhaust part configured to exhaust the gas within the process chamber; and a plasma generating part disposed to face the substrate support part. | 2011-09-01 |
20110212626 | SUBSTRATE PROCESSING APPARATUS AND SEMICONDUCTOR DEVICE PRODUCING METHOD - Disclosed is a substrate processing apparatus, including: a processing chamber for processing a substrate; a substrate rotating mechanism for rotating the substrate; a gas supply unit for supplying gas to the substrate, at least two kinds of gases A and B being alternately supplied a plurality of times to form a desired film on the substrate; and a controller for controlling a rotation period of the substrate or a gas supply period defined as a time period between an instant when the gas A is made to flow and an instant when the gas A is made to flow next time such that the rotation period and the gas supply period are not brought into synchronization with each other at least while the alternate gas supply is carried out predetermined times. | 2011-09-01 |
20110212627 | Low Temperature Dielectric Flow Using Microwaves - Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy (“MW dielectric layers”). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow. Using microwave energy permits the dielectric layer to be formed using low temperature processing, providing several benefits to the semiconductor device along with process flow efficiency and low cost. Other embodiments are described. | 2011-09-01 |
20110212628 | SEQUENTIAL PULSE DEPOSITION - A method for growing films on substrates using sequentially pulsed precursors and reactants, system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. | 2011-09-01 |
20110212629 | LIQUID COMPOSITION CONTAINING AMINOETHER FOR DEPOSITION OF METAL-CONTAINING FILMS - A formulation, comprising: a) at least one metal-ligand complex, wherein one or more ligands are selected from the group consisting of β-diketonates, β-ketoiminates, β-ketoesterates, β-diiminates, alkyls, carbonyls, alkyl carbonyls, cyclopentadienyls, pyrrolyls, alkoxides, amidinates, imidazolyls, and mixtures thereof; and the metal is selected from Group 2 to 16 elements of the Periodic Table of the Elements; and, b) at least one aminoether selected from the group consisting of R | 2011-09-01 |
20110212630 | METHOD FOR PREPARING A SELF-SUPPORTING CRYSTALLIZED SILICON THIN FILM - The invention relates to a method for preparing a self-supporting crystallized silicon thin film having a grain size of more than 1 mm. The invention also relates to the use of said method for preparing self-supporting silicon bands and to the bands thus obtained. | 2011-09-01 |
20110212631 | FEMALE CIRCUIT BOARD AND CONNECTOR ASSEMBLY - A female circuit board for use with a male circuit board has electrically conductive projections. The female circuit board includes a flexible insulating film. The flexible insulating film includes insertion portions into which the conductive projections of the male circuit board are allowed to be inserted. Each of the insertion portions includes a plurality of slits communicating with each other at the center of each of the insertion portions. The flexible insulating film further includes electrically conduction portions for making contact with the conductive projections to come into conduction with the male circuit board. The conduction portions are disposed around the insertion portions on the surface of the female circuit board facing the male circuit board when the female circuit board is in contact with the male circuit board. The conduction portions conform in shape to the insertion portions. | 2011-09-01 |
20110212632 | HIGH DENSITY ELECTRICAL CONNECTOR AND PCB FOOTPRINT - An interconnection system that includes a daughter card and backplane electrical connectors, each mounted to a printed circuit board at a connector footprint. The backplane connector has conductive elements with transition regions that allow the mating contact portions to be positioned on a uniform pitch while contact tail portions can be shaped to improve signal integrity or to provide a more compact and/or mechanically robust footprint. The conductive elements in both connectors are configured such that the contact tails of the ground conductors align from column to column, but the planar portions of the ground conductors in one column align with a pair of signal conductors in the other column, which improves mechanical and signal integrity. Mechanical integrity may be improved by forming the connector footprints with pads for the ground conductors that span multiple columns. | 2011-09-01 |
20110212633 | CONNECTOR WITH IMPEDANCE TUNED TERMINAL ARRANGEMENT - A connector housing includes a plurality of wafers containing terminal dedicated to either ground signals or differential signals. Terminals in adjacent wafers can be arranged to provide broadside coupled differential signal pairs. Terminals dedicated for use as ground terminals can be wider than the signal terminals to provide shielding between adjacent differential signal pairs. The signal terminals of each differential signal terminal pair can a constant width from their contact portions to a location proximate their tail portions and the terminals diverge from broadside alignment and increase in their width until they end at the terminal tail portions. | 2011-09-01 |
20110212634 | AC INTERCONNECT SCHEME FOR PSU - An ATX compatible power supply unit having at least one AC power inlet and at least one AC power cable, the AC power inlet configured to support nominal contact resistances of less than 8 milliohms per contact or the AC power cable configured to support series resistances of less than 4 milliohms per linear foot of individual conductor is disclosed. | 2011-09-01 |
20110212635 | ELECTRICAL CONNECTOR HAVING MOVABLE PROTECTIVE SHIELD - An electrical connector, comprising a connector body having an opening for receiving an electrical cable, a connector element disposed at least partly within the connector body and electrically coupleable to the electrical cable, an insulating shield operably associated with the connector body and movable between a first position, in which an electrical contact portion of the connector element is exposed for direct contact, and a second position, in which the insulating shield covers the electrical contact portion to limit direct contact with the electrical contact portion, and a catch mechanism for retaining the insulating shield in the second position, the catch mechanism having an actuable portion for releasing the insulating shield for movement to the first position. | 2011-09-01 |
20110212636 | ELECTRICAL CARD CONNECTOR WITH STOP MEMBER FOR PREVENTING CARD FROM FLYING OFF DURING EJECTING - An electrical card connector includes an insulative housing, a number of contacts and a push-push mechanism. The push-push mechanism includes a slider, an elastic member for driving the slider and a locking arm fixed to the slider. The locking arm includes a hook protruding into a card receiving space for locking with the card when the card is fully inserted into the card receiving space at a card locking position. When the card is ejected under a normal speed, the locking arm can be outwardly deformed to disengage from the card at a card release position. When the card is ejected under an abnormal speed faster than the normal speed, the slider gets over the card release position where the locking arm is restricted by a stop member to prevent the hook from releasing the card. | 2011-09-01 |
20110212637 | BASE FOR AN ELECTRONIC CARD AND ASSOCIATED EXTRACTION DEVICE | 2011-09-01 |
20110212638 | ELECTRIC PLUG HAVING FUEL RETURN - The invention relates to a plug module ( | 2011-09-01 |
20110212639 | Circuit card assembly connector and interconnection system - A circuit card assembly connector system includes a circuit card assembly and an edge connector including a set of resilient, spaced, conductive contacts electrically isolated from each other and extending from a surface of and over an edge of the circuit card assembly; an interconnection system for circuit card assemblies may include at least first and second circuit card assemblies, at least one having such an edge connector for interconnecting with a set of contacts of the other circuit card assembly. | 2011-09-01 |
20110212640 | ELECTRIC, WATER VAPOR DIFFUSION RESISTANT PIN-AND-SOCKET CONNECTOR - A nonconductive plate that is plated-through with an electric pin-and-socket connector in a water vapor diffusion resistant manner as well as its use as back side or side wall of a photovoltaic module is provided. The electric pin-and-socket connector includes a push-through element and a pressing element as well as a sealing element located on the pressing element and made of a material with a low water vapor diffusion rate. By the engagement of the push-through element into a retention element on a second side of the nonconducting plate, the sealing element is pressed against the first side of the plate by the pressing element and thus seals the bore in the plate in a water vapor diffusion resistant manner. | 2011-09-01 |
20110212641 | Socket for electric component - A socket for an electric component that prevents wiping when a contact piece provided in an upper end of a contact pin is pressed against a terminal of the electric component, and that prevents solder from adhering to the contact point, by a simple configuration, is provided. This electric component socket is provided with a plurality of contact pins ( | 2011-09-01 |
20110212642 | Receiving Unit for a Circuit Board Carrier, Connection System, Electric Machine With Receiving Unit and Motor Vehicle With Such an Electric Machine - A receiving unit is provided for a circuit board carrier, wherein the receiving unit has at least one electric contact. The circuit board carrier is insertable into the receiving unit at an angle to an end position of the circuit board carrier. The receiving unit is designed in such a manner that in an inserted state of the circuit board carrier there are in essence no bending forces that act on the circuit board carrier by way of the at least one electric contact. Furthermore, a connection system and an electric machine with such a receiving unit, as well as a motor vehicle with such a corresponding electric machine, are provided. | 2011-09-01 |
20110212643 | CONNECTOR WITH INTEGRATED LATCH ASSEMBLY - A connector utilizes a latching assembly that has a structure that connects horizontal movement of an actuator to vertical movement of a latching arm. A latching member is provided that grips the exterior of the connector and has a cantilevered latching arm that extends from the member over a mating portion for connection. In its simplest form the latching member includes a continuous retaining collar that fits over the exterior of the connector and exerts a clamping force on the connector so as to retain the latching member in place. | 2011-09-01 |
20110212644 | CONNECTOR POSITION ASSURANCE LOCK - A Connector Position Assurance (CPA) lock ( | 2011-09-01 |
20110212645 | CHARGING CONNECTOR - A charging connector ( | 2011-09-01 |
20110212646 | CONNECTOR - A connector includes: a housing having a plurality of cavities; and a plurality of terminal fittings that are inserted into the cavities individually and respectively, wherein a lance is formed in each of the cavities, the lance having a lock portion to be locked in a corresponding one of the terminal fittings, wherein the cavities are disposed to be aligned in a bending direction of the lances, and wherein an escape portion is provided in the terminal fitting which is inserted into the cavity disposed to be opposed to the back surface, the escape portion being formed to dent an outer surface of the terminal fitting opposed to the back surface of the lance so that at least a part of a back face portion of the lance is allowed to enter the escape portion when the lance bends elastically toward the back face. | 2011-09-01 |
20110212647 | ELECTRICAL CONNECTION APPARATUS FOR CONDUCTIVE CONTACTS, IN PARTICULAR BLADE CONTACTS - A connector apparatus connects the flat electrical conductors of a photovoltaic panel with a plurality of insulated electrical output conductors, respectively. The terminal portions of the flat conductors are bent into electrical engagement with corresponding blade contacts mounted on the photovoltaic panel. A plurality of resilient first electrical contacts are clamped in electrical engagement with the flat conductor bent portions, respectively, and a plurality of second electrical contacts are connected with the output conductors, respectively. An electrical circuit including a plurality of diodes is connected between the first and second electrical contacts. In order to dissipate the heat generated by the diodes, the diodes are mounted on a heat conducting plate that transmits the heat toward the photovoltaic panel. A cover member formed of heat conducting material is adhesively secured to the panel to enclose the connector arrangement, thereby to also transfer the diode-generated heat to the panel. | 2011-09-01 |
20110212648 | DEVICE AND METHOD OF INSTALLING CAPACITORS ON A UTILITY COMPANYS POWER METER - The Invention relates to the field of power factor correction in general. Specifically, the Invention comprises a device for insertion between the power meter of an electrical utility supply and the load which is further comprised of an electrical capacitance that is sized by the method of the Invention to improve the electrical power factor of the system as measured at the meter. The benefits of the Invention include increased power factor, lower power consumption, lower energy costs, and ease of installation due to its novel plug-in packaging approach wherein a utility meter adapter embodiment of the present invention containing power factor correcting circuit capacitor(s) plugs between a utility meter and its meter socket. The device of the invention installs between the power meter and power meter receptacle without requiring significant effort or time for installation. | 2011-09-01 |
20110212649 | HIGH DENSITY ELECTRICAL CONNECTOR WITH VARIABLE INSERTION AND RETENTION FORCE - An interconnection system that includes a daughter card and backplane electrical connectors mounted to printed circuit boards at connector footprints. The spring rate of beam-shaped contacts in the daughter card connector increases while mating with the backplane connector so that the retention force may be greater than the insertion force. Such a change in spring rate may be achieved by positioning the beam-shaped contacts adjacent a surface of a connector housing. That surface may include a projection that aligns with the beam-shaped contact. When the connectors are unmated, the beam-shaped contact may be spaced from the projection. As the connectors begin to mate, a central portion of the beam-shaped contact may be pressed against the projection, which has the effect of shortening the beam length and increasing its stiffness. | 2011-09-01 |
20110212650 | CONNECTOR WITH OVERLAPPING GROUND CONFIGURATION - A high speed connector ( | 2011-09-01 |
20110212651 | CONNECTOR FOR ELECTRONIC DEVICE - A connector ( | 2011-09-01 |
20110212652 | ELECTRICAL PLUG CONNECTOR WITH STRAND GUIDE - The invention relates to an electrical plug connector ( | 2011-09-01 |
20110212653 | TERMINAL COMPONENT - Terminal components ( | 2011-09-01 |
20110212654 | CONNECTOR - A connector includes: a terminal fitting having a body portion; and a housing having a cavity that receives the terminal fitting, wherein the body portion has a first protrusion that protrudes from an outer surface of the body portion and an interference avoiding portion, wherein the first protrusion and the interference avoiding portion are disposed to be opposed to each other substantially in a diagonal line on a virtual projection plane, and wherein the cavity is formed with, in an inner surface thereof, a first groove into which the first protrusion is allowed to enter only when the terminal fitting has a proper insertion posture relative to the cavity and an interference portion that is formed to swell from the inner surface of the cavity to narrow a gap with the interference avoiding portion. | 2011-09-01 |
20110212655 | TERMINAL SUPPORT STRUCTURE - A terminal support structure has a housing that is of a resin molding product having a terminal inserting hole, a connecting terminal that is inserted into the terminal inserting hole and supported by the housing, and a retaining projection including a press-in groove parallel to a direction of insertion of the connecting terminal that is provided in an opening edge portion of the terminal inserting hole. A press-in portion is integrally formed in a side portion of the connecting terminal. Upper and lower end portions of the press-in portion are latched and retained in upper and lower surfaces opposite to each other in the press-in groove, respectively. | 2011-09-01 |
20110212656 | TERMINAL FITTING - A terminal fitting includes: a body portion having a space for inserting a tab of a mating terminal therein; an elastic contact piece provided to face the space, having a configuration as to be extended like a cantilever in a direction of an insertion and pull-out of the tab with respect to the space through a wall-shaped portion constituting the body portion, and having a contact portion to come in contact with the tab; and an elastic reinforcing piece provided on an opposite side to the space with the elastic contact piece interposed therebetween, having a configuration as to be extended like a cantilever in the direction of the insertion and pull-out of the tab from the wall-shaped portion constituting the body portion, and causing an extended end to correspond to a displaced region in an elastic flexure in the elastic contact piece. | 2011-09-01 |
20110212657 | PROPELLER UNIT FOR MARINE VESSEL PROPULSION DEVICE AND MARINE VESSEL PROPULSION DEVICE INCLUDING THE SAME - A propeller unit for a marine vessel propulsion device includes an inner cylinder arranged to be fixed to the propeller shaft, an outer cylinder, a first driving force transmitting member, and a second driving force transmitting member. The propeller unit for marine vessel propulsion device further includes a pair of first engaging portions, and a pair of second engaging portions provided on the outer cylinder and the second driving force transmitting member. The pair of second engaging portions are arranged such that the mutual engaging of the respective second engaging portions is disengaged when a driving force is not transmitted to the propeller shaft and are arranged such that the respective second engaging portions become mutually engaged in a driving force transmittable manner by elastic deformation of the first driving force transmitting member when a driving force that is not less than a reference driving force is transmitted to the propeller shaft. | 2011-09-01 |
20110212658 | FIRE RETARDANT FABRIC - The invention relates generally to fabrics and, more particularly, to a fire retardant fabric for covering articles to provide fire retardancy or resistance to open flame ignition sources and the use of said fabrics in open flame resistant mattresses, mattress foundations, upholstered furniture article and other articles filled with resilient cushioning materials that are rendered resistant to open flame and smoldering ignition sources by a consumer/end-user. | 2011-09-01 |
20110212659 | METHOD OF MAKING WOVEN FABRIC THAT PERFORMS LIKE A KNITTED FABRIC - A fabric with wefts that include hard yarns and elastomeric yarns in a predetermined arrangement such that at least one hard yarn is alternately arranged with at least one elastomeric yarn, the elastomeric yarns having a greater shrinkage ratio than that of the hard yarns; the hard yarns form under portions and over portions with respect to warps, said under portions being formed when said hard yarns pass along the back side of the warps and defining loop portions, and said over portions being formed when the hard yarns pass along the front side of the warps and define connection portions, wherein for each hard yarn, an average number of warps passed by the loop portion is at least 6, and wherein the elastomeric yarns form under portions and over portions with respect to said warps in a weave that is tighter than the weave of the hard yarns. | 2011-09-01 |
20110212660 | CYCLIC OLEFIN-DERIVED RESIN FIBER AND CYCLIC OLEFIN-DERIVED RESIN NON-WOVEN FABRIC - Provided is a cyclic olefin-derived resin microfiber and a cyclic olefin-derived resin non-woven fabric. A polymer solution containing a volatile solvent and a cyclic olefin-derived resin is subjected to electrostatic spinning. The volatile solvent to be used preferably contains at least one solvent selected from the group consisting of chloroform, toluene, xylene, cyclohexane and decalin. In addition, by using a cyclic olefin-derived resin with a glass transition point of at least 160° C., high heat-resistance can be imparted to a cyclic olefin-derived resin fiber. | 2011-09-01 |
20110212661 | METHOD AND APPARATUS FOR MANUFACTURING TOUCH SCREEN - Disclosed herein is a method of manufacturing a touch screen, including: supplying a PET film; supplying and printing transparent conductive polymer electrodes on both sides of the PET film; printing conductive patterns on the transparent conductive polymer electrodes; supplying an adhesive to the transparent conductive polymer electrodes to form an adhesive layer; supplying a protective film to the adhesive layer; and cutting a laminate composed of the PET film, the printed transparent conductive polymer electrodes, the conductive patterns, the adhesive layer and the protective film. The method is advantageous in that a touch screen can be manufactured by an automated process using a roll-type feed or a sol-type feeder. | 2011-09-01 |
20110212662 | LAYOUT OF LIQUID CRYSTAL DISPLAY PANELS AND SIZE OF MOTHER SUBSTRATE - A layout of LCD panels and a size of the mother substrate are disclosed, to improve the efficiency in arrangement of the LCD panels, and to maximize the substrate efficiency, the layout comprising a mother substrate; a dummy region of 15 mm or less in a periphery of the mother substrate; and six LCD panels of the 26-inch model in a matrix of 2×3 on the mother substrate excluding the dummy region with a margin corresponding to 2˜4% of a length of the LCD panel. | 2011-09-01 |