| 35th week of 2011 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20110210362 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE THEREOF - A light emitting device includes a light emitting structure including a second conduction type semiconductor layer, an active layer, and a first conduction type semiconductor layer, a second electrode layer arranged under the light emitting structure, a first electrode layer having at least portion extending to contact the first conduction type semiconductor layer passing the second conduction type semiconductor layer and the active layer, and an insulating layer arranged between the second electrode layer and the first electrode layer, between the second conduction type semiconductor layer and the first electrode layer, and between the active layer and the first electrode layer, wherein said at least one portion of the first electrode layer contacting the first conduction type semiconductor layer has a roughness. | 2011-09-01 |
| 20110210363 | METHOD FOR FORMING OHMIC ELECTRODE AND SEMICONDUCTOR LIGHT EMITTING ELEMENT - The present invention relates to a method of forming an ohmic electrode in a semiconductor light emitting element, comprising: forming a semiconductor layer having a light emitting structure on a substrate, sequentially laminating a bonding layer, a reflective layer and a protective layer on the semiconductor layer, and forming an ohmic electrode by performing a heat treatment process to form ohmic bonding between the semiconductor layer and the bonding layer and to form an oxide film on at least a portion of the protective layer; and a semiconductor light emitting element using the ohmic electrode. According to the present invention, since a reflective layer is formed of Ag, Al and an alloy thereof with excellent light reflectivity, the light availability is enhanced. Further, since contact resistance between a semiconductor layer and a bonding layer is small, it is easy to apply large current for high power. | 2011-09-01 |
| 20110210364 | SILICONE COATED LIGHT-EMITTING DIODE - A silicone protective coating for an electronic light source and a method for applying the coating over an exposed or outer surface of the electronic light source assembled as part of or mounted to a circuit board or other substrate. | 2011-09-01 |
| 20110210365 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion. | 2011-09-01 |
| 20110210366 | LIGHT EMITTING DEVICE - Provided is a light emitting device. The light emitting device includes: a plurality of lead frame units spaced apart from each other, each of the lead frame units being provided with at least one fixing space perforating a body thereof in a vertical direction; a light emitting diode chip mounted on one of the lead frame units; and a molding unit that is integrally formed on top surfaces of the lead frame units and in the fixing spaces to protect the light emitting diode chip. | 2011-09-01 |
| 20110210367 | LIGHT EMITTING DIODE PACKAGES, LIGHT EMITTING DIODE SYSTEMS AND METHODS OF MANUFACTURING THE SAME - In a method of forming an LED semiconductor device, and in an LED semiconductor device, an LED is provided on a substrate. A first encapsulant material layer is provided on the LED, and the first encapsulant material layer is firstly annealed. A luminescence conversion material layer is provided on the firstly annealed first encapsulant material layer, and the first encapsulant material layer and the luminescence conversion material layer and secondly annealed. | 2011-09-01 |
| 20110210368 | MICRO-COMPOSITE PATTERN LENS, AND METHOD FOR MANUFACTURING SAME - The present invention relates to a micro-composite pattern lens and to a method for manufacturing same. The micro-composite pattern lens of the present invention has a micro-composite pattern with one or more protrusions formed on one side of the lens having a predetermined curvature, and optical polymer nanoparticles arranged in the lens. The micro-composite pattern of the lens may form a wider angle of light emission, thus enabling an LED source, which is a point light source, to be converted into a surface light source having superior luminous intensity uniformity. The lens of the present invention is advantageous in that a single lens may serve as a light guide plate, a prism plate, and a diffusion plate, this eliminating the necessity of stacking optical plates, which might otherwise be required for conventional backlight units. According to the present invention, the angle of emission of the LED source which is approximately 90 degrees can be widened to 160 degrees or higher, and the local change in the micro-pattern and the mixture of ultrafine particles may improve the luminous intensity uniformity and the angle of emission of the light source. Also, wafer levels can be manufactured using a microfluidic channel array based on three dimensional molding techniques and the mixture of ultrafine particles. In addition, the use of single lens having a wider angle of light emission reduces the number of LEDs, thus reducing manufacturing costs and heat generated by LEDs. Further, the micro-composite pattern lens of the present invention has a double curvature structure to achieve improved luminous intensity uniformity and an improved angle of light emission as compared to a single curvature structure. | 2011-09-01 |
| 20110210369 | LIGHT-EMITTING MODULE, MANUFACTURING METHOD FOR LIGHT-EMITTING MODULE, AND LIGHT FIXTURE UNIT - In a light emitting module | 2011-09-01 |
| 20110210370 | Light emitting device - On a through-electrode ( | 2011-09-01 |
| 20110210371 | COMPOSITION FOR THERMOSETTING SILICONE RESIN - The present invention relates to a composition for a thermosetting silicone resin including: (1) a dual-end silanol type silicone oil; (2) an alkenyl-containing silicon compound; (3) an organohydrogensiloxane; (4) a condensation catalyst; and (5) a hydrosilylation catalyst, in which the (4) condensation catalyst includes a tin complex compound. | 2011-09-01 |
| 20110210372 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A high-voltage vertical power component including a lightly-doped semiconductor substrate of a first conductivity type and, on the side of an upper surface, an upper semiconductor layer of the second conductivity type which does not extend all the way to the component periphery, wherein the component periphery includes, on the lower surface side, a ring-shaped diffused region of the second conductivity type extending across from one third to half of the component thickness; and on the upper surface side, an insulated ring-shaped groove crossing the substrate to penetrate into an upper portion of ring-shaped region. | 2011-09-01 |
| 20110210373 | Semiconductor Structure with Coincident Lattice Interlayer - A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 2011-09-01 |
| 20110210374 | Tri-Gate Field-Effect Transistors Formed by Aspect Ratio Trapping - Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach | 2011-09-01 |
| 20110210375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device including a tunnel FET, includes a gate electrode, which is formed on a first semiconductor layer formed of Si | 2011-09-01 |
| 20110210376 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm | 2011-09-01 |
| 20110210377 | NITRIDE SEMICONDUCTOR DEVICE - A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer. | 2011-09-01 |
| 20110210378 | HIGH ELECTRON MOBILITY TRANSISTOR, EPITAXIAL WAFER, AND METHOD OF FABRICATING HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor includes a free-standing supporting base having a III nitride region, a first III nitride barrier layer which is provided on the first III nitride barrier layer, a III nitride channel layer which is provided on the first III nitride barrier layer and forms a first heterojunction with the first III nitride barrier layer, a gate electrode provided on the III nitride channel layer so as to exert an electric field on the first heterojunction, a source electrode on the III nitride channel layer and the first III nitride barrier, and a drain electrode on the III nitride channel layer and the first III nitride barrier. The III nitride channel layer has compressive internal strain, and the piezoelectric field of the III nitride channel layer is oriented in the direction from the supporting base towards the first III nitride barrier layer. The first heterojunction extends along a plane having a normal axis that is inclined at an inclination angle in the range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to the c-axis of the III nitride region. | 2011-09-01 |
| 20110210379 | FIN-JFET - Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate. | 2011-09-01 |
| 20110210380 | CONTACT BARS WITH REDUCED FRINGING CAPACITANCE IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches. | 2011-09-01 |
| 20110210381 | TRANSISTOR, IMAGE SENSOR WITH THE SAME, AND METHOD OF MANUFACTURING THE SAME - Provided is an image sensor including a drive transistor as a voltage buffer, which can suppress generation of secondary electrons from a channel of the drive transistor to prevent generation of image defects caused by dark current. The transistor includes a gate electrode formed on a substrate, source and drain regions formed in the substrate exposed to both sides of the gate electrode, respectively, and an electric field attenuation region formed on the drain region and partially overlapping the gate electrode. | 2011-09-01 |
| 20110210382 | DIGITAL RADIOGRAPHIC FLAT-PANEL IMAGING ARRAY WITH DUAL HEIGHT SEMICONDUCTOR AND METHOD OF MAKING SAME - Method of manufacturing imaging arrays can include providing a silicon tile having a first surface and a second, opposite surface. A buried dielectric layer is formed in the silicon tile between the first and second surfaces to define a bottom silicon layer between the first surface and the dielectric layer. A separation boundary is formed in the silicon tile between the second surface and the dielectric layer to define a top silicon layer between the dielectric layer and the separation boundary and a removable silicon layer between the separation boundary and the second surface. An oxide layer formed on the first surface of the silicon tile and the silicon tile is bonded to a glass substrate at the oxide layer. The silicon tile is separated at the separation boundary to remove the removable silicon layer, exposing the top silicon layer. Semiconductive elements are formed using the exposed top silicon layer. | 2011-09-01 |
| 20110210383 | IMAGING DEVICE - First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region and a gate electrode, so that dark current noise tends to occur. The second diffusion region functioning as a protection layer prevents crystal defects in a manufacturing process. The second diffusion region isn't formed on a center of the surface of the first diffusion region where crystal defects don't tend to occur. In the first diffusion region where the second diffusion region isn't formed, the thickness of a depletion layer increases, which improves light detection sensitivity. This improves detection sensitivity of the photodiode without increasing the dark current noise. | 2011-09-01 |
| 20110210384 | Scalable integrated MIM capacitor using gate metal - According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps. | 2011-09-01 |
| 20110210385 | Non-volatile Semiconductor Device, Programmable Memory, Capacitor and Metal Oxide Semiconductor - A non-volatile semiconductor device, a programmable memory device, a capacitor and a metal oxide semiconductor are disclosed, wherein the non-volatile semiconductor device includes a gate dielectric layer, a floating gate, a coupling gate, a source and a drain. The gate dielectric layer is formed on a semiconductor substrate. The floating gate is formed on the gate dielectric layer. The source and the drain are formed in the semiconductor substrate and are disposed at opposing sides of the floating gate. The coupling gate consists essentially of a capacitor dielectric layer and a contact plug, where the capacitor dielectric layer is formed on the floating gate, and the contact plug is formed on the capacitor dielectric layer. | 2011-09-01 |
| 20110210386 | DEVICES WITH NANOCRYSTALS AND METHODS OF FORMATION - Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures can be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures include at least one of nanocrystals, nanowires, and nanotubes. According to various nanocrystal embodiments, the nanocrystals are positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein. | 2011-09-01 |
| 20110210387 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 2011-09-01 |
| 20110210388 | Integrated native device without a halo implanted channel region and method for its fabrication - According to one embodiment, a semiconductor structure including an integrated native device without a halo implanted channel region comprises an arrangement of semiconductor devices formed over a common substrate, the arrangement includes native devices disposed substantially perpendicular to non-native devices, wherein each of the native and non-native devices includes a respective channel region. The arrangement is configured to prevent formation of halo implants in the native device channel regions during halo implantation of the non-native device channel regions. In one embodiment, the disclosed native devices comprise native transistors capable of avoiding threshold voltage roll-up for channel lengths less than approximately 0.5 um. | 2011-09-01 |
| 20110210389 | Transistor Comprising a Buried High-K Metal Gate Electrode Structure - A buried gate electrode structures may be formed in the active regions of sophisticated transistors by providing a recess in the active region and incorporating appropriate gate materials, such as a high-k dielectric material and a metal-containing electrode material. Due to the recessed configuration, the channel length and thus the channel controllability may be increased, without increasing the overall lateral dimensions of the transistor structure. | 2011-09-01 |
| 20110210390 | MOS DEVICE WITH VARYING TRENCH DEPTH - A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width. | 2011-09-01 |
| 20110210391 | SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor device includes a drift region including a semiconductor of a first conductivity type; a first semiconductor region of a second conductivity type provided adjacently to the drift region; a main electrode, a plurality of first gate electrodes and a second gate electrode. The main electrode is provided adjacently to the first semiconductor region and electrically connected to the first semiconductor region, the first semiconductor region being disposed between the drift region and the main electrode. The first gate electrodes are provided along a boundary between the drift region and the first semiconductor region. The first gate electrode has a trench structure and faces the drift region and the first semiconductor region via a first gate insulating film. The second gate electrode of the trench structure is provided along the boundary between the drift region and the first semiconductor region. The second gate electrode is disposed between the two first gate electrodes and faces the drift region and the first semiconductor region via a second gate insulating film. A first portion facing the first semiconductor region in the second gate electrode is shorter than a second portion facing the first semiconductor region in the first gate electrode in a direction from the boundary to the main electrode. The main electrode is extended to a position close to the second gate electrode in the trench provided in the direction from the main electrode to the second gate electrode between the two first gate electrodes. The main electrode is in contact with the first semiconductor region exposed to an inner wall surface of the trench between an end of the first gate electrode on the main electrode side and an end of the second gate electrode on the main electrode side. | 2011-09-01 |
| 20110210392 | POWER SEMICONDUCTOR DEVICE - A structure of a power semiconductor device, in which a P-well region having a large area and a gate electrode are opposed to each other through a field oxide film having a larger thickness than that of a gate insulating film such that the P-well region having a large area and the gate electrode are not opposed to each other through the gate insulating film, or the gate electrode is not provided above the gate insulating film that includes the P-well region having a large area therebelow. | 2011-09-01 |
| 20110210393 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 2011-09-01 |
| 20110210394 | Semiconductor Device - A method for fabricating a semiconductor device comprises: performing a thermal process to expanding a local doped region formed between gate patterns on a semiconductor substrate; and etching a central region of an expanded local doped region so that the expanded local doped region remains at the total area of sidewalls of floating bodies isolated from each other. | 2011-09-01 |
| 20110210395 | TRANSISTORS WITH IMMERSED CONTACTS - Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. | 2011-09-01 |
| 20110210396 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer. | 2011-09-01 |
| 20110210397 | One-time programmable semiconductor device - According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar. | 2011-09-01 |
| 20110210398 | TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND ADAPTED CHANNEL SEMICONDUCTOR MATERIALS - In sophisticated semiconductor devices, a replacement gate approach may be applied, in which a channel semiconductor material may be provided through the gate opening prior to forming the gate dielectric material and the electrode metal. In this manner, specific channel materials may be provided in a late manufacturing stage for different transistor types, thereby providing superior transistor performance and superior flexibility in adjusting the electronic characteristics of the transistors. | 2011-09-01 |
| 20110210399 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate (e.g., a P-type semiconductor substrate), and an isolation region formed in the substrate to isolate an element formation region from the other region. The semiconductor device also includes a gate electrode formed over the element formation region. The gate electrode extends over each of first and second regions of the isolation region opposing each other with the element formation region interposed therebetween. The semiconductor device further includes a pair of diffusion regions (e.g., N-type diffusion regions) formed in the element formation region so as to be spaced apart from each other in a channel length direction with reference to the gate electrode. At least a portion of each of upper surfaces of the first and second regions is depressed to a depth of not less than 5% of a channel width to be located under an upper surface of the element formation region. In each of resultant depressions also, a portion of the gate electrode is present. | 2011-09-01 |
| 20110210400 | Integrated Circuitry - Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs. | 2011-09-01 |
| 20110210401 | MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE - A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate ( | 2011-09-01 |
| 20110210402 | METAL-GATE HIGH-K REFERENCE STRUCTURE - Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V. Also disclosed are method embodiments for forming the integrated circuit structure. | 2011-09-01 |
| 20110210403 | NOVEL STRUCTURES AND METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES - The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance. | 2011-09-01 |
| 20110210404 | Epitaxy Profile Engineering for FinFETs - A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin. | 2011-09-01 |
| 20110210405 | METAL NITRIDE FILM, SEMICONDUCTOR DEVICE USING THE METAL NITRIDE FILM, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a metal nitride film that realizes an intended effective work function (for example, a high effective work function) and has EOT exhibiting no change or a reduced change, a semiconductor device using the metal nitride film, and a manufacturing method of the semiconductor device. The metal nitride film according to an embodiment of the present invention contains Ti, Al and N, wherein the metal nitride film has such molar fractions of Ti, Al and N as (N/(Ti+Al+N)) of 0.53 or more, (Ti/(Ti+Al+N)) of 0.32 or less, and (Al/(Ti+Al+N)) of 0.15 or less. | 2011-09-01 |
| 20110210406 | STRUCTURES OF AND METHODS OF FABRICATING SPLIT GATE MIS DEVICES - A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent. | 2011-09-01 |
| 20110210407 | DOUBLE-FACED ADHESIVE FILM AND ELECTRONIC COMPONENT MODULE USING SAME - A double-faced adhesive film including: a supporting film; a first adhesive layer laminated on one surface of the supporting film; and a second adhesive layer laminated on the other surface of the supporting film, wherein the glass transition temperatures, after curing, of the first adhesive layer and the second adhesive layer are each 100° C. or lower, and the first adhesive layer and the second adhesive layer are the layers capable of being formed by a method including the steps of directly applying a varnish to the supporting film and drying the applied varnish. | 2011-09-01 |
| 20110210408 | SENSOR DEVICE, METHOD OF MANUFACTURING SENSOR DEVICE, MOTION SENSOR, AND METHOD OF MANUFACTURING MOTION SENSOR - A sensor device includes: a silicon substrate; a first electrode provided at an active surface side of the silicon substrate; an external connection terminal provided at the active surface side so as to be electrically connected to the first electrode; a stress relief layer provided between the silicon substrate and the external connection terminal; and a vibrating gyro element as a sensor element including a extraction electrode. The vibrating gyro element is held to the silicon substrate by connection between the extraction electrode and the external connection terminal. | 2011-09-01 |
| 20110210409 | Surface Mount Silicon Condenser Microphone Package - The present invention relates to a surface mount package for a silicon condenser microphone. The inventive package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate which performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the die and the package, and providing an exterior surface for making electrical connections between package and a user's printed circuit board. In some embodiments, the acoustic port is located in the substrate directly under the silicon condenser die which decreases the thickness of the inventive package. | 2011-09-01 |
| 20110210410 | Magnetic shielding in magnetic multilayer structures - Techniques and device designs associated with devices having magnetically shielded magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves that are configured to operate based on spin-transfer torque switching. | 2011-09-01 |
| 20110210411 | ULTRA THIN FLIP-CHIP BACKSIDE DEVICE SENSOR PACKAGE - An integrated circuit that senses a phenomenon, such as a magnetic field, may be mounted upside down on a carrier substrate so that the electrical connections to the integrated sensor circuit may be made on the side facing the carrier. This eliminates the need for wirebonds on the side of the sensor integrated circuit that faces the phenomenon being sensed, thereby substantially eliminating any uneven topography on that side. The sensor integrated circuit is able to sense the phenomenon by sensing it through the body of the sensor integrated circuit. The body of the sensor integrated circuit may have a thickness within a vicinity of fifty microns. | 2011-09-01 |
| 20110210412 | MEMORY ELEMENT, MEMORY DEVICE, AND SEMICONDUCTOR DEVICE - On object of the invention is to provide a nonvolatile memory device, in which data can be added to the memory device after a manufacturing process and forgery and the like by rewriting can be prevented, and a semiconductor device including the memory device. Another object of the invention is to provide a highly-reliable, inexpensive, and nonvolatile memory device and a semiconductor device including the memory device. A memory element includes a first conductive layer, a second conductive layer, a first insulating layer with a thickness of 0.1 nm or more and 4 nm or less being in contact with the first conductive layer, and an organic compound layer interposed between the first conductive layer, the first insulating layer, and the second conductive layer. | 2011-09-01 |
| 20110210413 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof. | 2011-09-01 |
| 20110210414 | Infrared sensor - An infrared sensor according to the present invention includes a semiconductor substrate, a thin-film pyroelectric element made of lead titanate zirconate and disposed on the semiconductor substrate, a coating film coating the pyroelectric element and having a topmost surface that forms a light receiving surface for infrared rays, and a cavity formed to a shape dug in from a top surface of the semiconductor substrate at a portion opposite to the pyroelectric element and thermally isolates the pyroelectric element from the semiconductor substrate. | 2011-09-01 |
| 20110210415 | FREESTANDING CARBON NANOTUBE NETWORKS BASED TEMPERATURE SENSOR - The present invention introduces a small-size temperature sensor, which exploits a random or oriented network of un-functionalized, single or multi-walled, carbon nanotubes to monitor a wide range of temperatures. Such network is manufactured in the form of freestanding thin film with an electric conductance proven to be a monotonic function of the temperature, above 4.2 K. Said carbon nanotube film is wire-connected to a high precision source-measurement unit, which measures its electric conductance by a standard two or four-probe technique. Said temperature sensor has a low power consumption, an excellent stability and durability, a high sensitivity and a fast response; its manufacturing method is simple and robust and yields low-cost devices. Said temperature sensor, freely scalable in dimension, is suitable for local accurate measurements of rapidly and widely changing temperatures, while introducing a negligible disturb to the measurement environment. | 2011-09-01 |
| 20110210416 | POLARIZATION ALIGNED AND POLARIZATION GRADED THERMOELECTRIC MATERIALS AND METHOD OF FORMING THEREOF - Exemplary embodiments of the invention include a thermoelectric material having an aligned polarization field along a central axis of the material. Along the axis are a first atomic plane and a second atomic plane of substantially similar area. The planes define a first volume and form a single anisotropic crystal. The first volume has a first outer surface and a second outer surface opposite the first outer surface, with the outer surfaces defining the central axis passing through a bulk. The bulk polarization field is formed from a first electrical sheet charge and a second opposing electrical sheet charge, one on each atomic plane. The opposing sheet charges define a bulk polarization field aligned with the central axis, and the bulk polarization field causes asymmetric thermal and electrical conductivity through the first volume along the central axis. | 2011-09-01 |
| 20110210417 | SEMICONDUCTOR DEVICE ISOLATION STRUCTURES - Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth. | 2011-09-01 |
| 20110210418 | Electrostatic Discharge Devices - Electrostatic discharge devices and methods of forming thereof are disclosed. In one embodiment, a semiconductor device includes an electrostatic discharge (ESD) device region disposed within a semiconductor body. A first ESD device is disposed in a first region of the ESD device region, and a second ESD device disposed in a second region of the ESD device region. The second region is separated from the first region by a first trench. | 2011-09-01 |
| 20110210419 | MULTI-CHIP PACKAGE WITH IMPROVED SIGNAL TRANSMISSION - Provided is an MCP including a plurality chips stacked therein. Each of the chips includes a plurality of inductor pads configured to transmit power or signals, and at both sides of a reference inductor pad, a first and a second inductor pads are formed to generate magnetic fluxes in different directions from each other. | 2011-09-01 |
| 20110210420 | Semiconductor Device Having IPD Structure with Smooth Conductive Layer and Bottom-Side Conductive Layer - A semiconductor device includes an interface layer, a smooth conductive layer disposed over the interface layer, and a first insulating layer disposed over a first surface of the smooth conductive layer. A first conductive layer is disposed over the first insulating layer and the interface layer, and the first conductive layer contacts the first insulating layer. A second insulating layer is disposed over the second insulating layer and the first conductive layer, and a second conductive layer is disposed below the first conductive layer and contacts a second surface of the smooth conductive layer. The second surface of the smooth conductive layer is opposite the first surface of the smooth conductive layer. A third insulating layer is disposed over the first insulating layer and the first surface of the smooth conductive layer, and a fourth insulating layer is disposed below the second conductive layer and the interface layer. | 2011-09-01 |
| 20110210421 | TRENCH-TYPE CAPACITOR, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR MODULE HAVING THE SEMICONDUCTOR DEVICE - Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided. | 2011-09-01 |
| 20110210422 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part. | 2011-09-01 |
| 20110210423 | INTEGRATED CIRCUIT DEVICES HAVING A STRONTIUM RUTHENIUM OXIDE INTERFACE - Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source. | 2011-09-01 |
| 20110210424 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Ferroelectric capacitors ( | 2011-09-01 |
| 20110210425 | FORMATION OF GROUP III-V MATERIAL LAYERS ON PATTERNED SUBSTRATES - Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described. | 2011-09-01 |
| 20110210426 | SEMICONDUCTOR DEVICE PROVIDING A FIRST ELECTRICAL CONDUCTOR AND A SECOND ELECTRICAL CONDUCTOR IN ONE THROUGH HOLE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device | 2011-09-01 |
| 20110210427 | STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors. | 2011-09-01 |
| 20110210428 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT, SEMICONDUCTOR COMPONENT AND INTERMEDIATE PRODUCT IN THE PRODUCTION THEREOF - Method for producing semiconductor components with a contact structure having a high aspect ratio comprising the following steps: providing an essentially plane semiconductor substrate having a first side and a second side, applying a mask onto at least a first partial area on at least one of the sides of the semiconductor substrate and applying a contact structure onto at least a second partial area, which is different from first partial area, on at least one of the sides of semiconductor substrate. | 2011-09-01 |
| 20110210429 | Semiconductor Substrate, Package and Device and Manufacturing Methods Thereof - A semiconductor substrate including a carrier, a first conductive layer and a second conductive layer is disclosed. The carrier has a first surface, a second surface, and a concave portion used for receiving a semiconductor element. The first conductive layer is embedded in the first surface and forms a plurality of electric-isolated package traces. The second conductive layer is embedded in the second surface and electrically connected to the first conductive layer. The semiconductor substrate can be applied to a semiconductor package for carrying a semiconductor chip, and combined with a filling structure for fixing the chip' Furthermore, a plurality of the semiconductor substrates can be stacked and connected via adhesive layers, so as to form a semiconductor device with a complicated structure. | 2011-09-01 |
| 20110210430 | DEVICE WITH GROUND PLANE FOR HIGH FREQUENCY SIGNAL TRANSMISSION AND METHOD THEREFOR - A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz. | 2011-09-01 |
| 20110210431 | MICROWAVE CIRCUIT PACKAGE - A microwave circuit package having a ball grid array, BGA, soldered on to a planar major surface of a metal housing of the package for the electrical connection of the ports of the microwave circuit through RF signal paths to an adjacent electrical device. Each of the RF signal paths comprises a pin electrically connected to a respective port of the microwave circuit package, projecting normally through an opening in the said major surface from which it is electrically insulated, and soldered to a ball of the BGA; the pin and the surrounding balls of the BGA, which are soldered to the metal housing, constituting a coaxial RF signal path. | 2011-09-01 |
| 20110210432 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a lead group including a plurality of leads; a plurality of semiconductor memory chips stacked in a step shape on the lead group; and a resin mold section that seals the semiconductor memory chips. One end of a third lead and the other end of a second lead is connected by a metal wire for relay crossing over a first lead section included in the lead group. The metal wire for relay is provided in a space between the semiconductor memory chips stacked in the step shape and the lead group. | 2011-09-01 |
| 20110210433 | SEMICONDUCTOR CHIP AND FILM AND TAB PACKAGE COMPRISING THE CHIP AND FILM - A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip. The connection surface includes a first edge and a second edge that are substantially parallel to each other and are opposite each other on a respective first side and second side of the chip, and a third edge and fourth edge that are substantially perpendicular to the first and second edges, and are opposite each other on a respective third side and fourth side of the chip. A plurality of input pads of the set of input pads are adjacent the first edge, and are arranged in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads of the set of output pads are adjacent the second edge, and are arranged in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads of the set of output pads are located between the first row and the second row. The plurality of second output pads include at least first and second outermost pads located a certain distance from the respective third edge and fourth edge, and at least first and second inner pads located a greater distance from the respective third edge and fourth edge than the first and second outermost pads. | 2011-09-01 |
| 20110210434 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's. | 2011-09-01 |
| 20110210435 | MEMS DEVICES - A method of manufacturing a MEMS device comprises forming a MEMS device element | 2011-09-01 |
| 20110210436 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier. | 2011-09-01 |
| 20110210437 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector. | 2011-09-01 |
| 20110210438 | Thermal Vias In An Integrated Circuit Package With An Embedded Die - In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts. | 2011-09-01 |
| 20110210439 | Semiconductor Package and Manufacturing Method Thereof - A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package. | 2011-09-01 |
| 20110210440 | STACKABLE ELECTRONIC PACKAGE AND METHOD OF FABRICATING SAME - An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween. | 2011-09-01 |
| 20110210441 | CHIP PACKAGE - A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers. | 2011-09-01 |
| 20110210442 | Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof - A semiconductor package, a method for manufacturing the semiconductor package, a trace substrate and a method for manufacturing the trace substrate are provided. The semiconductor package includes a trace substrate, a chip and a plurality of wires. The trace substrate includes a plurality of trace, a plurality of conductive studs, a plurality of traces pads and a trace modling compound. The conductive studs are formed on the lower surfaces of the traces. The trace modling compound encapsulates the conductive studs and the trace, and exposes the lower surfaces of the conductive studs and the upper surfaces of the traces. The chip is disposed on the trace substrate, and the wires electrically connect the chip and the trace pads. The trace pads are not overlapping to the conductive studs. | 2011-09-01 |
| 20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME - An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 2011-09-01 |
| 20110210444 | 3D Semiconductor Package Using An Interposer - A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die. | 2011-09-01 |
| 20110210445 | SEMICONDUCTOR DEVICE HAVING VIA CONNECTING BETWEEN INTERCONNECTS - A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via. | 2011-09-01 |
| 20110210446 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 2011-09-01 |
| 20110210447 | CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER - In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer. | 2011-09-01 |
| 20110210448 | Interconnect Structures Incorporating Air-Gap Spacers - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 2011-09-01 |
| 20110210449 | INTERCONNECT STRUCTURES INCORPORATING AIR-GAP SPACERS - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 2011-09-01 |
| 20110210450 | SEMICONDUCTOR DEVICE WITH HOLLOW STRUCTURE - A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed. | 2011-09-01 |
| 20110210451 | METHODS OF FORMING A METAL PATTERN AND SEMICONDUCTOR DEVICE STRUCTURE - A method of forming a metal pattern on a dielectric material that comprises forming at least one trench in a photosensitive, insulative material is disclosed. The at least one trench may be positioned over at least one bond pad. A metal is formed over the photosensitive, insulative material and into the at least one trench and a photoresist material is formed over the metal. A portion of the photoresist material may be removed to expose elevated areas of the metal such that a remaining portion of the photoresist material does not extend beyond sidewalls of the at least one trench and onto the elevated areas of the metal. The metal may be exposed laterally beyond the remaining portion of the photoresist material. | 2011-09-01 |
| 20110210452 | THROUGH-SUBSTRATE VIA AND REDISTRIBUTION LAYER WITH METAL PASTE - The invention relates to a semiconductor device for use in a stacked configuration of the semiconductor device and a further semiconductor device. The semiconductor device comprises: a substrate ( | 2011-09-01 |
| 20110210453 | METHOD FOR DESIGNING ELECTRONIC SYSTEM - When an electronic system is designed, then if an integrated circuit chip (LSI), a package (PKG), and a printed circuit board (PCB) are designed separately and in parallel, it will be found near the end of the design process that a satisfactory electrical characteristic is not achieved. Therefore, a design procedure of each part (e.g., an LSI, a PKG, a PCB, etc.) is decided, and allocation of resources to a part which is designed with a higher priority is decided, and thereafter, the other parts start to be designed. Therefore, a basic interconnect distribution for a circuit board is calculated based on a prediction function for predicting an interconnect distribution for the circuit board using design information of the circuit board as input data, and is output. | 2011-09-01 |
| 20110210454 | Phase Separated Curable Compositions - A curable composition, suitable for underfill encapsulant, has two distinct phase domains after cure, a continuous phase and a discontinuous phase, in which one phase has a modulus value of 2 GPa or greater, and the second phase has a modulus value at least 1 Gpa less than the first phase, characterized in that the phases are generated in situ as the composition cures. | 2011-09-01 |
| 20110210455 | DIE BOND FILM, DICING DIE BOND FILM, AND SEMICONDUCTOR DEVICE - The present invention provides a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element and that enables loading of the other semiconductor element and improvement in the manufacturing yield of a semiconductor device by preventing deformation and cutting of the bonding wire, and a dicing die bond film. The die bond film of the present invention is a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element, in which at least a first adhesive layer that enables a portion of the bonding wire to pass through inside thereof by burying the portion upon press bonding and a second adhesive layer that prevents the other semiconductor element from contacting with the bonding wire are laminated. | 2011-09-01 |
| 20110210456 | COOLING TOWER AND METHOD OF CONSTRUCTING SAME - A cooling tower comprising an enclosure, a body of fill material supported inside the enclosure, a liquid distribution system supported above the fill material having a liquid distribution header, and a fan assembly mounted directly to the header for drawing air upward through the fill material, and a drainage collection system located below the fill material. The liquid distribution system includes a liquid distribution header comprising at least one feeder conduit encased in a monolithic casting of concrete. The liquid distribution system distributes a liquid over the fill material in such a way that the liquid gravitates downward through the fill material. The header traverses the enclosure and is supported by the enclosure. The fan assembly draws air upwards through the fill material. The drainage collection system collects the liquid that gravitates through the fill material. | 2011-09-01 |
| 20110210457 | CONTACTOR - [Technical Problem] A contactor is provided which is capable of making fluids of two phases contact each other under a good dispersion state and which can be easily multi-staged. | 2011-09-01 |
| 20110210458 | Thin Film Capillary Vaporization: Device and Methods - The present invention relates to an apparatus and method for the generation of directed vapor from a liquid source. Vaporization takes place within a device capable of confining boiling to a geometrically small volume, and expelling it as heated vapor via capillary vaporization. The foregoing is accomplished through the use of a lightweight, compact and portable personal vaporization device that generates heated vapor by the flash boiling of small volumes of aqueous liquid in a safe and energy-efficient manner. Further, the production of vapor absent microbes in aqueous systems is accomplished through the combination of microporous componentry and flash vaporization. The apparatus and methods are directed toward personal humidification for comfort and therapeutic purposes in the case of aqueous liquids, but may also be used with other, non-aqueous liquids. | 2011-09-01 |
| 20110210459 | SYSTEM FOR FORMING AND MODIFYING LENSES AND LENSES FORMED THEREBY - A lens for placement in a human eye, such as intraocular lens, has at least some of its optical properties formed with a laser. The laser forms modified loci in the lens when the modified loci have a different refractive index than the refractive index of the material before modification. Different patterns of modified loci can provide selected dioptic power, toric adjustment, and/or aspheric adjustment provided. Preferably both the anterior and posterior surfaces of the lens are planar for ease of placement in the human eye. | 2011-09-01 |
| 20110210460 | PROCESS FOR PRODUCING PELLETS FOR PHARMACEUTICAL COMPOSITIONS - Water is used to control particle size in a process comprising mixing water with a composition comprising a rheology modifying agent and possibly sugar and cellulose to produce a paste. The paste is extruded to form particles which are then spheronised and dried. One advantage of using water to control particle size is that the number of particles having a diameter within a required range, e.g. between from about 800 to about 1500 μm, may be increased. | 2011-09-01 |
| 20110210461 | INJECTION MOLDING DEVICE AND INJECTION MOLDING METHOD - An injection molding device is provided with a mold, an injection unit equipped with an injection screw that is displaceably configured such that a molten resin is filled into a cavity by forward movement to perform plural injection operations including at least a filling operation and a pressure keeping operation by displacing the injection screw, a position sensor for detecting the position of the injection screw, a temperature sensor capable of measuring the temperature of the vicinity of the cavity of the mold, a temperature adjustment unit capable of adjusting the temperature of the mold by heating or cooling the mold, a control unit for controlling the displacement of the injection screw and the temperature of the mold and determining plural switching timings of the injection operations on the basis of the position of the screw, and a display unit for displaying an image. The control unit creates a temperature waveform of the vicinity of the cavity based on an input from the temperature sensor and displays a first correlation diagram showing the correlation between the temperature waveform and a predetermined variation corresponding to the change of the temperature waveform and showing at least part of the determined plural switching timings of the injection operations on the display unit. | 2011-09-01 |
