35th week of 2008 patent applcation highlights part 52 |
Patent application number | Title | Published |
20080206920 | PCRAM device with switching glass layer - A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. | 2008-08-28 |
20080206921 | METHODS OF FORMING PHASE CHANGEABLE LAYERS INCLUDING PROTRUDING PORTIONS IN ELECTRODES THEREOF - A method of forming a structure in a phase changeable memory cell can include forming a bottom electrode having an interlayer dielectric layer thereon, the bottom electrode having a recess therein that extends beyond a boundary between the bottom electrode and the interlayer dielectric. A phase changeable layer can be formed in the recess including a protruding potion of the phase changeable layer that protrudes into the bottom electrode beyond the boundary. | 2008-08-28 |
20080206922 | Methods for Fabricating Multi-Terminal Phase Change Devices - Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device. | 2008-08-28 |
20080206923 | Oxide semiconductor target, method of forming the same, method of forming oxide semiconductor layer using the same and method of manufacturing semiconductor device using the same - Provided are a method of forming an oxide semiconductor layer and a method of manufacturing a semiconductor device using the method of forming an oxide semiconductor layer. The method may include mounting an oxide semiconductor target in a chamber; loading a substrate into the chamber; vacuuming the chamber; applying a direct current power to the oxide semiconductor target while injecting oxygen and a sputtering gas into the chamber; and forming an oxide semiconductor layer on a surface of the substrate by applying plasma of the sputtering gas onto the oxide semiconductor target. Here, the oxide semiconductor target may have a resistance of 1 kΩ or less. The oxide semiconductor target may have a composition of x(first oxide).y(second oxide).z(third oxide) where x, y and z are molar ratios. Each of the first through third oxides may be one of Ga | 2008-08-28 |
20080206924 | METHOD FOR FABTRICATING SEMICONDUCTOR DEVICE - According to the first aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove in the periphery of a region on the silicon carbide film in which crystal defects are aggregated. | 2008-08-28 |
20080206925 | Methods and apparatus to improve frit-sealed glass package - A hermetically sealed package includes: a first plate including inside and outside surfaces; a second plate including inside and outside surfaces; frit material disposed on the inside surface of the second plate; and at least one dielectric layer disposed directly or indirectly on at least one of: (i) the inside surface of the first plate at least opposite to the frit material, and (ii) the inside surface of the second plate at least directly or indirectly on the frit material, wherein the frit material forms a hermetic seal against the dielectric layer in response to heating. | 2008-08-28 |
20080206926 | SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD - A transition layer | 2008-08-28 |
20080206927 | ELECTRONIC COMPONENT STRUCTURE AND METHOD OF MAKING - An external component, typically a surface mount passive, is attached to a semiconductor die. In some embodiments the passive is placed directly over exposed pads on the semiconductor die and attached using conductive tape or conductive epoxy. In some embodiments the passive is attached to the semiconductor die using non-conductive adhesive and wire bonded to bond pads on the semiconductor die and/or to pads on a substrate to which the semiconductor die is attached. | 2008-08-28 |
20080206928 | SOLDERING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING SOLDERING METHOD - A soldering method of soldering first and second members includes shooting a laser light to at least one part of an outer peripheral portion surrounding a soldering-target region of the first member thereby to form an oxide film, and bonding the second member with the soldering-target region through a solder. According to the method, the solder resist is never exfoliated even after cleaning with chemicals for removing flux residues contained in solder. | 2008-08-28 |
20080206929 | PRINTING DEVICE, PRODUCTION UNIT, AND PRODUCTION METHOD OF ELECTRONIC PARTS - A printing device, a production unit and a production method of electronic parts suitable for production of precise electronic parts are provided. A squeegee is attached to a rotating machine, and is autorotated and self-driven, and moreover, a printing pressure is generated in the squeegee, and resin is strongly filled, thereby achieving a print having a precision-shape. Further, with a perforated plate as a boundary, upper and lower chambers are provided so as to control a pressure, thereby performing cutting and dispensing of the resin and achieving a print having a precision-shape. This method is applied to the packaging of electronic parts. A printing device E | 2008-08-28 |
20080206930 | SYSTEMS AND METHODS FOR COMPRESSING AN ENCAPSULANT ADJACENT A SEMICONDUCTOR WORKPIECE - Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece are disclosed. A method in accordance with one aspect includes placing a semiconductor workpiece and an encapsulant in a mold cavity and driving some of the encapsulant from the mold cavity to an overflow chamber. The method can further include applying pressure to the encapsulant in the mold cavity via pressure applied to the encapsulant in the overflow chamber. | 2008-08-28 |
20080206931 | NONVOLATILE MEMORY ELEMENT AND PRODUCTION METHOD THEREOF AND STORAGE MEMORY ARRANGEMENT - A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form. | 2008-08-28 |
20080206932 | DATA LINE LAYOUT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n2008-08-28 | |
20080206933 | SEMICONDUCTOR FIN INTEGRATION USING A SACRIFICIAL FIN - There is a method for forming a semiconductor device. Portions of a sacrificial layer are removed to expose a first seed layer region. The first seed layer region corresponds to a first semiconductor region, and a remaining portion of the sacrificial layer corresponds to a second semiconductor region. An epitaxial semiconductor material is deposited over the first seed layer region. A capping layer is formed to overlie the epitaxial semiconductor material and the remaining portion of the sacrificial layer. Portions of the capping layer are removed to form a capping structure that overlies a part of the remaining portion of the sacrificial layer. Portions of the sacrificial layer not covered by the capping structure are removed to form a sacrificial structure having sidewalls. Fin structures are formed adjoining the sidewalls by depositing a semiconductor material along the sidewalls. Portions of the capping structure are removed to expose portions of sacrificial layer between adjacent fin structures. Portions of the sacrificial material between the adjacent fin structures are removed. | 2008-08-28 |
20080206934 | FORMING SEMICONDUCTOR FINS USING A SACRIFICIAL FIN - A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls. | 2008-08-28 |
20080206935 | METHOD FOR FABRICATING THIN FILM TRANSISTOR USING LOCAL OXIDATION AND TRANSPARENT THIN FILM TRANSISTOR - Disclosed is a method for fabricating a thin film transistor. Specifically, the method uses local oxidation wherein a portion of a transparent metal oxide layer is locally oxidized to be converted into a semiconductor layer so that the oxidized portion of the transparent metal oxide layer can be used as a channel region and the unoxidized portions of the transparent metal oxide layer can be used as source and drain electrodes. | 2008-08-28 |
20080206936 | Method of Forming Conducting Nanowires - A method of preparing an array of conducting or semi-conducting nanowires may include forming a vicinal surface of stepped atomic terraces on a substrate, and depositing a fractional layer of dopant material to form nanostripes having a width less than the width of the atomic terraces. Diffusion of the atoms of the dopant nanostripes into the substrate may form the nanowires. | 2008-08-28 |
20080206937 | WRAP-AROUND GATE FIELD EFFECT TRANSISTOR - A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces. | 2008-08-28 |
20080206938 | LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR DISPLAY AND METHOD OF FABRICATING THE SAME - A display comprises a substrate, a polysilicon layer which is crystallized by a solid phase crystallization (SPC) method, a gate dielectric layer made of silicon oxy-nitride (SiON) and formed on the polysilicon layer, and a gate electrode formed on the gate dielectric layer (i.e. SiON). | 2008-08-28 |
20080206939 | SEMICONDUCTOR DEVICE WITH INTEGRATED RESISTIVE ELEMENT AND METHOD OF MAKING - A resistive device ( | 2008-08-28 |
20080206940 | FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS - A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed. | 2008-08-28 |
20080206941 | Method for manufacturing sic semiconductor device - A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer. | 2008-08-28 |
20080206942 | METHOD FOR FABRICATING STRAINED-SILICON METAL-OXIDE SEMICONDUCTOR TRANSISTORS - A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants. | 2008-08-28 |
20080206943 | METHOD OF FORMING STRAINED CMOS TRANSISTOR - A method of fabricating CMOS transistor is disclosed. Initially, a semiconductor substrate having at least a first active area and a second active area is provided. A high-strained thin film is formed on the semiconductor substrate, the first active area, and the second active area. Thereafter, a mask is formed to cover a part of the high-strained thin film, which is disposed on the first active area. An implantation is performed to implant dopants into the part of the high-strained thin film on the second active area and to modify the stress status thereof. After that, the mask is removed and a rapid thermal annealing process is performed. Then, the high-strained thin film is removed and the method of the present invention is accomplished. | 2008-08-28 |
20080206944 | Method for fabricating trench DMOS transistors and schottky elements - A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors. In addition to the trench DMOS transistors, a Schottky contact is simultaneously formed at a junction between a conductive layer and a doped body region in the trench DMOS transistors without additional photolithography process. | 2008-08-28 |
20080206945 | PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor. | 2008-08-28 |
20080206946 | Memory and method of fabricating the same - A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode. | 2008-08-28 |
20080206947 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall. | 2008-08-28 |
20080206948 | Semiconductor device and method of fabricating the same - An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region. | 2008-08-28 |
20080206949 | APPARATUS FOR FORMING CONDUCTOR, METHOD FOR FORMING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device. | 2008-08-28 |
20080206950 | Methods of forming a plurality of capacitors - A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors. | 2008-08-28 |
20080206951 | HIGH PERFORMANCE FIELD EFFECT TRANSISTORS ON SOI SUBSTRATE WITH STRESS-INDUCING MATERIAL AS BURIED INSULATOR AND METHODS - The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer. | 2008-08-28 |
20080206952 | Silicon Substrate Processing Method - In a thin film forming step S | 2008-08-28 |
20080206953 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method including: (a) forming a protection film on the semiconductor substrate in the bulk region; (b) exposing a surface of the semiconductor substrate in the silicon-on-insulator region from under the protection film; (c) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region and in the bulk region, using an epitaxy method after the step (a); (d) etching the first semiconductor layer and the second semiconductor layer partially, so as to form a first trench which exposes a side surface of the first semiconductor layer in the silicon-on-insulator region; (e) etching the first semiconductor layer through the first trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between the semiconductor substrate and the second semiconductor layer in the silicon-on-insulator region; and (f) forming a buried insulating film inside the cavity. | 2008-08-28 |
20080206954 | METHODS OF REDUCING IMPURITY CONCENTRATION IN ISOLATING FILMS IN SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof. | 2008-08-28 |
20080206955 | Method of Forming an Isolation Film in a Semiconductor Device - A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region. | 2008-08-28 |
20080206956 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A method for fabricating a semiconductor device, includes forming a silicon nitride film on a base body, forming a silicon film on said silicon nitride film, forming at least one groove extending from said silicon film to inside of said base body, forming by high-density plasma-enhanced chemical vapor deposition a silicon-containing dielectric film in said groove and on said silicon film in such a way that a silicon-rich layer is formed at a height position spaced apart from said base body within said groove, said silicon-rich layer being higher in silicon content than remaining silicon-containing dielectric film, removing by etching a portion of said silicon-containing dielectric film above said silicon film and a portion of said remaining silicon-containing dielectric film above said silicon-rich layer, if any, and after having removed said silicon-containing dielectric film, removing by etching said silicon-rich layer and said silicon film. | 2008-08-28 |
20080206957 | Method of Forming Isolation Layer of Semiconductor Memory Device - The present invention relates to a method of forming an isolation layer of a semiconductor memory device. After a trench is formed by etching a semiconductor substrate, a liner insulating film is formed from a DCS-HTO material having a similar wet etch rate to that of a PSZ film that gap fills an isolation layer, and the trench is gap filled with the PSZ film. Accordingly, in a subsequent etch process for EFH control of the isolation layer, residues do not remain on sidewalls of a conductive film for a floating gate, thereby improving electrical properties of devices. | 2008-08-28 |
20080206958 | ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN - The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer. | 2008-08-28 |
20080206959 | Peeling method - A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high yield. Further, there are provided a semiconductor device, which is reduced in weight through adhesion of the layer to be peeled to various base materials, and a manufacturing method thereof. In particular, there are provided a semiconductor device, which is reduced in weight through adhesion of various elements, typically a TFT, to a flexible film, and a manufacturing method thereof. A metal layer or nitride layer is provided on a substrate; an oxide layer is provided contacting with the metal layer or nitride layer; then, a base insulating film and a layer to be peeled containing hydrogen are formed; and heat treatment for diffusing hydrogen is performed thereto at 410° C. or more. As a result, complete peeling can be attained in the oxide layer or at an interface thereof by using physical means. | 2008-08-28 |
20080206960 | REWORKABLE CHIP STACK - A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point. | 2008-08-28 |
20080206961 | Semiconductor device and semiconductor substrate - In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained. | 2008-08-28 |
20080206962 | METHOD AND STRUCTURE FOR THICK LAYER TRANSFER USING A LINEAR ACCELERATOR - A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature. In a specific embodiment, the method includes subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles generated using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature, which is higher than the first temperature. The method frees the thickness of detachable material using a cleaving process, e.g., controlled cleaving process. | 2008-08-28 |
20080206963 | Cleaving process to fabricate multilayered substrates using low implantation doses - A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane. The method also includes providing selected energy to the donor substrate to cleave the device layer from the cleave layer at the cleave plane, whereupon the selected energy is applied to create a controlled cleaving action to remove the device layer from a portion of the cleave layer in a controlled manner. | 2008-08-28 |
20080206964 | Carbon Nanotube Transistor Process with Transferred Carbon Nanotubes - During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure. | 2008-08-28 |
20080206965 | STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY - Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices. | 2008-08-28 |
20080206966 | QUANTUM DOTS NUCLEATION LAYER OF LATTICE MISMATCHED EPITAXY - Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies. | 2008-08-28 |
20080206967 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A thin semiconductor film is crystallized in a high yield by being irradiated with laser light. An insulating film, a semiconductor film, an insulating film, and a semiconductor film are stacked in this order over a substrate. Laser light irradiation is performed from above the substrate to melt the semiconductor films of a lower layer and an upper layer, whereby the semiconductor film of the lower layer is crystallized. With the laser light irradiation, the semiconductor film of the upper layer changes to a liquid state, thereby reflecting the laser light and preventing the semiconductor film of the lower layer from being overheated with the laser light. Further, by melting the semiconductor film of the upper layer as well, time for melting the semiconductor film of the lower layer can be extended. | 2008-08-28 |
20080206968 | Manufacturing method of semiconductor device - To create a laminated film of a silicon oxide film and a silicon nitride film, with large current driving force and large dielectric constant. A manufacturing method of a semiconductor device includes: forming an amorphous silicon film on the silicon oxide film; and forming a single crystal silicon film by annealing the amorphous silicon film. | 2008-08-28 |
20080206969 | Laser Optical Apparatus - There is provided a structure for reducing optical loss in an optical apparatus (homogenizer) for making the intensity distribution of a laser beam uniform. | 2008-08-28 |
20080206970 | Production Of Polycrystalline Silicon - Polysilicon is deposited onto a tube or other hollow body. The hollow body replaces the slim rod of a conventional Siemens-type reactor and may be heated internally with simple resistance elements. The hollow body diameter is selected to provide a surface area much larger than that of a silicon slim rod. The hollow body material may be chosen such that, upon cooling, deposited polysilicon readily separates from the hollow body due to differences in contraction and falls into a collection container. | 2008-08-28 |
20080206971 | DIVERGENT CHARGED PARTICLE IMPLANTATION FOR IMPROVED TRANSISTOR SYMMETRY - The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles ( | 2008-08-28 |
20080206972 | DOPED NANOPARTICLE-BASED SEMICONDUCTOR JUNCTION - A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including fused semiconductor nanoparticles; and a second layer in contact with the first semiconductor layer over a substrate to form the semiconductor junction. | 2008-08-28 |
20080206973 | Process method to optimize fully silicided gate (FUSI) thru PAI implant - An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch-stop layer, planarizing the blocking layer down to the etch-stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform silicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate silicide over the gates to form the FUSI gates, and forming source/drain silicide in moat areas of the NMOS and PMOS transistors. | 2008-08-28 |
20080206974 | FABRICATION OF SEMICONDUCTOR DEVICE HAVING COMPOSITE CONTACT - A method of fabricating a semiconductor device with a composite contact is provided. The fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure. The composite contact is formed by forming a DC conducting electrode attached to a semiconductor layer in a semiconductor structure and forming a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies. | 2008-08-28 |
20080206975 | METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film. | 2008-08-28 |
20080206976 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench. | 2008-08-28 |
20080206977 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 2008-08-28 |
20080206978 | ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material. | 2008-08-28 |
20080206979 | INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. | 2008-08-28 |
20080206980 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD AND STRUCTURE FOR IMPLEMENTING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved. | 2008-08-28 |
20080206981 | Semiconductor device and manufacturing method therefor - In a manufacturing method for a semiconductor storage device, an interlayer insulating film, a first hard mask made of an insulative material for coating the interlayer insulating film and a second hard mask are formed on a substrate. The second hard mask is opened, and with use of the second hard mask as a mask, a recess groove, where an embedded interconnection is to be embedded, is formed in the interlayer insulating film. A diffusion preventing film is formed for preventing an embedded interconnection material from diffusing into the interlayer insulating film. The second hard mask and the diffusion preventing film are made of an identical material, which is a conductive material containing a metallic element in its composition. A conductive metal to be a material of the embedded interconnection is deposited. The surface side of the conductive metal is polished to the level that the first hard mask is exposed therefrom. | 2008-08-28 |
20080206982 | INTERCONNECT STRUCTURES WITH A METAL NITRIDE DIFFUSION BARRIER CONTAINING RUTHENIUM AND METHOD OF FORMING - A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a substrate having a micro-feature opening formed within a dielectric material and forming a metal nitride diffusion barrier containing ruthenium, nitrogen, and a nitride-forming metal over the surfaces of the micro-feature. The nitride-forming metal is selected from Groups IVB, VB, VIB, and VIIB of the Periodic Table, and the metal nitride diffusion barrier is formed by exposing the substrate to a precursor of the nitride-forming metal, a nitrogen precursor, and a ruthenium precursor. | 2008-08-28 |
20080206983 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - The present invention is a method of manufacturing a photoelectric conversion device having a multilayered interconnection (wiring) structure disposed on a semiconductor substrate, including steps of forming a hole in a region of the interlayer insulation film corresponding to an electrode of the transistor; burying an electroconductive substance in the hole; forming a hydrogen supplying film; conducting a thermal processing at a first temperature to supply a hydrogen from the hydrogen supplying film to the semiconductor substrate; forming the multilayered interconnection structure using Cu in a wiring material; and forming a protective film covering the multilayered interconnection structure, wherein the step of forming the multilayered interconnection structure, and the step of forming the protective film are conducted at a temperature not higher than the first temperature. | 2008-08-28 |
20080206984 | CONDUCTIVE VIA FORMATION UTILIZING ELECTROPLATING - A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material. | 2008-08-28 |
20080206985 | Method of fabricating a semiconductor device - Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region. | 2008-08-28 |
20080206986 | METHOD OF FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAP LAYER BY AN ADVANCED INTEGRATION REGIME - By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences. | 2008-08-28 |
20080206987 | PROCESS FOR TUNGSTEN NITRIDE DEPOSITION BY A TEMPERATURE CONTROLLED LID ASSEMBLY - Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature within a range from about 120° C. to about 180° C., exposing the substrate to a reducing gas during a pre-nucleation soak process, and depositing a first tungsten nucleation layer on the substrate during a first atomic layer deposition process within the processing chamber. The method further provides depositing a tungsten nitride layer on the first tungsten nucleation layer during a vapor deposition process, depositing a second tungsten nucleation layer on the tungsten nitride layer during a second atomic layer deposition process within the processing chamber, and exposing the substrate to another reducing gas during a post-nucleation soak process. | 2008-08-28 |
20080206988 | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions - A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate. | 2008-08-28 |
20080206989 | Method for Producing Vertical Electrical Contact Connections in Semiconductor Wafers - The invention relates to a method for producing vertical electrical connections (micro-vias) in semiconductor wafers for the fabrication of semiconductor components. The method is characterized by the following steps: —application of a protective resist to the wafer front side—patterning of the protective resist on the wafer front side such that the contacts to be connected to the wafer rear side become free—laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side—cleaning of the wafer (debris removal)—application of a plating base to the wafer rear side and into the laser-drilled passage holes—application of gold by electrodeposition onto the metallized wafer rear side and the passage holes—resist stripping of the protective resist—application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side. | 2008-08-28 |
20080206990 | Methods For Fabricating Semiconductor Components With Conductive Interconnects - A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components. | 2008-08-28 |
20080206991 | METHODS OF FORMING TRANSISTOR CONTACTS AND VIA OPENINGS - A method of forming contacts to a transistor comprises depositing a dielectric layer on a substrate having the transistor, etching a first opening in the dielectric layer that contacts a gate stack of the transistor, depositing a sacrificial material in the first opening, and etching a second and a third opening in the dielectric layer that contact a source and a drain region of the transistor, wherein the second and third openings are etched after the first opening is etched. By etching the opening to the gate stack first, defects such as contact-to-gate shorts are reduced or eliminated. | 2008-08-28 |
20080206992 | Method for manufacturing high flatness silicon wafer - The present invention relates to a method for manufacturing a high flatness silicon wafer comprising (S | 2008-08-28 |
20080206993 | Using Spectra to Determine Polishing Endpoints - Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described. | 2008-08-28 |
20080206994 | METHOD OF REDUCING NON-UNIFORMITIES DURING CHEMICAL MECHANICAL POLISHING OF EXCESS METAL IN A METALLIZATION LEVEL OF MICROSTRUCTURE DEVICES
- Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity. | 2008-08-28 |
20080206995 | METAL-POLISHING LIQUID AND POLISHING METHOD THEREWITH - The present invention provides a metal-polishing liquid that is used in chemical mechanical polishing for a conductor film made of copper or a copper alloy during semiconductor device production, wherein the metal-polishing liquid comprises the following components (1), (2) and (3):
| 2008-08-28 |
20080206996 | SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS - A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W | 2008-08-28 |
20080206997 | Method for Manufacturing Insulating Film and Method for Manufacturing Semiconductor Device - A method for manufacturing an insulating film, by which the insulating film can be formed of a non-photosensitive siloxane resin and formed into a desired shape by wet etching. A thin film is formed with a suspension in which a siloxane resin or a siloxane-based material is included in an organic solvent; a first heat treatment is performed on the thin film; a mask is formed over the thin film after the first heat treatment; wet etching with an organic solvent is performed to process the shape of the thin film after the first heat treatment; and a second heat treatment is performed on the processed thin film. | 2008-08-28 |
20080206998 | SEMICONDUCTOR FABRICATION APPARATUSES TO PERFORM SEMICONDUCTOR ETCHING AND DEPOSITION PROCESSES AND METHODS OF FORMING SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes. | 2008-08-28 |
20080206999 | METHOD FOR WET ETCHING WHILE FORMING INTERCONNECT TRENCH IN INSULATING FILM - A wet etching method that includes forming an insulating film on a substrate, and irradiating laser light to the insulating film during wet etching of the insulating film using an etching solution. | 2008-08-28 |
20080207000 | METHOD OF MAKING HIGH-ASPECT RATIO CONTACT HOLE - A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer dielectric (ILD) layer on the contact etch stop layer. A photoresist pattern is formed on the ILD layer. The photoresist pattern has an opening directly above the conductive region. Using the photoresist pattern as an etch hard mask and the contact etch stop layer as an etch stop, an anisotropic dry etching process is performed to etch the ILD layer through the opening, thereby forming an upper hole region. The photoresist pattern is removed. An isotropic dry etching process is performed to dry etching the contact etch stop layer selective to the ILD layer through the upper hole region, thereby forming a widened, lower contact bottom that exposes an increased surface area of underlying conductive region. | 2008-08-28 |
20080207001 | Pulsed Etching Cooling - In an apparatus and method of vapor etching, a sample (S) to be etched is located in a main chamber ( | 2008-08-28 |
20080207002 | METHOD OF REMOVING GRAPHITIC AND/OR FLUORINATED ORGANIC LAYERS FROM THE SURFACE OF A CHIP PASSIVATION LAYER HAVING SI-CONTAINING COMPOUNDS - A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO | 2008-08-28 |
20080207003 | PRODUCTION METHOD OF SEMICONDUCTOR APPARATUS - In order to provide a production method of a semiconductor apparatus that can form a film, even in the case of forming a carbon film, on a semiconductor substrate while maintaining an improved optical transparency at a visible band and while maintaining a preferable adhesion property, the semiconductor apparatus production method includes: a first step of generating and controlling plasma by using oxygen and conducting a plasma operation on a surface of a semiconductor substrate set inside a reaction chamber in which a film is formed on the surface of the semiconductor substrate; and a second step of generating and controlling plasma by using hydrogen and conducting a plasma operation on the surface of the semiconductor substrate set inside the reaction chamber, wherein the second step is conducted after the first step and before forming the film on the surface of the semiconductor substrate inside the reaction chamber. | 2008-08-28 |
20080207004 | Method of Forming a Semiconductor Structure - A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium. | 2008-08-28 |
20080207005 | Wafer Cleaning After Via-Etching - When a semiconductor wafer bears porous dielectric materials it is still possible to perform post-via-etch cleaning of the wafer using aqueous cleaning fluids if, before and/or simultaneously with application of the aqueous cleaning fluid(s), a water-soluble organosilane or like passivation material is used to form a passivation layer on the porous dielectric material. | 2008-08-28 |
20080207006 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT - The present disclosure is directed to a process for plasma treating a film comprising titanium, nitrogen and impurities on a substrate. The process comprises forming a plasma of nitrogen gas and hydrogen gas, the flow ratio of hydrogen gas to nitrogen gas ranging from about 0.01 to about 0.7. The film is contacted with the plasma for a time sufficient to reduce the concentration of impurities in the film. | 2008-08-28 |
20080207007 | Plasma Enhanced Cyclic Chemical Vapor Deposition of Silicon-Containing Films - The present invention is a process of plasma enhanced cyclic chemical vapor deposition of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carboxynitride, and carbon doped silicon oxide from alkylaminosilanes having Si—H | 2008-08-28 |
20080207008 | Microwave hybrid and plasma rapid thermal processing of semiconductor wafers - Microwave energy is used as a radiation source for rapid thermal processing of semiconductor wafers. In one aspect, a hybrid material formed from a microwave modulator material is used to provide temperature uniformity across the wafer and to avoid cracking or breaking of wafers due to the development of thermal stresses. In another aspect, microwave-generated atmospheric pressure plasma is used to heat the wafer either directly or indirectly. | 2008-08-28 |
20080207009 | FEMALE TERMINAL FOR CONNECTOR, CONNECTOR, AND ELECTRICAL CONNECTION DEVICE - A female terminal for connector is electrically connected to a pin, and the pin is electrically connected to a squib to ignite an airbag. The female terminal for connector includes a tubular external wall part and a spring part contacting the pin. A tip portion of the spring part is capable of swinging so as to deflect from a main body portion. The external wall part is formed into a shape having two curved portions disposed to face one another in a swinging direction so as to be outward convex in a radial cross section, and two joining portions to linearly joint ends of the two curved portions together, and the external wall part is formed such that an outside diameter in the swinging direction of the spring part is made larger than an outside diameter in a direction perpendicular to the swinging direction. | 2008-08-28 |
20080207010 | Electrical connector and combination connector having the same - An electrical connector includes a housing having a first sidewall surface and a second sidewall surface extending in a first direction in parallel to each other with a first distance therebetween; a first terminal having a first contact portion protruding from the first sidewall surface in a second direction substantially perpendicular to the first direction; a second terminal having a second contact portion protruding from the second sidewall surface; and an extension portion having a first external wall surface and a second external wall surface. The extension portion is arranged so that a center point between the first external wall surface and the second external wall surface is shifted with respect to a center point between the first contact portion and the second contact portion. The first external wall surface extends in parallel to the second external wall surface with a second distance larger than the first distance. | 2008-08-28 |
20080207011 | Board-To-Board Connector - The invention relates to a board-to board connector ( | 2008-08-28 |
20080207012 | Electrical card connector - An electrical card connector includes a shell ( | 2008-08-28 |
20080207013 | Electrical Connector - An electrical connector, for connecting an electronic device with a circuit board, comprises an insulating substance and conductive terminals, wherein the insulating substance configures a plurality of terminal containing holes and the conductive terminals are configured in the terminal containing holes. The electronic device and the circuit board thereon respectively configure a conductive section electrically connecting with on of the conductive terminals, and an elastic protruding section, pressing on the conductive section or around the conductive section, is configured around each of the terminal containing holes. When the elastic protruding section presses on the electronic device and the circuit board, contact points of the conductive terminals and the electronic device and the circuit board are sealed up in the space surrounded by the elastic protruding section, so as to decrease the contact with air and to decrease the rate of the oxidation of the contact points. | 2008-08-28 |
20080207014 | Board Mounted Electrical Connector - A board-to-board electrical connector assembly includes a first connector having a dielectric housing for mounting on a first printed circuit board for receiving a plug portion of a second connector mounted on a second printed circuit board. The connectors are mateable in a mating direction. A plurality of first conductive terminals are mounted on the housing of the first connector along the receptacle for engaging a plurality of second conductive terminals mounted along the plug portion of the second connector. A first retention member is mounted on one of the connectors and is engageable with a second retention member on the other connector in the mating direction. The first retention member includes a flexible engaging portion which extends in a direction generally perpendicular to the mating direction. The second retention member includes a rigid engaging portion for engaging and flexing the flexible engaging portion to hold the connectors in mated condition. | 2008-08-28 |
20080207015 | Press-fit pin and board structure - Provided is a printed wiring board formed with a through-hole into which a press-fit pin is press-fitted. The printed wiring board includes at least one signal transmission layer, a signal transmission wiring pattern formed in the signal transmission layer, and an electrode portion of the signal transmission wiring pattern exposed at an inner circumferential surface of the through-hole. The electrode portion is not formed covering the entire inner circumferential surface of the through-hole but at a part of the inner circumferential surface of the through-hole. | 2008-08-28 |
20080207016 | COMMUNICATIONS MODULE - A communications module includes: a circuit board having a peripheral end; a first electronic component mounted on the circuit board; a plurality of second electronic components mounted on the circuit board and having a structural strength less than that of the first electronic component; and a metal cover secured to the peripheral end of the circuit board. The metal cover includes a top wall disposed over the first and second electronic components and formed with a protrusion protruding toward the first electronic component. The distance between the protrusion and the first electronic component is less than the distance between the top wall of the cover and the second electronic components. | 2008-08-28 |
20080207017 | MOUNTING ASSEMBLY FOR A VEHICLE POWER JUNCTION BOX - A mounting assembly for a vehicle power junction box includes a first mounting unit and a second mounting unit having a positioning relative to the first mounting unit. A weld bead is positioned between the first mounting unit and the second mounting unit to vibration weld the first mounting unit relative to the second mounting unit. | 2008-08-28 |
20080207018 | CONTACT LEAD - A contact lead for engaging with an aperture lead of a circuit carrier, including a substrate contact portion electrically connected to a pad on a substrate a chip contact portion extending from the substrate contact portion and forming an angle with the substrate contact portion raising from the substrate. The contact lead chip contact portion may also be of a cylindrical shape vertically extending from the substrate contact portion. The present invention also provides a module including a printed circuit board having a plurality of pad thereon, the contact lead electrically connected to the pad, an integrated circuit carrier having a plurality of aperture leads, the aperture leads passing through the contact leads and contacting respectively thereof, and a housing structure for housing the module and providing access for the user to assemble the integrated circuit carrier. | 2008-08-28 |
20080207019 | FLEXIBLE CIRCUIT CONNECTOR ASSEMBLY - An electrical connector assembly for connecting a flexible circuit to a circuit board includes a flexible circuit attached to a clamp member and a plurality of alignment posts extending from the circuit board. The clamp member has notches that receive the posts to place the contact field of the flexible circuit above the contact field of the circuit board. A spring assembly attached to the clamp member has a manually-operated drive that moves a cam member deflecting the spring against the posts, generating a spring force pressing the clamp member against the circuit board. Barriers formed on the posts prevent contact of the flexible circuit with the circuit board until the contact fields are properly aligned. | 2008-08-28 |