35th week of 2008 patent applcation highlights part 34 |
Patent application number | Title | Published |
20080205116 | THREE-DIMENSIONAL MAGNETIC MEMORY - Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. Bits may be written to a data storage layer in the form of magnetic domains. The bits can then be transferred between the stacked data storage layers by heating a neighboring data storage layer, which allows the magnetic fields from the magnetic domains to imprint the magnetic domains in the neighboring data storage layer. By imprinting the magnetic domains into the neighboring data storage layer, the bits are copied from one data storage layer to another. | 2008-08-28 |
20080205117 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate. | 2008-08-28 |
20080205118 | INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE - An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode. | 2008-08-28 |
20080205119 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In order to determine data stored in a memory cell of a resistive cross-point cell array, two reference cells having two different known resistance values (e.g., data “0” and data “1”) are provided, and a difference in current between a selected cell and the reference cell having data “0” and a difference in current between the selected cell and the reference cell having data “1” are compared. By comparison with a current of the reference cell which has a parasitic current as with the selected cell and has known data “0”/“1”, data can be determined while suppressing an influence of a parasitic current. | 2008-08-28 |
20080205120 | Multiple layer random accessing memory - The present invention provides a new semiconductor Random Access Memory, RAM which stores multiple bits per cell. When writing data, at least three levels of voltage sources are generated to charge the bit line and the RAM capacitive device through the selective devices. During reading data, at least three referencing voltage sources are input to at least three sense amplifiers to differentiate at least four levels of bit line voltages and convert the differential levels to at least two logic bits. | 2008-08-28 |
20080205121 | Current driven memory cells having enhanced current and enhanced current symmetry - A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on. | 2008-08-28 |
20080205122 | MRAM MEMORY CONDITIONING - According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition. | 2008-08-28 |
20080205123 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF REDUCING CRITICAL CURRENT OF THE SAME - A magnetic random access memory includes a substrate, a free layer and a spacer layer. The substrate and the free layer are made of a vertical anisotropy ferrimagentic thin film. The spacer layer is sandwiched between the substrate and the free layer and is made of an insulating layer. The method uses a modified Landau-Lifshitz-Gilbert equation to obtain a critical current value as a function of exchange coupling constant. The critical current value is predictable under several external magnetic fields being applied. When the exchange coupling constant is proportionally varied, the critical current value is reduced to a third of its original value under an optimum state. | 2008-08-28 |
20080205124 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHODS OF THE SAME - A semiconductor memory device includes first to third resistive memory elements, a first transistor having a first gate electrode, first and second source/drain electrodes, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of the third resistive memory element, a second transistor having a second gate electrode, third and fourth source/drain electrodes, the third source/drain electrode being connected to one terminal of the second resistive memory element, and the fourth source/drain electrode being connected to one terminal of the third resistive memory element, a first bit line connected to the other terminal of the third resistive memory element, a second bit line connected to the other terminal of each of the first and second resistive memory elements, and first and second word lines connected to each of the first and second gate electrodes. | 2008-08-28 |
20080205125 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD THEREOF - A magnetic random access memory includes first and second bit lines extending in a first direction, the second bit line being adjacent to the first bit line in a second direction, a first magnetoresistive effect element being connected to the first bit line and having a first fixed layer, a first recording layer, and a first nonmagnetic layer, and a second magnetoresistive effect element being adjacent to the first magnetoresistive effect element in the second direction and being connected to the second bit line and having a second fixed layer, a second recording layer, and a second nonmagnetic layer, the first and second recording layers being formed by a same first layer extending in the second direction. | 2008-08-28 |
20080205126 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni. | 2008-08-28 |
20080205127 | PHASE CHANGE STORAGE CELLS FOR MEMORY DEVICES - Storage cells for a semiconductor device can include a first layer of phase change material on a substrate and a second layer of phase change material being in contact with the first layer, the second layer of phase change material having a higher resistance than the first layer. | 2008-08-28 |
20080205128 | PHASE CHANGE MEMORY DEVICE - A phase change memory device has a memory cell that uses a phase change film as a storage element, and includes: a first phase change region formed on a side of one face of the phase change film; and a second phase change region formed on a side of another face of the phase change film in a position that corresponds to the first phase change region, wherein the phase change memory stores two-bit data using combinations of a high resistance state due to amorphization and a low resistance state due to crystallization in the first phase change region with the high resistance state and the low resistance state in the second phase change region, the resistance value of the low resistance state being lower than that of the high resistance state. | 2008-08-28 |
20080205129 | NON-VOLATILE MAGNETIC MEMORY DEVICE - A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line. The multiple magnetic elements are arranged such that remnant magnetic field stored in them can be cumulatively sensed. In another embodiment, the magnetic element is arranged to be magnetized in a single general direction, but is shaped such that magnetic flux lines emanate from it in different directions. The different directions are arranged to direct flux lines through the sensing region of a sensor, which measures their cumulative effect. | 2008-08-28 |
20080205130 | MRAM FREE LAYER SYNTHETIC ANTIFERROMAGNET STRUCTURE AND METHODS - A magnetic tunnel junction (MTJ) structure for use with toggle MRAM devices and the like includes a tunnel barrier layer and a synthetic antiferromagnet (SAF) structure formed on the tunnel barrier layer, wherein the SAF includes a plurality (e.g., three or more) ferromagnetic layers antiferromagnetically or ferromagnetically coupled by a plurality of respective coupling layers. The bottom ferromagnetic layer adjacent the tunnel barrier layer has a high spin polarization and a high intrinsic anisotropy field (H | 2008-08-28 |
20080205131 | Magnetic random access memory with selective toggle memory cells - A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni | 2008-08-28 |
20080205132 | Memory Element and Semiconductor Device, and Method for Manufacturing the Same - It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer. | 2008-08-28 |
20080205133 | Capacitor-less volatile memory cell, device, system and method of making same - A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor. | 2008-08-28 |
20080205134 | Charge pump to supply voltage bands - The present invention provides a voltage generating circuit and a control method thereof which is capable of preventing an increase in the occupied area and suitable for raising the voltage of the power supply in a wide range. | 2008-08-28 |
20080205135 | Method of reading the bits of nitride read-only memory cell - A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value. | 2008-08-28 |
20080205136 | READ METHOD OF MEMORY DEVICE - A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a N | 2008-08-28 |
20080205137 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter. | 2008-08-28 |
20080205138 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array. | 2008-08-28 |
20080205139 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each having a plurality of threshold levels corresponding to a plurality of programming data respectively; a voltage generator circuit which generates a plurality of programming voltage pulses and a plurality of verify voltage pulses which are applied to said nonvolatile memory cells; a counter circuit which counts the number of times said programming voltage pulse is applied to corresponding said nonvolatile memory cell; a storage circuit which stores data corresponding to said plurality of verify voltage pulses which are set for each of corresponding said threshold levels and the number of times said programming voltage pulse is applied, the number of times said programming voltage pulse is applied being standards for switching a plurality of said verify voltage pulses; a comparison circuit which compares the number of times said programming voltage pulse is applied with said standards and generates a comparison result; a control circuit which controls said plurality of verify voltage pulses step by step based on said comparison result. | 2008-08-28 |
20080205140 | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array - A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columnar bit line structure such that each column of the dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells. | 2008-08-28 |
20080205141 | Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell - A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell. | 2008-08-28 |
20080205142 | ERASE VOLTAGE GENERATOR CIRCUIT FOR PROVIDING UNIFORM ERASE EXECUTION TIME AND NONVOLATILE MEMORY DEVICE HAVING THE SAME - An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal. | 2008-08-28 |
20080205143 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION FOR EACH MEMORY BLOCK - A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value. | 2008-08-28 |
20080205144 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably. | 2008-08-28 |
20080205145 | MEMORY CONTROLLER CONTROLLING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DEVICE - A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value. | 2008-08-28 |
20080205146 | Nonvolatile RAM - A nonvolatile RAM for reading and writing data in a random manner includes a memory area configured by a plurality of memory cells suited to a nonvolatile-mode write operation, in which the stored content thereof is not lost irrespective of a power-off event, and a volatile-mode write operation, in which the stored content thereof is lost in the power-off event. A register designates a first portion of the memory area adapted to the nonvolatile-mode write operation regarding fixed data such as program codes and a second portion of the memory area serving as a work area adapted to the volatile-mode write operation. A control circuit performs the nonvolatile-mode write operation on the first portion of the memory area while performing the volatile-mode write operation on the second portion of the memory area. | 2008-08-28 |
20080205147 | Local self-boost inhibit scheme with shielded word line - A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of the set or pair to shield the other from word line to word line capacitive voltage coupling. In NAND memory string embodiments the various cells of strings of non-volatile memory cells are programmed utilizing modified or unmodified drain-side self boost, source-side self boost, local self boost, and virtual ground programming processes that utilize two or more “blocking” memory cells on either the source line side and drain line side of a selected memory cell. The paired blocking cells shield each other during programming to reduce coupled noise, to prevent charge leakage from the boosted channel of the selected memory cell. | 2008-08-28 |
20080205148 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line. | 2008-08-28 |
20080205149 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device enables a pump in response to a first program confirm command. The pump generates a voltage. An initial page of a memory block is programmed. Subsequent intermediate pages of the memory block are programmed in response to a second program confirm command while the pump remains enabled. A final page of the memory block is programmed in response to a third program confirm command. The pump is then disabled after the final page is programmed. | 2008-08-28 |
20080205150 | HYBRID NON-VOLATILE MEMORY - A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits. | 2008-08-28 |
20080205151 | Non-Volatile Memory Device and Method of Driving the Same - A non-volatile memory device capable of stably setting its operating environment and a method of driving the non-volatile memory device are provided. The method includes providing power to the non-volatile memory device having a memory cell array that stores initial setting data for setting the operating environment of the non-volatile memory device. An initial read operation is performed on the memory cell array. The operating environment of the non-volatile memory device is set using the initial setting data that is read through the initial read operation. The initial setting data stored in the memory cell array includes main data having information about the operating environment to be set and an indicator corresponding to the main data for indicating a start and an end of the main data. | 2008-08-28 |
20080205152 | FLASH MEMORY DEVICE FOR OVER-SAMPLING READ AND INTERFACING METHOD THEREOF - A memory system having a flash memory device that performs an over-sampling read operation to read data from a memory cell in the flash device by using an over-sampling read voltage that falls within a threshold voltage distribution range. A memory controller supplies a read mode signal to the flash memory device to perform the over-sampling read operation. | 2008-08-28 |
20080205153 | METHOD AND APPARATUS FOR CONTROLLING TWO OR MORE NON-VOLATILE MEMORY DEVICES - A method and apparatus for controlling two or more non-volatile memory devices includes activating a read enable signal or a write enable signal, which is input to the first and second non-volatile memory devices, using a controller. A first chip enable signal is alternately activated for selecting the first non-volatile memory device and a second chip enable signal is activated for selecting the second non-volatile memory device using the controller. This is done while the read enable signal or the write enable signal is input to the first and second non-volatile memory devices being activated. Accordingly, even when the minimum cycle of the controller is longer than that of a memory device read/write time is reduced, thereby improving read/write performance. | 2008-08-28 |
20080205154 | Semiconductor Memory Device - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 2008-08-28 |
20080205155 | Systems and methods to reduce interference between memory cells - Embodiments of the inventive subject matter provide systems and methods for programming a set of memory cells by inducing a first voltage on the lower page of a first group of memory cells to hold a first least significant bit, and by inducing a second voltage on the lower page of a second group of memory cells to hold a second least significant bit. Once the lower page is programmed, the voltage may be shifted to the upper page of each memory cell into a final range representing one or more most significant bits to be programmed. Each memory cell may store a voltage within a final programmed range representing a binary value. | 2008-08-28 |
20080205156 | Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation. | 2008-08-28 |
20080205157 | Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation. | 2008-08-28 |
20080205158 | READING METHOD AND CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE BASED ON THE ADAPTIVE GENERATION OF A REFERENCE ELECTRICAL QUANTITY - A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array memory cell, with a reference electrical quantity, and supplies an output signal indicative of the datum, based on the comparison; and a generator circuit, provided with an input receiving a target electrical quantity correlated to a current flowing in use in the reference memory cell, and an output, which supplies the reference electrical quantity with a controlled value close or equal to that of the target electrical quantity. The generator circuit is provided with a variable generator, and a control unit connected to, and designed to control, the variable generator so that it will generate the controlled value of the reference electrical quantity. | 2008-08-28 |
20080205159 | VERIFICATION PROCESS OF A FLASH MEMORY - A verification process is disclosed for verifying correctness of a data status of a flash memory after data of the flash memory is altered. The flash memory has a plurality of memory cells array and a volatile memory. The verification process includes reading memory-cell verification data stored in the volatile memory, wherein the memory-cell verification data is for indicating a previous verification result of each memory cell is ‘success’ or ‘failure’; and performing a verification procedure on the memory cells failed in previous verification according to the memory-cell verification data, but not on the remained memory cells successful in previous verification. | 2008-08-28 |
20080205160 | Non-volatile memory devices and operating methods thereof - Non-volatile memory devices and operating methods thereof are provided. In an operating method, a first operation is performed by applying a first voltage to at least one word line. The first operation includes one of a programming or erasing operation. The first operation is verified by applying a verify voltage to each of the at least one word lines. The voltage level of each verify voltage is determined according to position information of a corresponding one of the at least one word lines. | 2008-08-28 |
20080205161 | FLASH MEMORY DEVICE UTILIZING MULTI-PAGE PROGRAM METHOD - A flash memory device is configured to store multi-bit data on one cell utilizing fewer program operations. The flash memory device includes a memory cell, a sense amplifier and a write driver circuit. The sense amplifier is connected to a word line and a bit line. The sense amplifier and write driver circuit store data bits to be programmed on the memory cell. The sense amplifier and write driver circuit drives the bit line through a program voltage during a program execution period when at least one bit from among the data bits to be programmed is a program data bit, and performs a verify read operation when a program verify code representing a verify read period corresponds to a state of the data bits to be programmed. | 2008-08-28 |
20080205162 | Non-Volatile Memory Device and Driving Method Thereof - This patent relates to a non-volatile memory device and a driving method thereof The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line. | 2008-08-28 |
20080205163 | NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result. | 2008-08-28 |
20080205164 | Decoding control with address transition detection in page erase function - Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks. | 2008-08-28 |
20080205165 | Semiconductor Memory Device - Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in. | 2008-08-28 |
20080205166 | TRAPPING STORAGE FLASH MEMORY CELL STRUCTURE WITH INVERSION SOURCE AND DRAIN REGIONS - Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers. | 2008-08-28 |
20080205167 | Voltage generator for nonvolatile memory and writing and erasing method of nonvolatile memory - A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage. | 2008-08-28 |
20080205168 | APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE - An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations. | 2008-08-28 |
20080205169 | DEVICE FOR STORING A BINARY STATE - Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa. | 2008-08-28 |
20080205170 | DDR-SDRAM INTERFACE CIRCUITRY, AND METHOD AND SYSTEM FOR TESTING THE INTERFACE CIRCUITRY - According to one aspect of an embodiment of the present invention, there is provided a memory interface circuit including a first data output circuit which outputs a data signal based on a data strobe signal, the memory interface circuit comprising: a first delay-locked loop circuit that adjusts a delay of the data strobe signal and outputs the data strobe signal at a first timing; and a second data output circuit that outputs the data signal at a second timing different from the first timing during a normal operation, and outputs the data signal at the first timing during a test operation. | 2008-08-28 |
20080205171 | Redundant cross point switching system and method - A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the defective point cell. | 2008-08-28 |
20080205172 | DESIGN-FOR-TEST MICRO PROBE - Systems and techniques for testing a device having first and second interconnected chips that are internal to the device include selecting a site on a communication pathway along which an internal signal travels inside the device between the first and second chips, and connecting a test probe to the site. | 2008-08-28 |
20080205173 | Method and System for Testing an Integrated Circuit - An integrated circuit comprising:
| 2008-08-28 |
20080205174 | Semiconductor memory device and test method thereof - Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate. | 2008-08-28 |
20080205175 | Auto-precharge control circuit in semiconductor memory and method thereof - An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal. | 2008-08-28 |
20080205176 | MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL - A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations. | 2008-08-28 |
20080205177 | LAYOUT STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE HAVING IOSA - Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output lines have less loading and therefore enable higher-speed data transfer rates. Some embodiments of the invention include column selection line repeaters between the two memory blocks. The column selection line repeaters reduce loading in the column selection lines, and increase column selection speed. Embodiments of the invention include both input/output sense amplifiers and column selection line repeaters disposed between the two memory blocks to increase data transfer rates on the global input/output lines and also increase column selection speed. | 2008-08-28 |
20080205178 | DRAM writing ahead of sensing scheme - This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated. | 2008-08-28 |
20080205179 | INTEGRATED CIRCUIT HAVING A MEMORY ARRAY - An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. | 2008-08-28 |
20080205180 | Semiconductor memory device having bit-line sense amplifier - A semiconductor memory device including a bit-line sense amplifier is not affected by variation in manufacturing process and has a stable driving scheme. The semiconductor memory device includes: a unit memory cell for storing a data; a sense amplification unit including a bit-line sense amplifier (BLSA) for sensing and amplifying a voltage difference of a bit-line pair receiving the data of the unit memory cell; a variation detection unit for detecting a variation of a manufacturing process to output a detecting signal; and a sense amplifier controlling unit for controlling the BLSA to be activated after a predetermined time from an activation of unit memory cell in response to the detecting signal. | 2008-08-28 |
20080205181 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line. | 2008-08-28 |
20080205182 | Method of operating a memory cell, memory cell and memory unit - A method of operating a memory cell, a memory cell and a memory unit are described. For example, a memory cell comprises a capacitance and an access circuit in association with said capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust a potential at said access circuit terminal in a retention state such that a retention time of the memory cell is increased. A method of operating a memory cell includes, for example, adjusting a potential at an access circuit terminal of the memory cell to increase a retention time. | 2008-08-28 |
20080205183 | SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage. | 2008-08-28 |
20080205184 | SEMICONDUCTOR MEMORY DEVICE - This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage. | 2008-08-28 |
20080205185 | Semiconductor memory device and its driving method - A semiconductor memory device includes a bit line sense amplifier block array, upper and lower unit memory cell arrays and a switching controller. The bit line sense amplifier block array senses and amplifies data of a unit memory cell array. The upper and the lower unit memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the unit memory cell array. The switching controller selectively connects one of the upper and lower unit memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower unit memory cell arrays are not selected but overdriven. | 2008-08-28 |
20080205186 | Semiconductor memory device and method for driving the same - A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal | 2008-08-28 |
20080205187 | DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT - A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller. | 2008-08-28 |
20080205188 | Under Pedestal Tank Arrangement - Auxiliary fluid tanks associated with transit concrete mixing and dispensing systems are disclosed which include a hydraulic reservoir tank which is adapted to be stowed inside a mixing drum support pedestal. The hydraulic fluid reservoir tank further includes a shaped outer wall defining an enclosed inner space and includes one or more fluid discharge and return connections in the outer wall. The tank is also provided with an internal baffle shape in line with the fluid return connections such that it is addressed by returning hydraulic fluid and deflects and defuses the returning hydraulic fluid so that it thoroughly mixes with cooler reservoir fluid. An auxiliary water tank can also be nested beneath the hydraulic fluid reservoir tank under the hollow support pedestal. | 2008-08-28 |
20080205189 | DENSE PHASE PUMP FOR PULVERULENT MATERIAL - A vessel for fluidizing bulk pulverulent material to render the pulverulent material flowable for removal from the vessel includes first, second, third and fourth ports. The first port is provided for entry of a fluidizing gas or mixture of gases to the vessel. The second port controls a first stream of fluidizing gas or mixture of gases escaping from the vessel at a relatively constant rate to promote the fluidization of bulk pulverulent material introduced into the vessel. The third port is selectively controlled to vary the rate of escape of a second stream of fluidizing gas or mixture of gases. The fluidized pulverulent material is withdrawn from the vessel through the fourth port at a rate in opposition to the rate of escape of the second stream of fluidizing gas or mixture of gases. | 2008-08-28 |
20080205190 | Vortex stirring of vessels in a two-dimensional array - The contents of a two-dimensional array of vessels are mixed by a vortex created by continuous lateral tumbling of a magnetic stir element against the interior side wall of each vessel. The system includes a drive magnet having oppositely polarized sides, and a carousel including receptacles at different heights and at different positions about the carousel's axis of rotation for receiving a plurality of arrays of vessels. The magnet's vertical physical axis is aligned with the carousel's axis of rotation so that the magnet is disposed to one side of each of the receptacles. The magnet provides magnetic flux lines that rotate horizontally through 360 degrees within the received vessels when the magnet is rotated about its vertical physical axis to thereby cause magnetic stir elements in the vessels to continuously tumble laterally against the interior side wall of the vessel and thereby create the vortexes. | 2008-08-28 |
20080205191 | Methods and Apparatus of Source Control for Synchronized Firing of Air Gun Arrays with Receivers in a Well Bore in Borehole Seismic - Methods and apparatus for generating borehole seismic surveys are disclosed. The methods and apparatus enable more accurate surveys than previous surveying systems. In some embodiments, firing of remote seismic sources is synchronized with data recording in a borehole. In some embodiments, the synchronization is based on a universal time standard. In some embodiments, GPS positioning technology is used to predict firing times and synchronize firing times with downhole and surface recording. | 2008-08-28 |
20080205192 | Deflector Devices - A deflector device ( | 2008-08-28 |
20080205193 | Method for continuous sweeping and separation of multiple seismic vibrators - A method for simultaneously operating multiple seismic vibrators using continuous sweeps (little or no “listening” time between sweeps) for each vibrator, and recovering the separated seismic responses for each vibrator with the earth signature removed. Each vibrator is given a unique, continuous pilot signal. The earth response to the motion of each vibrator is measured or estimated. The vibrator motion records for each vibrator and the combined seismic data record for all the vibrators are parsed into separate shorter records. The shorter records are then used to form a system of simultaneous linear equations in the Fourier transform domain, following the HFVS method of Sallas and Allen. The equations are then solved for the separated earth responses. | 2008-08-28 |
20080205194 | Sonar Scanner - Detecting an object using sound waves includes outputting a sound wave from a transducer, receiving an echo after outputting the sound wave, obtaining a threshold value based on the echo and plural other echoes that are within a predetermined range of the echo, and determining if the echo is a result of the sound wave based on the threshold value. | 2008-08-28 |
20080205195 | Method of Amplitude Modulating a Message Signal in the Audible Frequency Range Onto a Carrier Signal in the Ultrasonic Frequency Range - This invention relates to signal processing and to acoustics. The invention provides a method of amplitude modulating a message signal ( | 2008-08-28 |
20080205196 | METHOD FOR SELECTIVE BANDLIMITED DATA ACQUISITION IN SUBSURFACE FORMATIONS - The method for exploring desired characteristics of a subsurface sector, having at least one resonant frequency, is based on selectively transmitting suitable narrowband energy waves into the subsurface sector, thereby producing narrowband signals reflected off the subsurface sector. The transmitted narrowband energy waves can be selectively and optimally adjusted in real time so as to provide optimum illumination of the desired characteristics from the explored sector. | 2008-08-28 |
20080205197 | Device and Methods Directed to Providing Reminders to Contact Lens Wearers - Devices and methods for providing reminders to a contact lens wearer comprise a timing circuit, manually actuatable controls for setting and controlling the timing circuit, and an electronic visual display responsive to the timing circuit. The electronic visual display comprises a clock display, a calendar display, and a message display configured to illuminate a reminder message instructing the contact lens wearer to replace the contact lenses and/or catalyzing platinum disks in the contact lens case. The manually actuatable controls comprise a plurality of use period actuation mechanisms, wherein each actuation mechanism corresponds to an intended period of use, and at least one reset actuation mechanism for updating the device upon replacement of the contact lenses and catalyzing platinum disk. | 2008-08-28 |
20080205198 | Adjustable time relating device for non-readers - A viewable time piece has a face from which relative time is read. The time piece has a changeable time indicator. Symbol or image changes on the time indicator are effected by placement or replacement of at least some non-alphanumeric symbols for view that are indicative of various events over the course of a day. The time piece allows exchange and replacement of the non-alphanumeric symbols so that different events may be indicated for similar respective times over the course of a day. There may also be a system that provides time variant changes in the symbols that are displayed over the course of the day. | 2008-08-28 |
20080205199 | Residual wound quantity display mechanism of timepiece and timepiece with residual wound quantity display mechanism - To provide a residual wound quantity display mechanism of a timepiece, in which it is possible to change a way of a display without changing a basic structure, and a timepiece with the mechanism concerned. A residual wound quantity display mechanism of a mechanical timepiece has an output gearwheel rotating in compliance with a change in a residual wound quantity of a mainspring; a drive lever possessing monolithically a fan-shaped gearwheel part meshing with the output gearwheel, and an arm part extending from a rotation center of the fan-shaped gearwheel part in a direction different from a fan-shaped portion of the fan-shaped gearwheel part; a display member possessing a drive gearwheel part rotatably supported to a tip part of the arm part of the drive lever, and a display arbor formed monolithically in the drive gearwheel part in a site separated from a rotation center of the drive gearwheel part; and a fixation gearwheel possessing a fixation tooth part with which a tooth part of the drive gearwheel part of the display member meshes. Typically the fixation gearwheel adopts a form of the internally-toothed gearwheel. | 2008-08-28 |
20080205200 | Transmission switching mechanism - A gear shifting mechanism intended to be integrated into an horological movement includes a gear pinion rotated by a first wheel of the movement, an element holding a first fly-back heart freely mounted on the gear pinion, and rotated by the first wheel or by a second wheel of the movement. A second fly-back heart is attached to the gear pinion, a gear wheel is mounted freely rotating around the gear pinion and holds a first hammer or also a second hammer pretensioned against the first heart or also the second heart by a first pretensioning spring or also a second pretensioning spring, and a shift wheel being rotatably mounted on the periphery of the gear wheel ( | 2008-08-28 |
20080205201 | Time display apparatus - A time display apparatus is disclosed and comprises at least a housing, a timetable panel, three pointers and a backlight unit. The timetable panel is disposed in the housing. The three pointers are coated with variety of phosphorescence materials respectively and vertically arranged on the timetable panel in order. The backlight unit is disposed below the timetable panel to generate a light source with a fixed wavelength to illuminate the phosphorescence materials of the three pointers, thereby generating different colors for showing hour, minute and second respectively. | 2008-08-28 |
20080205202 | THERMALLY ASSISTED MAGNETIC HEAD, HEAD GIMBAL ASSEMBLY, AND HARD DISK DRIVE - A thermally assisted magnetic head has a medium-facing surface facing a magnetic recording medium; a near-field light generator disposed on a light exit face in the medium-facing surface; a magnetic recording element located adjacent to the near-field light generator; and a light emitting element disposed so that emitted light thereof reaches the near-field light generator; the near-field light generator is comprised of a cusp portion and a base portion; when λin represents a wavelength of the emitted light from the light emitting element immediately before the emitted light reaches the near-field light generator, an intensity of near-field light generated when the material forming the cusp portion is irradiated with the light of the wavelength λin is stronger than an intensity of near-field light generated when the material forming the base portion is irradiated with the light of the wavelength λin. | 2008-08-28 |
20080205203 | Optical head having dual optical paths - An optical head to access data on an optical recording medium, which has two data storage densities, includes two sets of optical path systems to provide two optical paths that are crossed. Each optical path system includes a laser light generation unit, a light guiding unit, a converging objective lens and a photo detector. The light guiding unit is located on the optical path of the laser light generation unit, to direct the laser light to pass through the converging objective lens and focus on the data side of the optical recording medium to carry optical data signals from the data side. The laser light returns to the light guiding unit and travels along the optical path and is received by the photo detector. | 2008-08-28 |
20080205204 | RECORDING METHOD, REPRODUCTION METHOD, RECORDING APPARATUS, REPRODUCTION APPARATUS, AND INFORMATION RECORDING MEDIUM - A recording method for recording, on a write once type information recording medium, management information representing a recording state of the write once type information recording medium is provided. The information recording medium includes data including a first synchronization signal. The information recording medium has a second synchronization signal pre-recorded by cutting. The recording method includes the steps of (a) performing a recording operation for recording the management information at a predetermined position of the information recording medium based on the first synchronization signal; (b) determining whether the recording operation in step (a) is normally terminated or not; and (c) when the recording operation in step (a) is not normally terminated, performing a recording operation for recording the management information at the predetermined position of the information recording medium based on the second synchronization signal. | 2008-08-28 |
20080205205 | SYSTEM AND METHOD FOR PROVIDING VISUAL INDICATORS IN A MEDIA APPLICATION - A method is provided for providing a visual indicator of content existing in a play list while displaying available media items for adding to the play list. The method comprises the steps of: retrieving information related to the available media items; retrieving information related to the content existing in the play list; comparing the available media item information with the play list content information to determine items from the available media that are already included in the play list; displaying a menu showing the available media items; and displaying visual indicators next to the items in the menu of the available media that are already included in the play list. | 2008-08-28 |
20080205206 | METHOD FOR DETECTING A UTILIZATION STATUS OF AN OPTICAL DISC AND APPARATUS THEREOF - A method for detecting a utilization status of an optical disc is disclosed. The method includes: accessing the optical disc to generate a radio frequency signal; generating an estimated blank signal according to the radio frequency signal; generating a first reference signal to indicate a DC level of the radio frequency signal according to the radio frequency signal; and detecting a true overwrite area of the optical disc according to said blank signal and the first reference signal. | 2008-08-28 |
20080205207 | Radial Tracking Method and Apparatus for an Optical Information Carrier Format with Non-Uniformly Spaced Tracks - A radial tracking method for an optical information carrier format with non-uniformly spaced tracks is disclosed, wherein a plurality of tracks ( | 2008-08-28 |
20080205208 | Optical System With Filtered Push Pull Radial Tracking - The present invention relates to optical system capable of reproducing information from an optical carrier by a main beam (C) for reading information as readable effects on the carrier, and a first (A) and a second (B) auxiliary beam. The optical system is adapted to direct the main beam (C) and the first (A) and second (B) auxiliary beam onto the carrier so that the main beam is positioned on a first track, and the first and second auxiliary beam are oppositely positioned on a second and a third track. The optical system can adjust a push pull (PP) radial error signal from the main beam by a function; ƒ=ƒ(A, B, C), where the function ƒ is dependent upon adjacently positioned readable effects in the first, second and third track i.e. the local optical environment of the main beam. Therefore a filtering or “cleaning” of the push pull signal is performed depending on the local optical environment of the main beam. | 2008-08-28 |
20080205209 | OPTICAL DISC DEVICE - The invention provides an optical disc device conducting highly accurate skew adjustment, avoiding an increase in the number of components, and achieving downsizing. This optical disc device includes: a guide shaft for supporting an optical pickup and guiding its movement; a chassis the guide shaft is attached to; a coil spring attached to the chassis for applying force to an end of the guide shaft; an adjustment screw for adjusting the force applied by the coil spring, provided opposite the coil spring with respect to the guide shaft; and a weight addition member attached to the chassis, wherein internal threads for engaging with the adjustment screw are formed in the weight addition member, and the axis of the adjustment screw engaged with the internal thread, the center of a cross section of the guide shaft perpendicular to its axis, and the axis of the coil spring are aligned along the same line. | 2008-08-28 |
20080205210 | Apparatus and Method For Determining Write Strategy Parameters For Recording Data on an Optical Record Carrier and For Determining Read Parameters For Reading Data From an Optical Record Carrier - The present invention relates to an apparatus and a corresponding method for determining write strategy parameters for recording data on an optical record carrier ( | 2008-08-28 |
20080205211 | STRUCTURE AND METHOD FOR STORING DATA ON OPTICAL DISKS - During manufacturing of optical disks, mastering equipment inserts marks (“high frequency wobble marks” or “HFWMs”) into the wobble of the groove on optical disks to store data. The presence of a HFWM at a zero crossing of the wobble indicates an active bit and the absence of the HFWM indicates an inactive bit. The zero crossing is, for example, a negative zero crossing. A matched filter is used to detect the shape of the HFWMs. If a HFWM is detected during a wobble cycle, an active bit is saved in a register or a memory. If a HFWM is not detected during a wobble cycle, an inactive bit is saved in a register or a memory. The active and inactive bits may be coded bits that must be decoded to data bits. The data bits include information such as a synchronization mark, a sector identification data, and an error detection code. | 2008-08-28 |
20080205212 | OPTICAL HEAD APPARATUS, INFORMATION RECORDING/REPRODUCING APPARATUS INCLUDING THE OPTICAL HEAD APPARATUS, AND INFORMATION RECORDING/REPRODUCING METHOD - According to one embodiment, an optical head device provides a signal processing circuit which sets a control amount to move an objective lens so that a distance between the objective lens and a given recording layer of the an optical disc coincides with a focal position, an optical path length correction mechanism which corrects an influence of an aberration component producing an error in the focal distance, a thickness difference detection circuit which finds an amount of correction to be made by the optical path length, and an aberration correction circuit which generates a correction signal to correct the influence of the aberration component producing the error in the focal distance detected by the thickness difference detection circuit, and supplies the correction signal to the optical path length correction mechanism. | 2008-08-28 |
20080205213 | DATA RECORDING APPARATUS - When a blank DVD-RW disk is loaded into an optical disk drive, a host computer issues a FORMAT command to the disk drive. The optical disk drive having received the command performs quick formatting pursuant to a standard. Subsequently, the host computer issues a WRITE command to the optical disk drive in an idle time thereof, thereby instructing recording of dummy data. Consequently, an advantage analogous to that yielded as a result of background formatting of a DVD+RW disk is yielded, and the entirety of the DVD-RW disk can be formatted readily. | 2008-08-28 |
20080205214 | METHOD OF AND APPARATUS FOR MANAGING DISC DEFECTS IN DISC, AND DISC ON WHICH DEFECTS ARE MANAGED - A method of and apparatus for managing disc defects in a disc using a temporary defect management area in the disc, and the disc, where the method includes recording in a data area user data; and recording in a temporary defect management area, which is present in at least one of a lead-in area and a lead-out area, which temporary defect information and temporary defect management information regarding the user data recorded in the data area are recorded. Accordingly, the method and apparatus are applicable to recordable discs and capable of effectively using the defect management area. | 2008-08-28 |
20080205215 | INFORMATION RECORDING MEDIUM, INFORMATION RECORDING METHOD, INFORMATION REPRODUCING METHOD, INFORMATION RECORDING APPARATUS, AND INFORMATION REPRODUCING APPARATUS - According to one embodiment, the invention allows identification of a data recording unit that does not include any reference picture and a data recording unit that includes a reference picture. Specifying information indicating whether or not a target object includes the data unit that does not include any reference picture or I-picture is provided in management information associated with that object. | 2008-08-28 |