35th week of 2008 patent applcation highlights part 18 |
Patent application number | Title | Published |
20080203516 | IMAGE DEVICE AND METHOD OF FABRICATING THE SAME - An image device and a method of fabricating the image device include a substrate pattern formed to define an opening and to include a portion of a photodiode for receiving light. Stacked metal interconnection patterns and an interlayer dielectric layer are formed beneath the substrate pattern. A height of the opening equals a height of the substrate pattern, such that an exposed portion of a top surface of the interlayer dielectric layer provides a bottom surface of the opening. An external connection electrode is positioned on the bottom surface of the opening. | 2008-08-28 |
20080203517 | SEMICONDUCTOR COMPONENT HAVING RECTIFYING JUNCTIONS AND METHOD FOR PRODUCING THE SAME - A semiconductor component is proposed which has a semiconductor body having a first semiconductor zone of the first conduction type, at least one first rectifying junction with respect to the first semiconductor zone, at least one second rectifying junction with respect to the first semiconductor zone, wherein the three rectifying junctions each have a barrier height of different magnitude. | 2008-08-28 |
20080203518 | METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES - The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern. | 2008-08-28 |
20080203519 | MICROELECTRONIC ASSEMBLY WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE AND A METHOD FOR FORMING THE SAME - A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices ( | 2008-08-28 |
20080203520 | Isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 2008-08-28 |
20080203521 | Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate, and method for manufacturing semiconductor device - A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers. | 2008-08-28 |
20080203522 | Structure Incorporating Latch-Up Resistant Semiconductor Device Structures on Hybrid Substrates - Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up. | 2008-08-28 |
20080203523 | LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL - Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure and an associated method of forming the semiconductor structure with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals). | 2008-08-28 |
20080203524 | LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL - Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed. | 2008-08-28 |
20080203525 | Capacitance trimming circuit of semiconductor device having vertically stacked capacitor layers and operation method thereof - A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers. | 2008-08-28 |
20080203526 | Semiconductor device equipped with thin-film circuit elements - A plurality of wirings, column-shaped electrodes, sealing films, and soldering balls, are provided on a third upper-layer insulating film formed on a silicon substrate. A spirally configured thin-film inductive element is disposed beneath the bottom surface of a ground insulating film formed beneath the silicon substrate. The inner and outer end portions of the thin-film inductive element are respectively connected to the wirings via a vertical conductor disposed in the silicon substrate. In this case, it is not required to secure a certain area otherwise needed for the formation of the thin-film inductive element over the surface of the third upper-layer insulating film that accommodates the wirings. Hence, even when the thin-film inductive element has been provided, it is possible to evade a feasibility to incur restraint on the distribution of the wirings formed over the surface of the third upper-layer insulating film. | 2008-08-28 |
20080203527 | Semiconductor device having gate electrode connection to wiring layer - A semiconductor device includes a semiconductor substrate having an electrode formed above a surface thereof; a first insulating resin layer that is provided over the semiconductor substrate and has a first opening defined at a position corresponding to the electrode; a first wiring layer that is provided on the first insulating resin layer and is connected to the electrode through the first opening; a second insulating resin layer provided over the first insulating resin layer and the first wiring layer, the second insulating resin layer having a second opening that is defined at a position different from the position of the first opening in a direction of the surface of the semiconductor substrate; and a second wiring layer that is provided on the second insulating resin layer and is connected to the first wiring layer through the second opening, wherein the second wiring layer includes an induction element, and a sum of a thickness of the first insulating resin layer and a thickness of the second insulating resin layer is not less than 5 μm and not more than 60 μm. | 2008-08-28 |
20080203528 | METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR FABRICATING THE SAME - A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of silicon-hydrogen bonds and a plurality of nitride-hydrogen bonds. A ratio of silicon-hydrogen bonds to nitride-hydrogen bonds is equal to or smaller than 0.5. Accordingly, the nitrogen-rich and compressive silicon nitride film can improve the breakdown voltage of the MIM capacitor. | 2008-08-28 |
20080203529 | SEMICONDUCTOR DEVICE COMPRISING MULTILAYER DIELECTRIC FILM AND RELATED METHOD - A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film. | 2008-08-28 |
20080203530 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device includes a silicon substrate; a first interlayer insulating film provided on the silicon substrate; and a capacitor that is provided on the first interlayer insulating film and that includes a lower electrode, a capacitor dielectric film made of a ferroelectric substance, and an upper electrode, wherein the capacitor dielectric film does not contain a non-oriented component under the upper electrode. | 2008-08-28 |
20080203531 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved. | 2008-08-28 |
20080203532 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a transistor circuit and a bleeder resistance circuit is provided in which fluctuations in resistance value of a bleeder resistor are reduced. In the transistor circuit, a barrier metal film and a interconnect film are layered as a metal film on an interlayer insulating film above transistor structure. In the bleeder resistance circuit, the interconnect film is layered as a metal film on the interlayer insulating film above the bleeder resistor formed from polysilicon film. Alternatively, the metal film in the bleeder resistance circuit includes the barrier metal film only in a portion where the metal film is connected to the bleeder resistor. This reduces stress to the bleeder resistor formed from a polysilicon film, and the resistance value of the bleeder resistor accordingly fluctuates less. In addition, since the metal film used as interconnect of the transistor circuit includes the barrier metal film, interconnect reliability is not impaired. | 2008-08-28 |
20080203533 | SEMICONDUCTOR DEVICE - A semiconductor device includes a principal IGBT controllable in accordance with a gate voltage applied to a gate electrode thereof, a current detecting IGBT connected to the principal IGBT in parallel and a current detecting part including a detecting resistor capable of detecting a current passing through the current detecting IGBT. The base region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other, and the emitter region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other through the detecting resistor. | 2008-08-28 |
20080203534 | COMPLEMENTARY ZENER TRIGGERED BIPOLAR ESD PROTECTION - An electrostatic discharge (ESD) protection clamp ( | 2008-08-28 |
20080203535 | SEMICONDUCTOR DEVICE - A semiconductor device relating to the present invention comprises a base layer of an N-type impurity region. In the base layer, trenches are provided. In the each trench, a gate insulating film and a gate electrode are formed. A body layer of a P-type impurity region is formed in contact with the trenches, and in parallel adjacent to the base layer. On the main surface of the body layer, an emitter layer of an N-type impurity region is provided. On the main surface of the body layer, a contact layer of a P-type impurity region is provided spaced from the trenches. The emitter layer and the contact layer are exposed in different regions on the main surface of the body layer. A buried layer of a P-type impurity region is formed spaced from the trenches in closer to the base layer than to the contact layer in the body layer. | 2008-08-28 |
20080203536 | BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF - A bipolar transistor structure and related methods for fabrication thereof are provided. A vertical spacer layer is selectively deposited after implanting an extrinsic base region into a semiconductor substrate while using an ion implantation mask located upon a screen dielectric layer located upon the semiconductor substrate. A portion of the ion implantation mask may remain embedded and aligned within a sidewall of an aperture within the vertical spacer layer. The selective deposition of the vertical spacer layer allows for a reduced thermal budget and reduced process complexity when fabricating the bipolar transistor. | 2008-08-28 |
20080203537 | Differential Junction Varactor - Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions. | 2008-08-28 |
20080203538 | Semiconductor wafer with division guide pattern - A plurality of semiconductor elements and division regions are provided on a semiconductor subsubstrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region is guided by the division guide pattern. | 2008-08-28 |
20080203539 | Semiconductor Components With Conductive Interconnects - A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a substrate contact. A stacked semiconductor component includes multiple semiconductor components in a stacked array having bonded connections between conductive interconnects on adjacent components. An image sensor semiconductor component includes a semiconductor substrate having light detecting elements on the circuit side, and conductive interconnects on the backside. | 2008-08-28 |
20080203540 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 2008-08-28 |
20080203541 | Semiconductor device and manufacturing method of the same - A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state. | 2008-08-28 |
20080203542 | ION-ASSISTED OXIDATION METHODS AND THE RESULTING STRUCTURES - Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure. | 2008-08-28 |
20080203543 | Semiconductor integrated circuit substrate containing isolation structures - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 2008-08-28 |
20080203544 | SEMICONDUCTOR WAFER STRUCTURE WITH BALANCED REFLECTANCE AND ABSORPTION CHARACTERISTICS FOR RAPID THERMAL ANNEAL UNIFORMITY - Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. | 2008-08-28 |
20080203545 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - A ground line is exposed by removing a surface protecting film, which covers an uppermost metal wiring layer, and providing an opening portion at a portion of a top surface of a semiconductor chip, which portion is within a region contacted by a collet in a pick-up process and corresponds to an upper portion of, among plural metal wires provided at the uppermost metal wiring layer, the ground line which has ohmic connection to a semiconductor substrate. When the collet approaches the top surface of the semiconductor chip in the pick-up process, electrostatic discharge is occurred between the collet and the ground line via the opening portion, and neutralizing charges which have flowed into the ground line directly reach the semiconductor substrate. The semiconductor substrate thereby enters a state of electrostatic equilibrium with a mounting film. | 2008-08-28 |
20080203546 | QUAD FLAT NO-LEAD CHIP CARRIER WITH STAND-OFF - A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved. | 2008-08-28 |
20080203547 | INSERT MOLDED LEADFRAME ASSEMBLY - An insert molded leadframe assembly (IMLA) for an electrical connector is disclosed. The IMLA may include an array of electrically conductive contacts, a dielectric leadframe housing overmolded onto the array of contacts, and a mass disposed within the leadframe housing. The additional mass may shift the IMLA's center of gravity, thereby providing a counterbalance to a non-proportional ball-grid array connector. | 2008-08-28 |
20080203548 | High current semiconductor power device soic package - A high current semiconductor power SOIC package is disclosed. The package includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die soldered thereto; a pair of lead bonding areas being disposed in a same plane of a top surface of the die; large diameter bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum; and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame. | 2008-08-28 |
20080203549 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE - A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface. | 2008-08-28 |
20080203550 | Component, Power Component, Apparatus, Method Of Manufacturing A Component, And Method Of Manufacturing A Power Semiconductor Component - A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered. | 2008-08-28 |
20080203551 | MULTI-CHIP MODULE AND SINGLE-CHIP MODULE FOR CHIPS AND PROXIMITY CONNECTORS - A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure. | 2008-08-28 |
20080203552 | Stacked Package and Method of Fabricating the Same - Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is mounted on the other face of the circuit board. A signal connection member is provided for transmitting signals of the first BGA package and the second BGA package to each other. The second BGA package is provided with a signal connection pad. One end of the signal connection member is bonded to the signal connection pad and the other end of the signal connection member is bonded to the circuit pattern of the circuit board. A method of fabricating the stacked package is also disclosed. | 2008-08-28 |
20080203553 | Stackable bare-die package - A stackable bare-die package primarily comprises a substrate, a chip, a plurality of bonding wires and an encapsulant. The substrate has a slot where a step is formed inside the slot where a plurality of inner fingers are disposed on the step. A plurality of outer pads are disposed on the bottom surface and a plurality of transfer pads on the top surface. The chip is disposed on the top surface and is electrically connected to the inner fingers by a plurality of bonding wires passing through the slot. An encapsulant is formed inside the slot to encapsulate the bonding wires. There is a height difference between the step and the bottom surface so that the loop height of the bonding wires will not exceed the bottom surface. Therefore, when stacking the stackable bare-die packages, the exposed back surface of the chip will not be touched nor stressed to avoid die crack issues. | 2008-08-28 |
20080203554 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided. | 2008-08-28 |
20080203555 | Universal substrate and semiconductor device utilizing the substrate - A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can be utilized for connecting chips having various serial arrangements of bonding pads without replacing or manufacturing another substrate. | 2008-08-28 |
20080203556 | Through-Wafer Interconnection - A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array. | 2008-08-28 |
20080203557 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Warp of a circuit device manufactured by the wafer level packaging technology is reduced. A semiconductor substrate used in a circuit device is provided with a circuit device and electrodes connected to the circuit device. A wiring layer having bumps connected to the electrodes is provided on a major surface of the semiconductor substrate. A metal layer is provided on a surface opposite to the major surface of the semiconductor substrate. | 2008-08-28 |
20080203558 | Method of semiconductor device protection, package of semiconductor device - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 2008-08-28 |
20080203559 | Power device package and semiconductor package mold for fabricating the same - Provided are a power device package coupled to a heat sink using a bolt and a semiconductor package mold for fabricating the same. The power device package includes: a substrate; at least one power device mounted on the substrate; a mold member sealing the substrate and the power device; and at least one bushing member fixed to the mold member to provide a through hole for a bolt member for coupling a heat sink to the mold member. | 2008-08-28 |
20080203560 | Semiconductor device - A semiconductor device is produced using a housing having a hollow cavity for embracing a semiconductor sensor chip (e.g., a microphone chip) for detecting pressure variations and an LSI chip for driving the semiconductor sensor chip, both of which are mounted on a chip mount surface. An opening allowing the cavity to communicate with external space is formed at a prescribed position of the chip mount surface within the housing, wherein the LSI chip is positioned above the opening so as to cover at least a part of the opening of the housing. Thus, it is possible to reduce negative influences of environmental factors applied to the semiconductor sensor chip without using an environmental barrier, and it is possible to downsize the semiconductor device. | 2008-08-28 |
20080203561 | HIGH FREQUENCY DEVICE MODULE AND MANUFACTURING METHOD THEREOF - A high frequency device module of an embodiment of a current invention includes: an insulation substrate in which electrodes are provided on the front surface thereof and a grounding substrate is provided on the rear surface thereof; a high frequency device provided on the insulation substrate with a terminal of the device connected to the electrodes; potting material for covering the high frequency device; and a metallic layer provided on the potting material and connected to the grounding substrate. | 2008-08-28 |
20080203562 | Method for designing semiconductor device and semiconductor device - A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS. | 2008-08-28 |
20080203563 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A COF package in exemplary form includes a flexible base film, inner leads each made of metal and having a thickness d | 2008-08-28 |
20080203564 | Semiconductor device having stress alleviating portion positioned at outer circumference of chip, wiring substrate, and method for producing the same - A semiconductor device has a wiring substrate, a semiconductor chip, a conductive bump, and an under-fill resin. The wiring substrate has a solder resist layer, and a stress alleviating portion. The stress alleviating portion is mounted on the solder resist layer opposed to the outer circumference of the semiconductor chip. The material of the stress alleviating portion is different from that of the solder resist layer. The stress alleviating portion alleviates the stress acting on the solder resist layer and the under-fill resin. The semiconductor chip is mounted above the wiring substrate via the conductive bump. The gap between the wiring substrate and the semiconductor chip is filled with the under-fill resin. | 2008-08-28 |
20080203565 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device | 2008-08-28 |
20080203566 | Stress buffer layer for packaging process - A semiconductor package structure is provided. The semiconductor package structure includes a first module; a second module, wherein the first and the second modules each are selected from the group consisting essentially of a package substrate, a die and a package module; and an elastic die-attaching film having a hardness of less than about 150 MPa interposed between the first and the second modules. | 2008-08-28 |
20080203567 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor package includes a print substrate which has a plurality of wiring layers. The print substrate has a wiring for connect pins extending internally across the plurality of wiring layers from one surface of the print substrate; a wiring for a non connect pin insulated in the thickness direction of the plurality of wiring layers by a void formed to an intermediate wiring layer as one of the plurality of wiring layers; and a surge absorption wiring facing the wiring for the non connect pin across the void. The interval of the void between the wiring for the non connect pin and the surge absorption wiring is set smaller than the interval between a non connect pin to be disposed and a connect pin adjacent to the connect pin. | 2008-08-28 |
20080203568 | Semiconductor device - An improved reliability in a region of a junction between a bonding wire and an electrode pad at higher temperature is achieved. A semiconductor device | 2008-08-28 |
20080203569 | Semiconductor device and manufacturing method thereof - A semiconductor device comprising: a semiconductor substrate which has a plurality of connection pads on a top surface thereof; an insulating film which is provided on the semiconductor substrate and which has a plurality of openings formed at portions corresponding to the connection pads; a plurality of re-wirings each of which is provided to be connected to one of the connection pads via one of the openings of the insulating film; a re-wiring upper layer insulating film which is filled between the re-wirings on a top surface of the insulating film, and which is provided such that a top surface thereof is as high as or higher than a top surface of the re-wirings; and a plurality of columnar electrodes each of which is provided to be connected to a top surface-side connection pad section of each of the re-wirings. | 2008-08-28 |
20080203570 | STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD - Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface. | 2008-08-28 |
20080203571 | BACKSIDE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES - A method of forming backside metallization on a substrate that includes a plurality of integrated circuit die formed on a front side of the substrate is disclosed. The method includes forming an adhesion layer of aluminum or an aluminum alloy on a backside surface of the substrate, forming a barrier metal layer on the adhesion layer and forming a metal layer on the barrier metal layer. An integrated circuit device is also disclosed which includes a substrate having an integrated circuit die formed on a front side of the substrate, an adhesion layer on a backside surface of the substrate, wherein the adhesion layer is aluminum or an aluminum alloy, a barrier metal layer on the adhesion layer and a metal layer on the barrier metal layer. | 2008-08-28 |
20080203572 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer | 2008-08-28 |
20080203573 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate. | 2008-08-28 |
20080203574 | INSULATING FILM MATERIAL, MULTILAYER INTERCONNECTION STRUCTURE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection structure in which a parasitic capacitance between the interconnections can be reduced, efficient methods for manufacturing the multilayer interconnection structure, and an efficient method for manufacturing a semiconductor device with a high speed and reliability. The insulating film material contains at least a silicon compound having a steric structure represented by Structural Formula (1) below. | 2008-08-28 |
20080203575 | Integrated Circuit with Re-Route Layer and Stacked Die Assembly - An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die. | 2008-08-28 |
20080203576 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided. | 2008-08-28 |
20080203577 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads provided on the first and second buses. The contact pad has a probe testing region and a bonding region. | 2008-08-28 |
20080203578 | CIRCUIT DEVICE, A METHOD FOR MANUFACTURING A CIRCUIT DEVICE, AND A SEMICONDUCTOR MODULE - A circuit device includes a semiconductor substrate on which a circuit element is formed, an electrode formed on a surface of the semiconductor substrate, an insulating layer formed on the electrode, a second wiring layer formed on the insulating layer, and a conductive bump which penetrates the insulating layer and electrically connects the electrode and the second wiring layer. The conductive bump is such that the size of crystal grains in a direction parallel with the surface of the semiconductor substrate is larger than the size of crystal grains in a conduction direction of the electrode and the wiring layer. | 2008-08-28 |
20080203579 | SACRIFICIAL METAL SPACER DUAL DAMASCENE - A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs. | 2008-08-28 |
20080203580 | SEMICONDUCTOR CHIP AND SHIELDING STRUCTURE THEREOF - A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the guard ring comprises a plurality of individual segments, and the individual segments are individually and electrically coupled to the ground contacts. The circuit region disposed on the substrate. A projection of the dielectric ring on the substrate surface surrounds a projection of the circuit region on the substrate surface, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit region on the substrate surface. | 2008-08-28 |
20080203581 | INTEGRATED CIRCUIT - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal path being coupled to the first signal path, and a second substrate on the second interface layer. In one embodiment, the second substrate includes an electronic device, the electronic device being coupled to the second signal path of the second interface layer. | 2008-08-28 |
20080203582 | SEMICONDUCTOR DEVICE - A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced. | 2008-08-28 |
20080203583 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production. After the semiconductor chips are formed at wafer level, only the semiconductor chips having the excellent operation characteristic through the test are selectively bonded to the multilayer thin film structure, to provide the high quality package products in which the fault rate is maximally reduced. The light, thin, short and small BGA package according to the present invention enables small and slim communication devices, displayers and other diverse electronic devices, to be contributed to the increase of the competitiveness of the products to which the BGA package is applied. | 2008-08-28 |
20080203584 | Stacked-type semiconductor package - Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path. | 2008-08-28 |
20080203585 | INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. | 2008-08-28 |
20080203586 | Integrated Circuit and Methods of Manufacturing a Contact Arrangement and an Interconnection Arrangement - A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided. | 2008-08-28 |
20080203587 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process. | 2008-08-28 |
20080203588 | PACKAGED INTEGRATED CIRCUIT - A packaged integrated circuit has an integrated circuit over a support structure. A plurality of bond wires connected between active terminals of the integrated circuit and the support structure. An encapsulant overlies the support structure, the integrated circuit, and the bond wires. The encapsulant has a first open location in the encapsulant so that a first bond wire is exposed and a second open location in the encapsulant so that a second bond wire is exposed. First and second conductive structures are exposed outside the packaged integrated circuit and are located at the first and second open locations, respectively, and electrically connected to the first and second bond wires, respectively. | 2008-08-28 |
20080203589 | VARIABLE FILL AND CHEESE FOR MITIGATION OF BEOL TOPOGRAPHY - A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached. | 2008-08-28 |
20080203590 | INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE WITH OVERLAY KEY AND ALIGNMENT KEY AND METHOD OF FABRICATING THE SAME - An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench. | 2008-08-28 |
20080203591 | Flexible impeller pumps for mixing individual components - A flexible impeller pump includes first and second component housings. The first component housing includes a first flexible impeller and the second component housing includes a second flexible impeller. As these impellers rotate within their respective housings, they draw in and expel individual components into a common receiving chamber. In a particular application, one component is a foamable liquid, and the other component is air, and a mixture of foamable liquid and air is thus created in the common receiving chamber. | 2008-08-28 |
20080203592 | Method for imparting hydrogel contact lenses with desired properties - A cost-effective method for making hydrogel contact lenses with desired properties, such as antimicrobial property and/or increased surface hydrophilicity. The method comprises a step of contacting a dry or unhydrated hydrogel contact lens with an aqueous solution (or hydrating solution) containing silver nanoparticles and/or a lubricant or wetting agent. By using a method of the invention, resultant hydrogel contact lenses can have antimicrobial capability and/or enhanced lens wearer's comfort. | 2008-08-28 |
20080203593 | Polyvinyl Acetal-Containing Granulate, Method for the Production and the Utilization Thereof - The invention relates to a method for the production of a granulate containing at least one polyvinyl acetal, wherein a composition containing a polyvinyl acetal is transformed into molten state and granulated in accordance with the desired grain size. The invention also relates to a granulate produced according to said method and to the utilization of the inventive granulate. | 2008-08-28 |
20080203594 | METHOD FOR FABRICATING AERATION STONE - A method for fabricating an aeration stone is disclosed, which abandoned activated sludge, red soil and an alkaline metal oxide are separately dried firstly and then cracked, and next the cracked abandoned activated sludge, red soil and alkaline metal oxide are separately sieved to obtain smaller grains thereof, and then the grains are separately ground into fine particles thereof and are mixed to be a mixture. Next, the mixture is molded into a green aeration stone. Next, the green aeration stone is fired at a high temperature and then cooled down to obtain a finished aeration stone. Therefore, the present invention recycles the abandoned sludge of wastewater treatment works to reduce the secondary pollution of abandoned sludge. | 2008-08-28 |
20080203595 | SOLUTION CASTING METHOD - A dope is cast onto a drum whose surface is cooled, so as to form a casting film. After the peeling of the casting film, a cleaning gas containing dry ice particles is applied to a periphery of the casting drum with use of a drum cleaning unit. Thus the dry ice particles collide to the periphery of the casting drum, and the colliding energy is effective of removing from the periphery an organic material adhered on the casting drum. The organic material mainly contains aliphatic acid, aliphatic acid ester and metal salt of aliphatic acid. Before the increase of the amount of the organic material, it is removed and therefore isn't transmitted onto the surface of the casting film. Thus a high quality film having no optical unevenness is produced without the decrease of the productivity. | 2008-08-28 |
20080203596 | Molding Machine, Injection Apparatus, and Temperature Control Method for the Apparatus - An injection apparatus has a cylinder member having a feed opening ( | 2008-08-28 |
20080203597 | Method for Producing Expanding Styrene Polymer Granules - A method for supplying molten polymer and expanding agent flows to a mixing area, by dispersing the expanding agent in a polymer melt by a rapid dividing mixing in a first static mixer, holding and intensively dividingly mixing the thus obtained mixture in a second static mixer, cooling the mixture, during mixing, in a third static mixer to an intermediate temperature, cooling the mixture to a granulation temperature, extruding polymer threads and subsequently quenching and granulating them. During processing, a weight ratio between the polymer melt flow G | 2008-08-28 |
20080203598 | METHOD FOR PRODUCING FOAMED POLYMER MOLDED BODIES AND SAID FOAMED POLYMER MOLDED BODIES - Method for producing foamed microporous polymer molded bodies by melting a thermoplastic polymer in a first zone of an extrusion device, mixing in a highly volatile blowing agent, conveying the polymer melt containing the blowing agent into a second zone in which dissolution of the blowing agent occurs to saturation of the polymer melt at the foaming temperature, and molding and foaming of the loaded polymer melt to a foamed structure, whereby, in the second zone, a pressure above 90 bar, a blowing agent concentration above the critical minimum concentration for complete foaming, and the foaming temperature, lying above the solidification temperature of the polymer melt saturated with blowing agent, are set such that the polymer molded body obtained has a porosity in the range between 40 and 90 vol. % and an open-cell pore structure with uniform cross-sectional distribution. Foamed microporous polymer molded bodies in the form of particles comprising a thermoplastic polymer with uniform open-cell pore structure, a porosity of 40 to 90 vol. %, an accessible proportion of pore volume of at least 0.75 and an average cell size between 1 and 100 μm. | 2008-08-28 |
20080203599 | Molding Method of Polylactic Resin - In order to provide a molding method of polylactic resin by which a container or package having a transparent part can be fabricated with high heat resistance, polylactic resin is injected into a cavity, vibrations are added to the polylactic resin while a screw is kept at a charging completion position, and the process is switched to a pressure holding process after the addition of vibrations is completed. | 2008-08-28 |
20080203600 | Method and Device for Manufacturing Articles in the Form of Slabs of Conglomerate Stone or Stone-Like Material - During the manufacture of slabs of stone or stone-like material using the technology which envisages preparation of a mix formed by a granular product and by a binder consisting of a hardening synthetic resin, vacuum vibrocompression of a layer of said mix and hardening of the resultant rough slab by means of a catalytic action and by heating, the slab is cooled to room temperature by directing onto both its surfaces a flow of cooling fluid, in particular air at room temperature, while controlling the flowrate of the air, so as to ensure gradual and controlled cooling, and supporting the slab in a static and perfectly flat condition. The device consists of a flat structure provided with a plurality of spacers ( | 2008-08-28 |
20080203601 | Jig and method of manufacturing aircraft frames in a composite material - The present invention relates to a jig for the manufacture, by means of injection and curing processes, of preforms of composite material frames for aircraft fuselages by using the RTM (resin transfer molding) technology. Two preforms are thus manufactured, one with a C shaped section and another with a L shaped section, together with the preforms of the stabilization ribs for stabilizing the web of the frames and the preform of the roving or staple fiber to cover the gap between the C shaped preform and the L shaped preform. Theses preforms are previously manufactured by any known process for manufacturing preforms. According to a second aspect, the present invention relates to a method of manufacturing composite material load frames for aircraft. | 2008-08-28 |
20080203602 | Method for Producing Duroplastic Fine-Fiber Non-Wovens Having a High Flame-Retardant, Thermal Protective and Sound Insulating Effect - The invention relates to a method for producing duroplastic fine-fiber non-wovens, characterized in that: a) melts of reactive three-dimensionally cross-linkable, non-linear prepolymers are extruded by nozzles; b) the exiting melts are blown by means of hot air to form fine fibers; c) the fine fibers are separated by the flow of air and deposited to form a non-woven comprised of a fine-fiber weave; d) the non-woven is subsequently compacted, and; e) the non-woven is treated with a medium that initiates a three-dimensional cross-linking, and the fine fibers in the non-woven are inherently bonded and/or hardened in a subsequent thermal post-hardening. This enables duroplastic fine-fiber non-wovens to be economically produced that have both a high flame retardant effect as well as a high thermal protection, sound insulation and filtering capacity. | 2008-08-28 |
20080203603 | METHOD OF FORMING COMPOSITE ARTICLES - A method for forming a composite article includes injecting first and second compositions into a die head at different points so as to produce a partially mixed composition that is discharged from the die head. The second composition contains less filler material than the first composition. | 2008-08-28 |
20080203604 | Wood and Non-Wood Fibers Hybrid Composition and Uses Thereof - The present invention relates to a composition comprising a mixture of wood particles and non-wood plant particles for the manufacture composite boards or the like. The present invention also relates to methods of preparing composite boards. As described herein, the composition allows the production of panels, boards or logs that can be used in the construction of buildings, houses and furniture. | 2008-08-28 |
20080203605 | Method of Making Three Dimensional Structures Using Electronic Drawing Data - A method of modeling a three dimensional object defined by electronic data includes obtaining electronic data defining a first finished surface of the three dimensional object. A block of expanded polypropylene foam is shaped based on the electronic data. At least one surface of the expanded polypropylene foam block is offset from the first finished surface of the three dimensional object. A layer of hardenable paste is applied to the offset surface of the block of expanded polypropylene foam. The paste is hardened. The paste is machined to form the first finished surface of the three dimensional object. | 2008-08-28 |
20080203606 | BIODEGRADABLE COMPOSITION FOR THE PREPARATION OF TABLEWARE, DRINK CONTAINER, MULCHING FILM AND PACKAGE AND METHOD FOR PREPARING THE SAME - The present invention relates to a biodegradable composition for the preparation of table-ware, mulching film and package, which comprises: 2-6% by weight of starch; 35-45% by weight of plant powders; 20-30% by weight of calcium carbonate; 2-7% by weight of sorbitol; 7-13% by weight of polypropylene; 2-5% by weight of polyethylene; 2-6% by weight of coupling agent; 1-2% by weight of defoamer; 2-5% by weight of stearic acid; 2-6% by weight of stearate; 3-6% by weight of glycerine or epoxidized soybean oil; and 60-100 ppm photosensitizer. The present invention also relates to a method for preparing the composition, which comprises: treating a plant waste with a diluent acid, drying and pulverizing, then mixing it with starch, polypropylene, and polyethylene, sorbitol, defoamer, coupling agent, stearic acid, stearate, glycerine and photosensitizer homogeneously; and blending the mixture obtained in a double-screw extruder at a temperature of 160-180° C. to obtain the composition of the present invention. | 2008-08-28 |
20080203607 | Pipe Extrusion Die Flow Path Apparatus and Method - A method and apparatus is provided for distributing material through a multilayer pipe extrusion die. A first flow passageway, having a first cross-sectional area and extending along a first flow direction, may be connected to a second flow passageway, having a second cross-sectional area substantially the same as the first cross-sectional area of the first flow passageway, to provide a second flow direction different from the first flow direction of the first flow passageway. A conical passageway may extend from the second passageway toward a dispensing outlet. Material may be distributed from the first flow passageway into the second flow passageway. The method and apparatus may generally maintain the same flow properties of the material at a point before and after the connection of the first flow passageway and the second flow passageway. The flow properties of the material may be altered proximate to the outlet. | 2008-08-28 |
20080203608 | Defined Ratio Dual-Wall Pipe Die - A pipe extrusion die may be provided having an inner flow passageway having a first cross-sectional area, and an outer flow passageway having a second cross-sectional area, both being in communication with an inlet flow passageway. A ratio adjusting tube may be movably disposed in blocking engagement between the inlet flow passageway and the inner flow passageway. The ratio adjusting tube and the outer flow passageway both may be substantially concentric with the inner flow passageway. Material may be distributed from the inlet flow passageway to the inner and outer flow passageways. The method and apparatus may allow for the manual and automatic control of the proportion of material distributed between the inner and outer flow passageways by adjusting the position of the ratio adjusting tube in relation to a passageway between the inlet flow passageway and the inner flow passageway, based on various operating parameters. | 2008-08-28 |
20080203609 | Processes For Hydrolysis Of Polyphoshoric Acid In Polyareneazole Filaments - The present invention relates to processes for hydrolyzing polyphosphoric acid in polyareneazole filaments. | 2008-08-28 |
20080203610 | Hot Surface Hydrolysis of Polyphosphoric Acid in Spun Yarns - The present invention relates to processes for hydrolyzing polyphosphoric acid in spun multifilament yarns. | 2008-08-28 |
20080203611 | WIRE COOLING WATER TROUGH - The present invention generally relates to a cooling process and system that can be utilized in the manufacture of flexible elongate extruded materials, such as tubing or jacketed electrical wire and cable. More particularly, the present invention relates to a cooling trough for cooling flexible elongate extruded materials after extrusion. Cooling trough embodiments have a base, a wet cooling chamber above the base, and an air dry chamber above the wet cooling chamber. The base contains a reservoir for collecting and storing a cooling liquid. An extruded material, such as a cable, enters the wet cooling chamber, where the cooling liquid from the reservoir is sprayed onto the material, the material is then passed to the air dry chamber where it is dried. | 2008-08-28 |
20080203612 | MOULD LINING - Powder metallurgy techniques are utilised to form components and in particular titanium components in moulds. By the nature of the powder forming process, closed surfaces are created in the powder formed component, particularly when hot iso-static pressing techniques are utilised. In order to create surface texturing, and in particular entrant features, a mould lining is associated such that it reciprocates the shape of an underlying mould. The mould lining incorporates surface discontinuities such as holes, slots, spots or folds which result, once the moulded material is formed, in entrant features which can be utilised to enhance bonding through adhesives or other surface features beneficial to a component. | 2008-08-28 |
20080203613 | Apparatus and Method For Making Product Having Various Shapes - The present invention relates to an apparatus and a method for making products having various shapes. The apparatus is for making a product by shaping or processing work piece using a relative movement between the work piece and a tool. The apparatus is provided with a work piece support on which the work piece is located, a revolution-rotation driving device including a first axis and a second axis in parallel with the first axis and revolving around the first axis, the device revolving the work piece support around the first axis and rotating the work piece support on the second axis; and a tool support for supporting the tool in such a manner that the tool is maintained in a predetermined position with respect to the first axis. The revolution-rotation driving device further includes a revolution-radius adjustment for adjusting so a distance between the first axis and the second axis. Further, the revolution-rotation driving device maintains a direction of the revolution of the work piece support and a direction of the rotation of the work piece support in a same direction and allows a ratio of the number of revolution of the work piece support to the number of rotation of the work piece support to be maintained in a constant ratio of n (natural number):1. | 2008-08-28 |
20080203614 | Method for Making Filter Element - A filter includes a filter element formed of filter media, and a plastic framework molded and bonded to and structurally supporting the filter media. One embodiment desirably provides a two-component assembly consisting solely of two components, namely the filter media and the plastic framework molded thereon. In a further embodiment, the plastic framework includes a resilient seal integrally molded therewith and of the same plastic material thereof, eliminating a separate component for the seal. In a further embodiment, a filter combination includes a primary filter element and a secondary filter element. In a further embodiment, a resilient integrally molded seal is provided. | 2008-08-28 |
20080203615 | MOLD FOR FORMING GOLF BALL COVERS - The present invention is an improved single cavity molding device and method for compression molding polyurethane, polyurea or polyurethane/polyurea hybrid covers over golf ball sub-assemblies. The device utilizes top and bottom mold-halves and is particularly novel in that it does not require the use of bolts to secure the mold-halves. The molding device utilizes a pair mold halves, each having a backing plate and mold frame for housing a hemispherical cavity mold. The invention utilizes a plurality of clamping pins, each pin having its top portion reciprocally disposed in a recess of the backing plate of the top mold. Double spring Belleville washers are coupled to the top portion of each clamping pin and upon the application of a vertical force, the washers are compressed to place the device in a controlled state of tension and also cause the clamping pins, to move downward into a locking position with slidable retainers to therein maintain a compressive force of at least 384 pounds on the golf ball sub-assembly for the molding process. Upon completion of the molding process, a vertical force is applied to the top of the clamping pins wherein they are moved out of a coupled relationship with the engagement loops, and with a coordinating horizontal biasing, the retainers are moved away from the pins, whereby the mold-halves may be then opened and a covered golf ball removed. | 2008-08-28 |