35th week of 2015 patent applcation highlights part 60 |
Patent application number | Title | Published |
20150243699 | IMAGING SYSTEMS WITH THROUGH-OXIDE VIA CONNECTIONS - An imaging system may include an image sensor package with through-oxide via connections between the image sensor die and the digital signal processing die in the image sensor package. The image sensor die and the digital signal processing die may be attached to each other. The through-oxide via may connect a bond pad on the image sensor die with metal routing paths in the image sensor and digital signal processing dies. The through-oxide via may simultaneously couple the image sensor die to the digital signal processing die. The through-oxide via may be formed through a shallow trench isolation structure in the image sensor die. The through-oxide via may be formed through selective etching of the image sensor and digital signal processing dies. | 2015-08-27 |
20150243700 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a photodiode. The photodiode is embedded in a pixel region, and has a P-type region formed along a first trench at a side of a second surface. An impurity concentration of the P-type impurities along the first trench is different between at the side of the second surface and at a side of a first surface, and an impurity concentration of the P-type region is higher at the side of the second surface than at the side of the first surface. | 2015-08-27 |
20150243701 | CMOS IMAGE SENSORS HAVING A TRANSFER GATE ELECTRODE, AND METHODS OF FABRICATING CMOS IMAGE SENSORS HAVING A TRANSFER GATE ELECTRODE - Complementary metal-oxide-semiconductor (CMOS) image sensors are provided. A CMOS image sensor includes a substrate including a pixel array and a peripheral circuit region, a photodiode and a floating diffusion region in the pixel array of the substrate, a transfer gate insulating layer and a transfer gate electrode on the substrate between the photodiode and the floating diffusion region, and a peripheral gate insulating layer and a peripheral gate electrode on the peripheral circuit region. The transfer gate electrode includes a first edge that is rounded to have a first radius of curvature, and the peripheral gate electrode includes a second edge that is rounded to have a second radius of curvature smaller than the first radius of curvature. | 2015-08-27 |
20150243702 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE - Provided are a semiconductor device capable of detecting a light of each color with high accuracy without using a color filter, particularly enhancing detection accuracy of charges obtained by photoelectric conversion of a long-wavelength light, and manufacturing and control methods thereof. The semiconductor device has a p type semiconductor substrate, and first, second and third pixel regions. These regions each include a p type well region in the p type semiconductor substrate and an n type region configuring a pn junction therewith. The p type well region of the first pixel region is thinner, from the main surface to the lowermost portion, than that of the second and third pixel regions. On the side opposite to the main surface of the p type well region of the first and second pixel regions, a buried p type well region contiguous to the p type well region is further placed. | 2015-08-27 |
20150243703 | METHODS OF FABRICATING CAMERA MODULE AND SPACER OF A LENS STRUCTURE IN THE CAMERA MODULE - A camera module and a fabrication method thereof are provided. The camera module includes a lens structure and an image sensor device chip disposed under the lens structure. The lens structure includes a transparent substrate and a lens disposed on the transparent substrate. A spacer is disposed on the transparent substrate to surround the lens, wherein the spacer contains a base pattern and a dry film photoresist. The method includes forming a base pattern on a carrier and attaching a dry film photoresist on the carrier. The dry film photoresist is planarized by a lamination process and then patterned to form a spacer. A transparent substrate having a plurality of lenses is provided. The spacer is stripped from the carrier, attaching on the transparent substrate to surround each of the lenses, and then bonded with image sensor device chips. | 2015-08-27 |
20150243704 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a substrate, a first electrode on the substrate, a pixel defining layer on the substrate, the pixel defining layer having an opening exposing the first electrode, a metal layer on the pixel defining layer, a light emission layer on the first electrode exposed by the opening, and a second electrode on the light emission layer in the opening. The metal layer contacts the second electrode. | 2015-08-27 |
20150243705 | DISPLAY DEVICES AND METHODS OF MANUFACTURING DISPLAY DEVICES - A display device includes a substrate with a major surface and a cover opposing the substrate. An array of light emitting pixels is disposed over a generally central portion of the major surface, and interposed between the substrate and the cover. A seal is disposed over a peripheral portion of the substrate, and interposed between and interconnecting the substrate and the cover. Between the seal and the substrate, a lower insulation layer, an upper insulation layer, and a structure located between the lower and upper insulation layers and including at least one metal layer. The upper insulation layer includes an uneven top surface. A contour of the uneven top surface of the upper insulation layer may conform with or follow that of the top uneven surface of the structure. The seal contacts and is bonded to the uneven top surface of the upper insulation. | 2015-08-27 |
20150243706 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - An exemplary light emitting diode includes a substrate; a first light emitting cell and a second light emitting cell disposed over the substrate and separated from each other; and an interconnection electrically connecting the first light emitting cell to the second light emitting cell. Each of the first and second light emitting cells includes a first conductive-type semiconductor layer, a second conductive-type semiconductor layer disposed over the first conductive-type semiconductor layer, and an active layer disposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer. At least one of the first light emitting cell and the second light emitting cell includes a side surface inclined with respect to the substrate. The side surface includes a first inclined portion forming an acute angle with respect to the substrate, a second inclined portion forming an obtuse angle with respect to the substrate, and an inclination discontinuity section. | 2015-08-27 |
20150243707 | TUNNELING TRANSISTOR HAVING A VERTICAL CHANNEL, VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SAME - A tunneling transistor including a semiconductor substrate on which a source is formed in an upper region and having a first semiconductor material layer, a pillar formed on the semiconductor substrate and having a structure in which a channel layer and a drain are sequentially stacked, a gate formed to surround a circumference of the pillar, and a second semiconductor material layer constituting a portion of the source, formed between the source and the channel layer, having the same conductivity type as the source, and having a band gap smaller than the first semiconductor material layer. Wherein, the source and the drain have opposite conductivity types. | 2015-08-27 |
20150243708 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials. | 2015-08-27 |
20150243709 | SEMICONDUCTOR STRUCTURES INCLUDING LINERS COMPRISING ALUCONE AND RELATED METHODS - A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed. | 2015-08-27 |
20150243710 | Organic Optoelectronic Component and Method for Operating the Organic Optoelectronic Component - An organic optoelectronic component and a method for operating the organic optoelectronic component are disclosed. In an embodiment the organic optoelectronic component includes at least one organic light emitting element including an organic functional layer stack having at least one organic light emitting layer between two electrodes and at least one organic light detecting element including at least one organic light detecting layer, wherein the at least one organic light detecting element and the at least one organic light emitting element are laterally arranged on a common substrate. | 2015-08-27 |
20150243711 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display (OLED) device that includes a first substrate and a second substrate. An organic light emitting element and a sealing member are formed between the first substrate and the second substrate. A touch panel, a block pattern, and a protective layer are formed on the second substrate. The block pattern is arranged above the sealing member to prevent a center of the sealing member from being excessively illuminated by a laser beam during a curing process. | 2015-08-27 |
20150243712 | ORGANIC LIGHT EMITTING DISPLAY - An organic light emitting display including a first substrate and a second substrate is described. The first substrate has a pixel divided into a light emitting area and a non-light emitting area. The first substrate has an organic light emitting diode disposed in the light emitting area. The second substrate has an infrared sensor disposed corresponding to the non-light emitting area. In the organic light emitting display, the organic light emitting diode emits visible light and infrared light, and the infrared sensor is disposed corresponding to the non-light emitting area. | 2015-08-27 |
20150243713 | METHOD FOR MANUFACTURING ORGANIC EL DISPLAY AND ORGANIC EL DISPLAY - A method for manufacturing an organic electroluminescence display including multilayer structures that are each formed in a respective one of pixel areas in an effective area of a substrate and are each formed by a lower electrode, an organic layer, and an upper electrode, the organic electroluminescence display having a common electrode that electrically connects the pixel areas, the method including the steps of: forming a protective electrode and an outer-peripheral electrode that are electrically connected to the common electrode; forming the multilayer structures; and carrying out film deposition treatment involving electrification of the substrate. | 2015-08-27 |
20150243714 | ORGANIC ELECTROLUMINESCENCE DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - An organic electroluminescence device includes a substrate, an organic electroluminescence element provided at a pixel region of the substrate, a connection terminal provided at a terminal region of the substrate, and a temperature sensor provided above the substrate, in which the temperature sensor is provided between the pixel region and the terminal region. | 2015-08-27 |
20150243715 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes: a display panel including data lines, scan lines, a first power voltage line supplying a first power voltage, and pixels, a pixel of the pixels including: a driving transistor configured to control a drain-to-source current flowing from a first electrode of the driving transistor to a second electrode of the driving transistor according to a voltage at a gate electrode of the driving transistor; an organic light emitting diode (OLED) configured to emit light in accordance with the drain-to-source current; and a first transistor having a gate electrode coupled to a scan line of the scan lines, a first electrode coupled to the second electrode of the driving transistor, and a second electrode coupled to the gate electrode of the driving transistor, the first power voltage line being between the second electrode of the first transistor and an anode of the OLED. | 2015-08-27 |
20150243716 | ORGANIC LIGHT EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display includes a substrate, a first electrode, an organic emission layer, a second electrode, an insulating layer, and an auxiliary electrode. The substrate has at least one thin film transistor formed thereon. The first electrode is electrically coupled (e.g., electrically connected) to the thin film transistor on the substrate. The organic emission layer is formed on the first electrode. The second electrode is formed on the organic emission layer. The insulating layer is formed on the second electrode. The auxiliary electrode is formed on the insulating layer to be electrically coupled to the second electrode. | 2015-08-27 |
20150243717 | LIGHT-EMITTING DEVICE - There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is μ, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs | 2015-08-27 |
20150243718 | DISPLAY BACKPLANE HAVING MULTIPLE TYPES OF THIN-FILM-TRANSISTORS - There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor). | 2015-08-27 |
20150243719 | DISPLAY BACKPLANE HAVING MULTIPLE TYPES OF THIN-FILM-TRANSISTORS - There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor). | 2015-08-27 |
20150243720 | DISPLAY BACKPLANE HAVING MULTIPLE TYPES OF THIN-FILM-TRANSISTORS - There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor). | 2015-08-27 |
20150243721 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - A pixel includes a driving transistor to control an amount of drain-to-source current flowing from a first electrode to a second electrode based on a voltage applied to a first gate electrode. The current is used to control light emitted from an organic light emitting diode. The pixel also includes a first transistor coupled between the first gate electrode and second electrode of the driving transistor. The first gate electrode is under an active layer of the driving transistor, and the first gate electrode overlaps the active layer of the driving transistor. | 2015-08-27 |
20150243722 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Disclosed herein is an OLED (Organic Light Emitting Display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (Low Temperature Poly-Silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line. A pixel and another pixel adjacent to the pixel connected to a gate line in common, so that it is possible to provide an OLED device with high aperture ratio and high resolution. | 2015-08-27 |
20150243723 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor (TFT) substrate and a display using the same. A TFT substrate includes: a substrate, a first TFT on the substrate, including: a polycrystalline semiconductor layer, a first gate electrode thereover, a first source electrode, and a first drain electrode, a second TFT on the substrate, including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer, on the first gate electrode, and an oxide layer covering the second gate electrode, on the intermediate insulating layer, on the oxide layer, and overlapping the second gate electrode, wherein the first source, first drain, and second gate electrodes are between the intermediate insulating layer and the oxide layer, and wherein the second source and the second drain electrodes are on the oxide semiconductor layer. | 2015-08-27 |
20150243724 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor (TFT) substrate and a display using the same. A display includes: a first TFT, including: a polycrystalline semiconductor layer, a first gate electrode thereover, a first source electrode, and a first drain electrode, a second TFT, including: a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer, on the first gate electrode, and an oxide layer covering the second gate electrode, on the intermediate insulating layer, on the oxide layer, and overlapping the second gate electrode, wherein the first source, first drain, and second gate electrodes are between the intermediate insulating layer and the oxide layer, and wherein the second source and the second drain electrodes are on the oxide semiconductor layer. | 2015-08-27 |
20150243725 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS, METHOD OF MANUFACTURING THE SAME, AND MASK USED IN THE METHOD - A method of manufacturing an organic light emitting display apparatus is provided. A plurality of first electrodes is formed on a substrate. An intermediate layer including an emission layer is formed on the plurality of first electrodes. A deposition mold including a plurality of auxiliary patterning lines is formed by performing a deposition process twice using a mask. The mask includes a plurality of aperture sets, each of the plurality of aperture sets corresponding to part of each of the plurality of auxiliary patterning lines. A plurality of second electrodes is formed on the intermediate layer by depositing a conductive material into the deposition mold. | 2015-08-27 |
20150243726 | CIRCUIT FOR PREVENTING STATIC ELECTRICITY AND DISPLAY DEVICE HAVING THE SAME - A static electricity prevention circuit of a display device including: a driving circuit configured to drive a display unit that displays an image, at least one clock signal wire configured to transmit a clock signal to the driving circuit, at least one transistor electrically coupled to the clock signal wire, and at least one capacitor including a first electrode coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage. | 2015-08-27 |
20150243727 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers. | 2015-08-27 |
20150243728 | METAL-INSULATION-METAL DEVICE - A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. | 2015-08-27 |
20150243729 | MEMS FIXED CAPACITOR COMPRISING A GAS-CONTAINING GAP AND PROCESS FOR MANUFACTURING SAID CAPACITOR - The MEMS fixed capacitor includes a bottom metal electrode formed onto a substrate, a top metal electrode supported by metal pillars above the bottom metal electrode, and a gas-containing gap forming a non-solid dielectric layer between said top and bottom metal electrodes; the distance between the top and bottom metal electrodes is not more than 1 μm and the thickness of the top metal electrode is not less than 1 μm. | 2015-08-27 |
20150243730 | MULTI-STEP METHOD OF FORMING A METAL FILM - The present disclosure relates to an integrated chip having a titanium nitride film that provides for a reduced leakage path, and an associated method of formation. In some embodiments, the integrated chip comprises a semiconductor substrate. A titanium nitride film is disposed over the semiconductor substrate. The titanium nitride film comprises a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride. The grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film. The discontinuity of the grain boundaries between the different titanium nitride layers reduces leakage paths through the titanium nitride film (e.g., and thereby can improve operation of a MIM capacitor having titanium nitride electrodes). | 2015-08-27 |
20150243731 | SEMICONDUCTOR DEVICE - An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion. | 2015-08-27 |
20150243732 | NOVEL INTEGRATION PROCESS TO FORM MICROELECTRONIC OR MICROMECHANICAL STRUCTURES - The invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance. | 2015-08-27 |
20150243733 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE NANOWIRE TRANSISTOR - A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode. | 2015-08-27 |
20150243734 | Methods of Forming Transistors - Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate. | 2015-08-27 |
20150243735 | SEMICONDUCTOR DEVICE - A gate interconnection portion (GHB) includes a first gate interconnection portion (GHB | 2015-08-27 |
20150243736 | HIGH VOLTAGE GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A high voltage gallium nitride based semiconductor device includes an n-type gallium nitride freestanding substrate, and an n-type gallium nitride based semiconductor layer including a drift layer formed on the surface of the n-type gallium nitride freestanding substrate so as to have a reverse breakdown voltage of not less than 3000 V. The drift layer is configured such that a carbon concentration is not less than 3.0×10 | 2015-08-27 |
20150243737 | ELECTRONIC DEVICE WITH A REVERSE BIASED HEMT TRANSISTOR - An electronic device including at least: | 2015-08-27 |
20150243738 | SEMICONDUCTOR FILM, TRANSISTOR, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE - Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed. | 2015-08-27 |
20150243739 | Doping for FinFET - First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin. | 2015-08-27 |
20150243740 | BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE MITIGATION IN SOI DEVICES - A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors. | 2015-08-27 |
20150243741 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device according to the invention includes an epitaxial layer of a first conductivity type, a first well of a second conductivity type to which a first potential is applied, a second well of the second conductivity type to which a second potential that differs from the first potential is applied, a third well of the first conductivity type provided in the epitaxial layer between the first well and the second well, a first impurity region of the first conductivity type provided in the epitaxial layer under the first well, a first MOS transistor provided in the first well, a second MOS transistor provided in the second well, and a third MOS transistor provided in the third well, the first impurity region having a higher impurity concentration than the epitaxial layer. | 2015-08-27 |
20150243742 | METHOD TO FORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION - A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate. | 2015-08-27 |
20150243743 | SEMICONDUCTOR COMPONENT COMPRISING AT LEAST ONE CONTACT STRUCTURE FOR FEEDING IN AND/OR LEADING AWAY CHARGE CARRIERS - A semiconductor component having at least one first contact structure for feeding in and/or leading away charge carriers in relation to the semiconductor component, which first contact structure has at least one contact-making point for electrically conductively connecting the first contact structure to an external terminal, and which first contact structure has at least one first-order branching point proceeding from the contact-making point, at which first-order branching point at least one first-order subsequent conduction track branches off. Each first-order subsequent conduction track has at least one second-order branching point, at which second-order branching point at least one second-order subsequent conduction track branches off, and the electrical through-conduction resistance of each second-order subsequent conduction track is higher than the electrical through-conduction resistance of the first-order subsequent conduction track connected to said second-order subsequent conduction track via a common second-order branching point. | 2015-08-27 |
20150243744 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode. The first electrode and the edge of the gate electrode facing the first electrode are regular polygons, and have the same center. | 2015-08-27 |
20150243745 | FINFET DEVICE WITH EPITAXIAL STRUCTURE - A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure. | 2015-08-27 |
20150243746 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure. | 2015-08-27 |
20150243747 | INTEGRATED CIRCUIT DEVICES INCLUDING CONTACTS AND METHODS OF FORMING THE SAME - Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion. | 2015-08-27 |
20150243748 | VERTICAL ACCESS DEVICES, SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED METHODS - A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described. | 2015-08-27 |
20150243749 | SEMICONDUCTOR DEVICE AND PRODUCTION DEVICE THEREFOR - A semiconductor device includes a plurality of trench gates extending in a first direction and arranged with a space between one another in a second direction which is orthogonal to the first direction. Each of the plurality of trench gates includes: a first portion opened on a front surface of the semiconductor substrate; a second portion extending from the first portion in a direction inclined relative to a depth direction of the semiconductor substrate toward a positive direction of the second direction; and a third portion extending from the first portion in a direction inclined relative to the depth direction of the semiconductor substrate toward a negative direction of the second direction. | 2015-08-27 |
20150243750 | III-V COMPOUND SEMICONDUCTOR DEVICE HAVING METAL CONTACTS AND METHOD OF MAKING THE SAME - A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound. | 2015-08-27 |
20150243751 | Contact Etch Stop Layers of a Field Effect Transistor - The disclosure relates to a field effect transistor. An exemplary structure for a field effect transistor comprises a substrate; a source region and a drain region disposed in the substrate; a gate structure over the substrate comprising sidewalls and a top surface, wherein the gate structure interposes the source region and the drain region; a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; an interlayer dielectric layer over the CESL; a gate contact extending through the interlayer dielectric layer; and a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm. | 2015-08-27 |
20150243752 | Reacted Conductive Gate Electrodes and Methods of Making the Same - A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material. | 2015-08-27 |
20150243753 | SEMICONDUCTOR DEVICE - A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n | 2015-08-27 |
20150243754 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal. | 2015-08-27 |
20150243755 | DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE - A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain. | 2015-08-27 |
20150243756 | INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME - Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include In | 2015-08-27 |
20150243757 | BI-DIRECTIONAL ESD DIODE STRUCTURE WITH ULTRA-LOW CAPACITANCE THAT CONSUMES A SMALL AMOUNT OF SILICON REAL ESTATE - A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer. | 2015-08-27 |
20150243758 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL TRANSISTOR - A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate. | 2015-08-27 |
20150243759 | COUNTER POCKET IMPLANT TO IMPROVE ANALOG GAIN - A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region. | 2015-08-27 |
20150243760 | LOW-K SPACER FOR RMG FINFET FORMATION - A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess. | 2015-08-27 |
20150243761 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. | 2015-08-27 |
20150243762 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. | 2015-08-27 |
20150243763 | PERFORMANCE BOOST BY SILICON EPITAXY - The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance. | 2015-08-27 |
20150243764 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - The present invention discloses a method for manufacturing a semiconductor structure, which comprises the following steps: a) providing an SOI substrate, a shallow trench is formed on the SOI substrate, with the defined area of the shallow trench corresponding to the active region; b) forming the heavily doped layer on the shallow trench sidewall close to the active region; c) filling the shallow trench to form the shallow trench isolation structure; d) forming the semiconductor device in the active region. In the present disclosure, PN junctions are formed in the source electrode and the body region of the SOI, to provide a discharge channel for the charge accumulated in the body region, to reduce the impact of the floating body effect, and to improve the reliability of the device. | 2015-08-27 |
20150243765 | SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES - Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s). | 2015-08-27 |
20150243766 | METHOD AND APPARATUS FOR POWER DEVICE WITH MULTIPLE DOPED REGIONS - A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type. | 2015-08-27 |
20150243767 | SEMICONDUCTOR DEVICE INCLUDING FINFET AND DIODE HAVING REDUCED DEFECTS IN DEPLETION REGION - A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region. | 2015-08-27 |
20150243768 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment and the oxygen doping treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress test (BT test) can be reduced. | 2015-08-27 |
20150243769 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor layer. A gate dielectric film is provided on the semiconductor layer. A gate electrode is provided above the semiconductor layer via the gate dielectric film. A first conductivity-type drain layer is provided in the semiconductor layer on a one-end side of the gate electrode. A second conductivity-type source layer is provided in the semiconductor layer on an other-end side of the gate electrode and below at least a part of the gate electrode. A source extension layer faces at least a part of a bottom surface of the gate electrode via the gate dielectric film and has an impurity concentration lower than that of the source layer. A first conductivity-type pocket layer is provided in the semiconductor layer between the source extension layer and the drain layer. The pocket layer contacts the source extension layer and is separated from the drain layer. | 2015-08-27 |
20150243770 | VERTICAL BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process. | 2015-08-27 |
20150243771 | SEMICONDUCTOR DEVICE - A semiconductor device according to embodiments includes a semiconductor substrate, first semiconductor layers of a first conductive type provided on a surface of the semiconductor substrate, extend in a first direction, and are surrounded by a gate layer, second semiconductor layers of the first conductive type provided between the first semiconductor layers, a third semiconductor layer of the first conductive type provided at ends of the first direction of the first semiconductor layers and is surrounded by the gate layer, a fourth semiconductor layer of a second conductive type provided in the semiconductor substrate, a sixth semiconductor layer of the first conductive type provided on a back surface of the semiconductor substrate, a seventh semiconductor layer of the second conductive type provided between the sixth semiconductor layer and the first semiconductor layers, an emitter electrode, and a collector electrode. | 2015-08-27 |
20150243772 | SEMICONDUCTOR DEVICE - An insulated gate bipolar transistor having a gate electrode ( | 2015-08-27 |
20150243773 | III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS - A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer. | 2015-08-27 |
20150243774 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor multi-layer structure which includes at least an electron traveling layer and an electron supply layer on a substrate, wherein the electron supply layer includes a first portion which contains Sb and has at least a portion doped with Te, and a second portion which is located closer to the electron traveling layer side than the first portion and has a lattice constant smaller than that of the first portion. | 2015-08-27 |
20150243775 | NITRIDE SEMICONDUCTOR DEVICE - A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer. | 2015-08-27 |
20150243776 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND FIELD DRIFT METAL OXIDE SEMICONDUCTOR - A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided. | 2015-08-27 |
20150243777 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film. | 2015-08-27 |
20150243778 | SEMICONDUCTOR DEVICE - A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region. | 2015-08-27 |
20150243779 | TRANSISTOR STRUCTURE WITH FEED-THROUGH SOURCE-TO-SUBSTRATE CONTACT - An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer. | 2015-08-27 |
20150243780 | METHOD AND APPARATUS FOR POWER DEVICE WITH DEPLETION STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region. | 2015-08-27 |
20150243781 | RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall. | 2015-08-27 |
20150243782 | Transistor-Containing Constructions and Memory Arrays - Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays. | 2015-08-27 |
20150243783 | METHOD AND APPARATUS FOR MOS DEVICE WITH DOPED REGION - A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate. | 2015-08-27 |
20150243784 | METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE - Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer. | 2015-08-27 |
20150243785 | SEMICONDUCTOR ARRANGEMENT WITH STRESS CONTROL AND METHOD OF MAKING - One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack. | 2015-08-27 |
20150243786 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a first conductivity-type first source layer provided in a semiconductor layer. A second conductivity-type drain layer is provided in the semiconductor layer. A gate dielectric film is provided on the semiconductor layer between the first source layer and the drain layer. A first gate structure is provided on the gate dielectric film. A drain-side adjacent structure is adjacent to the first gate structure on a side of the drain layer of the first gate structure. A stress layer covers at least the first gate structure, the drain-side adjacent structure, and the first source layer. The stress layer has strain. A first gap between the first gate structure and the drain-side adjacent structure is narrower than four times a film thickness of the stress layer. The stress layer covers the first source layer along a channel-direction longer than the first gap. | 2015-08-27 |
20150243787 | METHOD FOR A UNIFORM COMPRESSIVE STRAIN LAYER AND DEVICE THEREOF - A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess. | 2015-08-27 |
20150243788 | Methods for Forming Semiconductor Device Structures - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 2015-08-27 |
20150243789 | SEMICONDUCTOR DEVICE WITH FIELD-INDUCING STRUCTURE - The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric. | 2015-08-27 |
20150243790 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - This TFT substrate ( | 2015-08-27 |
20150243791 | CIRCUIT BOARD AND DISPLAY DEVICE - The present invention provides a circuit substrate exhibiting an excellent transmittance and being capable of suitably repair broken conductive lines; and a display device. In the circuit substrate of the present invention, the first conductive lines are arranged in spaces between electrode rows, with two of the first conductive lines per space between the rows, the second conductive lines are arranged in spaces between electrode columns, with one of the second conductive lines in every other space between the columns, the storage capacitor lines including linear portions that extend in the direction in which the second conductive lines extend, in spaces between the electrode columns where the second conductive lines are not arranged, the pattern film including, in a plan view of main surface of the substrate, first linear portions extending in the direction in which the second conductive lines extend, in the spaces between the electrode rows, the first linear portions each including two end portions each overlapping an end portion of a linear portion of one of the storage capacity lines. | 2015-08-27 |
20150243792 | SEMICONDUCTOR DEVICE - To suppress a decrease in on-state current in a semiconductor device including an oxide semiconductor. A semiconductor device includes an insulating film containing silicon, an oxide semiconductor film over the insulating film, a gate insulating film containing silicon over the oxide semiconductor film, a gate electrode which is over the gate insulating film and overlaps with at least the oxide semiconductor film, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In the semiconductor device, the oxide semiconductor film which overlaps with at least the gate electrode includes a region in which a concentration of silicon distributed from an interface with the insulating film is lower than or equal to 1.1 at. %. In addition, a concentration of silicon contained in a remaining portion of the oxide semiconductor film except the region is lower than the concentration of silicon contained in the region. | 2015-08-27 |
20150243793 | THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, an oxide buffer layer, a protective layer, and source and drain electrodes. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate. The oxide semiconductor layer is formed on the gate insulating layer and includes a source, a channel and a drain region. The oxide buffer layer is formed on the oxide semiconductor layer, and has a carrier concentration lower than that of the oxide semiconductor layer. The protective layer is formed on the oxide buffer layer and the gate insulating layer, and has contact holes formed therein so that the oxide buffer layer in the source and drain regions are exposed therethrough. The source and drain electrodes are coupled with the oxide buffer layer in the source and drain regions through the contact holes. | 2015-08-27 |
20150243794 | DISPLAY DEVICE AND ELECTRONIC APPLIANCE - A display device with low manufacturing cost, with low power consumption, capable of being formed over a large substrate, with a high aperture ratio of a pixel, and with high reliability is provided. The display device includes a transistor electrically connected to a light-transmitting pixel electrode and a capacitor. The transistor includes a gate electrode, a gate insulating film over the gate electrode, and a first multilayer film including an oxide semiconductor over the gate insulating film. The capacitor includes the pixel electrode and a conductive electrode formed of a second multilayer film which overlaps with the pixel electrode with a predetermined distance therebetween, and has the same layer structure as the first multilayer film. A channel formation region of the transistor is at least one layer, which is not in contact with the gate insulating film, of the first multilayer film. | 2015-08-27 |
20150243795 | Low Electric Field Source Erasable Non-Volatile Memory and Methods for Producing Same - A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer. | 2015-08-27 |
20150243796 | BACK GATE SINGLE-CRYSTAL FLEXIBLE THIN FILM TRANSISTOR AND METHOD OF MAKING - A gate dielectric material and a gate conductor portion are formed on a single-crystal semiconductor material of a substrate. A dielectric structure is then formed surrounding the gate conductor portion and thereafter a stressor layer is formed on the dielectric structure. A controlled spalling process is then performed and thereafter a material removal process can be used to expose a surface of the single-crystal semiconductor material. A source region and a drain region are then formed on the exposed surface of the single-crystal semiconductor material, which exposed surface is opposite the surface including the gate dielectric. | 2015-08-27 |
20150243797 | PHOTOVOLTAIC MODULE AND PHOTOVOLTAIC PANEL - A concentrator photovoltaic module | 2015-08-27 |
20150243798 | SOLAR CELL MODULE - A solar cell module includes first and second solar cells each including a plurality of first and second electrodes formed on a back surface of a semiconductor substrate, a first conductive line connected to the first electrodes, and a second conductive line connected to the second electrodes, and an interconnector connecting the first conductive line of the first solar cell to the second conductive line of the second solar cell. At least one of an area of an overlap portion, an area of a connection portion, a connection position, and a connection shape between the interconnector and the first conductive line of the first solar cell is different from at least one of an area of an overlap portion, an area of a connection portion, a connection position, and a connection shape between the interconnector and the second conductive line of the second solar cell. | 2015-08-27 |