35th week of 2015 patent applcation highlights part 58 |
Patent application number | Title | Published |
20150243499 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A technique includes forming a film containing a first element, a second element, and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: forming a first solid layer containing the first element and carbon, and having a thickness of more than one atomic layer and equal to or less than several atomic layers, by supplying a precursor gas having a chemical bond of the first element and carbon to the substrate and confining the precursor gas within the process chamber, under a condition in which the precursor gas is autolyzed and at least a part of the chemical bond of the first element and carbon is maintained without being broken; and forming a second solid layer by supplying a reaction gas containing the second element to the substrate to modify the first solid layer. | 2015-08-27 |
20150243500 | METHOD OF FORMING A PHOTORESIST LAYER - A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material. | 2015-08-27 |
20150243501 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing may be deposited over the first layer. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act. | 2015-08-27 |
20150243502 | METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR - A method for forming a fin field effect transistor is provided. The method includes: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; implanting atoms, molecules, ions or plasmas containing an element Sn into the fin structure with the material Ge or GeSi to form a Ge-based GeSn layer or a Ge-based GeSnSi layer; and forming a gate stack on the Ge-based GeSn layer or the Ge-based GeSnSi layer, the gate stack being oriented transversely to the fin structure. | 2015-08-27 |
20150243503 | STACKED SIDEWALL PATTERNING - The present disclosure provides methods of forming patterning features in a semiconductor structure using a sidewall image transfer technique. The method includes first forming a plurality of sacrificial mandrels over a dielectric hard mask layer. Each sacrificial mandrel has a width greater than a minimum spacing between adjacent patterning features subsequently formed according to a circuit design. After forming a plurality of spacer material layer portions on sidewalls of the sacrificial mandrels, a plurality of filler material layer portions are formed adjacent the spacer material layer portions. The cycle of forming the spacer material layer portions and filler material layer portions may be repeated until spaces between sacrificial mandrels are completely filled. Removal of the sacrificial mandrels and the filler material layer portions provides patterning features. | 2015-08-27 |
20150243504 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer. | 2015-08-27 |
20150243505 | METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR - A method for forming a FinFET is provided, comprising: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; forming a gate stack or a dummy gate on the substrate; defining a first region and a second region in the fin structure; and implanting atoms, molecules, ions or plasmas containing an element Sn into the first region and the second region in the fin structure with the material Ge to form a strained GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the first region and the second region in the fin structure with the material GeSi to form a strained GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the first region and the second region in the fin structure with the material GeSi to form a strained GeSnSi layer. | 2015-08-27 |
20150243506 | METHOD FOR FORMING GERMANIUM-BASED LAYER - A method for forming a germanium-based layer is provided. The method includes: providing a substrate having a Ge or GeSi surface layer; and implanting atoms, molecules, ions or plasmas containing an element Sn into the Ge surface layer to form a Ge-based GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the GeSi surface layer to form a Ge-based GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the Ge surface layer to form a Ge-based GeSnSi layer. | 2015-08-27 |
20150243507 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device in accordance with the present invention provides a metal-containing film capable of adjusting a work function. The including: (a) alternately supplying a first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and at least one selected from the group consisting of a ligand of a methyl group, a ligand of an ethyl group and a ligand of a cyclopenta-based group onto a substrate in a process chamber to form a composite metal-containing film on the substrate; and (b) alternately supplying a third source containing a third metal element and a fourth source containing nitrogen onto the substrate in the process chamber to form a metal nitride film on the composite metal-containing film. | 2015-08-27 |
20150243508 | ELECTROPOSITIVE METAL CONTAINING LAYERS FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 Å thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals. | 2015-08-27 |
20150243509 | Method for Producing Fin Structures of a Semiconductor Device in a Substrate - A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures. | 2015-08-27 |
20150243510 | METHOD FOR CONTROLLING THE PROFILE OF AN ETCHED METALLIC LAYER - An ashing chemistry employing a combination of Cl | 2015-08-27 |
20150243511 | METHOD OF FORMING PATTERN AND PHOTO MASK USED THEREIN - According to one embodiment, there is provided a transferring method in which, from a mask pattern including a first region of a first pattern that is surrounded by a first space and a second region of a second pattern that is surrounded by a space wider than the first space, only the first pattern is selectively transferred on a mask layer. After transferring only the first pattern on the mask layer using the mask pattern and leaving a mask layer in the second region, a pattern on the mask layer is transferred on a film to be processed. | 2015-08-27 |
20150243512 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes forming a first mask layer on a workpiece layer. The method further includes forming a concave portion in the workpiece layer by first etching using the first mask layer. The method further includes forming a second mask layer on the workpiece layer in which the concave portion is formed. The method further includes processing the concave portion of the workpiece layer by second etching using the second mask layer. | 2015-08-27 |
20150243513 | FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES - Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate. | 2015-08-27 |
20150243514 | METHOD FOR DIRECTED SELF-ASSEMBLY (DSA) OF A BLOCK COPOLYMER (BCP) USING A BLEND OF A BCP WITH FUNCTIONAL HOMOPOLYMERS - A method for directed self-assembly (DSA) of block copolymers (BCPs) uses a BCP blend with a small portion of functional homopolymers, called “inks”, before deposition and annealing of the BCP. A substrate has a patterned sublayer formed on it. The BCP blend is deposited on the patterned sublayer and annealed. The BCP blend is guided by the sublayer pattern. The inks selectively distribute into blocks, and part of the inks graft on the substrate underneath the blocks. The BCP blend layer is rinsed away, leaving the grafted inks. The grafted inks form a chemical contrast pattern that has the same geometry with the BCP bulk morphology. This process is repeated, which results in the grafted inks forming a thicker and denser chemical contrast pattern. This chemical contrast pattern of grafted inks is used for the DSA of a BCP that self-assembles as lamellae perpendicular to the substrate. | 2015-08-27 |
20150243515 | METHODS OF PATTERNING LINE-TYPE FEATURES USING A MULTIPLE PATTERNING PROCESS THAT ENABLES THE USE OF TIGHTER CONTACT ENCLOSURE SPACING RULES - A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule. | 2015-08-27 |
20150243516 | Semiconductor Device And Manufacturing Method Of The Same - An object is to improve the electrical characteristics of a semiconductor device. A semiconductor device using a hexagonal semiconductor is provided. The semiconductor device comprises a semiconductor substrate, a first N-type semiconductor layer formed on the semiconductor substrate, a P-type semiconductor layer formed on the first N-type semiconductor layer, a second N-type semiconductor layer formed on the P-type semiconductor layer, and a trench concaved to pass through the second N-type semiconductor layer and the P-type semiconductor layer and reach the first N-type semiconductor layer. The trench is arranged to have a longitudinal direction thereof at right angle ±15 degrees to an [11-20] axis and has concavity/convexity in a striped pattern formed on a side wall of the trench to be at right angle to a [0001] axis. | 2015-08-27 |
20150243517 | ALKALINE PICKLING PROCESS - A process for edge isolation or texture smoothing of a substrate, in which a process medium which allows control treatment of limited regions of the substrate is used. The process is therefore particularly suitable for one-sided treatment of substrates. The viscosity of the process medium plays a central role here. Furthermore, an apparatus designed for the process is presented. | 2015-08-27 |
20150243518 | METHOD FOR MULTIPLYING PATTERN DENSITY BY CROSSING MULTIPLE PATTERNED LAYERS - Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A first line-generation sequence creates a first layer of parallel lines of alternating and differing material by using double-stacked mandrels, sidewall image transfer, and novel planarization schemes. This line-generation sequence is repeated on top of the first layer of parallel lines, but with the second layer of parallel lines of alternating and differing material being oriented to elevationally cross lines of the first layer. Etching selective to one of the materials within the double stack of parallel lines results in defining a pattern of openings, slots, etc., which can be transferred into underlying layers. Such patterning techniques herein can quadruple a density of features in a given pattern, which can be described as created a pitch quad. | 2015-08-27 |
20150243519 | Method for Patterning a Substrate for Planarization - Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A conformal spacer is applied on a bi-layer or tri-layer mandrel (multi-layer) or other relief feature. The conformal spacer thus wraps around the mandrels and is also deposited on an underlying layer. A fill material is deposited to fill gaps or spaces between sidewall spacers. A CMP planarization step then removes substrate stack material down to a material interface of the bi-layer or tri-layer mandrel, with a middle or lower material of the mandrel being a CMP-stop material. This technique essentially cuts off or removes rounded features such as upper portions of sidewall spacers, thereby providing a spacer material with a planar top surface that can be uniformly etched and transferred to underlying layers. | 2015-08-27 |
20150243520 | METHODS OF FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming a pattern of a semiconductor device, a hard mask layer is formed on a substrate. A photoresist film is coated on the hard mask layer. The photoresist film is exposed and developed to form a first photoresist pattern. A smoothing process is performed on the first photoresist pattern to form a second photoresist pattern having a roughness property lower from that of the first photoresist pattern. In the smoothing process, a surface of the first photoresist pattern is treated with an organic solvent. An ALD layer is formed on a surface of the second photoresist pattern. The ALD layer is anisotropically etched to form an ALD layer pattern on a sidewall of the second photoresist pattern. The hard mask layer is etched using the second photoresist pattern and the ALD layer pattern as an etching mask to form a hard mask pattern. | 2015-08-27 |
20150243521 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A main etching process of forming a recess portion in a multilayer film having a laminated film where a first film and a second film having different relative permitivities are alternately formed on a base silicon film to a preset depth and an over etching process of forming the recess portion until the base silicon film is exposed are performed by introducing a processing gas including a CF-based gas and an oxygen gas and by performing a plasma etching process. In the over etching process, a first over etching process where a flow rate ratio of the oxygen gas to the CF-based gas is increased as compared to the main etching process and a second over etching process where the flow rate ratio of the oxygen gas to the CF-based gas is reduced as compared to the first over etching process are repeatedly performed two or more times. | 2015-08-27 |
20150243522 | ETCHING METHOD - An etching method can etch a region formed of silicon oxide. The etching method includes an exposing process (process (a)) of exposing a target object including the region formed of the silicon oxide to plasma of a processing gas containing a fluorocarbon gas, etching the region, and forming a deposit containing fluorocarbon on the region; and an etching process (process (b)) of etching the region with a radical of the fluorocarbon contained in the deposit. Further, in the method, the process (a) and the process (b) are alternately repeated. | 2015-08-27 |
20150243523 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate including a transistor and a dummy gate disposed on the transistor, removing the dummy gate on the transistor, performing treatment using hydrogen (H | 2015-08-27 |
20150243524 | METHOD OF PROCESSING TARGET OBJECT AND PLASMA PROCESSING APPARATUS - A method of processing a target object includes (a) exposing a resist mask to active species of hydrogen generated by exciting plasma of a hydrogen-containing gas within a processing vessel while the target object is mounted on a mounting table provided in the processing vessel; and (b) etching a hard mask layer by exciting plasma of an etchant gas within the processing vessel after the exposing of the resist mask to the active species of hydrogen. The plasma is excited by applying of a high frequency power for plasma excitation to an upper electrode. In the method, a distance between the upper electrode and the mounting table in the etching of the hard mask layer ((b) process) is set to be larger than a distance between the upper electrode and the mounting table in the exposing of the resist mask to the active species of hydrogen ((a) process). | 2015-08-27 |
20150243525 | METHOD OF FORMING A FINE PATTERN BY USING BLOCK COPOLYMERS - A method of forming a fine pattern includes forming a phase separation guide layer on a substrate, forming a neutral layer on the phase separation guide layer, forming a first pattern including first openings on the neutral layer, forming a second pattern including second openings each having a smaller width than each of the first openings, forming a neutral pattern including guide patterns exposing a portion of the phase separation guide layer by etching an exposed portion of the neutral layer by using the second pattern as an etch mask, removing the second pattern to expose a top surface of the neutral pattern, forming a material layer including a block copolymer on the neutral pattern and the phase separation guide layer exposed through the guide patterns, and forming a fine pattern layer including a first block and a second block on the neutral pattern and the phase separation guide layer. | 2015-08-27 |
20150243526 | RE-CRYSTALLIZATION FOR BOOSTING STRESS IN MOS DEVICE - A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed. | 2015-08-27 |
20150243527 | ETCHING METHOD OF SEMICONDUCTOR SUBSTRATE, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - An etching method containing, at the time of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal, selecting a substrate in which a surface oxygen content of the first layer is from 0.1 to 10% by mole, and applying an etching liquid containing a hydrofluoric acid compound and an oxidizing agent to the substrate and thereby removing the first layer. | 2015-08-27 |
20150243528 | Fabrication Method For Microelectronic Components And Microchip Inks Used In Electrostatic Assembly - Charge-encoded chiplets are produced using a sacrificial metal mask and associated fabrication techniques and materials that are compatible with typical semiconductor fabrication processes to provide each chiplet with two different (i.e., positive and negative) charge polarity regions generated by associated patterned charge-inducing material structures. A first charge-inducing material (e.g., SiO | 2015-08-27 |
20150243529 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 2015-08-27 |
20150243530 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate. | 2015-08-27 |
20150243531 | Via Structure For Packaging And A Method Of Forming - A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps. | 2015-08-27 |
20150243532 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR MODULE - Disclosed is a technique capable of preventing an encapsulating material from covering a heat-dissipating surface of a semiconductor module, which releases heat of a switching element. Specifically disclosed a step for manufacturing a semiconductor module including a submodule having a collector and an emitter with heat-dissipating surfaces, including a step for placing the submodule in the cavity so that the submodule is pressed by the pressing device while covering the heat-dissipating surface of the emitter with the pressing device and covering the heat-dissipating surface of the collector with the lower mold, and a step for feeding the encapsulating material to the cavity by moving the piston so that the pressure of the cavity measured by the pressure measuring device does not exceed the pressure at which the pressing device presses the submodule. | 2015-08-27 |
20150243533 | DEVICE AND METHOD FOR REMOVING LIQUID FROM A SURFACE OF A DISC-LIKE ARTICLE - A device for removing liquid from a surface of a disc-like article comprises a spin chuck for holding and rotating a single disc-like article about an axis of rotation and a liquid dispenser for dispensing liquid onto the disc-like article. A first gas dispenser comprises at least one nozzle with at least one orifice for blowing gas onto the disc-like article, and a second gas dispenser comprises at least one nozzle with at least one orifice for blowing gas onto the disc-like article. A rotary arm moves the liquid dispenser and the second gas dispenser across the disc-like article so that the second gas dispenser and the liquid dispenser move to a point in a peripheral region of the spin chuck. The at least one nozzle of the second gas dispenser is elongated along a first horizontal line that defines an angle α of 5-20° relative to a second horizontal line connecting the center of the second gas dispenser and the rotation axis of the rotary arm. | 2015-08-27 |
20150243534 | Copper Wire Bonding Apparatus Using A Purge Gas to Enhance Ball Bond Reliability - A bonding apparatus and method of bonding copper bond wires to bond pads on an integrated circuit devices attached to a substrate. A heater block heats the devices and substrate prior to and during wire bonding. A clamp presses the substrate down onto the heater block during wire bonding and thereby forms a region of the substrate isolated from the remainder of the substrate. A bonder head creates ball bonds as it attaches one end of the bond wires to the bond pads on the devices within the isolated region. The bonder head also attaches the other end of the bond wires to substrate pads adjacent the devices being wire bonded. To prevent corrosion of the ball bonds, a gas source floods the substrate and the attached devices that have not yet wire bonded with a purge gas while the heater block heats the substrate and the attached devices. | 2015-08-27 |
20150243535 | CLUSTER TYPE SEMICONDUCTOR PROCESSING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A cluster type semiconductor processing apparatus and a method for manufacturing a semiconductor device using the same are provided. The cluster type semiconductor processing apparatus includes a polyhedral transfer module to transfer a wafer, a first process module communicating with the transfer module, a degassing process of removing fumes from a surface of the wafer being performed in the first process module, a second process module communicating with the transfer module, a plasma cleaning process of cleaning the surface of the wafer being performed in the second process module, a standby module communicating with the transfer module, the wafer having undergone the degassing process and the plasma cleaning process being maintained in the standby module for a certain time, and a third process module communicating with the transfer module, a metal sputtering process of depositing a metal film on the wafer being performed in the third process module. | 2015-08-27 |
20150243536 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - For execution of substrate processing using multiple processing units available in parallel, two or more processing units to be used in parallel are selected from the multiple processing units such that an conveying-out standby time does not exceed a given permissible time. The conveying-out standby time is a time when a substrate after subjected to substrate processing by the processing unit is placed in standby until the substrate is transported from the processing unit by a transporting part. A schedule is made that includes processing by the transporting part of transporting a substrate toward the two or more processing units, substrate processing by the two or more processing units, and processing by the transporting part of transporting a substrate from the two or more processing units. The processing unit and the transporting part are controlled to execute substrate processing on multiple substrates in order according to the schedule. | 2015-08-27 |
20150243537 | MECHANISMS FOR CLEANING SUBSTRATE SURFACE FOR HYBRID BONDING - The mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. The mechanisms for a hybrid bonding and a integrated system are also provided. | 2015-08-27 |
20150243538 | POD AND PURGE SYSTEM USING THE SAME - An object is to prevent the partial pressure of oxidative gas over time in an FOUP mounted on an FIMS system and left open. A surface purge unit is provided on a side opposite to the opening of the FOUP in such a way that wafers supported in the FOUP is located between the opening and the surface purge unit. The surface purge unit ejects inert gas from a plurality of vent holes provided in its surface toward the opening. Uniform purging or replacement of the interior of the FOUP with inert gas can be achieved by creating inert gas flow from an inert gas supply part extending over a surface in the direction from the interior of the FOUP toward the opening along the wafer surface. | 2015-08-27 |
20150243539 | WAFER TRANSPORT SYSTEM - A substrate transport system includes a substrate cart inside a chamber and a linearly driven shuttle outside the chamber configured to levitate the substrate cart into a non contact, spaced relationship with respect to outwardly opposing sides of an interior wall of the chamber and to linearly drive the substrate cart within the chamber. | 2015-08-27 |
20150243540 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - Provided is a substrate processing apparatus including: a carry-in area where a placing table is provided to place thereon a carrying container including a take-out opening, a flange formed on an upper portion of a side formed with the take-out opening, and a recess formed on a top surface of the flange; a transfer area maintained under an atmosphere different from that of the carry-in area; a partition wall configured to partition the carry-in area and the transfer area and formed with an opening; a door configured to open/close the opening; a carrying container pressing unit configured to press the carrying container placed on the placing table against the partition wall so that the take-out opening of the carrying container faces the opening of the partition wall; and a carrying container holding unit configured to be inserted into the recess to press the carrying container against the partition wall. | 2015-08-27 |
20150243541 | ELECTROSTATIC CHUCK, PLACING TABLE, PLASMA PROCESSING APPARATUS, AND METHOD OF MANUFACTURING ELECTROSTATIC CHUCK - Disclosed is an electrostatic chuck configured to hold a processing target object. The electrostatic chuck includes a dielectric substrate and a protective film. The substrate has a surface which is constituted by a bottom face, and a plurality of projecting portions. The plurality of projecting portions is formed to protrude from the bottom face. Each of the projecting portions includes a top face, and a side face. The top face comes in contact with the processing target object, and the side face extends from the bottom face to the top face. The protective film is made of yttrium oxide. The protective film is formed on the side faces of the plurality of projecting portions and the bottom face such that the top faces are exposed. | 2015-08-27 |
20150243542 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate heating unit arranged to heat the underside of a substrate while supporting the substrate thereon and an attitude changing unit arranged to cause the substrate heating unit to undergo an attitude change between a horizontal attitude and a tilted attitude. In an organic solvent removing step to be performed following a substrate heating step of heating the substrate, the substrate heating unit undergoes an attitude change to the tilted attitude so that the upper surface of the substrate becomes tilted with respect to the horizontal surface. | 2015-08-27 |
20150243543 | APPARATUS FOR LIQUID TREATMENT OF WAFER SHAPED ARTICLES - An apparatus for processing wafer-shaped articles comprises a spin chuck adapted to hold and spin a wafer-shaped article of a predetermined diameter during a processing operation. A liquid collector surrounds the spin chuck, and comprises a first inner surface. The first inner surface comprises a first conductive material. The collector further comprises a first conductive pathway for grounding the first conductive material. | 2015-08-27 |
20150243544 | FORMATION OF AIR-GAP SPACER IN TRANSISTOR - Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces. | 2015-08-27 |
20150243545 | INHIBITOR PLASMA MEDIATED ATOMIC LAYER DEPOSITION FOR SEAMLESS FEATURE FILL - Systems and methods for depositing film in a substrate processing system includes performing a first atomic layer deposition (ALD) cycle in a processing chamber to deposit film on a substrate including a feature; after the first ALD cycle, exposing the substrate to an inhibitor plasma in the processing chamber for a predetermined period to create a varying passivated surface in the feature; and after the predetermined period, performing a second ALD cycle in the processing chamber to deposit film on the substrate. | 2015-08-27 |
20150243546 | SEMICONDUCTOR SUBSTRATE FOR PHOTONIC AND ELECTRONIC STRUCTURES AND METHOD OF MANUFACTURE - A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate. | 2015-08-27 |
20150243547 | SEMICONDUCTOR LINE FEATURE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials. | 2015-08-27 |
20150243548 | Control of FET Back-Channel Interface Characteristics - A method and structure for control of FET back-channel interface characteristics of an integrated circuit by implanting of selected implantation species at or near a device interface accessible during manufacture of the integrated circuit using layer transfer technology, without adversely affecting the structure or characteristics of a principal front-side FET. | 2015-08-27 |
20150243549 | PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTAL MATERIAL - The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure. | 2015-08-27 |
20150243550 | METHOD FOR MANUFACTURING SOI WAFER - A method for manufacturing SOI wafer of forming an oxide film on a bond wafer of a semiconductor single crystal substrate, forming an ion implanted layer into the bond wafer by implanting ions of at least one kind of gas in hydrogen and rare gases through the oxide film, bonding together an ion implanted front surface of the bond wafer and base wafer front surface via the oxide film, thereafter delaminating the bond wafer along the ion implanted layer, and thereby fabricating an SOI wafer. The oxide film is formed on the bond wafer such that on a back surface it is made thicker than the oxide film on a bonded face. The method for manufacturing SOI wafer capable of suppressing scratches and SOI film thickness abnormality caused by warped shapes of the SOI and bond wafers after delamination where it has been delaminated by an ion implantation delamination method. | 2015-08-27 |
20150243551 | METHOD OF DETACHING A LAYER - The present disclosure concerns a method of detaching a layer to be detached from a donor substrate, comprising the following steps: a) assembling the donor substrate and a porous substrate, b) application of a treatment of chemical modification of the crystallites, the chemical modification being adapted to generate a variation of the volume of the crystallites, the volume variation generates deformation in compression or in tension of the porous substrate, the deformation in compression or in tension generates a stress in tension or in compression in the donor substrate, which causes fracture in a fracture plane, the fracture plane delimiting the layer to be detached, the stress leading to the detachment of the layer to be detached from the donor substrate. | 2015-08-27 |
20150243552 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks. | 2015-08-27 |
20150243553 | METHOD FORMING THROUGH-VIA USING ELECTROLESS PLATING SOLUTION - The present invention provides a method for forming a through-via, including the steps of (1) forming an alloy film as a diffusion-preventive layer that prevents diffusion of copper, in an area on a side wall of a hole formed in a substrate that extends from an entrance of the hole to a central part of the hole, by use of an electroless cobalt plating solution or an electroless nickel plating solution containing at least cobalt ion or nickel ion, a complexing agent, a reductant, and a pH adjusting agent; (2) forming an alloy film as a diffusion-preventive layer in an area on the side wall of the hole formed in the substrate that extends from the central part of the hole to a bottom of the hole, by use of an electroless cobalt plating solution or an electroless nickel plating solution containing at least the cobalt ion or the nickel ion, the complexing agent, the reductant, the pH adjusting agent, and an amino group-containing polymer; and (3) stacking a copper seed layer on the diffusion-preventive layer formed in each of steps (1) and (2) by use of an electroless copper plating solution. | 2015-08-27 |
20150243554 | Method for Creating Contacts in Semiconductor Substrates - Techniques include methods for creating contacts for microchips, solar films, etc., for electrically connecting conductive elements and/or for current spreading. Embodiments herein include using an oversized “board” or contact array positioned between a lower layer and an upper layer. This contact array is created by directed self-assembly (DSA) of block copolymers. The lower and upper layers can have conductive structures such as lines. The oversized board can be comprised of hundreds, thousands, millions (etc.) of small conductive contact cylinders, lines or other vertical structures, with each conductive structure electrically isolated from adjacent conductive structures in the array. A crossover location of a line on a lower level with a line on an upper level is connected with multiple conductive structures located at the cross over location. | 2015-08-27 |
20150243555 | INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME - After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP. | 2015-08-27 |
20150243556 | Method of Supplying Cobalt to Recess - A method of supplying cobalt to a recess formed in an insulation film of an object to be processed is disclosed. In one embodiment, the method includes forming a cobalt nitride film on a surface of the insulation film comprising a surface defining the recess, forming a cobalt film on the cobalt nitride film, and heating the cobalt film. | 2015-08-27 |
20150243557 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The layer may include a first metal and a second metal. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act. Thereafter, the stripped first structure may be subjected to a second annealing act. | 2015-08-27 |
20150243558 | SCRIBE ETCH PROCESS FOR SEMICONDUCTOR LASER CHIP MANUFACTURING - An improved scribe etch process for semiconductor laser chip manufacturing is provided. A method to etch a scribe line on a semiconductor wafer generally includes: applying a mask layer to a surface of the wafer; photolithographically opening a window in the mask layer along the scribe line; etching a trench in the wafer using a chemical etchant that operates on the wafer through the window opening, wherein the chemical etchant selectively etches through crystal planes of the wafer to generate a V-groove profile associated with the trench; and cleaving the wafer along the etched trench associated with the scribe line through application of a force to one or more regions of the wafer. | 2015-08-27 |
20150243559 | HYBRID WAFER DICING APPROACH USING TEMPORALLY-CONTROLLED LASER SCRIBING PROCESS AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a temporally-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The temporally-controlled laser scribing process involves scribing with a laser beam having a profile comprising a leading femto-second portion and a trailing lower-intensity, higher fluence portion. The method also involves plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits. | 2015-08-27 |
20150243560 | WAFER PROCESSING METHOD - A wafer processing method includes a cut groove forming step of positioning, from a back side of the substrate, a cutting blade to an area corresponding to a division line to form cut grooves in such a manner that the cutting blade does not reach a functional layer and part of a substrate is left, and a functional layer cutting step of performing irradiation with a laser beam along the division lines formed in the functional layer forming a wafer to perform ablation processing for the functional layer and cut the functional layer. In the cut groove forming step, the cut grooves are formed along the division lines in such a manner that an uncut part is left in a peripheral area of the wafer. | 2015-08-27 |
20150243561 | Semiconductor Devices and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a method for forming a semiconductor device includes forming a device region in a substrate. The device region extends continuously from one sidewall of the substrate to an opposite sidewall of the substrate. The method further includes forming trenches in the substrate. The trenches divide the device region into active regions. The method also includes singulating the substrate by separating the substrate along the trenches. | 2015-08-27 |
20150243562 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer. | 2015-08-27 |
20150243563 | INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES - In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack. | 2015-08-27 |
20150243564 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device may include the following steps: preparing a substrate having a PMOS region and an NMOS; forming a first gate trench on the PMOS region; forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first gate trench; forming a second gate trench on the NMOS region; forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer that are positioned on a side of the first gate trench; and removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer that are positioned on a side of the second gate trench. | 2015-08-27 |
20150243565 | METHODS OF FORMING LOW RESISTANCE CONTACTS - Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings. | 2015-08-27 |
20150243566 | METHOD OF MEASURING CONTAMINATION AMOUNT OF VAPOR PHASE GROWTH APPARATUS, AND METHOD OF MANUFACTURING EPITAXIAL WAFER - Carry out a vapor etching step of cleaning an inside of a chamber of a vapor phase growth apparatus by vapor etching using HCl gas (S | 2015-08-27 |
20150243567 | ELECTRON RADIATION MONITORING ELECTRODE SYSTEM TO PREVENT GOLD SPITTING AND RESIST CROSS-LINKING DURING EVAPORATION - An electrode system configured to be positioned within a vacuum chamber of an electron-beam metal evaporation and deposition apparatus including a metal slug from which metal is evaporated during operation of the electron-beam metal evaporation and deposition apparatus. The electrode system includes a substantially ring-shaped electrode formed of a conductive material and a plurality of insulating standoffs configured to support the substantially ring-shaped electrode in the vacuum chamber in a position substantially surrounding the metal slug. | 2015-08-27 |
20150243568 | INLINE RESIDUAL LAYER DETECTION AND CHARACTERIZATION POST VIA POST ETCH USING CD-SEM - Methods of determining an amount and/or a thickness of residual material in a via based on LL-BSE images of the material are disclosed. Embodiments include etching a plurality of vias through at least one material layer on a wafer; loading the wafer with predetermined measurement parameters in a CD-SEM; acquiring an image of each via of interest using LL-BSE imaging; quantifying grey level values of the images; characterizing residuals of the at least one material layer in each via based on the grey level values; determining an etching success rate based on the characterizing of the residuals; adjusting the etching based on the determining of the etching success rate; and repeating the steps of acquiring, quantifying, characterizing, determining, and adjusting until a desired etching success rate is achieved. | 2015-08-27 |
20150243569 | METHOD AND SYSTEM FOR CONTROLLING RESISTIVITY IN INGOTS MADE OF COMPENSATED FEEDSTOCK SILICON - Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides semiconductor predominantly of a single type (p-type or n-type) for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of boron, phosphorus, aluminum and/or gallium. The process further melts the silicon feedstock with the boron, phosphorus, aluminum and/or gallium to form a molten silicon solution from which to perform directional solidification and maintains the homogeneity of the resistivity of the silicon throughout the ingot. A balanced amount of phosphorus can be optionally added to the aluminum and/or gallium. Resistivity may also be measured repeatedly during ingot formation, and additional dopant may be added in response, either repeatedly or continuously. | 2015-08-27 |
20150243570 | TIM STRAIN MITIGATION IN ELECTRONIC MODULES - A lid including a lid body, and a wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion. | 2015-08-27 |
20150243571 | FINGERPRINT MODULE AND MANUFACTURING METHOD FOR SAME - A fingerprint module of fingerprint identification chip is provided. The fingerprint module includes a substrate, a fingerprint identification chip, a molding layer, a color layer, and a protecting layer. The substrate includes a pair of surfaces and a plurality of pads. The surfaces are on the opposite sides of the substrate. The pads are exposed on one of the surfaces. The fingerprint identification chip electrically connects with the substrate according to at least a wire. The molding layer disposes on the substrate and covers the fingerprint identification chip and the wire. The color layer disposes on the molding layer. The protecting layer disposes on the color layer. | 2015-08-27 |
20150243572 | INTEGRATED CIRCUIT PACKAGE CONFIGURATIONS TO REDUCE STIFFNESS - Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed. | 2015-08-27 |
20150243573 | WAFER LEVEL CHIP SCALE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a die including a top surface and a sidewall, and a molding surrounding the die and including a top surface, a sidewall interfacing with the sidewall of the die, and a curved surface including a curvature greater than zero and coupling the sidewall of the molding with the top surface of the molding. | 2015-08-27 |
20150243574 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring. | 2015-08-27 |
20150243575 | Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP) - A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die. | 2015-08-27 |
20150243576 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element. | 2015-08-27 |
20150243577 | CHIP THERMAL DISSIPATION STRUCTURE - Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board. | 2015-08-27 |
20150243578 | INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES - An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer | 2015-08-27 |
20150243579 | ELECTRONIC DEVICES WITH IMPROVED THERMAL PERFORMANCE - Electronic devices with improved thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. | 2015-08-27 |
20150243580 | METHODS FOR IMPROVING THERMAL PERFORMANCE OF FLIP CHIP PACKAGES - Methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. | 2015-08-27 |
20150243581 | SEMICONDUCTOR COOLING DEVICE - A semiconductor cooling device includes: a cooling medium flow channel, through which a cooling medium for cooling a semiconductor chip flows; a laminar flow section which is provided in a region upstream of the cooling medium flow channel and allows the cooling medium to flow in the form of laminar flow; and a turbulent flow section which is provided in a region downstream of the laminar flow section in the cooling medium flow channel and allows the cooling medium, which flows in the form of laminar flow from the laminar flow section, to flow in the form of turbulent flow. | 2015-08-27 |
20150243582 | NEW PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION - A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions. | 2015-08-27 |
20150243583 | INTERCONNECT ASSEMBLIES WITH THROUGH-SILICON VIAS AND STRESS-RELIEF FEATURES - A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap. | 2015-08-27 |
20150243584 | INTERMETALLIC COMPOUND FILLED VIAS - Electronic devices including intermetallic columns within vias are provided. Vias are filled with one or more pastes containing metal particles. Thermal treatment of the pastes within the vias converts the particles within the pastes to one or more intermetallic compounds that do not melt during next level packaging. | 2015-08-27 |
20150243585 | Semiconductor Device - A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate. | 2015-08-27 |
20150243586 | SEMICONDUCTOR DIE PACKAGE WITH PRE-MOLDED DIE - A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound. | 2015-08-27 |
20150243587 | HIGH RELIABILITY SEMICONDUCTOR PACKAGE STRUCTURE - The present invention discloses a high reliability semiconductor package structure, which includes a lower heat sink, a die, an upper heat sink, a lead frame and a package body. The lead frame and the upper heat sink contain separately a first bending unit and a second bending unit that are electrically connected. The upper and lower heat sinks are attached to two opposite surfaces of the die and sink the high power transient heat generated at the die. The lower heat sink also has an indentation that circles the die and contains extra solder that might otherwise contaminate the die. Package body contains and protects the die, the upper and lower heat sinks and the lead frame. With the implementation of the invention, the reliability of the semiconductor package structure is promoted and the EMC durability together with the operable power is enhanced. | 2015-08-27 |
20150243588 | MULTIPLE DIE LEAD FRAME - An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die. The plurality of packaging posts includes first and second sets of packaging posts extending inward from first and second opposite sides of the packaging enclosure, respectively. | 2015-08-27 |
20150243589 | COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE - A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation. | 2015-08-27 |
20150243590 | EMBEDDED DIE REDISTRIBUTION LAYERS FOR ACTIVE DEVICE - Embedded die packages are described that employ one or more substrate redistribution layers (RDL) to route electrode nodes and/or for current redistribution. In one or more implementations, an integrated circuit die is embedded in a copper core substrate. A substrate RDL contacts a surface of the embedded die, with at least one via (e.g., thermal via) in contact with the surface RDL to furnish electrical interconnection between the embedded die and an external contact. Additional substrate RDL or WLP RDL can be incorporated into the package to provide varying current distribution between the embedded die and external contacts. | 2015-08-27 |
20150243591 | Semiconductor Device with Plated Lead Frame, and Method for Manufacturing Thereof - A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices. | 2015-08-27 |
20150243592 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER - A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. | 2015-08-27 |
20150243593 | Method of Connecting a Semiconductor Package to a Board - A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package having a plurality of contact areas, selecting a specific contact area out of the plurality of contact areas, applying solder balls to the contact areas and therein applying two or more specific solder balls to the specific contact area, and connecting the semiconductor package to the board in such a way that the two or more specific solder balls are connected with each other and with a contact region of the plurality of contact regions of the board. | 2015-08-27 |
20150243594 | RECEIVING STRUCTURE FOR ELECTRICALLY CONNECTING A NANO-OBJECT ON A SURFACE THEREOF AND RE-ESTABLISH ELECTRICAL CONTACT WITH THE NANO-OBJECT ON THE OPPOSITE SURFACE, AND METHODS FOR MANUFACTURING THE STRUCTURE - Receiving structure for electrically connecting a nano-object on a surface thereof and re-establish electrical contact with the nano-object on the opposite surface, and methods for manufacturing the structure. | 2015-08-27 |
20150243595 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip is provided. The semiconductor chip includes a first circuit, a second circuit, a third circuit, a first signal path and a second signal path. The first circuit provides a reference signal. The first signal path includes a first conductive trace and transmits the reference signal from the first circuit to the second circuit. The second signal path transmits the reference signal from the first circuit to the third circuit. Timing skews of the first and second signal paths are balanced and the first and second signal paths are routed globally. | 2015-08-27 |
20150243596 | PACKAGE SUBSTRATES, PACKAGES INCLUDING THE SAME, METHODS OF FABRICATING THE PACKAGES WITH THE PACKAGE SUBSTRATES, ELECTRONIC SYSTEMS INCLUDING THE PACKAGES, AND MEMORY CARDS INCLUDING THE PACKAGES - A package substrate includes a substrate body and a plurality of patterns disposed on the substrate body. The substrate body has a first region including a chip attachment region and a second region adjacent to the first region. The plurality of patterns are disposed on the substrate body in the second region. Each of the plurality of patterns extends in a first direction to have a stripe shape, and the plurality of patterns are spaced apart from each other in a second direction which is substantially perpendicular to the first direction. Related fabrication methods, electronic systems and memory cards are also provided. | 2015-08-27 |
20150243597 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING WARPING - A semiconductor device includes a substrate having a front side and a rear side, a plurality of dielectric layers on the front side, a plurality of interconnection circuit structures in the dielectric layers, and at least one backside passivation layer on the rear side. The backside passivation layer and the top passivation layer are made of the same material and have substantially the same thickness. | 2015-08-27 |
20150243598 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners. | 2015-08-27 |