35th week of 2009 patent applcation highlights part 27 |
Patent application number | Title | Published |
20090213592 | LED LAMP WITH HEAT SINK ASSEMBLY - An LED lamp includes a support, an envelope, a heat sink assembly and a plurality of LED modules. The envelope is coupled to the support. The heat sink assembly includes a first heat sink mounted on the envelope, a cylindrical second heat sink attached to a bottom surface of the first heat sink and positioned in the envelope, and a plurality of heat pipes. The LED modules are mounted on an outside wall of the second heat sink. The heat pipes have condensing portions embedded in the bottom surface of the first heat sink and evaporating portions sandwiched between the outside wall of the second heat sink and the LED modules. | 2009-08-27 |
20090213593 | Optical device and system for black level enhancement and methods of use thereof - The present invention relates to an optical device for black level enhancement of a viewing display. Also disclosed are a system including the optical device and methods of improving black level of a viewing display, such as a plasma display panel, a liquid crystal display panel, an inorganic light emitting diode display panel, or an organic light emitting diode display panel. | 2009-08-27 |
20090213594 | Light source - An illuminator ( | 2009-08-27 |
20090213595 | Light fixture assembly and led assembly - A removable light fixture assembly is provided. The light fixture assembly includes an LED lighting element and a compression element. Operation of the compression element from a first position to a second position generates a compression force which reduces thermal impedance between the LED assembly and a thermally-conductive housing. | 2009-08-27 |
20090213596 | SUSPENSION - A suspension has a holding element to which an arm is rotatably fastened, wherein a coupling element is provided which is rotatable around the holding element independently of the arm and which forms a security against rotation. | 2009-08-27 |
20090213597 | LED CANDELABRA FIXTURE AND LAMP - An electric lighting lamp or bulb having an LED light source mounted to a candle base, and wherein driver circuitry for the LED light source is housed within the candle base. A transparent globe encloses the LED light source, and the lamp presents the appearance of a traditional candle and/or of an incandescent candelabra or chandelier-type lamp or bulb. | 2009-08-27 |
20090213598 | Wall mounted fixture for decoratively displaying an object - A fixture for decoratively displaying and illuminating an object, such as a guitar, includes a hanger adapted for attachment to a wall or other upstanding support. The hanger includes adjustable means for releasably supporting a guitar or other object. The fixture incorporates a lighting system having at least one light source carried on a malleable arm. The arm is adapted for positioning and aiming the light source and thereby controllably illuminating a hanging object. The lighting system includes an electric power source electrically connected to the light source through a switch. Electrical current control means may be provided for regulating the intensity of the light emitted by the light source. In a preferred embodiment, the lighting system includes a plurality of light sources mounted to the fixture on, and positioned and aimed by independently moveable elongated malleable arms. | 2009-08-27 |
20090213599 | Chain support - A chain support ( | 2009-08-27 |
20090213600 | Lighting device for motor vehicle - The invention concerns a lighting device ( | 2009-08-27 |
20090213601 | Light Sensor for Broadband Solar and Twilight Function Control - The present invention is directed to a sensor that detects external ambient light energy for automatically controlling vehicle headlights while also detecting solar loading within a vehicle passenger compartment for automatically controlling interior climate. The integrated circuit comprises a signal amplifier and a photodetector adapted for receiving ambient light energy. The integrated circuit produces a solar output signal having a first gain and a twilight output signal having a second gain, such that the spectral response of the sensor is dictated primarily by the spectral response of the photodetector. A transmissive layer covers the sensor, and the neutral density diffuser is disposed between the transmissive layer and the integrated circuit and lacks any pigments that would prevent light energy from reaching the photodetector at an undiminished level of intensity. | 2009-08-27 |
20090213602 | LIGHT-EMITTING DEVICE FOR THE INTERIOR OF A VEHICLE WITH MUSIC SYNCHRONIZATION - An illuminating apparatus shows music effects with light sequences in a vehicle. The apparatus includes a support structure that is installable on an electrical socket. A switch on the base structure activates the apparatus. A transparent container with cut-outs surrounds the base structure and includes a white light activated by the switch. A direct current motor has an axle configured to rotate the base structure within the container. A circuit board is attached to the axle enables rotation of the circuit board within the container. The circuit board can activate sequences of light upon detection of a music signal and can detect a signal from a remote control. Light emitting sources are operably connected to the circuit board to rotate with the circuit board and to project light through the container. A remote control comprises buttons for controlling apparatus operational functions. | 2009-08-27 |
20090213603 | PROJECTION GEAR KNOB - A projection gear knob is assembled on an end portion of a car gear lever. A projection lamp, a projection film are accommodated and a transparent push-button is assembled in the gear knob, such that interesting, ornate, or beautiful projection film pattern is irradiated on inner top of the car. The projection lamp is freely switched by an outer light-transmissive push-button, so as to increase interest and beauty in the decoration of the car. | 2009-08-27 |
20090213604 | MIRROR ASSEMBLY FOR VEHICLE - An interior rearview mirror assembly for a vehicle includes a reflective element, a frame portion around a perimeter of the reflective element, and one or more user inputs or buttons movably mounted to the frame portion. At least one bezel segment is positioned partially around the perimeter of the reflective element and frame portion and defines a space or gap along the frame portion between opposed and spaced apart ends of the bezel segment or segments. The input or button is mountable to the frame portion at the space and is movable by a user to engage and actuate an electronic switch within the mirror assembly. | 2009-08-27 |
20090213605 | Automobile Wheel Illuminating Device - A telescoping automobile wheel illuminating device having one end for attachment within a wheel well and an opposite end having a light source, wherein the device can be activated to extend the light source out of the wheel well to illuminate a tire rim and retract the light source back into the wheel well when not in use. | 2009-08-27 |
20090213606 | LED headlamp system - A solid-state light source ( | 2009-08-27 |
20090213607 | VEHICLE LIGHTING DEVICE - Light having entered a light transmitting member through a predetermined point (the light emission center of a light emitting element) on an optical axis undergoes internal reflection in a front surface perpendicular to the optical axis, then undergoes internal reflection again in a rear surface composed of a paraboloid of revolution having a focal point at a position of plane symmetry with the predetermined point, and then exits the front surface. An annular region around the optical axis in the front surface is mirror-finished. The position of its outer peripheral edge is set to be near a position where the incident angle of the light emitted from the light emitting element is equal to a critical angle. The position of the inner peripheral edge is set to be near a position where the light having exited the light emitting element and undergone internal reflection in the front surface enters a position immediately behind the outer peripheral edge in the rear surface. | 2009-08-27 |
20090213608 | Headlight lens for a vehicle headlight - The invention relates to a single-piece headlamp lens ( | 2009-08-27 |
20090213609 | Device for the Adjustable Fixing of a Headlamp - The invention relates to a device for the adjustable fixing of a headlamp with a housing ( | 2009-08-27 |
20090213610 | VEHICLE HEADLAMP - A vehicle headlamp is provided with a projection lens, a light source, a reflector, a first shade, and a second shade. The first shade includes an upper end crossing in a vicinity of a rear side focal point of the projection lens. The first shade shields a part of the light emitted from the light source and reflected by the reflector to form a first light distribution pattern. The second shade includes a light shielding portion for shielding a part of the light emitted from the light source and reflected by the reflector to form a second light distribution pattern. The second shade is movable between a first position and a second position. In the first position, the second shade is positioned above the first shade and is separated from the first shade so that the first light distribution pattern is formed. In the second position, the second shade covers the upper end of the first shade so that the second light distribution pattern is formed. | 2009-08-27 |
20090213611 | FLAGPOLE LAMP OF A VEHICLE HEAD - A flagpole lamp of a vehicle head includes a pole, a socket joint, a circuit board, a positioning base, a waterproof washer, a lucent bar and a pole head. The circuit board, the positioning base and the waterproof washer are fitted in the socket joint. The circuit board has a light inserted through a through hole in the positioning base and the waterproof washer respectively. The lucent bar is fixed on the socket joint and dug with a hole, having the pole head put thereon. The light of the circuit board can be lit up to emit light out of the lucent bar to enable a driver to clearly see the head corners and the position of an vehicle while turning on headlights, flashing other colored light to let drivers of cars running beside and behind the vehicle can be warned to advance traffic security. | 2009-08-27 |
20090213612 | Illumination Device - In order to provide an illumination device comprising at least one light source ( | 2009-08-27 |
20090213613 | Vehicle Headlight - A motor vehicle headlight comprising an illuminating device ( | 2009-08-27 |
20090213614 | Device for Production of a Polychromatic Light over a Continuous Spectrum by Excitation at One Wavelength - A device for producing a polychromatic light including an optical pump that delivers a first radiation at a first wavelength; a light guide; and a selective injector that injects the radiation into the guide, the guide being arranged to generate a harmonic corresponding to the selected injector and provide a polychromatic light at an outlet, by non-linear excitation of the first radiation and the harmonic. | 2009-08-27 |
20090213615 | LIGHT EMITTING DEVICE HAVING A STRAIGHT-LINE SHAPE - A light emitting device having a straight-line shape is provided with: a pair of first and second electrodes each having a straight-line shape which face each other; and a phosphor layer having a straight-line shape provided so as to be sandwiched between the pair of electrodes, wherein at least one of the pair of first and second electrodes is a transparent electrode, at least one buffer layer is provided so as to be sandwiched between the first or second electrode and the phosphor layer, and the buffer layer makes the height of a potential barrier between the electrode and the phosphor layer which sandwich the buffer layer lower than the height of a Schottky barrier when the electrode and the phosphor layer are brought into direct contact. | 2009-08-27 |
20090213616 | CO-FUNCTIONAL MULTI-LIGHT SOURCE LUMENAIRES AND COMPONENTS THEREOF - A lumenaire system for providing illumination by distributing and mixing light from multiple sources of illumination which includes a first light source providing Lambertian light radiation and a second light source providing collimated illumination. There is a prismatic light guide structure having at least two functions, the first function being to refract the light radiation from the first light source disposed as to at least partially surround the light source, and the second function is to guide and distribute light from the second light source so as to mix it with light from the first light source. | 2009-08-27 |
20090213617 | Illumination Device for a Microscope - An illumination device for a microscope, in particular for an operation microscope, has a light source with an improved lifetime. The light source is in the form of a gas discharge lamp having a microwave generator, a microwave waveguide and an electrodeless bulb. The bulb contains a luminescent material and is coupled to the microwave waveguide so that microwaves can stimulate the luminescent material to emit light. | 2009-08-27 |
20090213618 | ILLUMINATING DEVICE - An illuminating device ( | 2009-08-27 |
20090213619 | LIQUID CRYSTAL DISPLAY DEVICE - In a method of forming a thin light guide plate which includes a compression step in an injection molding step, an optical pattern is liable to be adhered to a mold. Further, in removing the light guide plate from the mold using an ejector pin, a stress is concentrated on a local area of the light guide plate thus generating warping, deformation or irregularities in size of the light guide plate. To overcome such drawbacks, a liquid crystal display device is configured such that an optical pattern portion is compressed, and the light guide plate is removed by making use of a peripheral portion of a mold thus preventing the generation of stress in a local area of the light guide plate due to an ejector pin. | 2009-08-27 |
20090213620 | Lamp with Shunt Compression Spring - A lamp with shunt compressing spring has a socket, two electrodes, a shunt compression spring, an insulating casing, a sliding lid, a bulb holder and a bulb. The shunt compression spring is mounted in the socket and has two electric contacting ends contacting selectively and respectively with the electrodes. The insulating casing covers the shunt compression spring and has a first and a second through openings respectively exposing the electric contacting ends of the shunt compression spring. The sliding lid connects movably to the insulating casing, corresponds to the first through opening of the insulating casing and exposes the corresponding electric contacting end of the shunt compression spring. The bulb holder has a protrusion pressing the sliding lid to compress the shunt compression spring and keep the electric contacting end of the shunt compression spring exposing through the sliding lid from contacting with the corresponding electrode. | 2009-08-27 |
20090213621 | LUMINAIRE PROFILE - A luminaire profile comprises a hollow basic profile and an illuminant profile insertable in said basic profile via a snap-in connection. Concave supports are formed on opposite insides of the basic profile and convex supports are formed on the illuminant profile which correspond to the concave supports of the basic profile, with the concave supports and/or the convex supports—viewed in the cross-sectional direction—following a radius (R). | 2009-08-27 |
20090213622 | Powering Unit with Full Bridge and Wide Adjusting Range Circuit - There is described a powering unit comprising at least one transformer, at least one full bridge circuit via which a primary winding of the transformer is connected to a direct current voltage input, a secondary winding for triggering an output circuit with an output direct current voltage via a bridge-type rectifier circuit as well as an output choke coil and an output capacitor, and a discharge circuit consisting a diode, for a capacitor and of a resistor for reducing the secondary-side peak voltages. The powering unit has another secondary winding, another bridge-type rectifier circuit and another discharge circuit operable to trigger the output circuit with part of the output direct current voltage via the output choke coil and the output capacitor. Thus, there are fewer losses in the resistors and the performance is enhanced. | 2009-08-27 |
20090213623 | METHOD AND APPARATUS OF PROVIDING SYNCHRONOUS REGULATION CIRCUIT FOR OFFLINE POWER CONVERTER - A synchronous regulation circuit is provided. A secondary-side switching circuit is coupled to the output of the power converter to generate a synchronous signal and a pulse signal in response to an oscillation signal and a feedback signal. An isolation device transfers the synchronous signal from the secondary side to the primary side of the power converter. A primary-side switching circuit receives the synchronous signal to generate a switching signal for soft switching a transformer. The pulse signal is utilized to control a synchronous switch for rectifying and regulating the power converter. The synchronous switch includes a power switch and a control circuit. The control circuit receives the pulse signal for turning on or off the power switch. The power switch is connected between the transformer and the output of the power converter. A flyback switch is operated as a synchronous rectifier to freewheel the inductor current of the power converter. The flyback switch is turned on in response to the off state of the power switch. The turn-on period of flyback switch is correlated to the turn-on period of the power switch. | 2009-08-27 |
20090213624 | AUDIO APPARATUS, SWITCHING POWER SUPPLY, AND SWITCHING CONTROL METHOD - When power is turned on and in a state in which a power supply voltage is not supplied from the switching power supply to the second clock generating section, the first clock generating section generates a first clock signal with a frequency that is preset in the first clock generating section, without using a third clock signal from the frequency dividing section, to cause the first switching section to operate. By the first switching section operating, a power supply voltage is supplied from the switching power supply to the second clock generating section. After the second clock generating section has started to operate, a third clock signal (a clock signal obtained by dividing the frequency of a second clock signal generated by the second clock generating section) is supplied from the frequency dividing section to the first clock generating section. The first clock generating section generates a first clock signal with a frequency that is synchronized with the frequency of the third clock signal, to cause the first switching section to operate. | 2009-08-27 |
20090213625 | HIGH VOLTAGE GENERATION SYSTEMS AND METHODS - Systems and methods presented herein generally provide for the controlled voltage of bipolar electrical energy through the selected operation of power stages. In one embodiment, a system that provides electrical energy includes a power supply and at least two power stages coupled to the power supply. The power stages are operable to selectively output electrical energy. By selecting the number of power stages which are turned on at a given time the total voltage of the electrical energy is controlled at that time. The system may further include one or more controllers coupled to the power stages to control selection of the power stages and thereby vary the output voltage. | 2009-08-27 |
20090213626 | SWITCHING CONTROLLER CAPABLE OF REDUCING ACOUSTIC NOISE FOR POWER CONVERTERS - The present invention provides a switching controller capable of reducing acoustic noise of a transformer for a power converter. The switching controller includes a switching circuit, a comparison circuit, an activation circuit, and an acoustic-noise eliminating circuit. The acoustic-noise eliminating circuit comprises a first-check circuit, a second-check circuit, a pulse-shrinking circuit, and a limit circuit. The first-check circuit receives a switching-current signal which is correlated to a switching current of the power converter and a PWM signal to generate a trigger signal. The second-check circuit receives the trigger signal to generate a control signal. When the frequency of the trigger signal falls into audio band, the control signal will be enabled to limit the switching current. Therefore, the acoustic noise of the transformer can be eliminated. | 2009-08-27 |
20090213627 | POWER SUPPLY SYSTEM WITH ADAPTIVE BLOWN FUSE DETECTION USING NEGATIVE SEQUENCE COMPONENT - Existing measurements of an input component (such as voltage or current) in a three phase power supply system are decomposed into a negative sequence component. The negative sequence component, which is significantly higher when a rectifier fuse is blown, is compared to a threshold and a determination made that a rectifier fuse is blown when the negative component exceeds the threshold. In an aspect, an adaptive algorithm is used to make the detection work better in the range of the nominal frequency of the input voltage. In an aspect, the negative sequence is determined indirectly from the existing measurements. | 2009-08-27 |
20090213628 | OFFLINE SYNCHRONOUS RECTIFYING CIRCUIT WITH CURRENT TRANSFORMER FOR SOFT SWITCHING POWER CONVERTERS - A synchronous rectifying circuit of soft switching power converter is provided to improve the efficiency. The integrated synchronous rectifier includes a power transistor connected from a transformer to the output of the power converter for rectifying. A controller having a latch circuit generates a drive signal to control the power transistor in response to a switching-current signal. A current transformer generates the switching-current signal in response to the switching current of the transformer. The controller turns off the power transistor when the switching-current signal is lower than a second threshold. The power transistor is turned on once the switching-current signal is higher than a first threshold. Furthermore, a pulse-width detection circuit generates a pulse signal coupled to disable the drive signal and turn off the power transistor. | 2009-08-27 |
20090213629 | POWERING CIRCUIT OF AC-DC CONVERTER - A powering circuit of an AC-DC converter, for converting a high AC input voltage into a low DC output voltage to provide a load voltage in a stable DC bias range, includes a rectifier, a sensing circuit, a control switching circuit, and a voltage regulating capacitor. The rectifier has a primary side coupled to an AC power supply and a secondary side for outputting a DC power supply. The sensing circuit compares the AC input voltage with a preset reference voltage, and turns on a second switch in the control switching circuit when the AC input voltage is lower than the reference voltage, thereby providing a low DC output voltage. The control switching circuit sustains the DC output voltage in a stable DC bias range. Therefore, in addition to reducing the power consumption of the second switch, this circuit structure is simple and can achieve the purpose of circuit integration. | 2009-08-27 |
20090213630 | Current-transformed power source connecting circuit device - A current-transformed power source connecting circuit device comprises a power source plug-in, in connection with an external power source; a current transformer, having a primary and a secondary windings, the primary winding of which is connected in series to a current path of the power source plug-in for detection of a current; a main socket, capable of connecting externally to a main electrical apparatus, one end of which is connected to the current transformer; a rectifying means, in connection with the secondary winding of the current transformer, for rectification of a current from the current transformer; a switching means, for receiving a voltage from the rectifying means, which is switched on at a time that the received voltage is sufficient and switched off at a time that the voltage is insufficient; and at least one subsidiary socket, for connecting with the switching means and parallel-connection with the main socket, capable of connecting to a peripheral electrical apparatus. | 2009-08-27 |
20090213631 | STEP-DOWN SWITCHING REGULATOR - A step-down switching regulator prevents an output voltage undershoot and enables a quick lowering of an output voltage immediately after turning off of power supply. The step-down switching regulator includes an NMOS transistor connected between an output terminal and a ground voltage and another NMOS transistor connected in parallel with a synchronous rectification transistor. Upon reception of an on/off signal for terminating the operation of the switching regulator, the NMOS transistors are turned on into an on-state. | 2009-08-27 |
20090213632 | System and Method for Providing Content-Addressable Magnetoresistive Random Access Memory Cells - A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking. | 2009-08-27 |
20090213633 | Four vertically stacked memory layers in a non-volatile re-writeable memory device - A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array. | 2009-08-27 |
20090213634 | STACKED MEMORY AND FUSE CHIP - A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit. | 2009-08-27 |
20090213635 | SEMICONDUCTOR MEMORY DEVICE HAVING REPLICA CIRCUIT - A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively. | 2009-08-27 |
20090213636 | Layered bi compound nanoplate array of such nanoplates, their making methods and devices using them | 2009-08-27 |
20090213637 | Ferroelectric random access memory device - An FRAM device can includes first ferroelectric capacitors, second ferroelectric capacitors, first plate lines and second plate lines. The first ferroelectric capacitors can be connected between word lines and bit lines. The second ferroelectric capacitors can be connected between the word lines and bit line bars. The first plate lines can be connected to upper electrodes of the first ferroelectric capacitors. The second plate lines can be connected to upper electrodes of the second ferroelectric capacitors. Thus, the first ferroelectric capacitors connected to the bit lines and the second ferroelectric capacitors connected to the bit line bars can be connected to the different plate lines, so that data can be output from any one of the bit line and the bit line bar. As a result, a layout of a core region can be simplified. | 2009-08-27 |
20090213638 | Magnectic memory element and magnetic memory apparatus - A magnetic memory element is provided with first and second ferromagnetic fixed layers, a ferromagnetic memory layer, nonmagnetic first and second intermediate layers. The memory layer is disposed between the first and second fixed layers, and has a variable magnetization direction. In order to cancel asymmetry of a write-in current of the element, the element is provided so that the memory layer receives a larger perpendicular stray field from the first fixed layer than from the second fixed layer, and then a magnetization direction of a portion of the memory layer being nearest to the first intermediate layer and the magnetization direction of the first fixed layer are antiparallel to each other whenever a magnetization direction of a portion of the memory layer being nearest to the second intermediate layer and the magnetization direction of the second fixed layer are parallel to each other, and vice versa. | 2009-08-27 |
20090213639 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively. | 2009-08-27 |
20090213640 | CURRENT DRIVEN MEMORY CELLS HAVING ENHANCED CURRENT AND ENHANCED CURRENT SYMMETRY - A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on. | 2009-08-27 |
20090213641 | MEMORY WITH ACTIVE MODE BACK-BIAS VOLTAGE CONTROL AND METHOD OF OPERATING SAME - Data storage cells of a static random access memory array are selectively provided with back-bias voltages to reduce current leakage during an active mode of operation. Circuitry electrically connected with the array receives control signals and provides the back-bias voltages to certain idle data storage cells of the array based on the control signals. | 2009-08-27 |
20090213642 | Integrated Circuit, Memory Cell Arrangement, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell - According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured to route a programming current through the magneto-resistive memory cell, wherein the programming current programs the magnetizations of the first ferromagnetic layer and of the second ferromagnetic layer by spin induced switching effects. | 2009-08-27 |
20090213643 | Integrated Circuit and Method of Improved Determining a Memory State of a Memory Cell - According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the first potential, thereby generating a memory state sensing current flowing through the resistivity changing memory cell; controlling the strength of the second potential in dependence on the strength of the memory state sensing current such that the strength of the memory state sensing current is kept constant. | 2009-08-27 |
20090213644 | Method and apparatus for accessing a multi-mode programmable resistance memory - A memory is configurable among a plurality of operational modes. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix. | 2009-08-27 |
20090213645 | Method and apparatus for accessing a multi-mode programmable resistance memory - A memory is configurable among a plurality of operational modes and types of interfaces. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix. Individual operational modes may be matched to individual interfaces, operated one at a time or in parallel. | 2009-08-27 |
20090213646 | Phase-change random access memories capable of suppressing coupling noise during read-while-write operation - A semiconductor memory device includes at least one write global bit line connected to a plurality of local bit lines and at least one read global bit line connected to the local bit lines. The phase-change memory device having the write global bit line and the read global bit line suppress coupling noise generated during a read-while-write operation. | 2009-08-27 |
20090213647 | Phase-change random access memory capable of reducing word line resistance - A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased. | 2009-08-27 |
20090213648 | Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor - An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal. | 2009-08-27 |
20090213649 | Semiconductor processing device and IC card - A semiconductor processing device according to the invention includes a first non-volatile memory ( | 2009-08-27 |
20090213650 | MIS-TRANSISTOR-BASED NONVOLATILE MEMORY - A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof. | 2009-08-27 |
20090213651 | TWO-BIT NON-VOLATILE FLASH MEMORY CELLS AND METHODS OF OPERATING MEMORY CELLS - A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell. Then a control activation voltage is applied to a first bit line select and a second bit line select, each bit line associated with the first bits and the second bits of each memory cell, respectively. Then an operating voltage is applied to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts. | 2009-08-27 |
20090213652 | PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE - Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse. | 2009-08-27 |
20090213653 | PROGRAMMING OF ANALOG MEMORY CELLS USING A SINGLE PROGRAMMING PULSE PER STATE TRANSITION - A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells. The data is stored in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse. | 2009-08-27 |
20090213654 | PROGRAMMING ANALOG MEMORY CELLS FOR REDUCED VARIANCE AFTER RETENTION - A method includes defining a nominal level of a physical quantity to be stored in analog memory cells for representing a given data value. The given data value is written to the cells in first and second groups of the cells, which have respective first and second programming responsiveness such that the second responsiveness is different from the first responsiveness, by applying to the cells in the first and second groups respective, different first and second patterns of programming pulses that are selected so as to cause the cells in the first and second groups to store respective levels of the physical quantity that fall respectively in first and second ranges, such that the first range is higher than and the second range is lower than the nominal level. The given data value is read from the cells at a later time. | 2009-08-27 |
20090213655 | MEMORY SYSTEM WITH USER CONFIGURABLE DENSITY/PERFORMANCE OPTION - The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block. | 2009-08-27 |
20090213656 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 2009-08-27 |
20090213657 | Electronic Device Comprising Non Volatile Memory Cells and Corresponding Programming Method - A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor. | 2009-08-27 |
20090213658 | READING NON-VOLATILE STORAGE WITH EFFICIENT SETUP - A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the unselected non-volatile storage element from the intermediate voltage to a read enable voltage. The control gate voltage for the selected non-volatile storage element is raised from a standby voltage (which is different than the intermediate voltage) to a read compare voltage. While the control gate for the selected non-volatile storage element is at the read compare voltage and the control gate for the unselected non-volatile storage element is at the read enable voltage, the state of the selected non-volatile storage element is sensed to determine information about the data stored in the selected non-volatile storage element. | 2009-08-27 |
20090213659 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 2009-08-27 |
20090213660 | Three-Terminal Single Poly NMOS Non-Volatile Memory Cell - A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed. | 2009-08-27 |
20090213661 | NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS - A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array. | 2009-08-27 |
20090213662 | MEMORY DEVICE AND APPLICATIONS THEREOF - A system that incorporates teachings of the present disclosure may include, for example, a memory device having a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values. Additional embodiments are disclosed. | 2009-08-27 |
20090213663 | Circuits, devices, systems, and methods of operation for capturing data signals - Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit. The write control circuit determines which of the data digits was latched first relative to an external timing, and generate a select control signal to drive the captured data digits onto the data bus in the order in which the data digits were received. | 2009-08-27 |
20090213664 | NONVOLATILE MEMORY UTILIZING MIS MEMORY TRANSISTORS WITH FUNCTION TO CORRECT DATA REVERSAL - A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell. | 2009-08-27 |
20090213665 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a nonvolatile semiconductor memory device which reads out a memory cell at high speed. A minute current source ( | 2009-08-27 |
20090213666 | LOW VOLTAGE OPERATION BIAS CURRENT GENERATION CIRCUIT - Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a drain coupled to a first node, and a gate coupled to a second node, a second transistor having a source coupled to a reference, and a drain and a gate coupled to the first node, a third transistor having a source coupled to the reference, a drain coupled to a third node, and a gate coupled to the first node, a first resistive element coupled between the voltage supply and the third node, a second resistive element coupled between the voltage supply and the second node, and a fourth transistor having a source coupled to the reference, a drain coupled to the second node, and a gate coupled to the third node. | 2009-08-27 |
20090213667 | SEMICONDUCTOR MEMORY DEVICE ENHANCING RELIABILITY IN DATA READING - An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition. | 2009-08-27 |
20090213668 | ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT - A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon. | 2009-08-27 |
20090213669 | HIGH VOLTAGE SWITCH CIRCUIT HAVING BOOSTING CIRCUIT AND FLASH MEMORY DEVICE INCLUDING THE SAME - A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies a feedback voltage to an input node in response to a switch control voltage generated from the output node when the output node is precharged. The boosting circuit boosts the feedback voltage and outputs a boosting voltage to the output node, in response to clock signals, thereby increasing the switch control voltage. The high voltage switch is turned on or off in response to the switch control voltage, and is turned on to receive a high voltage and output the received high voltage. The boosting circuit includes an amplification circuit of a cross-coupled type. | 2009-08-27 |
20090213670 | ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS - Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device. | 2009-08-27 |
20090213671 | CIRCUIT AND METHOD FOR CONTROLLING REDUNDANCY IN SEMICONDUCTOR MEMORY APPARATUS - Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral circuit redundancy control block also buffers and latches an external address to generate a global address by comparing the external address with a predetermined output signal of a fuse circuit. The memory bank redundancy control block receives the global address corresponding to the internal command to selectively activate a redundancy word line or a main word line, such that the fuse circuit is provided in the peripheral circuit redundancy control block. | 2009-08-27 |
20090213672 | LOGIC EMBEDDED MEMORY HAVING REGISTERS COMMONLY USED BY MACROS - A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register. | 2009-08-27 |
20090213673 | Data processor memory circuit - A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state. | 2009-08-27 |
20090213674 | Method and device for controlling a memory access and correspondingly configured semiconductor memory - Method and device for controlling a memory access and correspondingly configured semiconductor memory | 2009-08-27 |
20090213675 | SEMICONDUCTOR MEMORY DEVICE - A memory includes memory cells, wherein in a first cycle of writing first logic data, sense amplifiers apply a first potential to bit lines, drivers apply a second potential to a selected word line and a third potential to a selected source line, and the second and third potentials with reference to the first potential have the same polarities as polarities of the carriers, and in a second cycle of writing second logic data, the sense amplifiers apply a fourth potential to a selected bit line, the drivers apply a fifth potential to the selected word line and a sixth potential to the selected source line and, the sixth potential is nearer to the first potential than the second and third potentials, the fifth potential with reference to the sixth potential has the same polarity as polarities of the carriers, and the fourth potential with reference to the sixth potential has a polarity opposite to the polarities of the carriers. | 2009-08-27 |
20090213676 | Memory Device - A nonvolatile memory device contains at least one nonvolatile memory module and an electrical buffer for buffering a supply voltage for the at least one nonvolatile memory module. A microprocessor may be connected in parallel or serial fashion to the memory device, or may contain the memory device. | 2009-08-27 |
20090213677 | Memory Cell Array - A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level. | 2009-08-27 |
20090213678 | High yielding, voltage, temperature, and process insensitive lateral poly fuse memory - The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding, voltage, temperature, and process insensitive lateral poly fuse memory. In one embodiment, a fusible link memory circuit includes a fusible link memory element and a programming circuit. The programming circuit includes a replica of the fusible link memory element and a programming current source for producing a known current density in the fusible link memory element in spite of variations including at least process variations. | 2009-08-27 |
20090213679 | POWER DEPENDENT MEMORY ACCESS - An apparatus and method of accessing a memory by determining available power, and accessing a number of bits of the memory in parallel, wherein the number of bits accessed in parallel is based at least in part on the available power. | 2009-08-27 |
20090213680 | METHOD AND APPARATUS FOR MONITORING MEMORY ADDRESSES - Disclosed herein is a method and apparatus for monitoring a memory address transmitted along an address path and converted into a row or column address of memory. The method includes: generating a path decision signal for deciding whether to connect the address path to a data terminal of the memory according to a memory command; and when the address path is connected to the data terminal of the memory in response to the path decision signal, transmitting a memory address, corresponding to the memory command, to the data terminal of the memory so that the memory address is monitored through the data terminal of the memory. | 2009-08-27 |
20090213681 | Counter-rotating twin screw extruder - A screw extruder having a body forming a chamber of two barrels housing two counter-rotating axis-parallel rotors, a supply port for the material to be mixed in the chamber at one end of the body, a discharge port for discharging the mixed material at the other end of the body, a conveying section with screws for feeding the material from the supply port downstream to a mixing section which comprises at least two mixing zones, each mixing zone having at least one forward-conveying wing and at least one backward-conveying wing downstream of the forward-conveying wing on each rotor characterized in that a throttle valve is provided in the chamber downstream of the mixing section, and downstream of the throttle valve a second conveying section with screws and a second mixing section are provided. | 2009-08-27 |
20090213682 | Method of Decreasing Acetaldehyde Level in a Molded Article - There is provided a method for decreasing acetaldehyde level in a molded article. The method of decreasing acetaldehyde content in a molded article to be produced comprises introducing into a feed throat of an injection unit a PET material to be plasticized, the PET material having been dried in a pre-treatment chamber ; and introducing into the feed throat an un-treated agent configured to increase moisture level of the PET material to be plasticized. In some embodiments of the present invention, the un-treated agent is also configured to provide additional lubrication to the plasticizing screw. | 2009-08-27 |
20090213683 | KNEADING DISC SEGMENT AND TWIN-SCREW EXTRUDER - The kneading disc segment according to the present invention comprises plural disc sets each comprising two kneading discs and mounted on a kneading screw ( | 2009-08-27 |
20090213684 | Apparatus for distribution of a gas into a body of liquid - A mixing system includes a disc with a plurality of openings combined with a mixer located below the disc with the disc and mixer positioned with respect to one another such that gas exiting openings in the mixer may rise to contact the openings in the disc to sheer the gas into fine bubbles in order to enhance aeration of the liquid. | 2009-08-27 |
20090213685 | Electric-Motor Kitchen Appliance Comprising an Electric or Electronic Control - An electric-motor kitchen appliance, in particular an electric-motor handheld device, preferably a hand mixer, includes a switch. The invention also relates to a finger-actuated electric control for the switch, and to a method for switching on/off a kitchen appliance. The switch is unlocked when the safety switch is actuated by the finger of a user. The safety switch is electronically switched. The possibility of unintentionally operating the electric-motor of the kitchen appliance is reduced due to the manual operation of the two separate switches. As a result, the safety of the electric-motor kitchen appliance in the household is significantly increased. | 2009-08-27 |
20090213686 | Method and Apparatus for Feeding Gaseous or Liquid Fluid into a Medium - The present invention relates to a method of and an apparatus for feeding gaseous or liquid fluid into a medium. The method and apparatus in accordance with the present invention are especially suitable in various fields of industry for mixing gaseous and liquid chemicals and steams into a flow containing at least liquid. The method and apparatus in accordance with the present invention are most preferably suitable for feeding steam into the fiber suspensions of wood processing industry. Most preferably the method and apparatus in accordance with the present invention is used, for example, in such a way that a side flow is taken from a first medium flowing along a suction duct ( | 2009-08-27 |
20090213687 | Multi Fluid Injection Mixer - Multi Fluid Injection Mixer for injecting gas and/or liquid as admixture fluid to gas and/or liquid flowing through a pipe, and homogeneously mixing the admixture fluids and pipe fluids, said injection mixer constituting a section of the pipe, distinguished in that the injection mixer is comprising: at least one contacting element having at least one contacting surface facing and deflecting some of the pipe fluid flow, forming a constriction to the internal cross-section of the pipe, such that the pipe fluid flow is accelerated and fluid flowing in the vicinity of said surface is deflected to flow along the surface until the surface end over a sharp edge at the point of maximum constriction and flow velocity, at least one injection element arranged with a fluid connection to said surface of the contacting element, such that admixture fluid can be injected onto said surface and along said surface be entrained by the flowing pipe fluid over the sharp edge, but for a contacting element formed as a contracting pipe section at least two injection elements are provided. | 2009-08-27 |
20090213688 | Galvanized conveyor - A conveyor assembly for use with a vertical mixer is disclosed. The conveyor assembly has a conveyor support frame having a galvanized coating to protect the conveyor support frame from rust and wear. The conveyor assembly may further include a protected conveyor bed. The conveyor bed may comprise a polymer such as a high density polyethylene. Alternatively, the conveyor bed may include one or more creases and also be protected by a galvanizing coating. | 2009-08-27 |
20090213689 | ULTRASONIC LOGGING METHODS AND APPARATUS FOR AUTOMATICALLY CALIBRATING MEASURES OF ACOUSTIC IMPEDANCE OF CEMENT AND OTHER MATERIALS BEHIND CASING - Methods and apparatus for in situ, continuous, automatic, and real-time acoustic impedance calibration of a transducer in an acoustic logging system. By taking the frequency characteristics of the ultrasonic transducer which are present in the internal casing reflection and convolving them with the frequency characteristics of the casing being logged, a theoretical model is created with a theoretical acoustic impedance fluid producing a theoretical free pipe signal at each measure point. The measured signal is then compared to the theoretical free pipe signal thereby yielding a calibrated acoustic impedance value for at each measure point. The only model employed is in the theoretical calculation of spectrum characteristics of free pipe. | 2009-08-27 |
20090213690 | Composite Transducer for Downhole Ultrasonic Imaging and Caliper Measurement - A transducer assembly for downhole imaging includes a 1-3 Piezoelectric composite transducer of high Q ceramic rods in a polymer matrix. The assembly also includes a Teflon® window, a fluid-filled cavity adjacent to the window, and impedance matching material between the composite transducer and the fluid. The transducer is positioned to reduce the reverberation time. | 2009-08-27 |
20090213691 | SOURCE SIGNATURE DECONVOLUTION METHOD - A method of filtering seismic signals is described using the steps of obtaining the seismic signals generated by activating a seismic source and recording signals emanating from the source at one or more receivers; defining a source signature deconvolution filter to filter the seismic signal, wherein the filter is scaled by a frequency-dependent term based on an estimate of the signal-to-noise (S/N) based on the spectral power of a signal common to a suite of angle-dependent far-field signatures normalized by the total spectral power of the signatures within the angular suite and performing a source signature deconvolution using the source signature deconvolution filter. | 2009-08-27 |