34th week of 2010 patent applcation highlights part 27 |
Patent application number | Title | Published |
20100214810 | Push-Pull Inverter - A push-pull inverter allows a power supply unit to supply an input voltage to two primary windings of a transformer, and allows MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) to drive the transformer in push-pull mode so as to increase the input voltage supplied from the power supply unit and to output the increased voltage as an output voltage from a secondary winding of the transformer. The two primary windings of the transformer are mixedly wound on a same bobbin without being separated, so that when the transformer is driven, the two primary windings of the transformer are prevented from resonating with each other. This makes it possible to prevent turbulence in the input current, thereby reducing loss (power loss) of the MOSFETs, allowing the transformer to have a high efficiency. | 2010-08-26 |
20100214811 | CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES - A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word. | 2010-08-26 |
20100214812 | STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). | 2010-08-26 |
20100214813 | Memory module having a plurality of phase change memories, buffer RAM and nand flash memory - A memory module comprises a plurality of main memories; a buffer RAM configured to temporarily store data being provided to or read from the main memories and to perform a buffer function between an external device and the main memories; and a NAND flash memory configured to store data of the buffer RAM during an interruption of power being supplied to the buffer RAM. | 2010-08-26 |
20100214814 | SEMICONDUCTOR MEMORY DEVICE, MEMORY DEVICE SUPPORT AND MEMORY MODULE - In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal. | 2010-08-26 |
20100214815 | MULTIPLE THRESHOLD VOLTAGE REGISTER FILE CELL - In one embodiment, a memory circuit comprises a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of cross-coupled inverters. A plurality of transistors that form the pair of inverters have a first nominal threshold voltage. The first transistor is coupled to a first bit line, and has a second nominal threshold voltage that is lower than the first nominal threshold voltage. More specifically, in one embodiment, the first transistor is a write transistor and another write transistor having the second nominal threshold voltage is coupled to the other node of the pair of cross-coupled inverters. In an embodiment, a register file comprises a bit storage section comprising at least one pair of cross-coupled inverters, wherein transistors forming the inverters have a first nominal threshold voltage; a write transistor section comprising a first plurality of transistors; and a read transistor section comprising a second plurality of transistors. The first transistors and the second transistors have a second nominal threshold voltage that is lower than the first nominal threshold voltage. The write transistor section is physically located on a first side of the bit storage section, and the read transistor section is physically located on a second side of the bit storage section opposite the first side. | 2010-08-26 |
20100214816 | SEMICONDUCTOR DEVICES SUPPORTING MULTIPLE FUSE PROGRAMMING MODES - Semiconductor devices include a plurality of fuses and a plurality of program circuits, respective ones of which are configured to program respective ones of the plurality of fuses. The devices further include a shift register configured to activate at least two of the program circuits. In some embodiments, the shift register includes a first shift register configured to generate first select signals and a second shift register configured to generate second select signals corresponding to data to be programmed to the plurality of fuses. Respective ones of the program circuits may be configured to program respective ones of the fuses responsive to respective pairs of the first select signals and the second select signals. | 2010-08-26 |
20100214817 | SEMICONDUCTOR STORAGE DEVICE AND STORAGE SYSTEM - A pn junction type solar cell is formed in a predetermined region on a substrate made of glass. Light emitted from a light emitting unit reaches an n-type semiconductor layer after it passed through substrate. The solar cell generates electromotive force corresponding to a quantity of the emitted light. A control circuit, a mask ROM, a transmitting circuit and an antenna are formed on an upper side of the solar cell. A surface of a semiconductor storage device is entirely covered with an insulating film to block entry of outside air. The insulating film is typically formed of physicochemically stable glass or silicon dioxide. | 2010-08-26 |
20100214818 | Memory device and operation method of the same - Disclosed herein is a memory device including: first and second wires; memory cells including a variable-resistance storage element having a data storage state making a transition by a change of a voltage applied and an access transistor connected in series between the first and second wires; driving control sections controlling a direct verify sub-operation by applying a write/erase pulse between the first and second wires in a data write/erase operation respectively for causing a cell current to flow between the first and second wires through the memory cell for a transition of the data storage state; sense amplifiers sensing an electric-potential change occurring on the first wire in accordance with control on the direct verify sub-operation; and inhibit control sections determining whether or not to inhibit a sense node of the sense amplifier from electrically changing at the next sensing time on the basis of an electric potential appearing at the sense node at the present sensing time. | 2010-08-26 |
20100214819 | RESISTIVE MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF CONTROLLING INPUT AND OUTPUT OPERATIONS OF THE SAME - A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage | 2010-08-26 |
20100214820 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines and a control circuit configured to apply a first voltage to selected one or more of the first lines, and to apply a second voltage having a value smaller than the first voltage to selected one of the second lines, such that a certain potential difference is applied to selected one or more of the memory cells. The control circuit adjusts the second voltage based on a position of the selected one or more of the memory cells within the memory cell array and a number of the selected one or more of the memory cells on which an operation is simultaneously executed, during application of the potential difference to the selected one or more of the memory cells. | 2010-08-26 |
20100214821 | CAPACITIVE DIVIDER SENSING OF MEMORY CELLS - The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell. | 2010-08-26 |
20100214822 | VOLTAGE-STEPPED LOW-POWER MEMORY DEVICE - This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process. | 2010-08-26 |
20100214823 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR - A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer. | 2010-08-26 |
20100214824 | Converting SRAM cells to ROM Cells - A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value. | 2010-08-26 |
20100214825 | Programming MRAM Cells Using Probability Write - A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell. | 2010-08-26 |
20100214826 | MAGNETIC RANDOM ACCESS MEMORY, WRITE METHOD THEREFOR, AND MAGNETORESISTANCE EFFECT ELEMENT - A magnetic random access memory includes: a first ferromagnetic layet; an insulating layer provided adjacent to the first ferromagnetic layer; and a first magnetization pinned layer provided adjacent to the insulating layer on a side opposite to the first ferromagnetic layer. The first ferromagnetic layer includes a magnetization free region, a first magnetization pinned region, and a second magnetization pinned region. The magnetization free region has reversible magnetization, and overlaps with the second ferromagnetic layer. The first magnetization pinned region has first pinned magnetization, and is connected to a part of the magnetization free region. The second magnetization pinned region has second pinned magnetization, and is connected to a part of the magnetization free region. The first ferromagnetic layer has magnetic anisotropy in a direction perpendicular to a film surface. The first pinned magnetization and the second pinned magnetization are pinned antiparallel to each other in the direction perpendicular to the film surface. | 2010-08-26 |
20100214827 | Integrated Circuit with Memory Cells Comprising a Programmable Resistor and Method for Addressing Memory Cells Comprising a Programmable Resistor - A module comprises a bus invert encoder ( | 2010-08-26 |
20100214828 | SEMICONDUCTOR DEVICE - In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus. | 2010-08-26 |
20100214829 | MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range. | 2010-08-26 |
20100214830 | MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION - Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell. | 2010-08-26 |
20100214831 | Memory device, memory system having the same, and programming method of a memory cell - A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data. | 2010-08-26 |
20100214832 | PHASE-CHANGE RANDOM ACCESS MEMORY - A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal. | 2010-08-26 |
20100214833 | SEMICONDUCTOR DEVICE - For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized. | 2010-08-26 |
20100214834 | THIN FILM MAGNETIC MEMORY DEVICE INCLUDING MEMORY CELLS HAVING A MAGNETIC TUNNEL JUNCTION - In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, and therefore, the data read speed can be increased. | 2010-08-26 |
20100214835 | Magnetic shielding in magnetic multilayer structures - Techniques and device designs associated with devices having magnetically shielded magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves that are configured to operate based on spin-transfer torque switching. | 2010-08-26 |
20100214836 | Semiconductor storage apparatus - A semiconductor storage apparatus has a control circuit. The control circuit deactivates the first and second amplifier circuits, turns off the first, second, fourth and fifth switch circuits, and turns on the third and sixth switch circuits in response to an external signal based on reduction of current dissipation of a power supply which supplies the power supply voltage. | 2010-08-26 |
20100214837 | NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES - A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage. | 2010-08-26 |
20100214838 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer. | 2010-08-26 |
20100214839 | NAND FLASH MEMORY STRING APPARATUS AND METHODS OF OPERATION THEREOF - A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection transistor, wherein the second selection transistor has a process defined threshold voltage. | 2010-08-26 |
20100214840 | MULTI-DOT FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME - A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical. | 2010-08-26 |
20100214841 | MEMORY APPARATUS AND METHOD THEREOF FOR OPERATING MEMORY - A memory apparatus and a method thereof for operating a memory are provided herein. The apparatus has the memory and a controller. The memory has a plurality of memory cells, and each the memory cells has a first side and the second side. Each of the first side and the second side is programmable to store one bit of data. The controller programs the first sides and the second sides of the memory cells to different levels. Several threshold voltage distributions of the programmed memory cells could be overlapped with each other. The controller distinguishes the bits of the memory cells by comparing the threshold voltages of the memory cells with the different levels and by comparing the threshold voltages with those of neighbor sides. | 2010-08-26 |
20100214842 | NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A nonvolatile semiconductor memory includes a transistor, a first MOS, a second MOS, a first voltage circuit, and a second voltage circuit. The transistor includes a accumulation layer, a control gate, and a first impurity diffused layer. The first MOS includes a first electrode and a second layer. The second MOS includes a second electrode and a third layer, after the channels being formed, the first MOS and the second MOS being cut off. The first voltage circuit applies a first voltage to an active region to generate a forward bias. The second voltage circuit applies a second voltage, and a third voltage to the control gate of the transistor, after the first voltage circuit charges the first to third impurity diffused layer to the first voltage, the second voltage circuit applying the second voltage and the third voltage to the control gate of the transistor. | 2010-08-26 |
20100214843 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition. | 2010-08-26 |
20100214844 | Memory system and programming method thereof - Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage. | 2010-08-26 |
20100214845 | NAND MEMORY CELL ARRAY, NAND FLASH MEMORY HAVING NAND MEMORY CELL ARRAY, DATA PROCESSING METHOD FOR NAND FLASH MEMORY - A NAND memory cell array which can be programmed in a hot carrier injection scheme, a NAND flash memory having the NAND memory cell array, and a data processing method for the NAND flash memory are provided. The NAND memory cell array includes one select transistor and at least two storage transistors. The NAND memory cell array can be programmed by controlling a bulk bias voltage and a voltage applied to a gate in the hot carrier injection scheme. | 2010-08-26 |
20100214846 | Flash Memory Devices, Methods for Programming the Same, and Memory Systems Including the Same - A programming method of a nonvolatile memory device is provided including: applying a local voltage to a first unselected word line; applying a local voltage to a second unselected word line, after the local voltage is applied to the first unselected word line; and applying a pass voltage to the first unselected word line, after the local voltage is applied to the second unselected word line. Related devices and systems are also provided herein. | 2010-08-26 |
20100214847 | SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD - A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage. | 2010-08-26 |
20100214848 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a first node, a current source configured to have a current value determined according to a voltage supplied to the first node, and a memory cell string coupled to the first node, the memory cell string including at least one memory cell. Whether a memory cell included in the memory cell string has been programmed is determined based on the voltage supplied to the first node. | 2010-08-26 |
20100214849 | PAGE BUFFER CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed. | 2010-08-26 |
20100214850 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING DATA THEREIN - A semiconductor memory device includes a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line and a source line, respectively. The semiconductor memory device also includes dummy cells inserted in the NAND cell unit adjacent to the first and second selection transistors, respectively. The dummy cells in the NAND cell unit are erased simultaneously with the memory cells under a weaker erase potential condition than that for the memory cells and set in a higher threshold distribution than an erased state of the memory cells. | 2010-08-26 |
20100214851 | System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor. | 2010-08-26 |
20100214852 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 2010-08-26 |
20100214853 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare the measured threshold voltage distribution with a reference threshold voltage distribution, and to determine a read voltage having a least amount of errors upon the read operation being performed. | 2010-08-26 |
20100214854 | SHIFT REGISTER PROVIDING GLITCH FREE OPERATION IN POWER SAVING MODE - Disclosed is a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock, and a drive operation controller. The drive operation controller includes; a first logic gate configured to receive and logically combine selected outputs from selected ones of the plurality of flip-flops to generate a gate output signal, a drive operation controller flip-flop configured to receive the gate output signal and retime the gate output signal in response to a first clock applied to a clock terminal of a first flip-flop in the plurality of flip-flops to generate a clock enable signal, an inverter configured to receive the clock enable signal and generate an inverted clock enable signal, and a second logic gate configured to receive and logically combine the first clock and the inverted clock enable signal to generate a second clock, wherein the second clock signal is applied to a clock terminal of at least one later stage flip-flop following the first flip-flop in the plurality of flip-flops. | 2010-08-26 |
20100214855 | METHODS OF QUANTIZING SIGNALS USING VARIABLE REFERENCE SIGNALS - Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts. | 2010-08-26 |
20100214856 | Method to improve the write speed for memory products - A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip. | 2010-08-26 |
20100214857 | MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF - An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell. | 2010-08-26 |
20100214858 | Delay locked loop circuit for preventing failure of coarse locking - A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance. | 2010-08-26 |
20100214859 | Implementing Boosted Wordline Voltage in Memories - A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor. | 2010-08-26 |
20100214860 | SENSE AMPLIFIER SCHEME FOR LOW VOLTAGE SRAM AND REGISTER FILES - A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output. | 2010-08-26 |
20100214861 | Semiconductor memory cell array and semiconductor memory device having the same - A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage | 2010-08-26 |
20100214862 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 2010-08-26 |
20100214863 | MEMORY POWER GATING CIRCUIT AND METHODS - A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage. | 2010-08-26 |
20100214864 | MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode. | 2010-08-26 |
20100214865 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal. | 2010-08-26 |
20100214866 | SEMICONDUCTOR MEMORY DEVICE WITH REDUCED POWER NOISE - A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period. | 2010-08-26 |
20100214867 | MAGNETIC DRIVE FOR FOOD PROCESSING APPARATUS - Food processing apparati including magnetic drives are described herein. According to one exemplary embodiment, a food processing apparatus may include a motor having a motor shaft, a rotor rotatably mounted on the motor shaft, and a stator producing an electromagnetic field for interacting with the rotor. The rotor may magnetically drive a drive plate coupled to an impeller inside a food-contact chamber. | 2010-08-26 |
20100214868 | Agitator and Agitation Method - It is an object of the present invention to provide an agitator equipped with a bottom paddle that has favorable agitation performance also in a streamline flow region of low Re number and to provide an agitation method. According to the agitator and the agitation method of the present invention, an object is agitated within an agitation tank by the use of an agitator that includes a rotating shaft that is disposed outside of the tank along the axis of a vertically oriented cylindrical agitation tank to be rotatable, and a flat agitation impeller made up of a bottom paddle, which lower end edge is formed to be of a shape that conforms with a tank bottom wall such that a specified clearance is formed between the lower end edge and the tank bottom wall, the bottom paddle being provided with a communicating portions at a positions away from the lower end edge upward by a specified amount for communicating between the front side and the rear side of the bottom paddle, and being mounted to the rotating shaft so as to locate close to the tank bottom wall and extend towards a sidewall of the tank. | 2010-08-26 |
20100214869 | Apparatus and Methods for Controlling Position of Marine Seismic Sources - Apparatus and methods are described for remotely controlling position of marine seismic equipment. One apparatus comprises a source connected to a tow member; and an adjustment mechanism connected to the source and the tow member, the adjustment mechanism adapted to actively manipulate an angle of attack of the source. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2010-08-26 |
20100214870 | METHOD AND APPARATUS FOR DYNAMIC EXTRACTION OF EXTREMA-BASED GEOMETRIC PRIMITIVES IN 3D VOXEL VOLUMES - Methods and systems for investigating subterranean formations are disclosed. A method for extracting geological horizon on-demand from a 3D seismic data set, comprises collecting 3D seismic data and generating 3D seismic extrema cubes; obtaining a user-defined seed point in the 3D seismic data set; determining a starting extrema point for extracting the geological horizon, wherein the starting extrema point is associated with the seed point; growing an extrema patch consisting of multiple extrema points from multiple traces, wherein the growth begins from the starting extrema point; capturing statistics of the growing extrema patch; and outputting the extrema patch as the geological horizon, including spatial and attribute statistics. The geological horizon is incorporated into a collection with other geological horizons for subsequent analysis and interpretation for areal extent through combining geological horizon segments and geochronologic ordering based on positional overlapping of geological horizon segments. | 2010-08-26 |
20100214871 | COMMUNICATION IN A SEISMIC SENSOR ARRAY - A method, system, and apparatus for communicating data with a seismic sensor are provided. The method comprises identifying data to be transmitted and one or more seismic events that correspond to the data to be transmitted. One or more seismic events are created that are distinguishable into binary code from one or more seismic sensors within the array. Seismic events can be distinguished by their pattern or frequency. A first frequency can be assigned as a first binary code and a second frequency can be assigned as a second binary code. Likewise, different patterns of acoustic energy can designate different binary codes. Combinations of patterns and frequencies can be used together to create distinct distinguishable seismic events. | 2010-08-26 |
20100214872 | Ultrasonic Sensor Having Time-Variable Sensitivity Threshold Values - An ultrasonic sensor is described, in which a time curve for the sensitivity is specified via threshold values which are assigned to individual interpolation points. The position in time of the interpolation points for the ultrasonic sensor is variable. | 2010-08-26 |
20100214873 | SYSTEM AND METHOD FOR AUTOMATIC DETERMINATION OF THE PHYSICAL LOCATION OF DATA CENTER EQUIPMENT - The invention is directed to a system and method for automatic discovery of the physical location of at least one device in a data center, the device having an associated ultrasonic emitter. The system generally includes a plurality of ultrasonic detectors having known locations in the data center. A controller initiates the generation of an ultrasonic signal from an ultrasonic emitter associated with a device under test. Time of arrival circuitry generates time of arrival information associated with each ultrasonic detector based on the time of receipt of the ultrasonic signal. The controller determines the location of the device under test based on the known location of the ultrasonic detectors within the data center and the time of arrival information associated with each ultrasonic detector. | 2010-08-26 |
20100214874 | MULTIBEAM, MULTIFREQUENCY SONAR METHOD AND APPARATUS - The present invention relates to a sonar method and apparatus of tracking objects underwater. Specifically, the method and apparatus can be used to acoustically track a multitude of objects in a hemi-spherical volume 360° azimuth and 180° elevation relative to the location of the apparatus. The method and apparatus of the present invention provide four-dimensional, real-time tracking of underwater objects. | 2010-08-26 |
20100214875 | Electronic Device and Method of Controlling Same for Integrating Calendaring and Clock Functionality - A method of controlling an electronic device includes retrieving, from a memory at the electronic device, calendar-event records containing data for corresponding calendar events that satisfy a set of time constraints, the data for each calendar-event record including a start time and an end time for the corresponding calendar event, and for each of the retrieved calendar-event records, rendering on a display a corresponding calendar-event indicia positioned, based on the start time and the end time for that calendar event, within a predetermined rotary-clock region of the display. | 2010-08-26 |
20100214876 | Map Association With Calendar Entry - A map is associated with a calendar entry. An electronic calendar includes at least one calendar entry. The calendar entry includes at least one calendar entry location for indicating a geographic location of where the calendar entry is scheduled to occur. At least one option associated with the calendar entry is provided. In response to receiving a user selection of the option, a map associated with the calendar entry location is provided. | 2010-08-26 |
20100214877 | Event Reminding System - In a method for reminding a patient to take a medication, the medication is labeled with a predefined symbol. A device displays the predefined symbol each time the medication is to be taken by the patient. | 2010-08-26 |
20100214878 | METHOD AND APPARATUS FOR PROCESSING A CALENDAR DATABASE FOR TIME ZONE SHIFTING - A system, method and apparatus for processing a calendar database for time zone shifting are provided. The calendar database is processed to determine a first set of event data associated with a first time zone and a second set of event data associated with a second time zone. Time zone calendar view data is produced, the time zone calendar view data enabled to control a display device to produce a time zone calendar view comprising representations of the first set and the second set sorted according to their associated time zones, said representations displayed on a timeline adjacent to one another, with concurrent times in each of the first time zone and second time zone temporally aligned. A display device is controlled, via the time zone calendar view data, to produce the time zone calendar view. | 2010-08-26 |
20100214879 | TIMEPIECE COMPRISING A CHRONOGRAPH AND A WATCH - The timepiece includes a chronograph whose hands are driven by a first gear train ( | 2010-08-26 |
20100214880 | REINFORCED MICRO-MECHANICAL PART - The micro-mechanical part, for example a horological movement part, includes a silicon core ( | 2010-08-26 |
20100214881 | DIRECT-IMPULSE ESCAPEMENT, ESPECIALLY OF DETENT TYPE, FOR A HOROLOGICAL MOVEMENT - This escapement comprises a balance wheel ( | 2010-08-26 |
20100214882 | MULTI-STAGE ENAMELLED DIAL - The dial with an enamel coating ( | 2010-08-26 |
20100214883 | Oscilloscope Clock - My invention is a new way to use a cathode ray tube, as used in oscilloscopes. My electronic circuit design controls the crt so that a clock face is displayed on the crt's screen, showing the time like a clock. It is meant to be a novelty item, and it is built inside a clear acrylic case, to enhance the novelty by displaying the construction inside and the electronic circuitry, as well as the cathode ray tube. | 2010-08-26 |
20100214884 | TIMEPIECE COMPRISING AN ALARM - A timepiece equipped with an alarm mechanism having a striking device and a minute repeater mechanism provided with a striking device. The two striking devices share at least one gong and one hammer. A power source can be locked when the mechanism is at rest and unlocked when the mechanism is in operation. An adjustment system can be used to program the alarm time. A trigger system includes a control member which controls the unlocking of the power source and a cam which is kinematically connected to the movement and performs one revolution every 24 hours. A first striking mechanism is equipped with at least one hammer arranged to strike at least one gong, and a supplemental striking mechanism is equipped with at least one hammer arranged to strike at least one non-resonant object, wherein the power source drives one or the other of these striking mechanisms. | 2010-08-26 |
20100214885 | ADDRESS GENERATING AND DETECTING METHOD AND REPRODUCING AND RECORDING APPARATUS - Recording capacity per layer is detected from a disc and bit allocation of wobble addresses in a conventional optical disc and bit allocation in a high-density optical disc are controlled selectively to detect physical position addresses on the disc. Address detection can be performed for two kinds of discs which are equal in structure of addresses embedded in wobbles but different in bit allocation of addresses. | 2010-08-26 |
20100214886 | Optical Disc Apparatus Employing an Objective Lens Having a High Numerical Aperture - An optical disk apparatus that includes a movable part having an objective lens for focusing a laser beam onto an optical disk. A lens-holding member holds the objective lens. A protecting member prevents contact of the objective lens with the optical disk. An elastic supporting member supports the movable part, and an actuator drives the movable part toward or apart from the optical disk. The apparatus is constructed not to cause contact of the protecting member with the optical disk in a non-working state of the actuator, even when the elastic supporting member is bent by gravity toward the optical disk. | 2010-08-26 |
20100214887 | DEVICE AND METHOD FOR SCANNING AN OPTICAL RECORDING MEDIUM AND OPTICAL RECORDING MEDIUM - The present invention relates to a device ( | 2010-08-26 |
20100214888 | RANDOM ACCESS CONTROL METHOD AND OPTICAL DISC DRIVER - A random access control method is provided, implemented in an optical disc drive for recording data to an optical disc. In the optical disc drive, a buffer stores a plurality of write commands each associated with a data block bound to a destination address. A processor controls the buffer to build a disc write task from the write commands in which addresses are organized in order. A drive unit is controlled by the processor, performing a recording operation to record the data blocks to the optical disc according to the disc write task; wherein the processor further controls the drive unit to verify the recorded data blocks after completing the recording operation. | 2010-08-26 |
20100214889 | MEDIA PROCESSING DEVICE, MEDIA PROCESSING SYSTEM, AND MEDIA PROCESSING METHOD - A media processing device can identify particular attributes of the recording media, such as the type of recording medium, and can sort by attribute a plurality of intermingled recording media including recording media that may or may not have been previously used and recording media of uncertain type. The media processing device has a plurality of media storage units that are capable of storing a plurality of recording media; a data reading unit that executes a reading process to read data written to a plurality of the recording media; a transportation unit that can convey the recording media to the plural media storage units and the data reading unit; a media identification unit that can identify individual attributes of the plural recording media based on a result of the reading process executed by the data reading unit; and a transportation control unit that causes the transportation unit to convey the recording media to different media storage units according to said attributes based on the identification results of the media identification unit. | 2010-08-26 |
20100214890 | DRIVE APPARATUS FOR PERFORMING A SEQUENTIAL RECORDING AND REPRODUCTION ON A WRITE-ONCE RECORDING MEDIUM, AND METHOD OF REPRODUCING SAME - The drive apparatus of the present invention includes a recording/reproduction section and a drive control section. The drive control section determines a physical address indicating a location at which data can be recorded next in the determined track of a write-once recording medium as a next writable address, based on the last recorded address in the track; compares the physical address corresponding to the logical address included in the recording instruction with the next writable address; when the physical address corresponding to the logical address is smaller than the next writable address, controls the recording/reproduction section to record the data at a specific location in the user data area other than the location indicated by the physical address corresponding to the logical address in the recording instruction; generates new disc management information; and controls the recording/reproduction section to record the new disc management information in the disc management information area. | 2010-08-26 |
20100214891 | OPTICAL PICKUP DEVICE, OPTICAL DISC DEVICE, COMPUTER, OPTICAL DISC PLAYER, AND OPTICAL DISC RECORDER - A first light source | 2010-08-26 |
20100214892 | OPTICAL RECORDING DEVICE AND METHOD OF OPERATING AN OPTICAL RECORDING DEVICE - The position of a write spot on an optical record carrier, during a write operation by an optical recording device, is important for the quality of the data recorded. Radial positioning of the spot may be facilitated by means of tracking spots, signals from which identify the location of the write spot. Signals from the tracking spots may be affected by the characteristics of the optical record carrier in the their vicinity. Specifically, effects arise from the recorded or unrecorded nature of the tracks adjacent each spot. The invention comprises rotation of the means to generate tracking spots such that tracking spots may be placed in an optimum position for recording, regardless of which data layer on an optical record carrier is to be recorded or the recording direction. | 2010-08-26 |
20100214893 | COPY PROTECTION USING COMPLEXITY AND UNCOMPUTABILITY - A method and system for copy protection using complexity and uncomputability are disclosed. According to one embodiment, a computer-implemented method comprises placing protection structures on a media disc. The protection structures comprise complexity structures and imcomputability commands. Unauthorized reproduction of data stored on the media disc is impeded using the protection structures. | 2010-08-26 |
20100214894 | Optical Medium with Added Descriptor to Reduce Counterfeiting - Functionality is described for reducing the unauthorized reproduction of optical media, such as optical discs of various types. The functionality operates by adding a physical descriptor to an optical medium, forming reference descriptor information based on the descriptor (by reading the descriptor L | 2010-08-26 |
20100214895 | REPRODUCTION SIGNAL EVALUATION METHOD, REPRODUCTION SIGNAL EVALUATION UNIT, AND OPTICAL DISK DEVICE ADOPTING THE SAME - A reproduction signal evaluation unit has: a pattern detection section for extracting, from a binary signal, a specific state transition pattern which has a possibility of causing a bit error; a differential metric computing section for computing a differential metric based on the binary signal of the extracted state transition pattern; an error computing section for computing an error rate predicted based on an integration value that is integrated by an integration section, a count value that is counted by a pattern count section, an integration value that is integrated by another integration section, and a count value that is counted by another pattern count section, and a standard deviation computing section for computing a standard deviation based on the computed error rate. | 2010-08-26 |
20100214896 | MULTILAYERED OPTICAL DISC AND ITS RECORDING METHOD - In an optical disc having N (N is an integer larger than or equal to 3) information recording layers of rewritable or recordable type, each of the information recording layers includes an test area to adjust conditions for recording and reproduction and the test areas are arranged so that the radial positions thereof overlap those of other layers. Recording test is performed only to an area smaller than or equal to 1/N of the test area of each layer and any other area is always unrecorded (write inhibited). | 2010-08-26 |
20100214897 | METHOD AND APPARATUS FOR PROCESSING OPTICAL DISC SIGNAL - According to the present invention, whether recoding pits are larger or smaller than diffraction limit is determined. Then, a signal process suitable for processing of the recording pits larger than the diffraction limit and a signal process suitable for processing of the recording pits smaller than diffraction limit are divided to divisionally perform equalizer processing. The respective signals subjected to the divisional processing are synthesized to obtain a processed output signal. A reproduction signal with reduced impact of intersymbol interference is thus obtained. | 2010-08-26 |
20100214898 | INFORMATION RECORDING MEDIUM, ADDRESS GENERATION AND DETECTION METHOD, AND REPRODUCING AND RECORDING APPARATUSES - In a recording medium, an extension address is obtained without changing the number of bits of the address embedded in the wobble. The wobble address is partially or wholly encoded to embed the address information. At the time of reproducing the address information, the original address information is obtained by restoring the embedded information by the decoding process. | 2010-08-26 |
20100214899 | High Frequency Modulation of a Light Beam in Optical Recording - An optical storage system modulates a laser beam based on a high frequency modulation (HFM) signal and a pattern to be recorded on an optical storage medium. At least one of an amplitude and a frequency of the HFM signal is adjusted when using the light beam to record the pattern on the optical storage medium or read data from the medium. | 2010-08-26 |
20100214900 | METHOD FOR DELETING DATA OF OPTICAL DISK AND OPTICAL DISK DRIVE INCLUDING OPTICAL DISK EMULATION - Provided are a method and a device for permanently erasing data of an optical disk in an optical disk drive including an optical disk emulation. According to the method, an erase command of data recorded on an optical disk is received and it is determined whether the optical disk is a rewritable optical disk or not. Then, an output power of a laser to be projected is raised when the optical disk is the rewritable optical disk and then the data recorded on the optical disk are erased through an output power of the laser. Furthermore, the optical disk drive includes an optical disk storage unit, a contents memory unit, a disk type determination unit, a laser power adjustor, a pick-up unit, and a controller. | 2010-08-26 |
20100214901 | OPTICAL RECORDING MEDIUM AND METHOD OF RECORDING/READING IT - To provide an optical recording medium of which mechanical properties and storage stability will not be impaired, and which will show little deterioration in signal properties even after being left to stand at high temperature under high humidity. | 2010-08-26 |
20100214902 | OPTICAL PICKUP AND OPTICAL DISC DEVICE - An optical pickup includes: a light source outputting a light beam; an objective lens collecting the light beam on a target recording layer as a target of plural recording layers provided in an optical disc; a lens moving unit moving the objective lens in a tracking direction nearly orthogonal to track grooves helically or coaxially formed in the target recording layer; a collective lens collecting a reflected light beam formed when the light beam is reflected by the optical disc; a diffraction optical element diffracting part of the reflected first-order light beam in predetermined directions as first, second, third and fourth beams; and a photodetector receiving the first and second beams using first and second light receiving areas, and generating light reception signals, and receiving the third and fourth beams using third and fourth light receiving areas, and generates light reception signals. | 2010-08-26 |
20100214903 | EXTRACTION OPTICAL SYSTEM AND OPTICAL HEAD DEVICE INCLUDING THE SAME - An object of the present invention is to provide an extraction optical system capable of separating and extracting a signal light and a stray light with a simple configuration, and an optical head device including the same. A phase plate and a phase plate are +λ/4 phase plates, while a phase plate and a phase plate are −λ/4 phase plates. A focal line, a focal line and a focal line represent a focal line of a stray light, a focal line of a reproduction light and a focal line of a stray light, respectively. All beams of the reproduction light enter the state in which a polarization direction is rotated by 90 degrees after passing through the phase element. In contrast to the all light bundles of the reproduction light, polarization directions of all light bundles of the stray lights and are not rotated even after passing through the phase element. | 2010-08-26 |
20100214904 | Optical Pickup Having Radially Arranged Lenses in a Low Profile Construction - An optical pickup includes a first source which emits a first beam with a first wavelength; a second source which emits a second beam with a wavelength shorter than the first wavelength; a first collimate lens which collimates the first beam; a second collimate lens which collimates the second beam; a first objective lens which converges the first collimated beam onto an optical disc; and a second objective lens which converges the second collimated beam onto the disc. The first and second objective lenses are arranged in the disc radial direction. The second objective lens is arranged closer to the side of the disc outer circumference than the first objective lens. The first collimate lens is arranged on the right-hand side when the second objective lens is viewed from the first objective lens. The second collimate lens is arranged on the left-hand side when the first objective lens is viewed from the second objective lens. The gap between the first collimate lens and the first objective lens is larger than the gap between the second collimate lens and the second objective lens. | 2010-08-26 |
20100214905 | Stacking techniques for thin optical data storage media - This disclosure relates to thin optical storage media that may be compliant with conventional DVD drives. Unlike conventional DVDs, however, the described media generally has a thickness profile less than 1.2 mm. The media may further include one or more protrusions protruding from a major surface of the media which define a thickness of approximately 1.2 mm within the clamping area of the media. In some embodiments, the media may further include one or more recesses recessed into a major surface within the clamping area of the media. Two or more optical storage media may be packaged by stacking the media in a configuration that defines an overall stacked thickness that is less than 1.2 mm for each individual medium in the package. | 2010-08-26 |
20100214906 | Method And System For Dynamically Determining When To Train Ethernet Link Partners To Support Energy Efficient Ethernet Networks - Training, refreshing and/or updating Ethernet link partners for silent channels and/or silent directions of channels may be determined based on control parameters. This may be used to improve energy efficiency in Ethernet communication. Control parameters may comprise a default value and/or may be determined based on prior training, refreshing and/or updating. New values for the control parameters may be generated based on a magnitude of change between current and prior control parameter values or based on performance such as bit error rate. User input may be utilized to determine when to execute the training, refreshing and/or updating. The training, refreshing and/or updating may be done for one or more of a near-end crosstalk canceller, alien near-end crosstalk canceller, far-end crosstalk canceller, alien far-end crosstalk canceller and echo canceller. After the training, refreshing and/or updating, the silent channels may transition to active and/or may remain silent. | 2010-08-26 |
20100214907 | Method for Synchronizing Voice Traffic With Minimum Latency in a Communications Network - A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method is provided to convey and maintain information used to synchronize the packetization and burst operations within the network. During session setup, jitter constraints indirectly are used to explicitly communicate a synchronization timing reference. The timing reference is set at the beginning of a phase/period boundary used to service the session. In an embodiment, the announcement of the first grant is used as an explicit indication of the synchronization timing reference value. In another embodiment, the synchronization timing reference value is inferred if a remote device receives contiguous voice grants meeting certain conditions. In an embodiment implementing periodic scheduling, the actual arrival of the first grant is used to infer the synchronization timing reference value. In an embodiment, the present invention enables the synchronization timing reference value and/or the periodicity to be modified if network conditions indicate that packetization and burst operations are out-of-synchronization. | 2010-08-26 |
20100214908 | Mechanism for Transparent Real-Time Media Server Fail-Over with Idle-State Nodes - In one embodiment, a mechanism for transparent real-time media server fail-over with idle-state nodes is disclosed. In one embodiment, a method includes replicating a start time of a request related to a bidirectional stream of media sent to an original master media server, receiving notification of selection as a new master media server after failure of the original master media server, determining an offset time by subtracting the replicated request start time from a current time, and resuming playback of the request at the offset time within the request. | 2010-08-26 |
20100214909 | P2MP TRAFFIC PROTECTION IN MPLS-TP RING TOPOLOGY - In a connection-oriented network a point-to-multipoint working path is established between a source node and a plurality of destination nodes using a number of working path intermediate nodes. A point-to-multipoint protection path is established for possible points of failure in the working path. Each protection path connects a first working path intermediate node upstream of a point of failure and destination nodes of the working path downstream of the first working path intermediate node. The point-to-multipoint protection path only connects to destination nodes of the working path and working path intermediate nodes which must be transited to reach the destination nodes of the working path. | 2010-08-26 |