34th week of 2022 patent applcation highlights part 64 |
Patent application number | Title | Published |
20220271096 | DISPLAY DEVICE - A display device includes a display panel and an input sensor disposed on the display panel. The input sensor includes a plurality of first areas repeatedly arranged in a first direction, a plurality of second areas repeatedly arranged in the first direction, an inorganic insulating layer disposed in the first areas, an organic insulating layer disposed in the first areas and the second areas, and a sensing electrode disposed on the organic insulating layer. The first areas are alternately arranged in the first direction with the second areas, and the input sensor includes openings in the second areas that are formed by removing portions of the inorganic insulating layer from the second areas. | 2022-08-25 |
20220271097 | DISPLAY DEVICE - Provided display device includes a display layer including a display area and a hole area which is disposed adjacent to the display area and in which a through-hole is defined and an input sensor layer disposed on the display layer and including a flat part including a conductive layer and at least one insulating layer and a protruding pattern part including the at least one insulating layer and provided to correspond to the hole area. Therefore, cracks that occur when a through-hole is formed may be reduced then the reliability and durability of the display device have been improved. | 2022-08-25 |
20220271098 | Display Panel, Manufacturing Method Thereof, and Display Apparatus - Provided are a display panel, a manufacturing method thereof and a display apparatus. The display panel includes a fingerprint identification sensor, a first light shield layer disposed on the fingerprint identification sensor and a color film layer disposed on the first light shield layer, wherein the color film layer includes color filters with different colors and light transmission parts disposed between the color filters with different colors; the first light shield layer includes first openings and light shield parts, the light transmission parts and the first openings are used for allowing fingerprint reflected light to transmit and reach the fingerprint identification sensor, and the light shield parts are used for blocking out stray light. | 2022-08-25 |
20220271099 | DISPLAY DEVICE - A display device according to an embodiment of the present invention includes: a base material including a display region having a plurality of pixels and a frame region; a lower electrode provided in each of the plurality of pixels; an organic material layer arranged on the lower electrode; an upper electrode arranged on the organic material layer and covering the display region; a conductor portion provided in the frame region and connected to the upper electrode; and a rib provided on the conductor portion, wherein the upper electrode is arranged on the conductor portion via the rib, a first contact portion where the upper electrode and the conductor portion contact each other is located in the frame region, the rib has a side surface located at an opposite side of the first contact portion from the display region, and an end portion of the upper electrode faces the side surface. | 2022-08-25 |
20220271100 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device. The display panel includes a first electrode layer, a second electrode layer, and N light-emitting structural layers stacked between the first electrode layer and the second electrode layer; each of the light-emitting structural layers includes a plurality of light-emitting units corresponding to respective sub-pixels, the light-emitting unit includes a plurality of functional film layers arranged in a stacked manner, one of the plurality of functional film layers is a light-emitting layer; the first electrode layer and the light-emitting layers in the i-th light-emitting structural layer have a plurality of first optical lengths provided therebetween, the first optical lengths corresponding to the sub-pixels of a same color have a same value, and the first optical length has a linear relationship with a wavelength of light emitted by the light-emitting unit, i is 1, 2, 3 . . . N. | 2022-08-25 |
20220271101 | DISPLAY DEVICE, DISPLAY PANEL, AND MANUFACTURING METHOD THEREOF - The present invention provides a display panel including a pixel layer. The pixel layer includes a plurality of pixel units having a regular M polygon. Each inner angle of the regular M polygon is m, wherein | 2022-08-25 |
20220271102 | DISPLAY APPARATUS - A display apparatus includes a first pad at one side of a substrate; a first semiconductor layer on the substrate; a first crack detection electrode interposed between the substrate and the first semiconductor layer, and including a first end portion at the one side and a second end portion at another side; a second crack detection electrode disposed on the first semiconductor layer, and including a first end portion located at the one side and a second end portion connected to the second end portion of the first crack detection electrode; and a first auxiliary electrode disposed on the second conductive layer, and including a first end portion connected to the second end portion of the first crack detection electrode and a second end portion electrically connected to the first pad. | 2022-08-25 |
20220271103 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure discloses a display substrate and a display device. The display substrate includes: a base substrate; a plurality of light emitting devices, located on the base substrate; a plurality of photosensitive devices, located between a layer where the plurality of light emitting devices are located and the base substrate; a plurality of color resistors and a black matrix, located on a side of the layer where the plurality of light emitting devices are located facing away from the base substrate; a touch control structure, located between the layer where the plurality of light emitting devices are located and a layer where the black matrix is located; and an ultrathin glass cover plate, a whole face of which being disposed on a side of the layer where the black matrix is located facing away from the base substrate. | 2022-08-25 |
20220271104 | DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS - A display panel includes a display substrate. The display substrate includes: a base substrate; a display structure layer including a plurality of pixel circuits and a plurality of light-emitting devices on the base substrate; and a light detection layer located at a non-light exit side of the light-emitting devices. A pixel circuit in the plurality of pixel circuits is electrically connected to a respective light-emitting device to drive the light-emitting device to emit light. The light detection layer is configured to detect a luminous intensity of at least one light-emitting device. The display substrate further includes: a transparent cover plate at a light exit side of the light-emitting devices; and a polarizer and a first quarter-wave plate between the display substrate and the transparent cover plate. The polarizer is closer to the display substrate than the first quarter-wave plate. | 2022-08-25 |
20220271105 | DISPLAY SUBSTRATE, METHOD OF FORMING DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate, a method of forming a display substrate and a display device are provided. The display substrate includes: a plurality of pixel units arranged in an array, a substrate, a light-emitting device layer and an electrochromic functional layer, where the light-emitting device layer and the electrochromic functional layer are stacked on the substrate; the light-emitting device layer includes a plurality of light-emitting devices, an orthographic projection of the electrochromic functional device on the substrate is at least partially overlapped with an orthographic projection of the corresponding effective light-emitting area on the substrate. | 2022-08-25 |
20220271106 | DISPLAY DEVICE - A display device includes an optical module, a light emitting structure, a lower substrate including a display area, and in order within the display area a first area corresponding to the optical module, second area adjacent to the optical module, and a third area including the light emitting structure, a light-transmitting filling layer in the first area and corresponding to the optical module, a light blocking layer in the second area and defining an opening corresponding to the light-transmitting filling layer in the first area, and an upper substrate facing the lower substrate with the light emitting structure and the light blocking layer therebetween. | 2022-08-25 |
20220271107 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes sub-pixel units, and each sub-pixel unit includes a light emitting region and a non-light emitting region; each sub-pixel unit includes a light emitting element, the light emitting element includes a light emitting layer and a first electrode, and at least a part of the first electrode is in the light emitting region. A plurality of first wires are configured to supply a power signal to the light emitting element and include a first sub-wire; the first sub-wire includes a plurality of portions, adjacent two of the plurality of portions are spaced apart from each other by an opening in the light emitting region; at least a part of an orthographic projection of the opening on the array substrate does not overlap with an orthographic projection of the first electrode on the array substrate. | 2022-08-25 |
20220271108 | Display Substrate, Ink Jet Printing Method Thereof and Display Apparatus - A display substrate, an ink jet printing method and a display apparatus are provided. The display substrate includes a base substrate and a pixel define layer disposed on the base substrate, wherein the pixel define layer includes first define layers and a second define layer, a printing region is formed on the base substrate between the first define layers, and the second define layer is disposed on the printing region and divides the printing region into at least two sub-pixel regions, and a height of the first define layers is greater than that of the second define layer in a direction perpendicular to the base substrate. | 2022-08-25 |
20220271109 | Display Device and Electronic Device - A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit. | 2022-08-25 |
20220271110 | DISPLAY PANEL, DISPLAY DEVICE AND MANUFACTURING METHOD OF THE DISPLAY PANEL - The present disclosure provides a display panel, a display device including the display panel and a method of manufacturing the display panel. The display panel includes a substrate; a pixel-defining layer disposed on the substrate, wherein the pixel-defining layer defines a plurality of sub-pixel regions arranged in rows and columns; and an organic light emitting element disposed in at least one of the plurality of sub-pixel regions, wherein a side of the pixel-defining layer away from the substrate is provided with a groove, the groove has a depth less than a thickness of the pixel-defining layer and the groove is disposed between the organic light emitting elements that are adjacent to each other and emit light of different colors. | 2022-08-25 |
20220271111 | PIXEL HAVING AN ORGANIC LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE PIXEL - A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planarization dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap. | 2022-08-25 |
20220271112 | DISPLAY DEVICE - A display device is provided. The display device includes substrate, a lower conductive layer disposed on the substrate, and including a first lower conductive pattern and a second lower conductive pattern electrically isolated from each other, a first semiconductor layer including a first channel region, and a first source disposed on one side of the first channel region and a first drain region disposed on the other side of the first channel region. The first lower conductive pattern overlaps the first channel region and the first source region, and the second lower conductive pattern overlaps the first channel region and the first drain region in a plan view, and different voltages are applied to the first lower conductive pattern and the second lower conductive pattern. | 2022-08-25 |
20220271113 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes: a light transmission region; a display region; a bezel region located between the light transmission region and the display region; a plurality of data lines including a plurality of bezel region data lines and a plurality of display region data lines, and a plurality of gate lines including a plurality of bezel region gate lines and a plurality of display region gate lines, each bezel region gate line includes a first portion, each bezel region data line includes a first portion, an extending direction of the first portion of the bezel region gale line is same as that of the first portion of the bezel region data line, and the first portion of the bezel region gate line overlaps with the first portion of one bezel region data line in a direction perpendicular to the base substrate. | 2022-08-25 |
20220271114 | DISPLAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY PANEL, AND DISPLAY DEVICE - Provided are a display substrate, an organic light-emitting display panel, and a display device. A shielding layer is arranged between a first gate metal layer and a source-drain metal layer such that same are insulated from each other, an orthographic projection, on a base substrate, of the shielding layer covers at least an orthographic projection, on the base substrate, of an overlapping area of a scanning signal line and a detection signal line, and the shielding layer is coupled to a fixed voltage. | 2022-08-25 |
20220271115 | DISPLAY DEVICE - According to one embodiment, a display device including a first lower electrode, a second lower electrode, a first wiring that is disposed between the first lower electrode and the second lower electrode, a second insulation layer that is disposed on the first wiring, a first organic layer that is disposed on the first lower electrode, a second organic layer that is disposed on the second lower electrode, a first upper electrode that is disposed on the first organic layer, a second upper electrode that is disposed on the second organic layer, and a second wiring that is disposed on the second insulation layer, opposed to the first wiring, and forms a capacitance between the first wiring and the second wiring. | 2022-08-25 |
20220271116 | POLYSILICON RESISTOR WITH CONTINUOUS U-SHAPED POLYSILICON RESISTOR ELEMENTS AND RELATED METHOD - A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed. | 2022-08-25 |
20220271117 | THIN-FILM RESISTOR (TFR) HAVING A TFR ELEMENT PROVIDING A DIFFUSION BARRIER FOR UNDERLYING TFR HEADS - A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN). | 2022-08-25 |
20220271118 | METHOD AND APPARATUS RELATED TO CONTROLLABLE THIN FILM RESISTORS FOR ANALOG INTEGRATED CIRCUITS - An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer. | 2022-08-25 |
20220271119 | INTEGRATED CIRCUIT INCLUDING TRENCH CAPACITOR - A method of manufacturing a capacitor including the operations of etching a plurality of primary trenches into a first region of a substrate, the primary trenches extending in a first direction, etching a plurality of secondary trenches into the first region of the substrate, the secondary trenches extending in a second direction other than the first direction, with the adjacent secondary trenches and adjacent primary trenches jointly defining an island structure having an upper surface that is recessed relative to an upper surface a surrounding substrate, and depositing a series of film pairs including a dielectric layer and a conductive layer. | 2022-08-25 |
20220271120 | SUPERJUNCTION SEMICONDUCTOR DEVICE - A superjunction semiconductor device is disclosed. The superjunction semiconductor device includes a gate pad and first conductive type pillars in a ring region adjacent to the gate pad and crossing a gate pad region to a cell region, thereby securing a sufficient depletion region within a relatively short time and directing or guiding excess carriers below the gate pad and in the adjacent ring region toward a source end through or along the pillars during reverse recovery (RR). | 2022-08-25 |
20220271121 | SUPERJUNCTION SEMICONDUCTOR DEVICE HAVING REDUCED SOURCE AREA AND METHOD OF MANUFACTURING SAME - The present disclosure relates to a superjunction semiconductor device having a reduced source area and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same, in which the semiconductor device realizes a reduction in the area of a source in a body region to reduce the current during a short circuit fault, thus delaying a temperature increase and increasing the time before temperature-related device destruction. | 2022-08-25 |
20220271122 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature. The second gate electrode layer is disposed between the seventh and eighth source/drain epitaxial features. | 2022-08-25 |
20220271123 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a source/drain pattern disposed on a substrate and a source/drain contact connected to the source/drain pattern. The source/drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, and each of the first sub-sidewalls includes a concave surface. | 2022-08-25 |
20220271124 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapped around the first nanostructures. The structure also includes first source/drain epitaxial structures formed over opposite sides of the first nanostructures. The structure also includes second nanostructures formed over the first nanostructure. The structure also includes a second gate structure wrapped around the second nanostructures. The structure also includes second source/drain epitaxial structures formed over opposite sides of the second nanostructures. The first gate structure and the second gate structure have different conductivity types, and the Ge concentration of the first nanostructures and the Ge concentration of the second nanostructures are different. | 2022-08-25 |
20220271125 | TRANSISTOR DEVICES HAVING SOURCE/DRAIN STRUCTURE CONFIGURED WITH HIGH GERMANIUM CONTENT PORTION - Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures. | 2022-08-25 |
20220271126 | N-TYPE MOSFET - The present application discloses an N-type MOSFET, comprising: a gate structure formed on the surface of a semiconductor substrate; an embedded epitaxial layer formed on each of the two sides of the gate structure, wherein the embedded epitaxial layer fills in a groove, and the groove is formed in the semiconductor substrate; and a source region and a drain region formed in the embedded epitaxial layer on each side of the gate structure; wherein the width of the gate structure is less than 20 nm; and the embedded epitaxial layer comprises a first epitaxial layer of SiAs, or the embedded epitaxial layer is formed by stacking a second epitaxial layer of SiAs and a third epitaxial layer of SiP. The present application can improve the carrier mobility of the device and improve the short channel effect. | 2022-08-25 |
20220271127 | Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells - A transistor comprises a channel region having a frontside and a backside. The channel region comprises a frontside channel material at the frontside and a backside channel material at the backside. A gate is adjacent the frontside of the channel region, with a gate insulator being between the gate and the channel region. The frontside channel material has total n-type dopant therein of greater than 1×10 | 2022-08-25 |
20220271128 | HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMCONDUCTOR MATERIAL IN SILICON RECESS - A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon. | 2022-08-25 |
20220271129 | SEMICONDUCTOR DEVICE INCLUDING FIN AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate; and a fin protruding from the substrate. The fin includes a first material and a second material. The fin includes a lower section, a middle section, and an upper section. The middle section has a smaller width at a middle portion than a width at lower and upper portions of the middle section. A concentration of the second material gradually decreases from the middle portion in upward and downward directions. | 2022-08-25 |
20220271130 | METHOD OF FORMING CONTACT STRUCTURES - A method according to the present disclosure includes receiving a workpiece that includes a first gate structure including a first cap layer thereon, a first source/drain contact adjacent the first gate structure, a second gate structure including a second cap layer thereon, a second source/drain contact, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, and a first dielectric layer over the ESL. The method further includes forming a butted contact opening to expose the first cap layer and the first source/drain contact, forming a butted contact in the butted contact opening, after the forming of the butted contact, depositing a second dielectric layer, forming a source/drain contact via opening through the second dielectric layer, the ESL layer, and the first dielectric layer to expose the second source/drain contact, and forming a source/drain contact via in the source/drain contact via opening. | 2022-08-25 |
20220271131 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A method for forming a semiconductor structure includes: providing a substrate, grooves having a first depth being provided; forming a first gate oxide layer on side walls and a bottom surface of a groove, and a first gate conductive layer on a surface of the first gate oxide layer, the first gate oxide layer and the first gate conductive layer having a second depth which is less than the first depth; forming a second gate oxide layer on surfaces of the groove that are not covered by the first gate oxide layer, in a direction perpendicular to a side wall of the groove, an equivalent gate oxide thickness of the second gate oxide layer being greater than that of the first gate oxide layer; and forming a second gate conductive layer which fills up a recess surrounded by the second gate oxide layer and the first gate conductive layer. | 2022-08-25 |
20220271132 | Mesa Contact for MOS Controlled Power Semiconductor Device and Method of Producing a Power Semiconductor Device - A power semiconductor device includes: a semiconductor body having a first surface and a mesa portion that includes a surface part of the first surface and a body region; at least two trenches extending from the first surface into the semiconductor body along a vertical direction, each trench including a trench electrode and trench insulator insulating the trench electrode from the semiconductor body, the mesa portion being laterally confined by the trenches in a first vertical cross-section along a first lateral direction; and a contact plug in contact with the body region. The contact plug and trench electrode of a first trench laterally overlap at least partially in the first vertical cross-section. A protection structure having a portion arranged within the first trench is arranged between the contact plug and trench electrode of the first trench. The protection structure may be an electrically insulation structure or a protective device structure. | 2022-08-25 |
20220271133 | SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via. | 2022-08-25 |
20220271134 | TRANSISTOR - A transistor comprising a gallium nitride layer having a first gate electrode partially penetrating into it, having: a first side coated with a first thickness of a first insulating material and of a second insulating material; and with a second thickness of a conductive material; and a bottom coated with a third thickness, smaller than the first thickness, of the first insulating material. | 2022-08-25 |
20220271135 | NONVOLATILE MEMORY DEVICE - In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between. the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film. is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating. film and the second electrode film. | 2022-08-25 |
20220271136 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall. | 2022-08-25 |
20220271137 | MEMORY CELL AND FABRICATING METHOD OF THE SAME - A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate. | 2022-08-25 |
20220271138 | BACKSIDE GATE CONTACT - Semiconductor structures and methods of forming the same are provided. A semiconductor according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact. | 2022-08-25 |
20220271139 | Semiconductor Device With Backside Gate Isolation Structure And Method For Forming The Same - A semiconductor device includes nanostructures vertically arranged and spaced apart from one another along a first direction. The semiconductor device also includes a dielectric fin structure of a dielectric material of uniform composition and an isolation structure on opposite sides of the nanostructures. Moreover, the semiconductor device also includes a gate structure wrapping around the nanostructures. The gate structure extends between the nanostructure and the dielectric fin structure, and extends between the nanostructures and the isolation structure. Furthermore, the nanostructures are spaced apart from the dielectric fin structure along a second direction perpendicular to the first direction by a first distance, and from the isolation structure along the second direction by a second distance, where the first distance is greater than the second distance. Additionally, the gate structure interfaces with the dielectric fin structure on a surface extending perpendicular to the first direction. | 2022-08-25 |
20220271140 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for forming a semiconductor are provided. The semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, a work function metal layer over the gate dielectric layer, and a plurality of barrier granules between the gate dielectric layer and the work function metal layer. At least two adjacent barrier granules of the plurality of barrier granules are separated from each other by a portion of the work function metal layer. | 2022-08-25 |
20220271141 | MOSFET DEVICE STRUCTURE WITH AIR-GAPS IN SPACER AND METHODS FOR FORMING THE SAME - A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance. | 2022-08-25 |
20220271142 | Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells - A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of Al | 2022-08-25 |
20220271143 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material. | 2022-08-25 |
20220271144 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a nitride semiconductor device includes formation of a gate insulation film above a nitride semiconductor layer. The formation of the gate insulation film includes formation of silicon oxynitride film in contact with a surface of the nitride semiconductor layer. The formation of the silicon oxynitride film includes oxidation of a film source material having both of silicon and nitride in a molecule to form the silicon oxynitride film. | 2022-08-25 |
20220271145 | METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH AIR GAP BETWEEN TWO CONDUCTIVE FEATURES - The present disclosure provides a method for forming a semiconductor device with an air gap for reducing the parasitic capacitance between two conductive features. The method includes forming a first source/drain region and a second source/drain region in a semiconductor substrate, and forming a first conductive feature over and electrically connected to the first source/drain region. The method also includes forming a first spacer structure on a sidewall of the first conductive feature, and forming a second conductive feature over and electrically connected to the second source/drain region. The second conductive feature is adjacent to the first spacer structure, and the first spacer structure is etched during the forming the second conductive feature. The method further includes forming a second spacer structure over the etched first spacer structure, and performing a heat treatment process to transform a portion of the first spacer structure into an air gap. | 2022-08-25 |
20220271146 | METHOD AND RELATED APPARATUS FOR REDUCING GATE-INDUCED DRAIN LEAKAGE IN SEMICONDUCTOR DEVICES - In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure. | 2022-08-25 |
20220271147 | Group III Nitride-Based Transistor Device - In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l | 2022-08-25 |
20220271148 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a first layer, and a fill layer over the first layer. The gate structure includes a protection layer formed over the fill layer of the gate structure, and the protection layer is separated from the first layer by the fill layer. | 2022-08-25 |
20220271149 | METHOD OF ENGRAVING A THREE-DIMENSIONAL DIELECTRIC LAYER - A method is provided for etching a dielectric layer covering a top and a flank of a three-dimensional structure, the method including: a first etching of the dielectric layer, including: a first fluorine-based compound and oxygen, the first etching being performed to: form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and the second etchings being repeated until removing the dielectric layer located on the flank of the structure, and before deposition of the dielectric layer, a formation of an intermediate protective layer between the top and the dielectric layer. | 2022-08-25 |
20220271150 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having favorable electrical characteristics is provided. The semiconductor device is manufactured by a first step of forming a semiconductor layer containing a metal oxide, a second step of forming a first insulating layer, a third step of forming a first conductive film over the first insulating layer, a fourth step of etching part of the first conductive film to form a first conductive layer, thereby forming a first region over the semiconductor layer that overlaps with the first conductive layer and a second region over the semiconductor layer that does not overlap with the first conductive layer, and a fifth step of performing first treatment on the conductive layer. The first treatment is plasma treatment in an atmosphere including a mixed gas of a first gas containing an oxygen element but not containing a hydrogen element, and a second gas containing a hydrogen element but not containing an oxygen element. | 2022-08-25 |
20220271151 | DEVICE COMPRISING ELECTROSTATIC CONTROL GATES DISTRIBUTED ON TWO OPPOSITE FACES OF A SEMICONDUCTOR PORTION - A spin qubit quantum device, comprising:
| 2022-08-25 |
20220271152 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region. | 2022-08-25 |
20220271153 | HEMT AND FABRICATING METHOD OF THE SAME - An HEMT includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer. A gate is disposed on the aluminum gallium nitride layer. The gate includes a P-type gallium nitride and a schottky contact layer. The P-type gallium nitride contacts the schottky contact layer, and a top surface of the P-type gallium nitride entirely overlaps a bottom surface of the schottky contact layer. A protective layer covers the aluminum gallium nitride layer and the gate. A source electrode is disposed at one side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A drain electrode is disposed at another side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A gate electrode is disposed directly on the gate, penetrates the protective layer and contacts the schottky contact layer. | 2022-08-25 |
20220271154 | SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, the present disclosure relates to a superjunction semiconductor device and a method of manufacturing the same, in which the device includes a field oxide layer having an uppermost end or surface that is higher than that of a gate oxide layer, between a gate electrode and a second pillar region in a cell region. This enables a reduction in gate-drain parasitic capacitance, thereby increasing switching speed and reducing switching loss. | 2022-08-25 |
20220271155 | SEMICONDUCTOR DEVICE - A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type having a first region facing the gate electrode and a second region in contact with the first electrode, a second silicon carbide region of a second conductive type, and a third silicon carbide region of a second conductive type, the first region being interposed between the second silicon carbide region and the third silicon carbide region. A first width of the first region in a second direction perpendicular to the first direction is 0.5 μm or more than and 1.2 μm or less. A second width of the second region in the second direction 0.5 μm or more than and 1.5 μm or less. | 2022-08-25 |
20220271156 | SiC Device Having a Dual Mode Sense Terminal, Electronic Systems for Current and Temperature Sensing, and Methods of Current and Temperature Sensing - A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal. | 2022-08-25 |
20220271157 | LDMOS AND FABRICATING METHOD OF THE SAME - An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode. | 2022-08-25 |
20220271158 | HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMCONDUCTOR MATERIAL - A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon. | 2022-08-25 |
20220271159 | HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMCONDUCTOR MATERIAL IN SILICON RECESS WITH NITRIDE SPACER - A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure in a silicon recess on the silicon portion of the hybrid device. The silicon recess contains a silicon recess nitride sidewall. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon. | 2022-08-25 |
20220271160 | ACTIVE ANTENNA DEVICE BASED ON SILICON RING FIELD EFFECT TRANSISTOR ARRAY - An antenna device according to an example embodiment includes a silicon substrate of first type doping, at least two first doped regions formed by second type doping different from the first type doping, a second doped region formed by the second type doping outside a channel region surrounding the at least two first doped regions, and at least two gates disposed on a dielectric layer. In the antenna device, a resonant frequency is adjusted according to an external voltage individually applied to the at least two gates, and polarization information of a terahertz (THz) light source is obtained based on a pattern and an amount of an electric field measured at the at least two gates. | 2022-08-25 |
20220271161 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region. | 2022-08-25 |
20220271162 | P-TYPE FIELD EFFECT TRANSISTOR (PFET) ON A SILICON GERMANIUM (GE) BUFFER LAYER TO INCREASE GE IN THE PFET SOURCE AND DRAIN TO INCREASE COMPRESSION OF THE PFET CHANNEL AND METHOD OF FABRICATION - An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer. | 2022-08-25 |
20220271163 | CONTACT FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF - A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact. | 2022-08-25 |
20220271164 | METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH CONDUCTIVE LAYER BETWEEN GATE AND GATE CONTACT - A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer. | 2022-08-25 |
20220271165 | Stacked Gate-All-Around FinFET and Method Forming the Same - A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics. | 2022-08-25 |
20220271166 | THIN FILM TRANSISTOR INCLUDING A COMPOSITIONALLY-MODULATED ACTIVE REGION AND METHODS FOR FORMING THE SAME - A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer. | 2022-08-25 |
20220271167 | Semiconductor Device and Method For Manufacturing Semiconductor Device - A semiconductor device with high reliability is provided. The semiconductor device includes a first oxide; a first conductor, a second conductor, and a first insulator over the first oxide; and a third conductor over the first insulator. The first conductor includes a first crystal. The second conductor includes a crystal having the same crystal structure as the first crystal. The first crystal has (111) orientation with respect to a surface of the first oxide. The first oxide includes a second crystal. The second crystal has c-axis alignment with respect to a surface where the first oxide is formed. The lattice mismatch degree of the first crystal with respect to the second crystal is lower than or equal to 8 percent. | 2022-08-25 |
20220271168 | SEMICONDUCTOR DEVICE - A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor, a first conductor and a second conductor over the oxide semiconductor, a first insulator in contact with a top surface of the first conductor, a second insulator in contact with a top surface of the second conductor, a third insulator which is positioned over the first insulator and the second insulator and has an opening overlapping with a region between the first conductor and the second conductor, a fourth insulator positioned over the oxide semiconductor and in the region between the first conductor and the second conductor, and a third conductor over the fourth insulator. Each of the first insulator and the second insulator is a metal oxide including an amorphous structure. | 2022-08-25 |
20220271169 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device having a high on-state current is provided. | 2022-08-25 |
20220271170 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer. | 2022-08-25 |
20220271171 | NANOSHEET SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet. | 2022-08-25 |
20220271172 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor. | 2022-08-25 |
20220271173 | FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE - A method for forming a semiconductor device structure is provided. The method includes forming first nanostructures and second nanostructures over a semiconductor substrate. The method also includes forming a dielectric fin between the first nanostructures and the second nanostructures. The method further includes forming a metal gate stack wrapped around the first nanostructures, the second nanostructures, and the dielectric fin. In addition, the method includes forming an insulating structure penetrating into the metal gate stack and aligned with the dielectric fin. | 2022-08-25 |
20220271174 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V | 2022-08-25 |
20220271175 | SOLAR CELL-ATTACHED ELECTRONIC EQUIPMENT - Provided is solar cell-attached electronic equipment ( | 2022-08-25 |
20220271176 | LOCAL METALLIZATION FOR SEMICONDUCTOR SUBSTRATES USING A LASER BEAM - Local metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. For example, a solar cell includes a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality of semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding a semiconductor region. | 2022-08-25 |
20220271177 | SENSOR AND METHOD OF FORMING THE SAME - A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer. | 2022-08-25 |
20220271178 | PHOTOVOLTAIC DEVICE AND PHOTOVOLTAIC UNIT - A photovoltaic device includes: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on a first-face side; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region. | 2022-08-25 |
20220271179 | SOLAR CELL, METHOD FOR PRODUCING SAME AND SOLAR MODULE - A solar cell, a method for producing a solar cell, and a solar module are provided. The solar cell includes: an N-type substrate and a P-type emitter formed on a front surface of the substrate; a first passivation layer, a second passivation layer and a third passivation layer sequentially formed over the front surface of the substrate and in a direction away from the P-type emitter, and a passivated contact structure disposed on a rear surface of the substrate. The first passivation layer includes a first Silicon oxynitride (SiO | 2022-08-25 |
20220271180 | BACKSIDE EMITTER SOLAR CELL STRUCTURE HAVING A HETEROJUNCTION AND METHOD AND DEVICE FOR PRODUCING THE SAME - A backside emitter solar cell structure having a heterojunction, and a method and a device for producing the same. A backside intrinsic layer is first formed on the back side of the substrate, then a frontside intrinsic layer and a frontside doping layer are formed on the front side of the substrate, and finally a backside doping layer is formed on the back side of the substrate. | 2022-08-25 |
20220271181 | Stacked Thin-Film Photoconductive Semiconductor Switch - A photoconductive semiconductor switch (PCSS) comprises a plurality of planar semiconductor layers, adjacent semiconductor layers separated by an insulation layer, forming a thin-film stack; a pair electrical contacts fixed to a perimeter of each of the semiconductor layers; an optical source arranged to project light of a predetermined wavelength through the plurality of semiconductor layers. The thin-film stack may comprise at least 10 layers of alternating semiconductor and insulating layers. The semiconductor and insulator layers consist of at least one of GaAs, GaN, GaP, AlN, GaSe, ZnSe, ZnTe, GaSb, InAs, GaN, AlAs, InP, CdS, InSe, CdTe, HgTe, InSb, AlSb, and AlGaN. The contacts consist of at least one of a doped semiconductor material. The optical source illuminates the thin-film stack from at least one of their edges, i.e. parallel to the thin-film layers, or straight through the thin-film stack, i.e. perpendicular to the thin-film layers, or any angle in between. | 2022-08-25 |
20220271182 | BACKSIDE ILLUMINATED AVALANCHE PHOTODIODE AND MANUFACTURING METHOD THEREOF - Provided is a backside illuminated avalanche photodiode and a manufacturing method thereof. The backside illuminated avalanche photodiode comprises a semiconductor substrate; a semiconductor structure including a first semiconductor layer being arranged on a front surface of the semiconductor substrate and including a first conductivity type bottom electrical contact layer, a light absorption layer, and a multiplication layer, and a second semiconductor layer, stacked on the first semiconductor layer and including an etch stop layer and a second conductivity type top electrical conductivity layer stacked on the etch stop layer; a plurality of V-grooves in parallel with each other being formed by etching the top electrical contact layer; and a reflective top electrode formed by depositing a multi layer thin metal films on the top electrical contact layer wherein plurality of V-grooves parallel with each other are formed. | 2022-08-25 |
20220271183 | SPAD PIXEL STRUCTURE AND METHOD OF MANUFACTURING SAME - Disclosed are a SPAD pixel structure and a method of manufacturing the same, in which a cathode contact is formed on a back surface of a substrate instead of a front surface, thereby reducing or minimizing the distance between adjacent unit pixels and increasing the fill-factor of each unit pixel. | 2022-08-25 |
20220271184 | ANODE SENSING CIRCUIT FOR SINGLE PHOTON AVALANCHE DIODES - Disclosed herein is an array of pixels. Each pixel includes a single photon avalanche diode (SPAD) and a transistor circuit. The transistor circuit includes a clamp transistor configured to clamp an anode voltage of the SPAD to be no more than a threshold clamped anode voltage, and a quenching element in series with the clamp transistor and configured to quench the anode voltage of the SPAD when the SPAD is struck by an incoming photon. Readout circuitry is coupled to receive the clamped anode voltage from the transistor circuit and to generate a pixel output therefrom, the threshold clamped anode voltage being below a maximum voltage rating of transistors forming the readout circuitry. | 2022-08-25 |
20220271185 | Optoelectronic Integrated Substrate, Preparation Method Thereof, and Optoelectronic Integrated Circuit - An optoelectronic integrated substrate, a preparation method thereof and an optoelectronic integrated circuit. The electronic integrated substrate includes a base substrate and an electronic device and a photo-diode disposed on the base substrate, wherein the photo-diode includes an ohmic contact layer and an intrinsic amorphous silicon layer, and the ohmic contact layer and the intrinsic amorphous silicon layer are sequentially arranged along a direction parallel to the plane of the base substrate and are connected. | 2022-08-25 |
20220271186 | AVALANCHE PHOTODIODE AND AN OPTICAL RECEIVER HAVING THE SAME - Examples described herein relate to an avalanche photodiode (APD) and an optical receiver including the APD. The APD may include a substrate and a photon absorption region disposed on the substrate. The substrate may include a charge carrier acceleration region under the photon absorption region; a charge region adjacent to the charge carrier acceleration region; and a charge carrier multiplication region adjacent to the charge region. The charge carrier acceleration region, the charge region, and the charge carrier multiplication region are laterally formed in the substrate. When a biasing voltage is applied to the optoelectronic device, photon-generated free charge carriers may be generated in the photon absorption region and are diffused into the charge carrier acceleration region. The charge carrier acceleration region is configured to accelerate the photon-generated free charge carriers prior to the photon-generated free charge carriers entering into the charge region and undergoing impact ionization in the charge carrier multiplication region. | 2022-08-25 |
20220271187 | FAST SPATIAL LIGHT MODULATOR BASED ON ATOMICALLY THIN REFLECTOR - An optical device useful for spatial light modulation. The device comprises: a semiconductor layer having a first surface and a second surface, the semiconductor having an electric field-dependent resonance wavelength; a first electrode electrically connected to the semiconductor layer; a first insulating layer adjacent to the first surface of the semiconductor layer, and a second insulating layer adjacent to the second surface of the semiconducting layer, the first and the second insulating layers each being optically transparent at the resonance wavelength; a first group of at least one gate electrodes disposed adjacent to the first insulating layer, and a second group of at least one gate electrodes disposed adjacent to the second insulating layer, each gate electrode being at least 80% optically transparent at the resonance wavelength; wherein the first and the second groups of gate electrodes, taken together, form at least two regions in the semiconductor layer, an electrostatic field in each of the at least two regions being independently controllable by application of voltage to the first and the second groups of gate electrodes, the at least two regions abutting each other along at least one boundary. | 2022-08-25 |
20220271188 | ENERGY HARVESTING ELECTRO-OPTIC DISPLAYS - An energy harvesting electro-optic display is disclosed comprising a photovoltaic cell that converts part of the incident light to electric current or voltage, wherein the electric current or voltage is used for the operation of the electro-optic display upon the conversion or stored in a storage component to be used for the operation of the display. | 2022-08-25 |
20220271189 | FABRICATION METHOD FOR PHOTOVOLTAIC ASSEMBLY - Provided is a method for fabricating a photovoltaic module. The method includes: providing a cell sheet having a predetermined thickness, and cutting the cell sheet along a direction parallel to busbars of the cell sheet, to form cutting lines on a surface of the cell sheet; splitting the cell sheet along the cutting lines, to obtain multiple cell pieces; coating, for each of the cell pieces, a conductive adhesive material on a busbar located at an edge of the cell piece; arranging the multiple cell pieces in a preset overlapping manner; curing the conductive adhesive material among the cell pieces, to form a cell string in which the cell pieces are conductively connected; and encapsulating the cell string to obtain the photovoltaic module. | 2022-08-25 |
20220271190 | SHINGLED SOLAR CELL PANEL AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a shingled solar cell panel for producing a string in which a plurality of strips are partially overlapped with each other, and for electrically connecting the string and the string, and a method for producing the same, the method comprises providing a wafer made of a HIT in which a plurality of conductive layers are formed on upper and lower portions thereof, respectively, forming an adhesive layer by applying a conductive adhesive on the upper conductive layer, dividing the wafer on which the adhesive layer is formed into a plurality of strips, forming a string by overlapping a lower conductive layer of another strip on an area where an adhesive layer is provided among the divided strips. Accordingly, the upper conductive layer and the lower conductive layer of each of the plurality of strips can be configured to be electrically bonded via only the adhesive layer to provide a shingled solar cell panel at low cost. | 2022-08-25 |
20220271191 | PATTERNING TECHNIQUES FOR VERTICAL SOLID STATE DEVICES - Devices and methods for patterning the vertical solid state devices are provided. In some examples, a method of fabricating micro devices comprising forming device layers on a substrate, forming a first masking layer on a top layer of the device layers, forming a second masking layer on the first masking layer; and etching the device layers using the first and second masking layers to pattern the device layers. | 2022-08-25 |
20220271192 | OPTOELECTRONIC SEMICONDUCTOR CHIP - In one embodiment, the invention relates to an optoelectronic semiconductor chip comprising a semiconductor layer sequence. The semiconductor layer sequence has an n-conducting first layer region, a p-conducting second layer region and an active zone lying therebetween for generating radiation. The second layer region comprises a first subregion directly adjacent to the active zone, the first subregion being composed of p-conducting InvAl1−vP. The second layer region also comprises a second subregion directly adjacent to the first subregion, the second subregion having p-conducting Iny(GaxAl1−x)1−yP. The second layer region also comprises a third subregion as a p-contact layer directly adjacent to the second subregion. | 2022-08-25 |
20220271193 | LIGHT EMITTING DIODE WITH IMPROVED COLOUR PURITY - A light emitting diode is provided having a LED layer configured to emit pump light having a pump light wavelength from a light emitting surface, the LED layer comprising a plurality of Group III-nitride layers. A container layer is provided on the light emitting surface of the LED layer, the container surface including an opening defining a container volume through the container layer to the light emitting surface of the LED layer. A colour converting layer is provided in the container volume, the colour converting Got layer configured to absorb pump light and emit converted light of a converted light wavelength longer than the pump light wavelength. A lens is provided on the container surface over the opening, the lens having a convex surface on an opposite side of the lens to the colour converting layer. A pump light reflector laminate provided over the convex surface of the lens the pump light reflector laminate having a stop-band configured to reflect the pump light centred on a first wavelength. | 2022-08-25 |
20220271194 | STRAIN BALANCED DIRECT BANDGAP ALUMINUM INDIUM PHOSPHIDE QUANTUM WELLS FOR LIGHT EMITTING DIODES - Described herein are optoelectronic devices and methods incorporating strain balanced direct bandgap Al | 2022-08-25 |
20220271195 | PATTERNED SUBSTRATE, SEMICONDUCTOR DEVICE AND NANOTUBE STRUCTURE - Disclosed are a patterned substrate, a semiconductor device and a nanotube structure. The patterned substrate includes, in a vertical direction, a base plate and an AlN layer that are sequentially stacked. The patterned substrate includes, in the vertical direction, a first surface and a second surface that are oppositely arranged, a bottom surface of the base plate is the first surface of the patterned substrate, the second surface of the patterned substrate is a patterned surface, the second surface is provided with a plurality of grooves that are independent of each other in a horizontal direction and are arranged in an array, and at least part of the base plate is left below each of the plurality of grooves. According to the patterned substrate in the present application, a structure of the AlN layer is changed, so that an epitaxial structure grown subsequently is prevented from warping. | 2022-08-25 |