34th week of 2022 patent applcation highlights part 63 |
Patent application number | Title | Published |
20220270996 | COMMUNICATION INTERFACE STRUCTURE BETWEEN PROCESSING DIE AND MEMORY DIE - A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die. | 2022-08-25 |
20220270997 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier. | 2022-08-25 |
20220270998 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2022-08-25 |
20220270999 | DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS - In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die. | 2022-08-25 |
20220271000 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one hole slot; a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one hole slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer. | 2022-08-25 |
20220271001 | SEMICONDUCTOR STRUCTURE WITH NANO-TWINNED METAL COATING LAYER AND FABRICATION METHOD THEREOF - A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer. | 2022-08-25 |
20220271002 | Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly - A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-level assembly, including: align and fix at least one first-level device to a target position on a carrier plate by utilizing the self-alignment capability of first-level alignment solder joints; encapsulating the at least one first-level device to form a molded package body; and exposing the first-level interconnect terminals from the molded package body. The packaging method further comprises align and fix a second-level device to a target position on the first-level assembly by utilizing the self-alignment capability of second-stage alignment solder joints between the first-level assembly and the second-level device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-level device and the second-level device, resulting in improved process efficiency and reduced process cost. | 2022-08-25 |
20220271003 | THREE-DIMENSIONAL STACKED FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME - The present disclosure provides a three-dimensional stacked fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, an underfill layer under the second semiconductor chip, and a second packaging material layer. The formed three-dimensional stacked fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third-direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, the integration of the package is improved, and the package volume can shrink. | 2022-08-25 |
20220271004 | ELECTRONIC DEVICE AND METHOD OF TRANSFERRING ELECTRONIC ELEMENT USING STAMPING AND MAGNETIC FIELD ALIGNMENT - The present disclosure provides a method of transferring an electronic element using a stamping and magnetic field alignment technology and an electronic device including an electronic element transferred using the method. In the present disclosure, a polymer may be simultaneously coated on a plurality of electronic elements using the stamping process, and the polymer may be actively coated on the electronic elements without restrictions on process parameters such as size and spacing of the electronic elements. Moreover, the self-aligned ferromagnetic particles have an anisotropic current flow through which current flows only in the aligned direction. Therefore, the current may flow only vertically between the electronic element and the electrode, and there is no electrical short circuit between a peripheral LED element and the electrode. | 2022-08-25 |
20220271005 | NEAR TIER DECOUPLING CAPACITORS - An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view. | 2022-08-25 |
20220271006 | SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR MODULE MOUNTING BODY - A semiconductor module that enables reduction of manufacturing costs, a method for manufacturing the same, and a semiconductor module mounting body. The semiconductor module having a plurality of stacked dies includes: a first die; a second die disposed side by side with respect to the first die in a direction intersecting with a stacking direction; a third die disposed in the stacking direction, so as to straddle the first die and the second die and that is electrically connected to wiring surfaces of the first die and the second die opposing the third die; projection terminals projecting from the wiring surfaces of the first die and the second die and that project in a space adjacent to at least one of side surfaces of the third die in the direction intersecting with the stacking direction; and rewiring layers disposed so as to overlap with the projection terminals. | 2022-08-25 |
20220271007 | OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTURE - A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. | 2022-08-25 |
20220271008 | MULTI-CHIP PACKAGE WITH REINFORCED ISOLATION - A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation. | 2022-08-25 |
20220271009 | DOUBLE-LAYER PACKAGED 3D FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME - The present disclosure provides a double-layer packaged 3D fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and a second packaging material layer. The formed double-layer packaged 3D fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the integration level of the package and reducing the package volume. | 2022-08-25 |
20220271010 | METHOD FOR MANUFACTURING STACK COMPONENTS - In a method for manufacturing a stack component in which an interposer is interposed to form a space for inserting an interlayer connection pin between circuit layers to be stacked, the method includes a printing step of simultaneously printing and forming the circuit layer and the interposer side by side in a planar manner by a 3D printer, a step of mounting a circuit element on the circuit layer, a step of mounting the interposer on the circuit layer, a step of inserting the interlayer connection pin into the interposer mounted on the circuit layer, and a step of electrically connecting the circuit layer and another circuit layer by the interlayer connection pin by stacking the other circuit layer on the circuit layer via the interposer. | 2022-08-25 |
20220271011 | SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING STACKED INDIVIDUAL MODULES - A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module. | 2022-08-25 |
20220271012 | MANUFACTURING METHOD OF PACKAGE - A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die. | 2022-08-25 |
20220271013 | STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES - Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively. | 2022-08-25 |
20220271014 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a bottom die, a top die bonded to the bottom die, an insulating layer disposed on the bottom die and laterally covering the top die, a first dual-damascene connector overlying the insulating layer and the top die. The bottom die is wider than the top die, and a bonding interface of the top and bottom dies is substantially flat. The first dual-damascene connector is inserted into the insulating layer to be in electrical and physical contact with the bottom die. | 2022-08-25 |
20220271015 | Structures for Providing Electrical Isolation in Semiconductor Devices - Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. | 2022-08-25 |
20220271016 | FILM PATTERN AND METHODS FOR FORMING THE SAME - A method for forming a film pattern includes: providing a substrate having a surface on which the film pattern is to be formed; providing a pattern material containing a hot-melt glue; providing a mask, wherein the mask includes a light-transmitting portion and a light-non-transmitting portion, wherein the pattern material is between the substrate and the mask; irradiating the mask by using a light source capable of generating heat, wherein the light generated by the light source passes through the light-transmitting portion, so that the pattern material under the light-transmitting portion is attached to the surface of the substrate by the melting of the hot-melt glue; and removing the mask and the pattern material under the light-non-transmitting portion. | 2022-08-25 |
20220271017 | HIGH DENSITY PIXELATED LED AND DEVICES AND METHODS THEREOF - At least one array of LEDs (e.g., in a flip chip configuration) is supported by a substrate having a light extraction surface overlaid with at least one lumiphoric material. Light segregation elements registered with gaps between LEDs are configured to reduce interaction between emissions of different LEDs and/or lumiphoric material regions to reduce scattering and/or optical crosstalk, thereby preserving pixel-like resolution of the resulting emissions. Light segregation elements may be formed by mechanical sawing or etching to define grooves or recesses in a substrate, and filling the grooves or recesses with light-reflective or light-absorptive material. Light segregation elements external to a substrate may be defined by photolithographic patterning and etching of a sacrificial material, and/or by 3D printing. | 2022-08-25 |
20220271018 | DOUBLE-LAYER STACKED 3D FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME - The present disclosure provides a double-layer stacked 3D fan-out packaging structure and a method making the structure. The structure includes: a first semiconductor chip, a packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and an underfill layer under the second semiconductor chip. The formed double-layer stacked 3D fan-out packaging structure is capable to package two sets of fan-out wafers in the three-dimension. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the package integration level and reducing the package volume. | 2022-08-25 |
20220271019 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device. | 2022-08-25 |
20220271020 | LIGHT EMITTING SUBSTRATE, LIGHT EMITTING MOTHERBOARD, METHOD FOR OBTAINING LIGHT EMITTING SUBSTRATE, AND DISPLAYING DEVICE - A light emitting substrate, a light emitting motherboard, a method for obtaining a light emitting substrate, and a displaying device. The light emitting substrate comprises a substrate and multiple light emitting units, wherein the substrate is provided with a light emitting region and a bind region located on one side of the light emitting region; each light emitting unit comprises a light zone provided with at least one light emitting diode and a drive circuit provided with multiple pins, and the multiple light emitting units are arranged on the substrate in an array; a direction pointing from the light emitting region to the bind region is a first direction; and in the first direction, the drive circuit of at least one light emitting unit in the last row of the light emitting units is connected to an address line. | 2022-08-25 |
20220271021 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device and a method of fabricating a display device. The display device includes a substrate including an emission area and a subarea adjacent to the emission area, a bank disposed in the emission area of the substrate, a height difference compensation pattern disposed in the subarea of the substrate, a first electrode and a second electrode that are disposed on the bank, the first electrode and the second electrode being spaced apart from each other, and a light-emitting element disposed in the emission area, between the first electrode and the second electrode. | 2022-08-25 |
20220271022 | DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF INTEGRATED CIRCUIT DIES - Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption. | 2022-08-25 |
20220271023 | PROTECTIVE WAFER GROOVING STRUCTURE FOR WAFER THINNING AND METHODS OF USING THE SAME - A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly. | 2022-08-25 |
20220271024 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test. | 2022-08-25 |
20220271025 | INTEGRATED CIRCUIT DEVICE - An IC device includes a first active area extending away from a first endpoint in a first direction, a second active area extending away from a second endpoint in the first direction, a third active area positioned between the first and second active areas, and a gate structure perpendicular to the first through third active areas. The gate structure overlies each of the first and second endpoints and the third active area, and the third active area extends away from the gate structure in a second direction opposite the first direction. | 2022-08-25 |
20220271026 | DUAL SUBSTRATE SIDE ESD DIODE FOR HIGH SPEED CIRCUIT - An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel. | 2022-08-25 |
20220271027 | TVS Diode Circuit with High Energy Dissipation and Linear Capacitance - A TVS circuit having a first diode with a cathode coupled to a first terminal and an anode coupled to a first node. A second diode has an anode coupled to a second node and a cathode coupled to a third node. A third diode is coupled between the first node and second node. A fourth diode is coupled between the first node and third node. A fifth diode is coupled between the second node and a second terminal. A sixth diode is coupled between the second terminal and the third node. A seventh diode can be coupled between the second terminal and an intermediate node between the fifth diode and sixth diode. The first diode is disposed on a first semiconductor die, while the second diode is disposed on a second semiconductor die. Alternatively, the first diode and second diode are disposed on a single semiconductor die. | 2022-08-25 |
20220271028 | FIN-BASED AND BIPOLAR ELECTROSTATIC DISCHARGE DEVICES - The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region. | 2022-08-25 |
20220271029 | DUAL-DIRECTIONAL SILICON-CONTROLLED RECTIFIER - A dual-directional silicon-controlled rectifier includes: a substrate, a well region, a shallow trench isolation structure, heavily doped regions of a first conductive type, heavily doped regions of a second conductive type, and ESD implantations of the first conductive type. Four active regions are provided side by side in the well region. Forward and reverse SCRs and the ESD implantations are provided in the middle active regions. Forward and reverse diodes are provided in the active regions on both sides. One of the heavily doped regions of the first conductive type in contact with the ESD implantations is disposed between the SCRs and the diodes, so as to be electrically connected to a heavily doped region of the second conductive type of the diodes. | 2022-08-25 |
20220271030 | INTEGRATED CIRCUIT COMPRISING A THREE-DIMENSIONAL CAPACITOR - The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor. | 2022-08-25 |
20220271031 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer. | 2022-08-25 |
20220271032 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A transistor is formed on a substrate. The transistor includes a plurality of semiconductor sheets and two source/drain structures. The semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two source/drain structures are disposed at two opposite sides of each of the semiconductor sheets in a horizontal direction respectively, and the two source/drain structures are connected with the semiconductor sheets. | 2022-08-25 |
20220271033 | INVERTED TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3-DIMENSION INTEGRATION (3DI) - Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically. | 2022-08-25 |
20220271034 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail. | 2022-08-25 |
20220271035 | INTEGRATED CIRCUIT STRUCTURE WITH SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME - An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate. | 2022-08-25 |
20220271036 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNING CONTACT AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide. | 2022-08-25 |
20220271037 | SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench. | 2022-08-25 |
20220271038 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present application provides a semiconductor structure and a manufacturing method thereof, and relates to the field of display technology. The semiconductor structure includes a substrate. The substrate includes an array region and a peripheral circuit region surrounding the array region. Multiple capacitors are arranged in an array in the array region. Virtual lines connecting centers of any three consecutively adjacent capacitors among the multiple capacitors located at an edge of the array region define a virtual angle greater than 90°. | 2022-08-25 |
20220271039 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - The present disclosure provides a semiconductor structure and a forming method thereof, including: providing a substrate and a plurality of discrete bit line structures, the bit line structures being located on the substrate, capacitor contact windows being provided between adjacent bit line structures; forming first isolation layers, the first isolation layers covering sidewalls of the bit line structures; forming a sacrificial layer, the sacrificial layer covering sidewalls of the first isolation layers; forming second isolation layers, the second isolation layers covering sidewalls of the sacrificial layer and exposing the top surfaces and bottoms of the sacrificial layer; etching the exposed bottoms of the sacrificial layer to form bottom gaps between the first isolation layers and the second isolation layers; etching the exposed top surfaces of the sacrificial layer to remove the remaining of the sacrificial layer so as to form gaps between the layers. | 2022-08-25 |
20220271040 | MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a memory cell array in which a plurality of memory cells is vertically stacked to a substrate, wherein each of the memory cells includes: a bit line vertically oriented to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate facing each io other with the active layer interposed therebetween, and wherein an edge of the word line and an edge of the back gate have a step shape along a stacking direction of the memory cells. | 2022-08-25 |
20220271041 | SEMICONDUCTOR DEVICES - A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion. | 2022-08-25 |
20220271042 | DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a dynamic random access memory is provided and includes: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on a sidewall of the opening; forming a first part of a buried word line in a lower part of the opening; forming a hard mask layer on a top surface of the hindering layer, where the hindering layer has overhangs covering top corners of the hard mask layer; depositing a first barrier layer on the substrate through hindrance of the overhangs, where the first barrier layer covers the hindering layer and a top surface of the first part and exposes the dielectric layer on the sidewall of the opening; and forming a first conductive layer in the opening, where a sidewall of the first conductive layer contacts the dielectric layer. | 2022-08-25 |
20220271043 | INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches. | 2022-08-25 |
20220271044 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate comprising a cell region; a cell region isolation film in the substrate and extending along an outer edge of the cell region; a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film; a cell spacer on a vertical side surface of the distal end of the bit-line structure; an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film includes silicon nitride. | 2022-08-25 |
20220271045 | SEMICONDUCTOR DEVICE AND STACK OF SEMICONDUCTOR CHIPS - A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region. | 2022-08-25 |
20220271046 | STACKED FERROELECTRIC STRUCTURE - The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost. | 2022-08-25 |
20220271047 | ANNEALED SEED LAYER TO IMPROVE FERROELECTRIC PROPERTIES OF MEMORY LAYER - In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent. | 2022-08-25 |
20220271048 | COMMON-CONNECTION METHOD IN 3D MEMORY - One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure. | 2022-08-25 |
20220271049 | INTEGRATED CIRCUIT DEVICE - An IC device includes first through third device pairs positioned in first through third active areas extending in a first direction, each pair including first and second transistors coupled between respective first and second anti-fuse structures and a shared bit line contact, and each of the first and third active areas being adjacent to the second active area. First through fourth conductive lines extend in a second direction, first and second conductive paths couple the first conductive line to the first anti-fuse structures, a third conductive path couples the fourth conductive line to the second anti-fuse structures, and a fourth conductive path couples the third conductive line to the second transistors. The first and third conductive paths are aligned along the first direction between the first and second active areas, and the second and fourth conductive paths are aligned along the first direction between the second and third active areas. | 2022-08-25 |
20220271050 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device for controlling memory cell transistors includes a substrate, a first well of a first conductivity type in the substrate, a second well of a second conductivity type that electrically separates the first well from the substrate therein and includes a first portion surrounding the first well, and a second portion facing a bottom portion of the first well and having a side surface contacting a side surface of the first portion, a third well of the first conductivity type in the substrate, the third well surrounding the first portion of the second well with being separated therefrom, and a first transistor that includes a gate electrode facing the first well via a first insulating film. A bottom surface of the first portion of the second well is closer to a surface of the substrate than a bottom surface of the second portion of the second well. | 2022-08-25 |
20220271051 | MICROELECTRONIC DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED ELECTRONIC DEVICES AND METHODS - A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed. | 2022-08-25 |
20220271052 | DEVICES INCLUDING FLOATING VIAS - A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices. | 2022-08-25 |
20220271053 | THREE-DIMENSIONAL MEMORY DEVICE WITH PERIPHERAL CIRCUIT LOCATED OVER SUPPORT PILLAR ARRAY AND METHOD OF MAKING THEREOF - A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers. | 2022-08-25 |
20220271054 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate extending in a first and a second directions, memory blocks arranged in the first direction, and an inter-block structure disposed between the memory blocks. The memory block includes conductive layers, first semiconductor layers, and electric charge accumulating portions. The conductive layers are arranged in the third direction, and extend in the second direction. The first semiconductor layers extend in the third direction and are opposed to the conductive layers. The electric charge accumulating portions are disposed between the conductive layers and the first semiconductor layers. The inter-block structure includes a second semiconductor layer extending in the second direction and the third direction. The first semiconductor layers and second semiconductor layers are a part of the semiconductor substrate. | 2022-08-25 |
20220271055 | MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE - There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other. | 2022-08-25 |
20220271056 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole. | 2022-08-25 |
20220271057 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer. | 2022-08-25 |
20220271058 | METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING BURIED BIAS PAD - A method of making an integrated circuit includes surrounding a first bias pad with dielectric material of a buried oxide layer. The method includes adding dopants to a layer of semiconductor material over the first bias pad. The method includes depositing a gate dielectric and a gate electrode over a top surface of the layer of semiconductor material. The method includes etching the gate dielectric and the gate electrode to isolate a gate electrode over the layer of semiconductor material. The method includes depositing an inter layer dielectric (ILD) material over the gate electrode and the layer of semiconductor material. The method includes etching at least one bias contact opening down to the first bias pad. The method includes filling the at least one bias contact opening with a bias contact material. The method includes electrically connecting at least one bias contact to an interconnect structure of the semiconductor device. | 2022-08-25 |
20220271059 | DISPLAY SUBSTRATE, DISPLAY DEVICE, DISPLAY SUBSTRATE, METHOD OF FORMING DISPLAY SUBSTRATE, AND METHOD OF FORMING DISPLAY DEVICE - A display substrate, a display device, a method of forming a display substrate, and a method of forming a display device are provided. The display substrate includes: a first insulation structure, including a display area and a frame area, where the frame area is arranged around the display area, and at least one first groove is arranged in the first insulation structure of the display area; a first wiring layer arranged on the first insulating structure and covering a side surface and a bottom surface of the first groove; a second insulation structure arranged on the first wiring layer, where at least one first through-hole is formed in the second insulation structure of the frame area; a first conductive structure covering a part of an upper surface of the second insulating structure and at least a sidewall and a bottom surface of the first via-hole. | 2022-08-25 |
20220271060 | DISPLAY DEVICE - A thin film transistor substrate includes a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The first conductive layer is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The second conductive layer is disposed on the first conductive layer and includes a wiring portion extending along a second direction. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. When viewed in a third direction perpendicular to the first direction and the second direction, an interface disposes between the trace portion and the protrusive portion, a virtual extending line overlaps the second edge and the interface, and the semiconductor layer extends beyond the virtual extending line. | 2022-08-25 |
20220271061 | MANUFACTURING METHOD OF PIXEL STRUCTURE OF REFLECTIVE DISPLAY - The present disclosure discloses a manufacturing method of a pixel structure of a reflective display comprising: providing a substrate; forming a shielding layer on the substrate; forming a low reflective layer on the shielding layer; and forming a reflective layer on the low reflective layer, wherein the reflective layer comprises a plurality of reflection regions, the plurality of reflection regions are arranged at intervals, and a part of the low reflective layer is exposed between the plurality of reflection regions. In the present disclosure, the reflection of light in the gap between the pixels is avoided by the low reflective layer, such that the notice of liquid crystal disturbance by human eyes is reduced, and a reflective display with good display function and low power consumption is implemented. | 2022-08-25 |
20220271062 | DISPLAY DEVICE AND ELECTRONIC DEVICE - A display device capable of improving image quality is provided. A storage node is provided in each pixel and first data can be held in the storage node. Second data is added to the first data by capacitive coupling, which can be supplied to a display element. Thus, the display device can display a corrected image. A reference potential for the capacitive coupling operation is supplied from a power supply line or the like, and thus the first data and the second data can be supplied from a common signal line. | 2022-08-25 |
20220271063 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C. | 2022-08-25 |
20220271064 | Driving Backplane, Preparation Method for Same, and Display Device - Provided are a driving backplane, a preparation method for the same, and a display device. The driving backplane includes a driving structure layer arranged on a base and a supporting structure arranged on a side of the driving structure layer away from the base. The driving structure layer includes a first conductive layer and a second conductive layer which are stacked. There is no overlapping region between an orthographic projection of the supporting structure on the base and an orthographic projection of at least one of the first conductive layer and the second conductive layer on the base. | 2022-08-25 |
20220271065 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING SAME - An array substrate and a method of manufacturing the same are provided. The array substrate includes an active island and a gate insulating layer, a gate, and an interlayer dielectric layer stacked on the active island. A color resist layer is disposed on the interlayer dielectric layer, and an orthographic projection of the color resist layer on a base substrate covers an orthographic projection of a channel region of the active island on the base substrate. | 2022-08-25 |
20220271066 | TRANSISTOR ARRAY SUBSTRATE, METHOD OF MANUFACTURING TRANSISTOR ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY APPARATUS, AND ELECTRIC EQUIPMENT - A transistor array substrate includes a scan line formed on a support substrate, a capacitive section formed above the scan line, and a thin film transistor formed above the capacitive section, in which a perimeter of the thin film transistor is surrounded by a wall-shaped horizontal light-blocking film that extends in a normal direction with respect to the support substrate and is in contact with a surface of an electrode that is an uppermost layer of the capacitive section, and an upper light-blocking film is formed above the thin film transistor. | 2022-08-25 |
20220271067 | PHOTODETECTOR - A solid-state image sensor includes at least two or more APDs formed on a substrate. First regions are arranged outside the APDs as viewed in plane. Adjacent ones of the APDs and the first regions are separated from each other through a separation region. A first voltage V | 2022-08-25 |
20220271068 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Electromagnetic noise is inhibited in a semiconductor package provided with rewiring. | 2022-08-25 |
20220271069 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a first semiconductor substrate, an isolation region, a charge holding section, and a charge accumulation section. The first semiconductor substrate is a substrate in which a photoelectric converter is provided for each of unit regions. The isolation region is provided to run through the first semiconductor substrate in a thickness direction and electrically isolates the unit regions from each other. The charge holding section is electrically coupled to the photoelectric converter and configured to receive signal charge from the photoelectric converter. The charge accumulation section is shared by two or more of the unit regions and is a section to which the signal charge is transferred from the photoelectric converter and the charge holding section of each of the unit regions sharing the charge accumulation section. | 2022-08-25 |
20220271070 | SOLID-STATE IMAGING DEVICE - There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections. | 2022-08-25 |
20220271071 | METHOD OF FORMING BACKSIDE ILLUMINATED IMAGE SENSOR DEVICE WITH SHIELDING LAYER - A backside illuminated image sensor device with a shielding layer and a manufacturing method thereof are provided. In the backside illuminated image senor device, a patterned conductive shielding layer is formed on a dielectric layer on a backside surface of a semiconductor substrate and surrounding a pixel array on a front side surface of the semiconductor substrate. | 2022-08-25 |
20220271072 | SOLID-STATE IMAGE PICKUP DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE - Provided are a solid-state image pickup device capable of improving heat dissipation property, and an electronic apparatus including the solid-state image pickup device. A solid-state image pickup device according to the present technology includes: at least one photoelectric converter formed in a semiconductor substrate; and a thermal conductive layer that is arranged on one surface side and/or another surface side of the semiconductor substrate and includes a material having a thermal conductivity higher than that of SiO | 2022-08-25 |
20220271073 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTODETECTOR, PHOTODETECTION SYSTEM, ELECTRONIC APPARATUS, AND MOBILE BODY - A highly functional photoelectric conversion element is provided. The photoelectric conversion element includes: a first photoelectric converter that detects light in a first wavelength range and photoelectrically converts the light; a second photoelectric converter that detects light in a second wavelength range and photoelectrically converts the light to obtain distance information of a subject; and an optical filter that is disposed between the first photoelectric converter and the second photoelectric converter, and allows the light in the second wavelength range to pass therethrough more easily than the light in the first wavelength range. The first photoelectric converter includes a stacked structure and an electric charge accumulation electrode. The stacked structure includes a first electrode, a first photoelectric conversion layer, and a second electrode that are stacked in order, and the electric charge accumulation electrode is disposed to be separated from the first electrode and be opposed to the first photoelectric conversion layer with an insulating layer interposed therebetween. | 2022-08-25 |
20220271074 | DETECTION DEVICE - A detection device includes a sensor area in which a plurality of detection elements each comprising a photoelectric conversion element are arranged in a detection region, a drive circuit configured to supply a plurality of drive signals to the detection elements, and a detection circuit configured to process a detection signal output from each of the detection elements. | 2022-08-25 |
20220271075 | FAST CHARGE TRANSFER FLOATING DIFFUSION REGION FOR A PHOTODETECTOR AND METHODS OF FORMING THE SAME - A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel. | 2022-08-25 |
20220271076 | PHOTOSENSOR HAVING GATE-ALL-AROUND STRUCTURE AND METHOD FOR FORMING THE PHOTOSENSOR - A photosensor includes a substrate, a photo-detecting column, a gate structure, a floating node structure and a channel structure. The substrate has a first doping type. The photo-detecting column has a second doping type and is disposed in the substrate. The gate structure is disposed on the substrate in a vertical direction, and is electrically insulated from the photo-detecting column. The floating node structure is disposed on the gate structure opposite to the photo-detecting column in the vertical direction, and is electrically insulated from the gate structure. The channel structure extends through the gate structure, is electrically insulated from the gate structure, and is electrically connected to the photo-detecting column and the floating node structure. | 2022-08-25 |
20220271077 | IMAGE SENSOR - An image sensor includes a semiconductor substrate having a first surface and a second surface. The first surface includes an element isolation trench. An element isolation layer is arranged inside the element isolation trench. The element isolation layer defines an active region. A gate electrode is arranged on the first surface of the semiconductor substrate. An interlayer insulating layer is arranged on the first surface of the semiconductor substrate and covers the gate electrode. A ground contact is configured to penetrate the element isolation layer and the interlayer insulating layer and contacts the semiconductor substrate. A color filter is arranged on the second surface of the semiconductor substrate. | 2022-08-25 |
20220271078 | SOLID-STATE IMAGING ELEMENT - Provided is a solid-state imaging element including a support 1 having a photoelectric conversion unit 10 and an optical filter 20 provided on a light incident side with respect to the photoelectric conversion unit 10. The optical filter 20 has two or more kinds of pixels 21, 22, and 23 arranged in a patterned manner and a partition wall 25 disposed between the pixels. A refractive index of the partition wall with respect to light having a wavelength of 533 nm is 1.10 to 1.30, a width W | 2022-08-25 |
20220271079 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING - A semiconductor arrangement is provided. The semiconductor arrangement includes a first photodiode in a substrate. The semiconductor arrangement includes a lens array over the substrate. A first plurality of lenses of the lens array overlies the first photodiode. Radiation incident upon the first plurality of lenses is directed by the first plurality of lenses to the first photodiode. | 2022-08-25 |
20220271080 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element. | 2022-08-25 |
20220271081 | MULTI-SPECTRAL IMAGE SENSOR - In some examples, an apparatus comprises: a first photodiode to sense a first component of light associated with a first wavelength, and a second photodiode configured to sense a second component of the light associated with a second wavelength, the first component and the second component being associated with, respectively, a first wavelength and a second wavelength. The apparatus further comprises a first optical structure and a second optical structure positioned over, respectively, the first photodiode and the second photodiode. The first optical structure is configured to increase a propagation path of the first component of the light within the first photodiode and has a first optical property based on the first wavelength. The second optical structure is configured to increase a propagation path of the second component of the light within the second photodiode, and has a second optical property based on the second wavelength. | 2022-08-25 |
20220271082 | FLIP-CHIP LIGHT-EMITTING DIODE STRUCTURE CAPABLE OF EMITTING TRICHROMATIC SPECTRUM AND MANUFACTURING METHOD THEREOF - A flip-chip light-emitting diode structure capable of emitting trichromatic spectrum and a manufacturing method thereof, including a blue-green light layer with a light-stimulated green light-emitting structure and an electron-stimulated blue light-emitting structure, a bonding layer and a red light layer with a light-stimulated red light-emitting structure. The manufacturing method uses a sapphire bonding layer as the bonding layer, and forming the blue-green light layer and the red light layer by growing epitaxy on two sides of the sapphire bonding layer; or, after growing the blue-green light layer and the red light layer by epitaxy respectively, uses the bonding layer to connect. Accordingly, an externally applied voltage stimulates the electron-stimulated blue light-emitting structure to generate a blue light, the blue light stimulates the light-stimulated green light-emitting structure to generate a green light, and the blue and green lights stimulate the light-stimulated red light-emitting structure to generate a red light. | 2022-08-25 |
20220271083 | LIGHT-EMITTING DEVICE - A first light emission region includes an n-type contact layer, a first light-emitting layer, a p-type contact layer, and a wavelength conversion layer. The second light emission region includes an n-type contact layer, a first light-emitting layer, a first intermediate layer, a second light-emitting layer, and a p-type contact layer. The third light emission region includes an n-type contact layer, a first light-emitting layer, a first intermediate layer, a second light-emitting layer, a second intermediate layer, a third light-emitting layer, and a p-type contact layer. The wavelength conversion layer is disposed between the p-type contact layer of the first light emission region and the driving circuit substrate. | 2022-08-25 |
20220271084 | u-LED, u-LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-08-25 |
20220271085 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-08-25 |
20220271086 | DISPLAY APPARATUS - A display apparatus includes a substrate, a light-emitting device provided on the substrate, a driving transistor device configured to control the light-emitting device, a first power supply line electrically connected to a source region of the driving transistor device, a conductive pattern electrically connected to a gate electrode of the driving transistor device, and a second power supply line electrically connected to the first power supply line, wherein the conductive pattern and the first power supply line constitute a first capacitor, and the conductive pattern and the second power supply line constitute a second capacitor, wherein the first capacitor and the second capacitor are connected in parallel. | 2022-08-25 |
20220271087 | MEMORY DEVICE AND METHOD FOR FORMING THEREOF - A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench. | 2022-08-25 |
20220271088 | MEMORY ARRAY - A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region. | 2022-08-25 |
20220271089 | THREE-DIMENSIONAL STACKED PHASE CHANGE MEMORY AND PREPARATION METHOD THEREOF - The disclosure belongs to the technical field of microelectronic devices and memories, and discloses a three-dimensional stacked phase change memory and a preparation method thereof. The preparation method includes: preparing a multilayer structure in which horizontal electrode layers and insulating layers are alternately stacked, then performing etching to form trenches and separated three-dimensional strip electrodes, next filling the trenches with an insulating medium, and then forming small holes at the boundary region between the three-dimensional strip electrodes and the insulating medium, thereafter sequentially depositing a phase change material on the walls of the small holes, and filling the small holes with an electrode material to prepare vertical electrodes, so as to obtain a three-dimensional stacked phase change memory stacked in multiple layers. By improving the overall process of the preparation method, the disclosure realizes the establishment of a three-dimensional phase change memory array by using a vertical electrode structure. | 2022-08-25 |
20220271090 | VERTICAL MEMORY DEVICES - The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell. | 2022-08-25 |
20220271091 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device includes a memory cell structure on a substrate, the memory cell structure including conductive layers, each of the conductive layers including conductive lines spaced apart from each other in a direction parallel to a top surface of the substrate, and memory cell arrays alternatingly stacked with the conductive layers in a first direction perpendicular to a top surface of the substrate, a first peripheral circuit layer between the substrate and the memory cell structure, the first peripheral circuit layer including first transistors, and a second peripheral circuit layer between the first peripheral circuit layer and the memory cell structure, the second peripheral circuit layer including second transistors, and the second transistors including core transistors that are connected to corresponding ones of the conductive lines. | 2022-08-25 |
20220271092 | CONDUCTIVE BRIDGING RANDOM ACCESS MEMORY FORMED USING SELECTIVE BARRIER METAL REMOVAL - A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines. | 2022-08-25 |
20220271093 | MEMORY DEVICE - A memory device according to an embodiment includes a fluid layer extending in a first direction, a particle in the fluid layer, a first control electrode made of a first material, a first insulating film provided between the fluid layer and the first control electrode, a second control electrode made of a second material and provided to be spaced apart from the first control electrode in the first direction, a second insulating film provided between the fluid layer and the second control electrode, a third control electrode made of a third material different from the first material and the second material and provided between the first control electrode and the second control electrode, and a third insulating film provided between the fluid layer and the third control electrode. | 2022-08-25 |
20220271094 | IMAGE SENSOR PIXEL - A pixel includes a CMOS support and at least two organic photodetectors. A same lens is vertically in line with the organic photodetectors. | 2022-08-25 |
20220271095 | DISPLAY PANEL - A display panel, includes: a base substrate including a pixel region and a peripheral region adjacent to the pixel region; a reflection pattern disposed on the base substrate; a light conversion pattern disposed on the base substrate and overlapping the reflection pattern, the light conversion pattern including a top surface and a side surface; an emitter disposed on the light conversion pattern to emit a source light, the emitter being in contact with at least the side surface of the light conversion pattern; a color filter disposed on the top surface of the light conversion pattern; and a light-blocking pattern disposed outside the color filter. | 2022-08-25 |