34th week of 2022 patent applcation highlights part 62 |
Patent application number | Title | Published |
20220270896 | DEVICE FOR ALIGNMENT OF TWO SUBSTRATES - A device and method for alignment of a first contact surface of a first substrate with a second contact surface of a second substrate which can be held on a second platform includes first X-Y positions of first alignment keys located along the first contact surface, and second X-Y positions of second alignment keys which correspond to the first alignment keys and which are located along the second contact surface. The first contact surface can be aligned based on the first X-Y positions in the first alignment position and the second contact surface can be aligned based on the second X-Y positions in the second alignment position. | 2022-08-25 |
20220270897 | SYSTEM AND METHOD FOR SPATIALLY CONTROLLING AN AMOUNT OF ENERGY DELIVERED TO A PROCESSED SURFACE OF A SUBSTRATE - System for spatially controlling an amount of energy delivered to a processed surface of a processed substrate including a first area and a second area, the first area having a first combination of optical properties and thermal properties, and the second area having a second combination of optical properties and thermal properties, the first combination and second combination being different, the system including a light source configured to emit a pulsed light beam towards the processed surface, wherein the pulsed light beam delivers a first amount of energy onto the first area of the processed surface so that the first area reaches a first target temperature, and a second amount of energy to the second area of the processed surface so that the second area reaches a second target temperature. A corresponding method is also described. | 2022-08-25 |
20220270898 | ISOLATED VOLUME SEALS AND METHOD OF FORMING AN ISOLATED VOLUME WITHIN A PROCESSING CHAMBER - A method and apparatus for substrate processing and a cluster tool including a transfer chamber assembly and a plurality of processing assemblies. Processing chamber volumes are sealed from the transfer chamber volume using a support chuck on which a substrate is disposed. A seal ring assembly is coupled to the support chuck. The seal ring assembly includes an inner assembly, an assembly bellows circumscribing the inner assembly, and a bellows disposed between the inner and outer platform. An inner ring is disposed between inner assembly of the seal ring assembly and the bottom surface of the support chuck. An outer ring disposed between the seal ring assembly and the lower sealing surface of the process chamber wall. The support chuck is raised to form an isolation seal between the processing chamber volume and the transfer chamber volume using the bellows, the inner ring, and the outer ring. | 2022-08-25 |
20220270899 | METHODS AND APPARATUS FOR MEASURING TEMPERATURE USING CENTERFIND SYSTEMS - Disclosed are systems and methods for measuring the temperature change of one or more substrates within a semiconductor processing system. The temperature change information may be used to optimize throughput of substrates within the system and to troubleshoot quality issues that may be impacted by temperature. | 2022-08-25 |
20220270900 | WAFER TEMPERATURE ADJUSTING DEVICE, WAFER PROCESSING APPARATUS, AND WAFER TEMPERATURE ADJUSTING METHOD - A wafer temperature adjusting device includes an upper surface, a wafer support mechanism that supports a wafer above the upper surface in a state where a distance between the upper surface and the wafer is maintained within a predetermined range and a first space between the upper surface and the wafer communicates with a second space above the wafer, a stage that adjusts a temperature of the upper surface, and a gas supply unit that supplies a heat transfer gas to the first space and the second space. | 2022-08-25 |
20220270901 | INTEGRATED HARDWARE-SOFTWARE COMPUTER VISION SYSTEM FOR AUTONOMOUS CONTROL AND INSPECTION OF SUBSTRATE PROCESSING SYSTEMS - A substrate processing system comprises an edge computing device including processor that executes instructions stored in a memory to process an image or video captured by camera(s) of at least one of a substrate and a component of the substrate processing system. The component is associated with a robot transporting the substrate between processing chambers of the substrate processing system or between the substrate processing system and a second substrate processing system. The cameras are located along a travel path of the substrate. The instructions configure the processor to transmit first data from the image to a remote server via a network and to receive second data from the remote server via the network in response to transmitting the first data to the remote server. The instructions configure the processor to operate the substrate processing system according to the second data in an automated or autonomous manner. | 2022-08-25 |
20220270902 | COMPONENT CONVEYING INSTRUMENT WITH AN ADJUSTING UNIT AND METHOD OF ADJUSTING A COMPONENT CONVEYING INSTRUMENT - A component conveying instrument comprising a first and second conveying instrument for conveying a component. The first conveying instrument is arranged to transfer the component to the second conveying instrument at a transfer location. The component conveying instrument further comprises an adjustment unit for adjusting one of the conveying instruments relative to the other conveying instrument along at least one or about at least one adjustment axis and an imaging unit. The imaging unit captures at least one image of the transfer location showing an end region of the first conveying instrument, and an end region of the second conveying instrument. The component conveying instrument also comprises an analyzing unit for analyzing the image, where the analyzing unit is coupled to the adjusting unit and is adapted to determine an asymmetry measure between the end region of the first conveying instrument and the end region of the second conveying instrument. | 2022-08-25 |
20220270903 | SUBSTRATE TRANSPORT APPARATUS - A transport apparatus including a drive section connected to a frame and including a multi-drive shaft spindle, with at least one coaxial shaft spindle, more than one different interchangeable motor module arranged in a stack, each having a motor operably coupled thereto and defining a corresponding independent drive axis, and a can seal disposed between the stator and rotor of each motor module and hermetically sealing the stator and rotor from each other, at least one of the motor modules is selectable for placement in the stack from other different interchangeable motor modules, each having a different predetermined characteristic, independent of placement in the stack, that defines a different predetermined drive characteristic of the corresponding drive axis, independent of shaft spindle location, so that selection of the at least one motor module determines the different predetermined drive characteristic of the corresponding axis different from another of the independent drive axis. | 2022-08-25 |
20220270904 | SUBSTRATE PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD - A substrate processing method includes: carrying out a substrate from a substrate transfer container by a substrate transfer device; placing the substrate in a first position of a substrate holder; moving the substrate holder into a reaction container and processing the substrate in the reaction chamber; obtaining a film thickness measurement result of the substrate processed in the reaction container; creating a model from the film thickness measurement result; determining a second position where the substrate is placed in the substrate holder and a transfer position setting value obtained from the model; adjusting the first position of the substrate to the second position; calculating an eccentricity state of the substrate from a newly obtained film thickness measurement result; calculating an optimization such that the eccentricity state is minimized; and determining a third position to which a new substrate is placed from the transfer position setting value. | 2022-08-25 |
20220270905 | APPARATUS AND METHODS FOR DETERMINING WAFER CHARACTERS - Apparatus and methods for determining wafer characters are disclosed. In one example, an apparatus is disclosed. The apparatus includes: a processing tool configured to process a semiconductor wafer; a device configured to read an optical character disposed on the semiconductor wafer while the semiconductor wafer is located at the apparatus for wafer fabrication; and a controller configured to determine whether the optical character matches a predetermined character corresponding to the semiconductor wafer based on the optical character read in real-time at the apparatus. | 2022-08-25 |
20220270906 | ELECTROSTATIC CHUCK WITH DIFFERENTIATED CERAMICS - Electrostatic chucks (ESCs) for reactor or plasma processing chambers, and methods of fabricating ESCs, are described. In an example, a substrate support assembly includes a ceramic bottom plate having heater elements therein, the ceramic bottom plate composed of alumina having a first purity. The substrate support assembly also includes a ceramic top plate having an electrode therein, the ceramic top plate composed of alumina having a second purity higher than the first purity. A bond layer is between the ceramic top plate and the ceramic bottom plate. The ceramic top plate is in direct contact with the bond layer, and the bond layer is in direct contact with the ceramic bottom plate. | 2022-08-25 |
20220270907 | FORMING MESAS ON AN ELECTROSTATIC CHUCK - A body of an electrostatic chuck comprises mesas disposed on a polished surface of the body. Each of the mesas comprises an adhesion layer disposed on the polished surface of the body, a transition layer disposed over the adhesion layer, and a coating layer disposed over the transition layer. The coating layer has a hardness of at least 14 Gpa. The body further comprises a sidewall coating disposed over a sidewall of the body. A method for preparing the body comprises polishing the surface of the body and cleaning the polished surface. The method further comprises depositing the mesas by depositing the adhesion layer on the body, the transition layer over the adhesion layer, and the coating layer over the transition layer. Further, the method includes, polishing the mesas. | 2022-08-25 |
20220270908 | HIGH THROUGHPUT MICROPRINTING PROCESS - Embodiments disclose methods of transferring selected microdevices on a receiver substrate. In one embodiment, a high resolution display comprising a light emitting device (LED) array may be provided to assist in transferring the microdevices. The LED array can selectively either release a layer by using light or cure a bonding layer. The pixels in the display can be turned on corresponding to a set of selected microdevices with predefined intensities to release the set of selected microdevices from the donor substrate. | 2022-08-25 |
20220270909 | GLASS CARRIER STACKED PACKAGE ASSEMBLY METHOD - A method for assembling at least one stacked substrate package, each stacked substrate package includes binding a laminated base substrate, configured to route interconnections between circuitry on a first surface of the laminated base substrate and circuitry on a second surface of the laminated base substrate, to a surface of a rigid carrier to prevent warping of the laminated base substrate. Each base substrate is coupled to at least one dielectric build-up substrate, which is configured to route integrated interconnections between a top surface and a bottom surface of the dielectric build-up substrate, to the laminated base substrate. At least one integrated circuit die is coupled to the at least one dielectric build-up substrate, and then the carrier is released from the laminated base substrate to form an assembled stacked substrate package. Also, multiple stacked substrate packages may be assembled in parallel on one carrier. | 2022-08-25 |
20220270910 | PROCESSING APPARATUS - A processing apparatus includes a wafer carrying-out unit, a wafer table that supports a wafer carried out, a frame carrying-out unit, a frame table that supports an annular frame carried out, a tape sticking unit that sticks a tape to the annular frame, a tape-attached frame conveying unit, a tape pressure bonding unit that executes pressure bonding of the tape of a tape-attached frame to the back surface of the wafer, a frame unit carrying-out unit, and a reinforcing part removing unit that cuts and removes a ring-shaped reinforcing part from the wafer of a frame unit. | 2022-08-25 |
20220270911 | PROCESSING APPARATUS - A processing apparatus includes a wafer carrying-out unit, a wafer table that supports a wafer carried out, a frame carrying-out unit, a frame table that supports an annular frame carried out, a tape sticking unit that sticks a tape to the frame, a tape-attached frame conveying unit, a tape pressure bonding unit that executes pressure bonding of the tape of a tape-attached frame to a back surface of the wafer, a frame unit carrying-out unit, and a beveled part removing unit that cuts and removes, in a ring manner, a beveled part formed in an outer circumferential surplus region from the wafer of a frame unit. | 2022-08-25 |
20220270912 | SUBSTRATE TRANSFER MECHANISM AND SUBSTRATE TRANSFERRING METHOD - A substrate transfer mechanism for transferring a substrate to each of a plurality of stacked processing modules that process the substrate includes: an arm base provided with a first driver; a lift configured to move up and down the arm base; a first arm extending transversely from a lower side of the arm base, and having a tip end that pivots around a vertical axis with respect to the arm base by the first driver; a second arm extending transversely from an upper side of the tip end of the first arm, and having a tip end that pivots around a vertical axis with respect to the first arm along with the pivoting of the first arm; and a substrate holder provided on an upper side of the tip end of the second arm, and configured to rotate around a vertical axis with respect to the second arm. | 2022-08-25 |
20220270913 | WAFER-HOLDING DEVICE AND THIN-FILM-DEPOSITION EQUIPMENT USING THE SAME - The present disclosure provides a wafer-holding device, which mainly includes a wafer carrier, a first lid ring and a second lid ring, wherein the wafer carrier includes a carrying surface for carrying a wafer. The second lid ring is connected to the first-lid ring and placed on a radial-inner side of the first lid ring, wherein the first lid ring has a circumference larger than that of the second lid ring, for carrying the second lid ring. When the wafer carrier moves toward the first lid ring and the second lid ring, the second lid ring contacts the wafer on the wafer carrier, to fasten the wafer on the carrying surface of the wafer carrier, for performing a thin-film deposition to the wafer. | 2022-08-25 |
20220270914 | SUBSTRATE TREATMENT DEVICE - A substrate treatment device according to an embodiment includes a placement part that includes a placement platform on which a substrate is placeable and that is configured to rotate the placed substrate, a cooling nozzle configured to supply a cooling gas to a space between the placement platform and the substrate, a liquid supplier configured to supply a liquid to a surface of the substrate opposite to the placement platform side, and a dispersion plate located at a discharge side of the cooling gas of the cooling nozzle. The dispersion plate includes a first hole extending through the dispersion plate in a thickness direction. The first hole is located at a position overlapping a central axis of the cooling nozzle when viewed along a direction along the central axis of the cooling nozzle. | 2022-08-25 |
20220270915 | CHEMICAL MECHANICAL POLISHING TOPOGRAPHY RESET AND CONTROL ON INTERCONNECT METAL LINES - A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap. | 2022-08-25 |
20220270916 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, where a functional structure layer is formed on a surface of the substrate, and particles are provided on the surface of the functional structure layer; forming a first dielectric layer on the surface of the substrate, where the first dielectric layer covers the functional structure layer; grinding to remove part of the first dielectric layer until the particles are exposed, and removing the particles, to form first recesses on a surface of the remaining first dielectric layer; and forming a second dielectric layer on the surface of the first dielectric layer, where the second dielectric layer fills the first recesses. | 2022-08-25 |
20220270917 | CYCLICAL DEPOSITION METHOD AND APPARATUS FOR FILLING A RECESS FORMED WITHIN A SUBSTRATE SURFACE - There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber; introducing a first reactant, to form first active species, for a first pulse time to the substrate; introducing a second reactant for a second pulse time to the substrate; and introducing a third reactant, to form second active species, for a third pulse time to the substrate. An apparatus for filling a recess is also disclosed and a structure formed using the method and/or apparatus is disclosed. | 2022-08-25 |
20220270918 | METHOD OF MAKING A SEMICONDUCTOR ARRANGEMENT - A method of making a semiconductor arrangement includes forming a first layer of molecular ions in a first wafer interface region of a first wafer, forming a second layer of molecular ions in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region. | 2022-08-25 |
20220270919 | METHOD FOR FORMING LEAD WIRES IN HYBRID-BONDED SEMICONDUCTOR DEVICES - Embodiments of a hybrid-bonded semiconductor structure are disclosed. The semiconductor structure comprises a first conductive structure and a second conductive structure in a base dielectric layer. The base dielectric layer has a non-flat top surface. A first top surface of the first conductive structure is non-coplanar with a second top surface of the second conductive structure. The semiconductor structure further comprises an alternating dielectric layer stack comprising a plurality of dielectric layers sequentially disposed on the base dielectric layer, wherein at least two of the plurality of dielectric layers have non-uniform thickness. The semiconductor structure further comprises a first lead wire and a second lead wire formed in the alternating dielectric layer stack and electrically connected to the first conductive structure and the second conductive structure, respectively. | 2022-08-25 |
20220270920 | SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY USING THE SAME - Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer. | 2022-08-25 |
20220270921 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure includes: providing a substrate; forming a plurality of first barrier structures that are distributed at intervals on the substrate, in which first trench structures exposing the substrate is provided between the adjacent first barrier structures; forming an initial dielectric layer, in which the initial dielectric layer fills up the first trench structure; removing part of the initial dielectric layer to form a dielectric layer which has second trench structures exposing part of the first barrier structures, in which a compactness of a material forming the first barrier structure is larger than that of a material forming the dielectric layer; and forming a conductive layer which fills up the second trench structures. | 2022-08-25 |
20220270922 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - This application relates to a memory device and a method for manufacturing the same, including: a substrate on which an insulation structure and a plurality of first active structures are formed is provided. The plurality of first active structures are arranged at intervals in the insulation structure. A word line conductive layer is formed on the substrate by a physical vapor deposition process. The word line conductive layer is patterned and etched to obtain a plurality of word line structures arranged in parallel and at intervals and filling slots located between adjacent word line structures. The filling slots comprise first filling slots that expose both parts of top surfaces of the first active structures and parts of the top surface of the insulation structure. Second active structures are formed in the first filling slots, and isolation structures are formed in the first filling slots. | 2022-08-25 |
20220270923 | SYSTEMS AND METHODS FOR IMPROVING WITHIN DIE CO-PLANARITY UNIFORMITY - Exemplary methods of producing a semiconductor substrate may include plating a metal within a plurality of vias on the semiconductor substrate. A target average fill thickness of the metal within the plurality of vias may be between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias. At least one via of the plurality of vias may be filled to a height below the target average fill thickness of the metal. The methods may include heating the metal to cause reflow of the metal within each via of the plurality of vias. The reflow may adjust the metal within the at least one via to increase in height towards the target average fill thickness. | 2022-08-25 |
20220270924 | METHOD FOR PRODUCING A THROUGH SEMICONDUCTOR VIA CONNECTION - The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection. | 2022-08-25 |
20220270925 | FLEXING SEMICONDUCTOR STRUCTURES AND RELATED TECHNIQUES - Aspects include a method of fabricating a semiconductor structure including providing a semiconductor layer, scribing the semiconductor layer to provide one or more scribe lines, disposing a flexible support layer on the semiconductor layer, and applying a force to the scribed semiconductor layer so as to induce cracks along the scribe lines. | 2022-08-25 |
20220270926 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes preparing a stacked substrate including a first substrate divided into multiple chips, a protective film divided for each of the multiple chips to protect the chip, a second substrate supporting the first substrate, and an adhesive film configured to attach the protective film and the second substrate; reducing adhesive strength of the adhesive film with a light beam configured to penetrate the second substrate; and picking-up, from the adhesive film by a pick-up device, the chip and the protective film with the reduced adhesive strength to the adhesive film. | 2022-08-25 |
20220270927 | CARRIER SUBSTRATE AND ELEMENT TRANSFER METHOD USING THE SAME - A carrier substrate includes a base layer, an antireflection layer, and an energy absorption layer, wherein the antireflection layer is formed on one surface of the base layer and allows an elastic wave generated by a first laser beam transmitted through an element adhesively bonded to the antireflection layer to be transmitted through the base layer without being reflected towards the element, the first laser beam being applied to the element through a source substrate of the element, and the energy absorption layer is formed between the base layer and the antireflection layer to be aligned with the element, and evaporates upon energy absorption. | 2022-08-25 |
20220270928 | Notched Gate Structure Fabrication - A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack. | 2022-08-25 |
20220270929 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer. | 2022-08-25 |
20220270930 | CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIONAL SRAM ARCHITECTURES - A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability. | 2022-08-25 |
20220270931 | GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE - A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers. | 2022-08-25 |
20220270932 | SEMICONDUCTOR DEVICE HAVING DEEP TRENCH STRUCTURE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating. | 2022-08-25 |
20220270933 | Superjunction Transistor Device - A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and transistor cells each having a body region and a source region in the inner region of the semiconductor body. An effective lateral doping dose of the first regions in the edge region is lower than an effective lateral doping dose of the first regions in the inner region. An effective lateral doping dose of the second regions in the edge region is lower than an effective lateral doping dose of the second regions in the inner region. | 2022-08-25 |
20220270934 | MULTI-GATE DEVICE AND RELATED METHODS - A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer. | 2022-08-25 |
20220270935 | POWER RAILS FOR STACKED SEMICONDUCTOR DEVICE - The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening. | 2022-08-25 |
20220270936 | METHODS, SYSTEMS, AND APPARATUS FOR CONDUCTING CHUCKING OPERATIONS USING AN ADJUSTED CHUCKING VOLTAGE IF A PROCESS SHIFT OCCURS - Methods, systems, and apparatus for conducting chucking operations are disclosed that use an adjusted chucking voltage if a process shift occurs. In one implementation, a method includes conducting a first processing operation on a substrate in a processing chamber. The first processing operation includes applying a chucking voltage to an electrostatic chuck (ESC) in the processing chamber while the substrate is supported on the ESC. The method includes determining that a process shift has occurred. The determining that the process shift has occurred includes one or more of: determining that a center of the substrate has moved by a post-processing shift relative to a pre-processing location of the center prior to the first processing operation, or determining that a defect count of a backside surface of the substrate exceeds a defect threshold. The method includes determining an adjusted chucking voltage based on the occurrence of the process shift. | 2022-08-25 |
20220270937 | METHODS OF DETERMINING SHEAR STRENGTH OF BONDED FREE AIR BALLS ON WIRE BONDING MACHINES - A method of determining a shear strength of a bonded free air ball on a wire bonding machine is provided. The method includes the steps of: (a) providing a free air ball at a working end of a wire bonding tool; (b) bonding the free air ball to a bonding location of a workpiece; (c) moving the wire bonding tool, while in contact with the bonded free air ball, in a direction along the bonding location; (d) monitoring wire bonding process signals during step (c); and (e) determining a shear strength using the wire bonding process signals monitored in step (d). | 2022-08-25 |
20220270938 | BACK END OF LINE (BEOL) PROCESS CORNER SENSING - Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages. | 2022-08-25 |
20220270939 | SYSTEM AND METHOD FOR CONTROLLING CHEMICAL MECHANICAL PLANARIZATION - A chemical mechanical planarization system includes a chemical mechanical planarization head configured to hold a semiconductor wafer during a chemical mechanical planarization process. The system includes a camera positioned to capture an image of the chemical mechanical planarization after chemical mechanical planarization has unloaded the semiconductor wafer. A control system analyzes the image to determine if the chemical mechanical planarization head is damaged. If the chemical mechanical planarization head is damaged, the control system prevents further chemical mechanical planarization operations until the chemical mechanical planarization head is repaired. If the control system does not detect any damage, then the control system permits the chemical mechanical planarization head to receive a next semiconductor wafer for chemical mechanical planarization. | 2022-08-25 |
20220270940 | ABNORMALITY DETECTION METHOD AND PROCESSING APPARATUS - An abnormality detection method includes: supplying a gas controlled to a selected rate to a gas supply pipe via the gas pipe connected to the gas supply pipe, thereby introducing the gas into a reaction region of a processing container provided in a processing apparatus from a gas hole of the gas supply pipe; measuring a pressure inside the gas pipe by a pressure gauge attached to the gas pipe; and detecting an abnormality of at least one of the gas supply pipe and the gas pipe based on the pressure measured at the measuring. | 2022-08-25 |
20220270941 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An object is to provide a technique capable of suppressing an occurrence of a non-filled portion. A semiconductor device includes a base plate, a case, and a semiconductor element. The semiconductor element is disposed in a space of the base plate and the case. The semiconductor device includes a lead electrode. The lead electrode is connected to an upper surface of the semiconductor element in the space. The semiconductor device includes a raised portion. The raised portion is disposed on an upper surface of the lead electrode in the space. The semiconductor device includes a sealing resin. The sealing resin seals the semiconductor element and the lead electrode in the space. | 2022-08-25 |
20220270942 | FLIP CHIP SEMICONDUCTOR PACKAGE WITH A LEADFRAME TO ENHANCE PACKAGE MECHANICAL STABILITY AND HEAT DISSIPATION - A flip chip package is disclosed. The package includes a leadframe surrounding a flip chip. The leadframe and flip chip are encapsulated by a mold compound. The leadframe provides package support to enhance the mechanical stability of the package. In some cases, a heat dissipating structure is disposed on top of the package, connecting the flip chip to enhance heat dissipation. | 2022-08-25 |
20220270943 | SEMICONDUCTOR MEMORY DEVICE HAVING COMPOSITE DIELECTRIC FILM STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance. | 2022-08-25 |
20220270944 | PACKAGE STRUCTURE WITH ANTENNA PATTERN - Provided is a package structure and an antenna structure. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant. | 2022-08-25 |
20220270945 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a plurality of stacked semiconductor chips each of which has a first surface having an electrode formed thereon, a plurality of wires each of which has one end portion connected to each of the electrodes of the plurality of semiconductor chips and extends in a stacking direction of the semiconductor chips, a sealing resin that covers the plurality of semiconductor chips, has a second surface having recesses formed therein, and is formed so that the other end portions of the plurality of wires and the recesses overlap each other when viewed from the stacking direction, and a plurality of terminals that is provided so as to fill the recesses, each of which has one end portion connected to the other end portion of each of the plurality of wires and has the other end portion exposed from the sealing resin. | 2022-08-25 |
20220270946 | SEMICONDUCTOR MODULE - A semiconductor module includes: a dissipating metal plate including a recess provided on an upper surface; an insulating substrate provided on a bottom surface of the recess and including a circuit pattern; a semiconductor device provided on the insulating substrate and connected to the circuit pattern; a case bonded to a peripheral portion on the upper surface of the dissipating metal plate and surrounding the insulating substrate and the semiconductor device; a case electrode provided on the case; a wire connecting the semiconductor device and the case electrode; and a sealant provided in the case and sealing the insulating substrate, the semiconductor device, and the wire, wherein a sidewall of the recess has a taper. | 2022-08-25 |
20220270947 | HEAT SINK - A heat sink includes a first surface including an attachment area to which a semiconductor module is attached and is installed such that a first side of the first surface extends in a vertical direction. Thermal grease containing oil is applied to the attachment area. A first groove extending in a horizontal direction is formed below the attachment area in the first surface. An inner wall of the first groove includes a groove top surface and a groove bottom surface spaced below the groove top surface. The length of the first groove in the horizontal direction is shorter than the length of the first surface in the horizontal direction. A wall includes a first wall extending in the horizontal direction and second walls respectively connected to both end portions of the first wall in the horizontal direction and inclined upward as the second walls extend away from the first wall. | 2022-08-25 |
20220270948 | SEMICONDUCTOR DEVICE - The semiconductor device includes a semiconductor module and a cooler. The semiconductor module includes an insulator substrate, an inner conductor film disposed on a first surface of the insulator substrate, a semiconductor element connected to the inner conductor film, a sealing body sealing the inner conductor film and the semiconductor element, and an outer conductor film disposed on a second surface of the insulator substrate and exposed from a surface of the sealing body. The cooler is disposed adjacent to the outer conductor film via a thermal interface material having fluidity. The outer conductor film has a protruding portion or a recessed portion on a surface being in contact with the thermal interface material. | 2022-08-25 |
20220270949 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Semiconductor device includes circuit substrate, first semiconductor die, thermal interface material, package lid. First semiconductor die is disposed on and electrically connected to circuit substrate. Thermal interface material is disposed on first semiconductor die at opposite side of first semiconductor die with respect to circuit substrate. Package lid extends over first semiconductor die and is bonded to the circuit substrate. Package lid includes roof, footing, and island. Roof extends along first direction and second direction perpendicular to first direction. Footing is disposed at peripheral edge of roof and protrudes from roof towards circuit substrate along third direction perpendicular to first direction and second direction. Island protrudes from roof towards circuit substrate and contacts thermal interface material on first semiconductor die. Island is disconnected from footing along second direction. | 2022-08-25 |
20220270950 | INSULATED METAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME - An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm | 2022-08-25 |
20220270951 | PACKAGING-LEVEL CHIP AND CHIP MODULE PACKAGED WITH MAGNETIC COVER, AND ELECTRONIC PRODUCT - The present disclosure provides a packaging-level chip and a chip module packaged with a magnetic cover, and an electronic product. The packaging-level chip packaged with a magnetic cover comprises a die, a packaging material, a substrate and a magnetic cover. The packaging material is packaged on the outside of the die which is arranged on the substrate, and the magnetic cover is packaged on the top of the packaging material and is magnetic. | 2022-08-25 |
20220270952 | POWER DEVICE, POWER DEVICE ASSEMBLY, AND RELATED APPARATUS - This disclosure provides a power device, a power device assembly, and a related apparatus. The power device includes a package body and a plurality of pins. The package body includes a substrate structure, a semiconductor die, and a molded package. The semiconductor die is disposed on the substrate structure. The substrate structure includes a heat dissipation surface connectable to a heat sink. A first end of each pin is connected to the substrate structure. The molded package covers the semiconductor die and the substrate structure excluding the heat dissipation surface. A second end of each pin and the heat dissipation surface are both uncovered from the molded package. The second end of each pin includes a mounting surface connectable to a circuit board through a surface-mount technology to form an electrical connection. | 2022-08-25 |
20220270953 | THERMAL PEAK SUPPRESSION DEVICE - A thermal peak suppression device includes a heat dissipation fin set, a heat dissipator, a thermal phase change material, a filling gas, a fin-array frame and a capillary tube. The heat dissipator includes a thermal conductive block thermally coupled to the heat dissipation fin set, and a closed cavity formed inside the thermal conductive block to have a hot zone and a cold zone. The thermal phase change material is disposed within the hot zone. The filling gas is disposed within the cold zone. The fin-array frame is connected to the thermal conductive block within the cold zone. Two opposite ends of the capillary tube are respectively located within the cold zone and the hot zone. When the thermal phase change material is transformed into a liquid state, the thermal phase change material is sent to the hot zone through the capillary tube. | 2022-08-25 |
20220270954 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a multi-gate transistor having a plurality of gates in a common active region, in which the multi-gate transistor has a comb-shaped metal structure in which a first metal is drawn out and bundled in a W length direction from contacts arranged in a single row in each of a source region and a drain region, and the multi-gate transistor has a wiring layout in which a root section of the first metal coincides immediately above an end of the source region and the drain region or is disposed inside the end of the source region and the drain region in the W length direction. | 2022-08-25 |
20220270955 | Packaging Technologies for Temperature Sensing in Health Care Products - Temperature sensor packages and methods of fabrication are described. The temperature sensor packages in accordance with embodiments may be rigid or flexible. In some embodiments the temperature sensor packages are configured for touch sensing, and include an electrically conductive sensor pattern such as a thermocouple or resistance temperature detector (RTD) pattern. In some embodiments, the temperature sensor packages are configured for non-contact sensing an include an embedded transducer. | 2022-08-25 |
20220270956 | ELECTRICAL AND/OR ELECTRONIC COMPONENT AND CONTACT SYSTEM - An electrical and/or electronic component including at least one electrical outside connecting contact. This contact is a terminal lug, which is attached at one side, for the electrical contacting with a contacting partner. The terminal lug includes a connecting side including a planar connecting surface for the electrical contacting. The exposed end of the terminal lug includes a bending leg, which is bent out of the plane by a compensating angle toward the connecting side. The bending leg includes the connecting surface. The terminal lug is designed such that, when a contacting partner, which is planar at least in this area, makes site contact with the free end of the bending leg with a force applied from the connecting side, a position orientation of the connecting surface is adaptable counter to the compensating angle until a gap-free contact is made between the connecting surface and the planar contacting partner. | 2022-08-25 |
20220270957 | QUAD FLAT NO-LEAD (QFN) MANUFACTURING PROCESS - A lead frame includes a metal structure having opposite first and second sides and prospective device portions having leads with first and second lateral sides extending from a tie bar toward a die attach pad. One or more of the leads includes a first indent in the first lateral side that extends to the first side of the metal structure, and a second indent that extends to the second side of the metal to reduce saw blade loading and mitigate saw burr and lead smear during package singulation. A packaged electronic device includes a package structure, a semiconductor die enclosed by the package structure, and leads having a first side, a second side, and first and second lateral sides, where the leads include a first indent in the first lateral side that extends to the first side, and a second indent that extends to the second side of the lead. | 2022-08-25 |
20220270958 | ELECTRONIC ELEMENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, ELECTRONIC MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC ELEMENT MOUNTING SUBSTRATE - An electronic element mounting substrate includes a first insulating layer, a second insulating layer, a first metal layer, and a through-hole conductor. The first insulating layer and the second insulating layer are aligned in a first direction. The first metal layer is positioned between the first insulating layer and the second insulating layer. The through-hole conductor extends in the first direction from the first insulating layer through the second insulating layer. The first metal layer includes a first portion positioned away from the through-hole conductor and a second portion in contact with the through-hole conductor. The second portion has a larger thickness than the first portion. | 2022-08-25 |
20220270959 | REDISTRIBUTION SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern. | 2022-08-25 |
20220270960 | Open-Cavity Package for Chip Sensor - In described examples, a device includes an interconnect substrate that has an aperture through the interconnect substrate. An integrated circuit (IC) die that has an on-chip element is mounted on the interconnect substrate with the on-chip element aligned with and facing the aperture. The IC die is over-molded with mold compound only on one side of the interconnect substrate so that the aperture remains free of mold compound to allow the on-chip element to have access to the environment. | 2022-08-25 |
20220270961 | STRUCTURES WITH DEFORMABLE CONDUCTORS - A method includes stacking a first layer of insulating material having one or more passages on a substrate. A deformable conductive material is deposited in at least one of the passages in the first insulating layer. A second layer of insulating material is stacked on the first layer of insulating material. The second layer of insulating material at least partially encloses the deformable conductive material in the at least one passage in the first layer of insulating material, and unitizing the first and second layers in a unitizing operation | 2022-08-25 |
20220270962 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less. | 2022-08-25 |
20220270963 | CHIP PACKAGE STRUCTURE WITH METAL-CONTAINING LAYER - A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip. | 2022-08-25 |
20220270964 | METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPACITANCE INTERCONNECTS BY ALTERNATING RECESSED TRENCHES - Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased. | 2022-08-25 |
20220270965 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode. | 2022-08-25 |
20220270966 | INTEGRATED CIRCUIT - An integrated circuit includes first power supply lines which extend in a first direction and are spaced apart from each other in a second direction different from the first direction. A second power supply line extends in the first direction and is placed between the first power supply lines adjacent to each other in the second direction. A decoupling filler cell is placed between the first power supply lines adjacent to each other in the second direction. The decoupling filler cell includes a decoupling capacitor region formed by a gate electrode and a decap transistor including a first source/drain region of a first conductive type. The gate electrode is connected to the second power supply line, the first source/drain region is connected to the first power supply lines, and the second power supply line passes through the decoupling capacitor region. | 2022-08-25 |
20220270967 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PLURAL METAL OXIDE BLOCKING DIELECTRIC LAYERS AND METHOD OF MAKING THEREOF - A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a first metal oxide blocking dielectric layer, and a second metal oxide blocking dielectric layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the first metal oxide blocking dielectric layers and each of the electrically conductive layers. | 2022-08-25 |
20220270968 | INTEGRATED CIRCUIT E-FUSE HAVING AN E-FUSE ELEMENT PROVIDING A DIFFUSION BARRIER FOR UNDERLYING E-FUSE TERMINALS - An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW | 2022-08-25 |
20220270969 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5. | 2022-08-25 |
20220270970 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a two-dimensional material layer, a second conductive feature disposed over the first conductive feature, and a dielectric material disposed adjacent the first and second conductive features. The dielectric material extends from a level of a bottom of the first conductive feature to a level of a top of the second conductive feature. | 2022-08-25 |
20220270971 | SEMICONDUCTOR DEVICES INCLUDING METAL GATE PROTECTION AND METHODS OF FABRICATION THEREOF - Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer. | 2022-08-25 |
20220270972 | CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer. | 2022-08-25 |
20220270973 | BONDED SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region. | 2022-08-25 |
20220270974 | DIELECTRIC-FILLED TRENCH ISOLATION OF VIAS - An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed. | 2022-08-25 |
20220270975 | SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER - Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other. | 2022-08-25 |
20220270976 | MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES - Disclosed herein are microelectronic assemblies including bridges, as well as related methods. In some embodiments, a microelectronic assembly may include a bridge in a mold material. | 2022-08-25 |
20220270977 | HETEROGENEOUS INTEGRATED CIRCUIT FOR SHORT WAVELENGTHS - A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm. | 2022-08-25 |
20220270978 | METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS - At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line. | 2022-08-25 |
20220270979 | FORMATION OF METAL VIAS ON METAL LINES - Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C. | 2022-08-25 |
20220270980 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature. The tungsten barrier layer surrounds the second tungsten contact feature, and is connected to the second tungsten contact feature, the non-cobalt conductive feature and the second dielectric layer. | 2022-08-25 |
20220270981 | ELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF - The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package. | 2022-08-25 |
20220270982 | PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF - A packaging structure and fabrication method thereof are provided. The method includes: providing semiconductor chips including soldering pads and metal bumps; providing a base plate, wiring structures, input terminals, and output terminals; mounting the semiconductor chips on the front surface of the base plate inversely, such that each metal bump is connected to a corresponding input terminal; forming a bottom filling layer between a functional surface of each semiconductor chip and the front surface of the base plate; forming a first shielding layer covering a non-functional surface and sidewalls of each semiconductor chip, and covering sidewalls of a corresponding bottom filling layer; forming a second shielding layer on each first shielding layer; forming a plastic encapsulation layer on second shielding layers and on a portion of the base plate between semiconductor chips; and forming external contact structures connected to the output terminals. | 2022-08-25 |
20220270983 | EMI Shielding for Flip Chip Package with Exposed Die Backside - A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die. | 2022-08-25 |
20220270984 | ELECTRONIC DEVICE WITH CRACK ARREST STRUCTURE - A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction. | 2022-08-25 |
20220270985 | SEMICONDUCTOR CHIP HAVING A CRACK STOP STRUCTURE - A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip. | 2022-08-25 |
20220270986 | ENHANCED BONDING BETWEEN III-V MATERIAL AND OXIDE MATERIAL - When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere. | 2022-08-25 |
20220270987 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate. | 2022-08-25 |
20220270988 | ELECTRONIC PART AND SEMICONDUCTOR DEVICE - Provided is an electronic part that includes a first substrate including a first base and a first coil, the first coil being electrically insulated from the first base, a second substrate including a second base and a second coil, the second coil being electrically insulated from the second base, and a support member that supports the first substrate and the second substrate. The first substrate is arranged between the second substrate and the support member in a thickness direction of the support member and overlaps the second substrate as viewed in the thickness direction, the first base is positioned between the first coil and the second coil in the thickness direction, and the first coil and the second coil are magnetically coupled. | 2022-08-25 |
20220270989 | INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS - Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a first microstrip; a first surface dielectric region over the first microstrip, wherein the first surface dielectric region has a first thickness, and the first thickness is nonzero; a second microstrip; and a second surface dielectric region over the second microstrip, wherein the second surface dielectric region has a second thickness, the second thickness is nonzero, and the first thickness is different than the second thickness. | 2022-08-25 |
20220270990 | INTEGRATED FAN-OUT PACKAGE - An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure. | 2022-08-25 |
20220270991 | CONTACT PAD STRUCTURES AND METHODS FOR FABRICATING CONTACT PAD STRUCTURES - A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects. | 2022-08-25 |
20220270992 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a stack above a peripheral circuit on a first substrate, in which first conductive layers and first insulation layers are alternately stacked in a first direction each; a first pillar through the stack, in which a semiconductor layer and each first conductive layer form a memory cell at their intersection; a second substrate including a first region above the stack and the first pillar, being connected to a semiconductor layer, and a second region juxtaposed with the first region in a second direction; a second insulation layer through the second substrate, insulating the regions from each other; and a second conductive layer including a first portion through the second substrate, and a second portion extending in the second direction above the second substrate and including a part defining a bonding pad. The second portion overlaps with the second insulation layer in the first direction. | 2022-08-25 |
20220270993 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a lower interconnect layer including a plurality of lower interconnects, and a plurality of lower pads provided on the lower interconnects. The device further includes a plurality of upper pads provided on the lower pads and being in contact with the lower pads, and an upper interconnect layer including a plurality of upper interconnects provided on the upper pads. The lower pads include a plurality of first pads and a plurality of second pads. The upper pads include a plurality of third pads provided on the second pads and a plurality of fourth pads provided on the first pads, a lower face of each third pad is larger in area than a upper face of each second pad, and a lower face of each fourth pad is smaller in area than a upper face of each first pad. | 2022-08-25 |
20220270994 | INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure. | 2022-08-25 |
20220270995 | SIDEWALL WETTING BARRIER FOR CONDUCTIVE PILLARS - Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems. | 2022-08-25 |