| 34th week of 2011 patent applcation highlights part 43 |
| Patent application number | Title | Published |
|---|
| 20110207230 | EVALUATION OF 24S-HYDROXYCHOLESTEROL IN HAIR FOR METABOLIC BIOMARKER OF ALZHEIMER'S DISEASE - Disclosed is a method for detection of 24S-hydroxycholesterol in hair. More specifically, a trace amount of hair is hydrolyzed under basic condition and metabolites including 24S-hydroxycholesterol are purified and extracted by solid-phase extraction (SPE). Then, after derivatization of the resulting extract with trimethylsilyl (TMS), 24S-hydroxycholesterol is detected by gas chromatography-mass spectrometry (GC-MS). | 2011-08-25 |
| 20110207231 | Melamine Assay Methods and Systems - A method of detecting melamine which includes providing a quantity of SERS-active particles and mixing the SERS-active particles with a solution containing melamine. The method further includes detecting a surface enhanced Raman spectrum of the melamine. The foregoing method may optionally include aggregating the SERS-active particles. Aggregation may occur before or after the SERS-active particles are mixed with a solution containing melamine. The method of detecting melamine may optionally include concentration of the SERS-active particles. The method may further include mixing a chaotropic agent having a higher affinity for a selected binding site than melamine into the solution containing melamine. The method may further include mixing a quantity of a SERS-active standard having a known SERS spectrum with the solution containing melamine and SERS-active particles. Assay apparatus and systems are also disclosed. | 2011-08-25 |
| 20110207232 | WATER SOLUBLE PH RESPONSIVE FLUORESCENT NANOPARTICLES - A nano-pH sensor can include a nanoparticle having an outer surface functionalized by a carboxy functional group. The nanoparticle is reversibly aggregated as a function of pH and is generally non-toxic. A fluorometer can be oriented to expose the nanoparticles to a light source at a given wavelength. Further, the fluorometer can be configured to detect changes in fluorescence of the gold nanoparticle with changes in pH. | 2011-08-25 |
| 20110207233 | METHOD FOR MEASURING INHIBITORY ACTIVITY ON LIGAND-RECEPTOR BINDING - A method for measuring the presence or absence and/or strength of the inhibitory activity of a test substance on binding between a ligand and a receptor thereof, which comprises the following steps (1) to (3): | 2011-08-25 |
| 20110207234 | Synthesis and Use of Cross-Linked Hydrophilic Hollow Spheres for Encapsulating Hydrophilic Cargo - Cross-linked hydrophilic nanocapsules and various compositions and methods for their preparation and use are provided. | 2011-08-25 |
| 20110207235 | USE OF PERFLUOROPOLYMERS IN THE DETERMINATION OF THE RECEPTOR-LIGAND BINDING CONSTANT - A method for determining the binding constant of interacting molecular species comprises the use of flat surfaces comprising perfluorinated polymers and measurements of reflected light intensity. The surfaces comprise at least one molecule with the receptor function absorbed or immobilized on the surface and at least one ligand that interacts with the receptor. | 2011-08-25 |
| 20110207236 | SONICATION-ASSISTED METAL-ENHANCED FLUORESCENCE (SAMEF)-BASED BIOASSAYS - The present invention provides for sonication-assisted metal-enhanced fluorescence, luminescence, and/or chemiluminescence assay systems using low-intensity ultrasound waves to significantly reduce the assay time by increasing the kinetic movement of molecules within the system. | 2011-08-25 |
| 20110207237 | OPTICAL FIBER PROBE - A biosensor having an optical fiber having at least one curved portion configured to enhance penetration of evanescent waves; and one or more nanoparticles associated with the optical fiber, and configured to enhance localized surface plasmon resonance. | 2011-08-25 |
| 20110207238 | BIOLOGICAL SUBSTANCE ANALYZING METHOD, AND BIOLOGICAL SUBSTANCE ANALYZING CELL, BIOLOGICAL SUBSTANCE ANALYZING CHIP, AND BIOLOGICAL SUBSTANCE ANALYZING APPARATUS EMPLOYED IN THE BIOLOGICAL SUBSTANCE ANALYZING METHOD - Detection of detection target substances at a sensor portion is expedited and the efficiency thereof is improved in biological substance analysis, to enable accelerated analysis with high sensitivity. A biological substance analyzing cell equipped with a reaction chamber having a sample supply space, an acoustic matching layer which is provided at a predetermined region of an inner wall of the reaction chamber that faces another inner wall, and a sensor portion provided within the reaction chamber is employed. Ultrasonic waves are emitted such that a standing wave are generated between the acoustic matching layer and the inner wall of the reaction chamber that faces the acoustic matching layer. The detection target substance is concentrated by the capturing forces of the standing waves, and the concentrated detection target substance is detected at the sensor portion. | 2011-08-25 |
| 20110207239 | BICOMPATIBLE ELECTRODES - A biocompatible electrode is manufactured by depositing filling metal | 2011-08-25 |
| 20110207240 | Information storage devices using movement of magnetic domain walls and methods of manufacturing the same - An information storage device using movement of magnetic domain walls includes a writing magnetic layer having a magnetic domain wall. A stack structure is formed on the writing magnetic layer. The stack structure includes a connecting magnetic layer and an information storing magnetic layer stacked sequentially. The information storage device also includes a reader for reading information stored in the information storing magnetic layer. | 2011-08-25 |
| 20110207241 | Formation method of metallic electrode of semiconductor device and metallic electrode formation apparatus - A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength. | 2011-08-25 |
| 20110207242 | METHOD OF MANUFACTURE OF AN INTEGRATED CIRCUIT PACKAGE - A method of manufacturing an integrated circuit, IC, package comprising radio frequency, RF, components, the method comprising:
| 2011-08-25 |
| 20110207243 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased. Further, the cross section of the channel structure is structured so as to be reduced from the second channel areas towards a third channel areas, and thereby the heat transfer coefficient of the refrigerant is prevented from decreasing. Accordingly, the heat transfer coefficient of the refrigerant can be uniformed in the channel structure. | 2011-08-25 |
| 20110207244 | Apparatus for depositing and inspecting an organic light emitting display panel and method of depositing and inspecting an organic light emitting display panel using the apparatus - An apparatus for depositing and inspecting an organic light emitting display panel includes a depositor part configured to deposit thin film layers on a panel, the thin film layers including an anode layer, an organic film layer, and a cathode layer, and an inspector part configured to measure spectra of light reflected from the thin film layers, compare the measured spectra to reference spectra, and determine thickness correctness of individual thin film layers. | 2011-08-25 |
| 20110207245 | STAGE, SUBSTRATE PROCESSING APPARATUS, PLASMA PROCESSING APPARATUS, CONTROL METHOD FOR STAGE, CONTROL METHOD FOR PLASMA PROCESSING APPARATUS, AND STORAGE MEDIA - A stage onto which is electrostatically attracted a substrate to be processed in a substrate processing apparatus, which enables the semiconductor device yield to be improved. A temperature measuring apparatus | 2011-08-25 |
| 20110207246 | METHODS FOR REDUCING THE WIDTH OF THE UNBONDED REGION IN SOI STRUCTURES - The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided. | 2011-08-25 |
| 20110207247 | METHOD OF CORRECTING OVERLAY AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME - A method of correcting an overlay includes setting a reference map having information relating to predetermined positions of a substrate. An overlay value is measured at each of the predetermined positions to obtain a plurality of overlay measurement values. The plurality of overlay measurement values is applied to a polar coordinate function to calculate a correlation coefficient of the polar coordinate function. The polar coordinate function uses coordinate values of the predetermined positions as parameters. | 2011-08-25 |
| 20110207248 | Light Emitting Device and Manufacturing Method Thereof - The concentration of oxygen, which causes problems such as decreases in brightness and dark spots through degradation of electrode materials, is lowered in an organic light emitting element having a layer made from an organic compound between a cathode and an anode, and in a light emitting device structured using the organic light emitting element. The average concentration of impurities contained in a layer made from an organic compound used in order to form an organic light emitting element having layers such as a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer, is reduced to 5×10 | 2011-08-25 |
| 20110207249 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE AND FABRICATING METHOD THEREOF - An organic electro-luminescence display device includes at least one light emission device, the organic light emission device having a first electrode; at least one thin film transistor for driving the light emission device, a pixel electrode being connected to the at least one thin film transistor; a conductive layer formed of a conductive polymer material to electrically connect the light emission device and the pixel electrode. | 2011-08-25 |
| 20110207250 | BACK-ILLUMINATED TYPE IMAGING DEVICE AND FABRICATION METHOD THEREOF - Light is illuminated from a back-surface side of a silicon substrate | 2011-08-25 |
| 20110207251 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - It is provided a contacting method when a plurality of films to be peeled are laminating. Reduction of total layout area, miniaturization of a module, weight reduction, thinning, narrowing a frame of a display device, or the like can be realized by sequentially laminating a plurality of films to be peeled which are once separately formed over a plastic film or the like. Moreover, reliable contact having high degree of freedom is realized by forming each layer having a connection face of a conductive material and by patterning with the use of a photomask having the same pattern. | 2011-08-25 |
| 20110207252 | LIGHT EMTTING DEVICE, METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING APPARATUS - A light emitting device according to the embodiment includes a reflecting layer; an adhesion layer including an oxide-based material on the reflecting layer; an ohmic contact layer on the adhesion layer; and a light emitting structure layer on the ohmic contact layer. | 2011-08-25 |
| 20110207253 | FLIP-CHIP LED MODULE FABRICATION METHOD - A flip-chip LED module fabrication method includes the steps of (a) growing an epitaxial layer consisting of a N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer on a wafer substrate, (b) dividing the wafer into individual light-emitting chips, (c) selecting qualified light-emitting chips, (d) coating an UV-curable adhesive on o a film and then bonding the selected light-emitting chips to the film by means of the UV-curable adhesive, (e) curing the UV-curable adhesive with ultraviolet rays, and (f) operating push-up needles of an equipment to knock the opposite side of the film to let the light-emitting chips be separated from the film without causing damage. | 2011-08-25 |
| 20110207254 | Method of manufacturing organic light emitting display device - A method of manufacturing an organic light emitting display device includes providing a panel including a first opening portion formed in a first substrate and a second opening portion spaced apart from the first opening portion, disposing a transmissive-window forming composition in the second opening portion, forming an organic layer in the first opening portion, forming a metal layer on the panel so as to cover the first opening portion and the second opening portion, and forming a transmissive window by volatilizing the transmissive-window forming composition to open a region of the metal layer corresponding to the second opening portion. | 2011-08-25 |
| 20110207255 | Semiconductor Device and Method for Manufacturing the Same - A manufacturing method of an active matrix light emitting device in which the active matrix light emitting device can be manufactured in a shorter time with high yield at low cost compared with conventional ones will be provided. It is a feature of the present invention that a layered structure is employed for a metal electrode which is formed in contact with or is electrically connected to a semiconductor layer of each TFT arranged in a pixel area of an active matrix light emitting device. Further, the metal electrode is partially etched and used as a first electrode of a light emitting element. A buffer layer, a layer containing an organic compound, and a second electrode layer are stacked over the first electrode. | 2011-08-25 |
| 20110207256 | IN-SITU ACCEPTOR ACTIVATION WITH NITROGEN AND/OR OXYGEN PLASMA TREATMENT - Embodiments of the present invention generally relate to methods and apparatus for the manufacturing of devices, such as light emitting diodes (LEDs), laser diodes (LDs) and, more particularly, to processes for forming Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes. In one embodiment, a method for fabricating a compound nitride structure on a substrate is provided. The method comprises depositing a p-type doped Group III-nitride film over one or more substrates in a processing chamber and exposing the p-type doped Group III-nitride film to a plasma in the processing chamber to activate the p-type dopant by breaking up hydride complexes formed between the p-type dopant and hydrogen. | 2011-08-25 |
| 20110207257 | MANUFACTURING METHOD FOR A SOLID-STATE IMAGE PICKUP DEVICE - Provided is a manufacturing method for a solid-state image pickup device, which enables easily manufacturing a thin-type solid-state image pickup device at a wafer level. A support substrate is bonded to a cover glass substrate. A surface of the cover glass substrate on an opposite side to the support substrate is mechanically polished. A part of the support substrate is removed, and a plurality of frame-shaped spacers are formed on the cover glass substrate. The cover glass substrate is made thinner by wet etching so as to have a predetermined thickness. The cover glass substrate and a silicon wafer on which solid-state image pickup elements are formed are attached to each other via the spacers. The cover glass substrate is divided into individual pieces. The silicon wafer is divided into individual pieces. In this way, the solid-state image pickup device is manufactured. | 2011-08-25 |
| 20110207258 | METHOD FOR FORMING PAD IN WAFER WITH THREE-DIMENSIONAL STACKING STRUCTURE - A method for forming a pad in a wafer with a three-dimensional stacking structure includes: (a) a first process of bonding a device wafer and a handling wafer; (b) a second process of thinning a back side of an Si substrate which is formed on the device wafer, after the first process; (c) a third process of forming an anti-reflective layer and a PMD (preferential metal deposition) dielectric layer, after the second process; (d) a fourth process of forming vias on back sides of super contacts which are formed on the Si substrate, after the third process; and (e) a fifth process of forming a pad, after the fourth process. | 2011-08-25 |
| 20110207259 | LOW-COST SOLAR CELLS AND METHODS FOR THEIR PRODUCTION - Methods for fabricating solar cells without the need to perform gasification of metallurgical-grade silicon are disclosed. Consequently, the costs and health and environmental hazards involved in fabricating the solar or silicon grade silicon are being avoided. A solar cell structure comprises a metallurgical grade doped silicon substrate and a thin-film structure formed over the substrate to form a p-i-n junction with the substrate. The substrate may be doped p-type, and the thin film structure may be an intrinsic amorphous layer formed over the substrate and an n-type amorphous layer formed over the intrinsic layer. | 2011-08-25 |
| 20110207260 | METHOD OF PRODUCING A SOLID-STATE IMAGE SENSING DEVICE INCLUDING SOLID-STATE IMAGE SENSOR HAVING A PILAR-SHAPED SEMICONDUCTOR LAYER - It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including: a first conductive type semiconductor layer; a first conductive type pillar-shaped semiconductor layer formed on the first conductive type semiconductor layer; a second conductive type photoelectric conversion region formed on the top of the first conductive type pillar-shaped semiconductor layer, an electric charge amount of the photoelectric conversion region being changed by light; and a high-concentrated impurity region of the first conductive type formed on a surface of the second conductive type photoelectric conversion region, the impurity region being spaced apart from a top end of the first conductive type pillar-shaped semiconductor layer by a predetermined distance, wherein a transfer electrode is formed on the side of the first conductive type pillar-shaped semiconductor layer via a gate insulating film, a second conductive type CCD channel region is formed below the transfer electrode, and a read channel is formed in a region between the second conductive type photoelectric conversion region and the second conductive type CCD channel region. | 2011-08-25 |
| 20110207261 | MASK AND FILM FORMATION METHOD USING THE SAME - A mask includes: a tabular first section which includes a side portion and an opening portion formed at a position corresponding to a film formation region of a substrate and on which the substrate is to be disposed so that the first section overlaps a face of the substrate on which a film is to be formed; and a second section which is provided along the side portion of the first section, and covers at least one of portions of a side face of the substrate, wherein second sections of two adjacent masks overlap each other and a superposed section is thereby formed when a plurality of masks are arrayed in a lateral direction thereof. | 2011-08-25 |
| 20110207262 | Method For Manufacturing A Semiconductor Structure - The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips. | 2011-08-25 |
| 20110207263 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present invention relates to a method of manufacturing a semiconductor device including (1) forming a laminated structure on a major surface of a semiconductor substrate, the laminated structure comprising at least a first metal layer that forms a Schottky junction with the semiconductor substrate, a second metal layer primarily composed of aluminum, and a third metal layer primarily composed of molybdenum or titanium, (2) patterning the laminated structure into a predetermined configuration, (3) forming a solder bonding metal layer comprising at least nickel, ion or cobalt on the major surface of the semiconductor substrate having the patterned laminated structure formed thereon, (4) patterning the solder bonding metal layer into a pattern configuration identical to that of the laminated structure, (5) cutting the semiconductor substrate on which the laminated structure and the solder bonding metal layer are patterned to form a plurality of semiconductor chips, and (6) bonding the semiconductor chip to a first frame using at least one solder layer formed on the solder bonding metal layer on the major surface of the semiconductor substrate, and bonding a rear face of the semiconductor chip to a second frame. | 2011-08-25 |
| 20110207264 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes cutting a part of a resin insulating layer formed on a surface of a semiconductor substrate with a cutting tool. The cutting the part of the resin insulating layer includes cutting a portion of the resin insulating layer that has a surface on which a metal layer is disposed. The cutting the portion of the resin insulating layer is performed in such a manner that, in a stress distribution inside the resin insulating layer along an edge portion of the cutting tool and a peripheral portion of the edge portion, a width at 90% of a maximum value is not more than 1.3 μm. | 2011-08-25 |
| 20110207265 | Nonvolatile memory devices and method of manufacturing the same - Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage. | 2011-08-25 |
| 20110207266 | PRINTED CIRCUIT BOARD (PCB) INCLUDING A WIRE PATTERN, SEMICONDUCTOR PACKAGE INCLUDING THE PCB, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE PCB, AND METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE - A printed circuit board (PCB) includes a wire pattern that has a low processing cost and a high yield by simplifying the structure of the PCB and can increase the joining characteristics and reliability of minute bumps when a flip-chip bonding process is performed. The PCB includes a body resin layer having lower and upper surfaces, a wire pattern on or in one of the upper and lower surfaces of the body resin layer, at least one through-hole contact extending from the wire pattern through the body resin layer, and a solder resist on the upper and lower surfaces of the body resin layer, openings of the solder resist corresponding to at least one of a solder ball land and a bump land, the solder ball land and the bump land being configured to couple the PCB to a semiconductor chip. If the solder ball land is on the one-layer wire pattern, the bump land is on the through-hole contact, and if the bump land is on the wire pattern, the solder ball land is on the through-hole contact. | 2011-08-25 |
| 20110207267 | REVERSE BLOCK-TYPE INSULATED GATE BIPOLAR TRANSISTOR MANUFACTURING METHOD - A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface. | 2011-08-25 |
| 20110207268 | Thin Film Transistor, Method of Fabricating the Same and Organic Light Emitting Diode Display Device Having the Same - A thin film transistor which has improved characteristics, a method of fabricating the same, and an organic light emitting diode (OLED) display device having the same. The thin film transistor includes a substrate, a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions, the channel region being doped with impurities, a thermal oxide layer disposed on the semiconductor layer, a silicon nitride layer disposed on the thermal oxide layer, a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer, an interlayer insulating layer disposed on the entire surface of the substrate, and source and drain electrodes electrically connected with the semiconductor layer. | 2011-08-25 |
| 20110207269 | TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process. | 2011-08-25 |
| 20110207270 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion. | 2011-08-25 |
| 20110207271 | WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE, METHOD OF FORMING THE WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug. | 2011-08-25 |
| 20110207272 | Semiconductor device and manufacturing process therefor - A process for manufacturing a semiconductor device includes preparing a semiconductor substrate including an N-type region and a P-type region isolated by an isolation region, forming a gate insulating film including an Hf-containing high-dielectric insulating film at least in an uppermost surface over the semiconductor substrate, forming a silicon layer over the gate insulating film, implanting a dopant into only any one of silicon layers over the P-type region and the N-type region, processing the silicon layers to form a gate pattern including a silicon region extending from a region over the N-type region through a region over the isolation region to a region over the P-type region, forming a gate sidewall on a sidewall of the gate pattern, implanting a dopant into the semiconductor substrate using the gate pattern and the gate sidewall as a mask, activating the dopant in the silicon region and the semiconductor substrate by heating, forming an interlayer insulating film over the gate pattern, removing the interlayer insulating film to expose the gate pattern, and depositing a silicide-formable metal M layer over the exposed gate pattern. | 2011-08-25 |
| 20110207273 | Methods of Manufacturing Transistors - A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics. | 2011-08-25 |
| 20110207274 | METHOD FOR FORMING A SPLIT-GATE MEMORY CELL - A method for forming a semiconductor device includes forming a first semiconductor layer over a substrate, forming a first photoresist layer over the first semiconductor layer, and using only a first single mask patterning the first photoresist layer to form a first patterned photoresist layer. The method further includes using the first patterned photoresist layer etching the first semiconductor layer to form a select gate and forming a charge storage layer over the select gate and a portion of the substrate. The method further includes forming a second semiconductor layer over the charge storage layer, forming a second photoresist layer over the second semiconductor layer, and using only a second single mask patterning the second photoresist layer to form a second patterned photoresist layer. The method further includes forming a control gate by anisotropically etching the second semiconductor layer and then subsequently isotropically etching the second semiconductor layer. | 2011-08-25 |
| 20110207275 | METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT - A method of producing a semiconductor device according to the present invention includes: a step of implanting an impurity into a semiconductor layer | 2011-08-25 |
| 20110207276 | POWER MOS DEVICE FABRICATION - Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom. | 2011-08-25 |
| 20110207277 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER - In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device. | 2011-08-25 |
| 20110207278 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a method of fabricating a semiconductor device that includes both an enhancement-mode FET and a depletion-mode FET. The method includes forming an opening in a gate electrode for the depletion-mode FET. The opening is located in or in the vicinity of one of the overlapping regions in which the gate electrode extends over active regions. The method further includes ion-implanting dopant impurities into the active regions at an oblique angle using the gate electrode as a mask, thereby to form the doped region that is located under the opening and continuously extending from one of the opposite sides of the gate electrode to the other. | 2011-08-25 |
| 20110207279 | INTEGRATED METHOD FOR FORMING HIGH-K METAL GATE FINFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 2011-08-25 |
| 20110207280 | SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC - A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y M | 2011-08-25 |
| 20110207281 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device includes the steps of forming a trench in a semiconductor substrate of a first conductive type so that an active region having a first portion and a second region is formed; implanting a first impurity of the first conductive type at an implantation angle between 30 degrees and 45 degrees relative to a normal line in an implantation direction rotating relative to the normal line so that a first channel diffusion region and a channel stopper region of the first conductive type are formed; filling the trench with an insulation layer; implanting a second impurity of a second conductive type so that a second channel diffusion region of the second conductive type is formed; forming a gate insulation film on the first portion and the second portion; and forming a gate electrode on the gate insulation film. | 2011-08-25 |
| 20110207282 | Methods for Producing a Tunnel Field-Effect Transistor - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 2011-08-25 |
| 20110207283 | HIGH TEMPERATURE ATOMIC LAYER DEPOSITION OF DIELECTRIC OXIDES - Methods are provided herein for forming metal oxide thin films by atomic layer deposition. The metal oxide thin films can be deposited at high temperatures such that the thin film is crystalline as deposited. The metal oxide thin films can be used, for example, as dielectric oxides in transistors, flash devices, capacitors, integrated circuits, and other semiconductor applications. | 2011-08-25 |
| 20110207284 | SOLID-STATE MEMORY MANUFACTURING METHOD - A method of at least one embodiment of the present invention of manufacturing a solid-state memory is a method of manufacturing a solid-state memory, the solid-state memory including a recording film whose electric characteristics are varied by phase transformation, the method including: forming the recording film by forming a laminate of two or more layers so that a superlattice structure is provided, each of the layers having a parent phase which shows solid-to-solid phase-transformation, the recording film being formed at a temperature not lower than a temperature highest among crystallization temperatures of the parent phases. It is thus possible to manufacture a solid-state memory which requires lower current for recording and erasing data and has a greater rewriting cycle number. | 2011-08-25 |
| 20110207285 | Method Of Forming Pattern Structure And Method Of Fabricating Semiconductor Device Using The Same - A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed. | 2011-08-25 |
| 20110207286 | Reprogrammable Fuse Structure and Method - A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry. | 2011-08-25 |
| 20110207287 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer. | 2011-08-25 |
| 20110207288 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 2011-08-25 |
| 20110207289 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM - Provided are a method of fabricating a semiconductor device and an electronic system. The method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region. The semiconductor substrate is etched to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns a first space between the upper semiconductor patterns projecting from the lower semiconductor patterns and a second space between the lower semiconductor patterns. The upper semiconductor patterns have sidewalls vertically arranged with facing sidewalls of the lower semiconductor patterns and facing each other, and the second space between the lower semiconductor patterns has a bottom surface disposed at a lower level than the lower impurity region. Top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns are disposed at a lower level than the upper impurity region and disposed at a higher level than the lower impurity region. An isolation layer filling the first and second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively is formed. | 2011-08-25 |
| 20110207290 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films. | 2011-08-25 |
| 20110207291 | WAFER BONDING DEVICE AND WAFER BONDING METHOD - A wafer bonding method includes: holding a first substrate with an upper holding mechanism | 2011-08-25 |
| 20110207292 | METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time. | 2011-08-25 |
| 20110207293 | METHOD OF PRODUCING A HYBRID SUBSTRATE HAVING A CONTINUOUS BURIED EECTRICALLY INSULATING LAYER - A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallisation of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface. | 2011-08-25 |
| 20110207294 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes: pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon; and pressing a second polishing tape against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth. | 2011-08-25 |
| 20110207295 | METHOD OF DETACHING SEMI-CONDUCTOR LAYERS AT LOW TEMPERATURE - A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds. | 2011-08-25 |
| 20110207296 | FABRICATION METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench. | 2011-08-25 |
| 20110207297 | Method for Manufacturing Chalcopyrite Film - A highly safe method of obtaining chalcopyrite film wherein a Ib group metal and IIIb group metal are sufficiently combined with a VIb group element by only heat treatment without using an atmosphere containing a VIb group element (Se, S, Te). | 2011-08-25 |
| 20110207298 | DENSE PITCH BULK FINFET PROCESS BY SELECTIVE EPI AND ETCH - Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features. | 2011-08-25 |
| 20110207299 | COMPOUND SEMICONDUCTOR MANUFACTURING DEVICE, COMPOUND SEMICONDUCTOR MANUFACTURING METHOD, AND JIG FOR MANUFACTURING COMPOUND SEMICONDUCTOR - When compound semiconductor layers are formed on a compound semiconductor substrate ( | 2011-08-25 |
| 20110207300 | ELECTRONIC DEVICES - A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region. | 2011-08-25 |
| 20110207301 | ATMOSPHERIC PRESSURE CHEMICAL VAPOR DEPOSITION WITH SATURATION CONTROL - A process for coating a substrate heated to a temperature below the condensation temperature of a semiconductor material at atmospheric pressure is disclosed, the process including the steps of mixing a mass of semiconductor material and a heated inert gas stream, vaporizing the controlled mass of semiconductor material within the inert gas to generate a sub-saturated fluid mixture, directing the sub-saturated fluid mixture at the substrate, wherein the substrate is at substantially atmospheric pressure, depositing a layer of the semiconductor material onto a surface of the substrate, extracting undeposited semiconductor material, and repeating the steps of generating, directing, depositing, and extracting, to minimize an amount of undeposited semiconductor material. | 2011-08-25 |
| 20110207302 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SUBSTRATE PROCESSING METHOD AND APPARATUS - Embodiments described herein relate to improving the quality of a substrate and the performance of a semiconductor device, which is caused by contaminates or particles being engrained into a substrate with a silicon film formed thereon, and forming a silicon film with a small surface roughness. Provided is a semiconductor device manufacturing method that includes forming a silicon film on a substrate, supplying an oxidation seed onto the substrate, performing heat treatment on the silicon film, modifying the surface layer of the silicon film into an oxidized silicon film, and removing the oxidized silicon film. | 2011-08-25 |
| 20110207303 | Methods of Fabricating Semiconductor Devices - Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process. | 2011-08-25 |
| 20110207304 | Method of Fabricating Semiconductor Devices - Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed. | 2011-08-25 |
| 20110207305 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region. | 2011-08-25 |
| 20110207306 | SEMICONDUCTOR STRUCTURE MADE USING IMPROVED ION IMPLANTATION PROCESS - Methods and apparatus for producing a semiconductor structure include: subjecting an implantation surface of a semiconductor wafer to an ion implantation process to create an exfoliation layer therein, wherein the ion implantation process includes simultaneously implanting two different species of ions into the implantation surface of the semiconductor wafer. | 2011-08-25 |
| 20110207307 | PLASMA IMMERSION ION IMPLANTATION METHOD USING A PURE OR NEARLY PURE SILICON SEASONING LAYER ON THE CHAMBER INTERIOR SURFACES - Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction. | 2011-08-25 |
| 20110207308 | TECHNIQUE FOR LOW-TEMPERATURE ION IMPLANTATION - A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter; a cooling mechanism within the pre-chill station configured to cool a wafer from ambient temperature to a predetermined range less than ambient temperature; a loading assembly coupled to the pre-chill station and the end station; and a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to the predetermined temperature range before any ion implantation into the wafer, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process. | 2011-08-25 |
| 20110207309 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film. | 2011-08-25 |
| 20110207310 | SEMICONDUCTOR DEVICE WITH A FIELD STOP ZONE AND PROCESS OF PRODUCING THE SAME - Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone. | 2011-08-25 |
| 20110207311 | Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device may include sequentially forming a tunnel insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate, forming hard mask patterns on the second conductive layer, forming a passivation layer on surfaces of the hard mask patterns, and etching the second conductive layer, the dielectric layer, and the first conductive layer using the hard mask patterns and the passivation layer as an etch mask. | 2011-08-25 |
| 20110207312 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film ( | 2011-08-25 |
| 20110207313 | Semiconductor Devices and Methods of Fabricating the Same - Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The methods may include forming a pattern on a substrate, forming a capping dielectric layer on the pattern, and thermally processing the substrate. After thermally processing the substrate, the methods may further include forming a diffusion barrier layer by a nitride process that may include supplying nitrogen to the capping dielectric layer. The methods may also include forming an etching stop layer on the diffusion barrier layer, forming an inter-layer dielectric layer on the etching stop layer, and planarizing the inter-layer dielectric layer. | 2011-08-25 |
| 20110207314 | Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed. | 2011-08-25 |
| 20110207315 | METHOD OF FABRICATING GATE STRUCTURES - An embodiment of the disclosure includes a method of forming metal gate structures. A substrate is provided. A first dummy gate electrode and a second dummy gate electrode are formed on the substrate. The first dummy gate electrode comprises first spacers on its sidewalls and the second dummy gate electrode comprises second spacers on its sidewalls. A hardmask layer is formed to covers both the first dummy gate electrode and the second dummy gate electrode. A patterned photoresist layer on the hardmask layer that covers a portion of the hardmask layer over the second dummy gate electrode and that leaves a portion of the hardmask layer over the first dummy gate electrode exposed. The portion of the exposed hardmask layer over the first dummy gate electrode is removed. The first spacers and the first dummy gate electrode is exposed to a first plasma environment comprising O2, HBr, and Cl | 2011-08-25 |
| 20110207316 | Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same - Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections. | 2011-08-25 |
| 20110207317 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole. | 2011-08-25 |
| 20110207318 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device, includes burying a conductive pattern in an insulating film made of SiOH, SiCOH or organic polymer, treating surfaces of the insulating film and the conductive pattern with plasma which includes a hydrocarbon gas as a treatment gas, and forming a diffusion barrier film, which is formed of an SiCH film, an SiCHN film, an SiCHO film or an SiCHON film, over the insulating film and the conductive pattern with performing a plasma CVD by adding an Si-containing gas to the treatment gas while increasing the addition amount gradually or in a step-by-step manner. | 2011-08-25 |
| 20110207319 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes forming an insulating film above a semiconductor substrate, forming an opening in the insulating film, forming a conductive film above the insulating film with the opening formed, removing the conductive film above the insulating film to bury the conductive film in the opening, and processing a surface of the insulating film with a silicon compound including Si—N or Si—Cl. | 2011-08-25 |
| 20110207320 | Noble Metal Activation Layer - Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials | 2011-08-25 |
| 20110207321 | SEMICONDUCTOR DEVICE MANUFACTURIING METHOD - A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer. The step (b) comprises steps of: (b1) depositing a lower surface electrode material layer on the lower surface of the substrate, the lower surface electrode material layer being a raw material layer of the lower surface electrode, and (b2) annealing the lower surface electrode material layer with a laser to make an ohmic contact between the lower surface electrode and the substrate. | 2011-08-25 |
| 20110207322 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes, but is not limited to, the following processes. A seed layer is formed over a substrate. The seed layer includes first, second, and third portions. A first electrode covering the first portion of the seed layer is formed without forming an electrode on the second and third portions of the seed layer. The third portion of the seed layer is removed so that the first and second portions remain over the substrate, and the first and second portions are separated from each other. | 2011-08-25 |
| 20110207323 | Method of forming and patterning conformal insulation layer in vias and etched structures - Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask. | 2011-08-25 |
| 20110207324 | NEW METAL PRECURSORS FOR SEMICONDUCTOR APPLICATIONS - Methods and compositions for depositing metal films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising gold, silver, or copper. More specifically, the disclosed precursor compounds utilize pentadienyl ligands coupled to a metal to increase thermal stability. Furthermore, methods of depositing copper, gold, or silver are disclosed in conjunction with use of other precursors to deposit metal films. The methods and compositions may be used in a variety of deposition processes. | 2011-08-25 |
| 20110207325 | METHOD OF MANUFACTURING SUBSTRATE AND ORGANIC EMITTING DISPLAY DEVICE HAVING THE SUBSTRATE - Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a substrate; an sealing substrate facing the substrate, an organic light emitting unit disposed between the substrate and the sealing substrate and having a plurality of organic light emitting devices emitting light, and a plurality of grooves formed in a light extracting surface of the organic light emitting display device through which the light is emitted to the outside. In one embodiment, the grooves are formed on the sealing substrate, and in another embodiment, the grooves are formed on the substrate. | 2011-08-25 |
| 20110207326 | SLURRY FOR POLISHING AND PLANARIZATION METHOD OF INSULATING LAYER USING THE SAME - A polishing slurry includes an abrasive, a dispersion agent, a polish accelerating agent and an adhesion inhibitor. The adhesion inhibitor includes a benzene compound combined with a carboxyl group. Methods of planarizing an insulating layer using the slurry are also provided. | 2011-08-25 |
| 20110207327 | ABRASIVE, POLISHING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention relates to a polishing method for polishing a to-be-polished surface including a polysilicon film having a silicon dioxide film directly thereunder, in manufacturing a semiconductor integrated circuit device, the method including: a first polishing step of polishing and planarizing the polysilicon film with a first abrasive containing a cerium oxide particle, water and an acid; and a second polishing step of polishing the polysilicon film planarized in the first polishing step with a second abrasive containing at least a cerium oxide particle, water, an acid and a water-soluble polyamine or a salt thereof and stopping polishing by exposure of the silicon dioxide film. | 2011-08-25 |
| 20110207328 | METHODS AND APPARATUS FOR THE MANUFACTURE OF MICROSTRUCTURES - A method of manufacturing microstructures is disclosed, the method comprising a applying a mask to substrate; forming a pattern in the mask; processing the substrate according to the pattern; and mechanically removing the mask from the substrate. A polymer mask is disclosed for manufacturing micro scale structure, the polymer mask comprising a thin, preferably ultra thin flexible film. A method of manufacturing an integrated circuit is disclosed, the method comprising forming a plurality of isolated semiconductor devices on a common substrate; and connecting some of the devices. Apparatus for manufacturing microstructures is disclosed comprising: a mechanism for coating a mass substrate to create a structure; a mechanism for removing a mask from the substrate; and processing apparatus. A thin film transistor is disclosed comprising drain source and gate electrodes, the drain and source electrode being separated by a semiconductor, and the gate electrode being separated from the semiconductor by an insulator, comprising a bandgap alignment layer disposed between a semiconductor and the insulator. | 2011-08-25 |
| 20110207329 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well. | 2011-08-25 |
