| 34th week of 2011 patent applcation highlights part 15 |
| Patent application number | Title | Published |
|---|
| 20110204427 | CAPACITOR HAVING AN ELECTRODE STRUCTURE, METHOD OF MANUFACTURING A CAPACITOR HAVING AN ELECTRODE STRUCTURE AND SEMICONDUCTOR DEVICE HAVING AN ELECTRODE STRUCTURE - A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics. | 2011-08-25 |
| 20110204428 | IMPLEMENTING EDRAM STACKED FET STRUCTURE - A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM. | 2011-08-25 |
| 20110204429 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME - A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor. | 2011-08-25 |
| 20110204430 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 2011-08-25 |
| 20110204431 | FULLY DEPLETED SILICON-ON-INSULATOR CMOS LOGIC - A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects. | 2011-08-25 |
| 20110204432 | Methods and Devices for Forming Nanostructure Monolayers and Devices Including Such Monolayers - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided. | 2011-08-25 |
| 20110204433 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device is disclosed. The nonvolatile semiconductor storage device includes a semiconductor substrate including a surface layer; an element isolation insulating film isolating the surface layer of the semiconductor device into a plurality of active regions; a first gate insulating film formed above the active regions; a charge storing layer formed above the first gate insulating film and including a silicon layer containing an upper layer selectively doped with carbon; a second gate insulating film formed above the charge storing layer; and a control gate electrode formed above the second gate insulating film. | 2011-08-25 |
| 20110204434 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes, a gate structure having a gate dielectric layer, a gate electrode, and a spacer, which are each formed on a substrate, a first impurity area formed in a portion of the substrate located below the spacer, a second impurity area in contact with a sidewall of the first impurity area and formed in the substrate on both sides of the gate structure, and a dielectric pattern in contact with a portion of the first impurity area and formed on a sidewall of the second impurity area. At this time, the second impurity area may include an upper part with an upward-narrowing width and a lower part with a downward-narrowing width. | 2011-08-25 |
| 20110204435 | VERTICAL CAPACITIVE DEPLETION FIELD EFFECT TRANSISTOR - Vertical capacitive depletion field effect transistors (VCDFETs) and methods for fabricating VCDFETs are disclosed. An example VCDFET includes one or more interleaved drift and gate regions. The gate region(s) may be configured to capacitively deplete the drift region(s) though one or more insulators that separate the gate region(s) from the drift region(s). The drift region(s) may have graded/non-uniform doping profiles. In addition, one or more ohmic and/or Schottky contacts may be configured to couple one or more source electrodes to the drift region(s). | 2011-08-25 |
| 20110204436 | Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region - A field effect transistor (FET) in a semiconductor die including an active region housing active cells, a non-active region with no active cells therein, a drift region of a first conductivity type, a body region of a second conductivity type over the drift region, and a plurality of trenches extending through the body region and into the drift region. Each trench includes a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode. The FET further includes source regions of the first conductivity type in the body region adjacent to each trench, heavy body regions of the second conductivity type in the body regions adjacent the source regions, and a source interconnect layer contacting the source regions and heavy body regions. The shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer. | 2011-08-25 |
| 20110204437 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed. | 2011-08-25 |
| 20110204438 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a first insulating film; a second insulating film; a first gate electrode; a second gate electrode; and a first semiconductor region. The semiconductor substrate has first and second grooves crossing each other in plan view. The first insulating film covers an inner surface of the first groove. The second insulating film covers an inner surface of the second groove. The first gate electrode fills at least a bottom portion of the first groove. The second gate electrode fills at least a bottom portion of the second groove. The first semiconductor region is positioned in the semiconductor substrate. The first semiconductor region contains a first impurity. The first semiconductor region is adjacent to a first portion of the second insulating film. The first portion of the second insulating film covers at least a bottom region of the second groove. | 2011-08-25 |
| 20110204439 | SEMICONDUCTOR DEVICE - Embodiments provide a semiconductor device including an N-type semiconductor layer | 2011-08-25 |
| 20110204440 | Shielded gate trench (SGT) mosfet devices and manufacturing processes - This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate. | 2011-08-25 |
| 20110204441 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 2011-08-25 |
| 20110204442 | CORNER LAYOUT FOR SUPERJUNCTION DEVICE - A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions. | 2011-08-25 |
| 20110204443 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER - Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on a bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., a single-fin or multi-fin MUGFET or multiple series-connected single-fin or multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections). Also disclosed is a SOI structure formed using the above-described method. | 2011-08-25 |
| 20110204444 | Semiconductor intergrated device and method of manufacturing same - A semiconductor integrated device of the invention can enhance a radiation resistance. In an exemplary embodiment, the semiconductor integrated device includes a semiconductor supporting substrate, an insulation layer provided on the semiconductor supporting substrate, and a silicon thin film provided on the insulation layer. A predetermined region in the silicon thin film that is adjacent to the boundary between the insulation layer and the silicon thin film (i.e., boundary neighboring region) has an impurity-concentration-increased region. In this region, the impurity concentration becomes higher as the position approaches the boundary. | 2011-08-25 |
| 20110204445 | Selective Floating Body SRAM Cell - A memory cell has N≧16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. | 2011-08-25 |
| 20110204446 | METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH REDUCED GATE HEIGHT, AND RELATED FABRICATION METHODS - A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses. | 2011-08-25 |
| 20110204447 | ESD TOLERANT I/O PAD CIRCUIT INCLUDING A SURROUNDING WELL - An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body. | 2011-08-25 |
| 20110204448 | SEMICONDUCTOR DEVICE - In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have third and fourth regions having the same active region pattern. The active regions of the third and fourth transistors have a longer length in the channel length direction than that of the active regions of the first and second transistors. The third and fourth regions have a narrower width in the channel length direction than that of the first and second regions. | 2011-08-25 |
| 20110204449 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 2011-08-25 |
| 20110204450 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device of the present invention includes a silicon substrate having a logic region and a RAM region, an NMOS transistor formed in the logic region, and an NMOS transistor formed in the RAM region. The NMOS transistor has a stack structure obtained by sequentially stacking the gate insulating film and the metal gate electrode over the silicon substrate. The NMOS transistor has a cap metal containing an element selected from a group consisting of lanthanum, ytterbium, magnesium, strontium, and erbium as a composition element between the silicon substrate and metal gate electrode. The cap metal is not formed in the NMOS transistor. | 2011-08-25 |
| 20110204451 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction. | 2011-08-25 |
| 20110204452 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 2011-08-25 |
| 20110204453 | Methods Of Forming Electrically Conductive Lines, Methods Of Forming An Electrically Conductive Buried Line And An Electrical Contact Thereto, Electrically Conductive Lines, And Integrated Circuitry Comprising A Line Of Recessed Access Devices - A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed. | 2011-08-25 |
| 20110204454 | SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS - An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion. | 2011-08-25 |
| 20110204455 | HYDROGEN ION SENSING DEVICE USING OF ARRAYED GATED LATERAL BJT - A hydrogen ion sensing device includes: a reference electrode; a sensing portion which senses hydrogen ions by contacting an ion aqueous solution; and a plurality of ring-like lateral bipolar junction transistors, each including a lateral collector, an emitter, a vertical collector and a floating gate connected to the reference electrode, with the emitter surrounded by the floating gate and the lateral collector, wherein the plurality of ring-like lateral bipolar junction transistors are formed on a common substrate and are connected in parallel. With this configuration, an operation point can be adjusted by the bases current with the emitter voltage fixed. In addition, polarities of values of X and Y axes are positive in comparison with a p-channel MOSFET driven with the common collector setting and the device can be operated in a linear region (an active mode) in comparison with ISFET operating in a saturation region. In addition, a sensing area and ion sensitivity can be greatly improved over a single gated lateral BJT and the ion sensitivity can be adjusted by the gate voltage and the base current. Further, the device is capable of operating in a first quadrant even in an n-well, which results in significant reduction of production costs. | 2011-08-25 |
| 20110204456 | PACKAGED DEVICE WITH ACOUSTIC TRANSDUCER AND AMPLIFIER - A device includes: a lead frame having an aperture in a central portion thereof; at least one acoustic transducer mounted on the lead frame above the aperture and configured to convert between acoustic energy and an electrical signal with low signal losses; a housing connected to the lead frame and including a base portion on a same side of the lead frame as the acoustic transducer; an amplifier is provided on a base portion of the housing in close proximity to the acoustic transducer; and a lid configured together with the base portion of the housing to define a cavity, wherein the acoustic transducer and the amplifier are closely positioned within the MEMS device cavity. | 2011-08-25 |
| 20110204457 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor element having a base, a cavity having a polygonal horizontal cross-section penetrating vertically through the base, a diaphragm arranged on the base to cover the cavity, and a substrate formed with a die bonding pad. A lower surface of the semiconductor element is adhered on the die bonding pad with a die bonding resin. The die bonding pad is formed so as not to contact a lower end of a valley section formed by an intersection of wall surfaces of an inner peripheral surface of the cavity of the semiconductor element. | 2011-08-25 |
| 20110204458 | Semiconductor Device and Method of Manufacturing the Same - The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO | 2011-08-25 |
| 20110204459 | SIDEWALL COATING FOR NON-UNIFORM SPIN MOMENTUM-TRANSFER MAGNETIC TUNNEL JUNCTION CURRENT FLOW - A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls. | 2011-08-25 |
| 20110204460 | Integrated Hall Effect Element Having a Germanium Hall Plate - An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element. | 2011-08-25 |
| 20110204461 | Stack-type image sensor - Example embodiments are directed to a stack-type image sensor including resistance change elements. The stack-type image sensor includes at least two light-sensing layers that detect different color light stacked on different layers. The stack-type image sensor may not require a size of a unit pixel that detects a light color to be less than 1 μm in order to generate a high resolution color image. As such, resolution saturation may be avoided. | 2011-08-25 |
| 20110204462 | METHOD AND APPARATUS PROVIDING AN IMAGER MODULE WITH A PERMANENT CARRIER - Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer. | 2011-08-25 |
| 20110204463 | WAVELENGTH OPTICAL FILTER STRUCTURE AND ASSOCIATED IMAGE SENSOR - The invention relates to an optical filter structure composed of at least two adjacent elementary optical filters, an elementary optical filter being centred on an optimum transmission frequency, characterised in that it comprises a stack of n metallic layers (m | 2011-08-25 |
| 20110204464 | Micro-Optical Device Packaging System - According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate. | 2011-08-25 |
| 20110204465 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE DEVICE - In an optical device having a direct attachment structure and a method of manufacturing the optical device, a light-transmissive member can be bonded to an element region without being misaligned. | 2011-08-25 |
| 20110204466 | PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD, PHOTOELECTRIC CONVERSION DEVICE, AND PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM - A photoelectric conversion device manufacturing method, includes: continuously forming a first p-type semiconductor layer, a first i-type semiconductor layer, and a first n-type semiconductor layer, which constitute a first-photoelectric conversion unit, and a second p-type semiconductor layer which constitutes a second-photoelectric conversion unit, in decompression chambers that are different from each other; exposing the second p-type semiconductor layer to an air atmosphere; and forming a second i-type semiconductor layer and a second n-type semiconductor layer, which constitute the second-photoelectric conversion unit, on the second p-type semiconductor layer of the second-photoelectric conversion unit which was exposed to the air atmosphere, in the same decompression chamber. | 2011-08-25 |
| 20110204467 | SOLID-STATE IMAGE PICKUP DEVICEAND FABRICATION PROCESS THEREOF - A solid-state image pickup device has photodiodes, each of which includes an N-type region formed in a semiconductor substrate, a first silicon carbide layer formed above the N-type region, and a P-type region including a first silicon layer formed above the first silicon carbide layer and doped with boron. A fabrication process of such a solid-state image pickup device is also disclosed. | 2011-08-25 |
| 20110204468 | Image sensor and method of manufacturing the same - Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern. | 2011-08-25 |
| 20110204469 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with a peripheral region that has a narrow width and exhibits good electric field relaxation and high robustness against induced charges. The device has an active region for main current flow and a peripheral region surrounding the active region on a principal surface of a semiconductor substrate of a first conductivity type. The peripheral region has a guard ring of a second conductivity type composed of straight sections and curved sections connecting the straight sections formed in a region of the principal surface surrounding the active region, and a pair of polysilicon field plates in a ring shape formed separately on inner and outer circumferential sides of the guard ring. The surface of the guard ring and the pair of polysilicon field plates of the inner circumferential side and the outer circumferential side are electrically connected with a metal film in the curved section. | 2011-08-25 |
| 20110204470 | METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN - An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density. | 2011-08-25 |
| 20110204471 | SEMICONDUCTOR WAFERS WITH REDUCED ROLL-OFF AND BONDED AND UNBONDED SOI STRUCTURES PRODUCED FROM SAME - The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided. | 2011-08-25 |
| 20110204472 | Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame - A semiconductor device is made by mounting a semiconductor component over a carrier. A ferromagnetic inductor core is formed over the carrier. A pillar frame including a plurality of bodies is mounted over the carrier, semiconductor component, and inductor core. An encapsulant is deposited around the semiconductor component, plurality of bodies, and inductor core. A portion of the pillar frame is removed. A first remaining portion of the pillar frame bodies provide inductor pillars around the inductor core and a second remaining portion of the pillar frame bodies provide an interconnect pillar. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. | 2011-08-25 |
| 20110204473 | VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD - A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein. | 2011-08-25 |
| 20110204474 | MEMORY CELL WITH SILICON-CONTAINING CARBON SWITCHING LAYER AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (MIM) stack, the MIM stack including (a) a first conductive carbon layer; (b) a low-hydrogen, silicon-containing carbon layer above the first conductive carbon layer; and (c) a second conductive carbon layer above the low-hydrogen, silicon-containing carbon layer; and (2) forming a steering element coupled to the MIM stack. Numerous other aspects are provided. | 2011-08-25 |
| 20110204475 | ENHANCED WORK FUNCTION LAYER SUPPORTING GROWTH OF RUTILE PHASE TITANIUM OXIDE - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 2011-08-25 |
| 20110204476 | Electronic Package with Fluid Flow Barriers - The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region. | 2011-08-25 |
| 20110204477 | Semiconductor integrated circuit device - A capacitance cell includes a substrate structure layer having pair diffusion regions, and an interconnect layer having pair of power supply lines. The capacitance cell also includes a capacitance composed of a first electrode, a dielectric member and a second electrode stacked together, and is formed in a frame shape and disposed in a space between the substrate structure layer and the interconnect layer so as to extend along an outer rim of the frame shape of a standard cell region in which a standard cell is arranged. The capacitance cell also includes a first substrate contact that electrically connects one of the pair of power supply lines to one of the diffusion regions externally of the standard cell region. The capacitance cell also includes a second substrate contact that electrically connects the other power supply line to the other diffusion region, externally of the standard cell region. The capacitance cell further includes a first capacitance contact electrically connecting the first electrode to the other diffusion region internally of the standard cell region, and a second capacitance contact electrically connecting the second electrode to the one power supply line internally of the standard cell region. | 2011-08-25 |
| 20110204478 | INSULATOR LAYER BASED MEMS DEVICES - The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die. | 2011-08-25 |
| 20110204479 | SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film. | 2011-08-25 |
| 20110204480 | 3D INTEGRATION OF A MIM CAPACITOR AND A RESISTOR - The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, ( | 2011-08-25 |
| 20110204481 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION - The present invention provides a semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween. | 2011-08-25 |
| 20110204482 | Method and Electronic Device for a Simplified Integration of High Precision Thinfilm Resistors - The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR. | 2011-08-25 |
| 20110204483 | Electroluminescent device for the production of ultra-violet light - The invention provides a method of producing an opto-electronic device wherein a layer of lattice matched material is grown on a substrate, the lattice matched material being a cubic zincblend material and the substrate being a cubic diamond or zincblend material, to form a coated substrate. | 2011-08-25 |
| 20110204484 | Sub-Wavelength Segmentation in Measurement Targets on Substrates - Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions. | 2011-08-25 |
| 20110204485 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion. | 2011-08-25 |
| 20110204486 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other. | 2011-08-25 |
| 20110204487 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate; a through electrode passing through the semiconductor substrate in a thickness direction of the semiconductor substrate; an internal electrode provided in a part of the top surface of the semiconductor substrate and electrically connected to the through electrode which reaches the part; a first protective film covering the top surface except a part of the internal electrode; a second protective film formed apart from the first protective film, on the part of the internal electrode, the part being not covered by the first protective film; and metal wiring formed on the back surface of the semiconductor substrate and electrically connected to the through electrode, the second main surface being on a side of the semiconductor substrate opposite the first main surface. | 2011-08-25 |
| 20110204488 | SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes preparing a semiconductor wafer including a silicon substrate and a laminate having a compound semiconductor layer; etching and removing a part of the laminate in a thickness direction to form trench regions in a grid, each trench region including a plurality of stripe grooves extending in parallel to each other; filling the groove with a material having a lower hardness than the compound semiconductor layer to form a buried region; and dividing the semiconductor wafer into a plurality of chips by dicing using a blade at a dicing line which is defined within the trench region and includes a plurality of the buried regions. | 2011-08-25 |
| 20110204489 | SILICON SUBSTRATE HAVING NANOSTRUCTURES AND METHOD FOR PRODUCING THE SAME AND APPLICATION THEREOF - A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nano structures. | 2011-08-25 |
| 20110204490 | FILM FORMING APPARATUS, FILM FORMING METHOD, AND SEMICONDUCTOR DEVICE - According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading. | 2011-08-25 |
| 20110204491 | DIELECTRIC LAYER STRUCTURE - A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer. | 2011-08-25 |
| 20110204492 | Microelectronic structure including a low K dielectric and a method of controlling carbon distribution in the structure - Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole. | 2011-08-25 |
| 20110204493 | SHIELDING STRUCTURE FOR TRANSMISSION LINES - A shielding structure comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias all being at substantially the same potential, preferably ground. In one embodiment, one or more signal lines are located in the second metallization layer between the first and second planar structures; and in another embodiment they are located in a third metallization layer between the first and second metallization layers. | 2011-08-25 |
| 20110204494 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed. | 2011-08-25 |
| 20110204495 | DEVICE HAVING WIRE BOND AND REDISTRIBUTION LAYER - A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip. | 2011-08-25 |
| 20110204496 | CIRCUIT MODULE, ELECTRONIC DEVICE INCLUDING THE SAME, AND CIRCUIT MODULE MANUFACTURING METHOD - Provided is a circuit module reduced in size. The circuit module includes: a substrate to which electronic parts are mounted; a shield case; and a bonding material for bonding the substrate and the shield case. The shield case includes legs extending from given side walls of the shield case to overlap with portions of the side faces of the substrate, and the portions of the side faces of the substrate are bonded to the legs of the shield case by the bonding material. The shield case includes openings formed in the given side walls of the shield case to expose overlapping portions where the portions of the side faces of the substrate overlap with the legs of the shield case. | 2011-08-25 |
| 20110204497 | Semiconductor integrated circuit and method for manufacturing the same - A semiconductor integrated circuit having a semiconductor chip mounted over a tape- or film-like substrate, the semiconductor integrated circuit having a higher strength against bending, as well as a method for manufacturing the semiconductor integrated circuit, are disclosed. The semiconductor integrated circuit comprises a bendable tape-like substrate, the tape-like substrate including external terminals, internal terminals provided for coupling to a rectangular semiconductor chip, and wiring lines for coupling the internal terminals and the external terminals with each other; and a reinforcing member for reinforcing the semiconductor chip over the tape-like substrate in a longitudinal direction of the semiconductor chip, the semiconductor chip and the reinforcing member being sealed with resin. | 2011-08-25 |
| 20110204498 | LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED THEREWITH - A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length. The second set lead parallel length of each second set lead has a constant width and edges that are parallel to edges of all other second set lead parallel lengths in the second set of leads and also parallel to the edges of first set lead parallel lengths. At least one second set lead has an extension length extending inwardly from the second set lead tapered length, the extension length has a constant width and provides a second set lead bond target region. Wire bond leads electrically couple both the first set lead bond target region and second set lead bond target region to respective die external electrical connection pads on a surface of the die and a package body encloses the die. | 2011-08-25 |
| 20110204499 | SEMICONDUCTOR DEVICE ASSEMBLIES - An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages. In addition, methods for designing and fabricating the interposer are disclosed, as are methods for forming assemblies, packages, and multi-chip modules that include the interposer. | 2011-08-25 |
| 20110204500 | POWER DEVICE PACKAGES HAVING THERMAL ELECTRIC MODULES USING PELTIER EFFECT AND METHODS OF FABRICATING THE SAME - Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module. | 2011-08-25 |
| 20110204501 | INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING NON-LEADED PACKAGE - An integrated circuit packaging system includes: a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; each one of the plurality of leads includes first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and a lead-to-lead gap formed between the second terminal ends of alternating leads in excess of the predetermined interval gap. | 2011-08-25 |
| 20110204502 | Method of Manufacturing A Semiconductor Device - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 2011-08-25 |
| 20110204503 | MICROELECTRONIC PACKAGE ASSEMBLY, METHOD FOR DISCONNECTING A MICROELECTRONIC PACKAGE - A microelectronic package assembly comprises a lead frame having a holding bar ( | 2011-08-25 |
| 20110204504 | Reducing Susceptibility to Electrostatic Discharge Damage during Die-To-Die Bonding for 3-D Packaged Integrated Circuits - Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact. | 2011-08-25 |
| 20110204505 | Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier - A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV. | 2011-08-25 |
| 20110204506 | Thermal Interface Material Design for Enhanced Thermal Performance and Improved Package Structural Integrity - An electronic package | 2011-08-25 |
| 20110204507 | TWO-SHELF INTERCONNECT - Consistent with the present disclosure, a package is provided that includes a housing having a recessed portion to accommodate an integrated circuit or chip. The housing has an inner periphery that defines or delineates the recessed portion. The inner periphery may be stepped and includes first and second surfaces that are spaced vertically from one another and extend in respective parallel planes, for example, to thereby constitute first and second shelves. First bonding pads or contacts (“housing pads”) may be provided on the first surface, which may electrically connect or interconnect with first pads on the integrated circuit (“IC pads”), and second housing pads may be provided on the second surface, which can electrically connect or interconnect with second IC pads. Thus, the IC pads connect to corresponding housing pads on the inner periphery of the housing that are above and below one another. Since the housing pads are not provided on the same surface, the number of housing pads on each step or shelf of the periphery can be reduced, and the housing pads can be spaced from one another by a spacing or pitch that is greater than that of the IC pads. Accordingly, the dimensions and spacing of the housing pads may comply with relevant design rules, while providing connection to an increased number of IC pads. | 2011-08-25 |
| 20110204508 | SEMICONDUCTOR PACKAGING SYSTEM WITH AN ALIGNED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a semiconductor packaging system includes: providing a base substrate having edges; mounting an electrical interconnect on the base substrate; and applying an encapsulant having a reference marker and an opening over the electrical interconnect, the reference marker around the electrical interconnect based on physical locations of the edges. | 2011-08-25 |
| 20110204509 | Semiconductor Device and Method of Forming IPD in Fan-Out Level Chip Scale Package - A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer. | 2011-08-25 |
| 20110204510 | CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer. | 2011-08-25 |
| 20110204511 | System and Method for Improving Reliability of Integrated Circuit Packages - An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer. | 2011-08-25 |
| 20110204512 | Wirebondless Wafer Level Package with Plated Bumps and Interconnects - A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip. | 2011-08-25 |
| 20110204513 | Device Including an Encapsulated Semiconductor Chip and Manufacturing Method Thereof - A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body. | 2011-08-25 |
| 20110204514 | PACKAGE DEVICE AND FABRICATION METHOD THEREOF - A package device and a fabrication method thereof comprises providing a plurality of package units each having a plurality of penetrated holes; stacking the plurality of package units in a manner such that the penetrated holes of the plurality of package units are aligned; filling a conductive material into the plurality of penetrated holes substantially, so as to electrically connect the plurality of package units through the conductive material; and disposing a plurality of solder balls on the bottom of the conductive material filling the plurality of penetrated holes, and connecting the plurality of solder balls with the conductive material electrically. | 2011-08-25 |
| 20110204515 | IC DIE INCLUDING RDL CAPTURE PADS WITH NOTCH HAVING BONDING CONNECTORS OR ITS UBM PAD OVER THE NOTCH - An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second net, respectively. A redirect layer (RDL) coupled to the die pads over a first dielectric vias includes a first RDL trace lateral coupling the first die pad and first RDL pad and a second RDL trace coupling the second die pad and second RDL pad. The first RDL pad includes an RDL notch facing the second RDL trace. Under bump metallization (UBM) pads on a second dielectric include a first UBM pad coupled to the first RDL pad over a second dielectric via. A first metal bonding connector is on the first UBM pad. The first UBM pad or first metal bonding connector overhangs the first RDL pad over the notch. | 2011-08-25 |
| 20110204516 | SINGLE CHIP SEMICONDUCTOR COATING STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a single chip semiconductor coating structure includes following steps. Step 1 is providing a single chip semiconductor which has a plurality of surfaces, and two opposite surfaces selected from the plurality of surfaces are manufacturing surfaces and have a conductive area with a pad thereon, respectively. Step 2 is providing a tool to cover one of the conductive areas with the pad. Step 3 is providing a coating step to form an insulating layer on the single chip semiconductor. Step 4 is providing a removing step to remove the insulating layer for exposing the covered conductive area and the pad. Step 5 is forming two electrodes and each of the two electrodes covers the conductive area with the pad. | 2011-08-25 |
| 20110204517 | Semiconductor Device with Vias Having More Than One Material - A semiconductor die includes a via within a substrate material of the semiconductor die. The via includes a first conductive material having a first Coefficient of Thermal Expansion (CTE) and a second conductive material between the first conductive material and the substrate material of the semiconductor die. The second conductive material has a second CTE between the first CTE and a CTE of the substrate material of the semiconductor die. The first conductive material can be copper. The second conductive material can be tungsten and/or nickel. The substrate material can be silicon. | 2011-08-25 |
| 20110204518 | SCALABILITY WITH REDUCED CONTACT RESISTANCE - Miniaturized semiconductor devices are formed with improved liner/barrier layer properties and, hence, improved contact resistance. Embodiments include semiconductor devices comprising contacts and vias with annealed liner/barrier layers having decreased carbon content and increased density. An embodiment includes depositing a metal containing layer, such as at least one member selected from the group consisting of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), cobalt (Co), and ruthenium (Ru) to line an opening formed in a dielectric layer, and annealing the deposited metal containing layer, as in a non-oxidizing atmosphere, to increase its density, decrease defects, and alter its material composition, for example, reduce its carbon content. As a result, a metal, e.g., W or Cu, plug filing the contact/via exhibits a reduced surface roughness and defectivity, and thereby improved contact resistance and reliability. | 2011-08-25 |
| 20110204519 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers. | 2011-08-25 |
| 20110204520 | METAL ELECTRODE AND SEMICONDUCTOR ELEMENT USING THE SAME - A metal electrode is used for a pair with a semiconductor so as to sandwich a high-dielectric constant thin film between the metal electrode and the semiconductor. A metal electrode | 2011-08-25 |
| 20110204521 | CHIP-SCALE SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip-scale semiconductor device package includes a die, an insulating substrate having a through hole, a first metal layer, a second metal layer, and an insulating layer. The first metal layer is on a first surface of the insulating substrate and a first side of the through hole. The insulating layer is overlaid on a second surface of the insulating substrate and surrounds a second side of the through hole. The second metal is on the insulating layer and the second side of the through hole. The die is in the through hole and includes a first electrode and a second electrode. The first electrode is electrically connected to the first metal layer, and the second electrode is electrically connected to the second metal layer. | 2011-08-25 |
| 20110204522 | METHOD FOR FABRICATING THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING - A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations. | 2011-08-25 |
| 20110204523 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 2011-08-25 |
| 20110204524 | STRUCTURES AND METHODS OF FORMING PRE FABRICATED DEEP TRENCH CAPACITORS FOR SOI SUBSTRATES - Structures and methods are provided for forming pre-fabricated deep trench capacitors for SOI substrates. The method includes forming a trench in a substrate and forming a dielectric material in the trench. The method further includes depositing a conductive material over the dielectric material in the trench and forming an insulator layer over the conductive material and the substrate. | 2011-08-25 |
| 20110204525 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - An interlayer insulating film containing a pore-forming agent is formed on a semiconductor substrate, and then the interlayer insulating film is irradiated with ultraviolet (UV). This ultraviolet irradiation is performed in at least two separate times. | 2011-08-25 |
| 20110204526 | Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices - The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated. | 2011-08-25 |
