34th week of 2018 patent applcation highlights part 57 |
Patent application number | Title | Published |
20180240754 | NITRIDE STRUCTURE HAVING GOLD-FREE CONTACT AND METHODS FOR FORMING SUCH STRUCTURES - A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces. | 2018-08-23 |
20180240755 | Cobalt Manganese Vapor Phase Deposition - Described are semiconductor devices and methods of making semiconductor devices with a barrier layer comprising cobalt and manganese nitride. Also described are semiconductor devices and methods of making same with a barrier layer comprising CoMn(N) and, optionally, an adhesion layer. | 2018-08-23 |
20180240756 | FIDUCIAL MARK FOR CHIP BONDING - A flexible multilayer construction ( | 2018-08-23 |
20180240757 | EMI Shielded Integrated Circuit Packages And Methods Of Making The Same - An integrated circuit package with a plurality of embedded electromagnetic interference (EMI) shielding and methods of making the same are disclosed. The integrated circuit packages include the use of a pre-assembled circuit module and an interposer. The circuit module has a plurality of spaced electrical component sections separated by a series of contiguous conductive spacers, and a first shielding means comprises the spacers, vias and an embedded conductive plane. In an example, the interposer has a second shielding means comprises conductive cavities, conductive ridges, vias, and a conduction pattern. In another example, the interposer further comprises conductive strips to form the second shielding means. The first shielding means overlaps the second shielding means to form a plurality of EMI shielded enclosures for holding the spaced electrical component sections therein. | 2018-08-23 |
20180240758 | SEMICONDUCTOR APPARATUS AND COMPOSITE SHEET - A semiconductor apparatus | 2018-08-23 |
20180240759 | INTEGRATED MODULE WITH ELECTROMAGNETIC SHIELDING - The present disclosure relates to a shielded integrated module, which includes a module substrate with a number of perimeter bond pads, at least one electronic component attached to the module substrate and encapsulated by a mold compound, a number of perimeter vertical shield contacts, and a shielding structure. The perimeter bond pads are surrounding the at least one electronic component and encapsulated by the mold compound. Each perimeter vertical shield contact is coupled to a corresponding perimeter bond pad and extends through the mold compound, such that a top tip of each perimeter vertical shield contact is exposed at a top surface of the mold compound. The shielding structure completely covers the top surface of the mold compound and is in contact with the perimeter vertical shield contacts. | 2018-08-23 |
20180240760 | MOUNTING COMPONENT, WIRING SUBSTRATE, ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer. | 2018-08-23 |
20180240761 | RESONANCE-COUPLED SIGNALING BETWEEN IC MODULES - Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative system embodiment includes first and second integrated circuits. The first integrated circuit includes: a transmitter that produces a modulated carrier signal on a primary conductor; a first transfer conductor connected to a first connection terminal; and a first floating loop electromagnetically coupled to the primary conductor and to the transfer conductor to convey the modulated carrier. The second integrated circuit includes: a second transfer conductor connected to a second connection terminal, the second connection terminal being electrically connected to the first connection terminal; a receiver that demodulates the modulated carrier signal; and a second floating loop electromagnetically coupled to the second transfer conductor and to the receiver to convey the modulated carrier signal to the receiver. The first and second floating loops are each resonant at the carrier frequency to provide resonance-coupled signalling between the integrated circuits. | 2018-08-23 |
20180240762 | MICROELECTRONIC DEVICES DESIGNED WITH COMPOUND SEMICONDUCTOR DEVICES AND INTEGRATED ON AN INTER DIE FABRIC - Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. | 2018-08-23 |
20180240763 | DUAL-SIDED MODULE WITH LAND-GRID ARRAY (LGA) FOOTPRINT - A packaged radio-frequency device is disclosed, including a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The packaging substrate may include a first component mounted on the first side of the packaging substrate and a first overmold structure implemented on the first side of the packaging substrate, the first overmold structure substantially encapsulating the first component. The packaging substrate may further include a set of through-mold connections implemented on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins, a second component mounted on the second side of the packaging substrate, the second component being located in an area of the second side configured to implement redundant ground pins and a second overmold structure substantially encapsulating one or more of the second component or the set of through-mold connections. | 2018-08-23 |
20180240764 | Method of Forming Contact Holes in a Fan Out Package - Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns. | 2018-08-23 |
20180240765 | PROCESS OF FORMING SEMICONDUCTOR APPARATUS MOUNTING ON SUBSTRATE - A process of forming a semiconductor apparatus is disclosed. The process includes steps of: depositing a first metal layer containing Ni in a back surface of a substrate, plating the back surface of the substrate so as to expose the first metal layer in a portion of the scribe line, depositing a third metal layer on the whole back surface of the substrate, and selectively removing the third metal layer in the portion of the scribe line so as to leave the first metal layer in the scribe line. | 2018-08-23 |
20180240766 | COMPOUND SEMICONDUCTOR SUBSTRATE AND POWER AMPLIFIER MODULE - A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about θ degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ϕ degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface. | 2018-08-23 |
20180240767 | ELECTRONIC COMPONENT, TRANSPOSING COMPONENT, METHOD FOR FABRICATING THE ELECTRONIC COMPONENT, AND METHOD FOR TRANSPOSING A MICRO-ELEMENT - An electronic component includes a circuit substrate, a connecting electrode, a micro-element, and a solder. The connecting electrode is located on the circuit substrate. The connecting electrode has a first transparent conductive layer. A surface of the first transparent conductive layer is located opposite the circuit substrate, and has a plurality of micrometer or nanometer particles. The micro-element is electrically connected to the connecting electrode. The solder is located between the connecting electrode and the micro-element, and fixes the micro-element on the connecting electrode. | 2018-08-23 |
20180240768 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding. | 2018-08-23 |
20180240769 | BONDED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface. | 2018-08-23 |
20180240770 | CLIP-BONDED SEMICONDUCTOR CHIP PACKAGE USING METAL BUMPS AND METHOD FOR MANUFACTURING THE PACKAGE - A clip-bonded semiconductor chip package comprises a lead frame having a pad and a lead; a semiconductor chip bonded onto the pad of the lead frame; a bonding pad on the semiconductor chip; metal bumps formed on the bonding pad; a clip having first and second portions coupled to each other wherein the first portion is bonded to the bonding pad via the metal bumps, wherein the second portion is bonded to the lead of the lead frame; and a package body made of a molding material around the lead frame, the semiconductor chip and the clip. | 2018-08-23 |
20180240771 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball. | 2018-08-23 |
20180240772 | Electronic Device By Laser-Induced Forming and Transfer of Shaped Metallic Interconnects - An electronic device made from the method of providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, laser bending the shaped metallic interconnects; and transferring the shaped metallic interconnects onto a receiving substrate or device. | 2018-08-23 |
20180240773 | Embedded Wire Bond Wires for Vertical Integration With Separate Surface Mount and Wire Bond Mounting Surfaces - In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires. | 2018-08-23 |
20180240774 | ULTRASONIC TRANSDUCER SYSTEMS INCLUDING TUNED RESONATORS, EQUIPMENT INCLUDING SUCH SYSTEMS, AND METHODS OF PROVIDING THE SAME - An ultrasonic transducer system is provided. The ultrasonic transducer system includes: a transducer mounting structure; a transducer, including at least one mounting flange for coupling the transducer to the transducer mounting structure; and a tuned resonator having a desired resonant frequency, the tuned resonator being integrated with at least one of the transducer mounting structure and the at least one mounting flange. | 2018-08-23 |
20180240775 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a substrate, an electronic element mounted on the substrate, bumps that electrically connect the substrate to the electronic element, dummy bumps that are formed on the substrate to surround the electronic element, and a side fill that is formed around the electronic element and is in contact with the dummy bumps. | 2018-08-23 |
20180240776 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS - A method for manufacturing semiconductor chips ( | 2018-08-23 |
20180240777 | SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS - A semiconductor process includes: applying an encapsulation material on an upper surface of a first substrate to encapsulate a die and first conductive parts, wherein the encapsulation material is a B-stage adhesive; forming a plurality of openings on the encapsulation material to expose the first conductive parts; pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate includes second conductive parts, and each of the first conductive parts contacts a corresponding one of the second conductive parts; and heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and solidify the encapsulation material to form a C-stage adhesive. | 2018-08-23 |
20180240778 | EMBEDDED MULTI-DIE INTERCONNECT BRIDGE WITH IMPROVED POWER DELIVERY - Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include at least two integrated circuit dies that communicate using an embedded multi-die interconnect bridge (EMIB) in a substrate of the multi-chip package. The EMIB may receive power at contact pads formed at a back side of the EMIB that are coupled to a back side conductor on which the EMIB is mounted. The back side conductor may be separated into multiple regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal from a printed circuit board. These power supply voltage signals and data signals may be provided to the two integrated circuit dies through internal microvias or through-silicon vias formed in the EMIB. | 2018-08-23 |
20180240779 | ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF - An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness. | 2018-08-23 |
20180240780 | PACKAGE SUBSTRATE AND PACKAGE STRUCTURE USING THE SAME - A package substrate is provided. The package substrate includes a base layer having a first surface and a second surface opposite to the first surface, a plurality of through holes penetrating the base layer, a first metal layer disposed on the first surface, and comprising an encircling portion and a plurality of upper pads arranged separately, wherein the encircling portion surrounds the upper pads to form a trench between the encircling portion and the upper pads, and a second metal layer disposed on the second surface and comprising a plurality of bottom pads arranged separately, wherein the bottom pads are electrically connected to the upper pads via the through holes respectively. The through holes are positioned under the upper pads and the encircling portion of the first metal layer is electrically floating. | 2018-08-23 |
20180240781 | Three-Dimensional Package Structure and the Method to Fabricate Thereof - The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component. | 2018-08-23 |
20180240782 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUBSTRATE EXTENSIONS - Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform. | 2018-08-23 |
20180240783 | MICROSTRUCTURE MODULATION FOR METAL WAFER-WAFER BONDING - A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements. | 2018-08-23 |
20180240784 | SEMICONDUCTOR DEVICE - A semiconductor device includes multiple semiconductor chips and a control unit. Each of the semiconductor chips has multiple signal processing units that can be connected with each other, multiple in-chip signal lines that are respectively connected to the signal processing units and that can be connected with each other, and a connection-state changing unit that changes the connection state between the in-chip signal lines according to an instruction from the control unit. The connection-state changing unit of each semiconductor chip changes the connection state between the in-chip signal lines according to the instruction from the control unit, so that the connection state between the signal processing units is changed. | 2018-08-23 |
20180240785 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die. | 2018-08-23 |
20180240786 | SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES - A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly. | 2018-08-23 |
20180240787 | HALF-BRIDGE POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME - A half-bridge power semiconductor module has an insulating wiring substrate including a single insulating plate, and a positive electrode wiring conductor, a bridge wiring conductor, and a negative electrode wiring conductor disposed on or above the insulating plate while being electrically isolated from one another, at least one high side power semiconductor device having a rear surface electrode bonded onto the positive electrode wiring conductor, at least one low side power semiconductor device having a rear surface electrode bonded onto the bridge wiring conductor, a stand-up bridge terminal connected to the bridge wiring conductor, a stand-up high side terminal disposed between the high side power semiconductor device and the bridge terminal, and connected to the positive electrode wiring conductor, and a stand-up low side terminal disposed between the bridge terminal and the low side power semiconductor device, and connected to the negative electrode wiring conductor. | 2018-08-23 |
20180240788 | INORGANIC INTERPOSER FOR MULTI-CHIP PACKAGING - Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry. | 2018-08-23 |
20180240789 | STACKABLE ELECTRONIC PACKAGE AND METHOD OF FABRICATING SAME - An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween. | 2018-08-23 |
20180240790 | Method and Structure for Semiconductor Mid-End-Of-Line (MEOL) Process - A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers. | 2018-08-23 |
20180240791 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, a method of forming a HEM diode may comprise forming the HEM diode with high forward voltage that is greater than one of a gate-to-source threshold voltage of a HEMT or a forward voltage of a P-N diode. | 2018-08-23 |
20180240792 | SEMICONDUCTOR DEVICE - A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode. | 2018-08-23 |
20180240793 | LED CHIP HAVING ESD PROTECTION - Disclosed herein is a light emitting diode chip having ESD protection. An exemplary embodiment provides a flip-chip type light emitting diode chip, which includes a light emitting diode part aligned on a substrate, and a reverse-parallel diode part disposed on the substrate and connected to the light emitting diode part. Within the flip-chip type light emitting diode chip, the light emitting diode part is placed together with reverse-parallel diode part, thereby providing a light emitting diode chip exhibiting strong resistance to electrostatic discharge. | 2018-08-23 |
20180240794 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer. | 2018-08-23 |
20180240795 | SEMICONDUCTOR DEVICE - A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode electrode provided above the semiconductor substrate; a resistance layer provided above the semiconductor substrate and having a resistivity higher than the sense anode electrode; a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode comprises a first anode region of a p-type connected to the sense anode electrode via the resistance layer and a first cathode region of an n-type connected to the lower main electrode. | 2018-08-23 |
20180240796 | SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME - A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings. | 2018-08-23 |
20180240797 | STACKED BODY - A stacked body according to an embodiment of the present technology includes: a plurality of transistors; a first substrate; and a second substrate that is stacked with the first substrate and is electrically coupled to the first substrate, in which a first transistor to be driven at a first driving voltage being a lowest voltage of the plurality of transistors is provided only in the first substrate of the first substrate and the second substrate to form a first circuit. | 2018-08-23 |
20180240798 | SEMICONDUCTOR DEVICE WITH DUMMY PATTERN IN HIGH-VOLTAGE REGION AND METHOD OF FORMING THE SAME - A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height (h | 2018-08-23 |
20180240799 | HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE III-V SEMICONDUCTOR MATERIAL AND SILICON GERMANIUM SEMICONDUCTOR MATERIAL - An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing. | 2018-08-23 |
20180240800 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material. | 2018-08-23 |
20180240801 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof. | 2018-08-23 |
20180240802 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space. A conductive fill material is provided in the electrode space, and a dielectric layer electrically separates the conductive fill material into a first electrode electrically connected to the first contact of the first semiconductor device and a second electrode electrically connected to the second semiconductor device and electrically insulated from the first electrode. A first circuit terminal extends vertically from the top or bottom surface of the electrode structure and is electrically connected to the first electrode. | 2018-08-23 |
20180240803 | FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant. | 2018-08-23 |
20180240804 | FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. Further, the ferroelectric memory device includes a gate electrode layer disposed on the superlattice structure. | 2018-08-23 |
20180240805 | METHOD OF MANUFACTURING VERTICAL MEMORY DEVICES - A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs. | 2018-08-23 |
20180240806 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells. | 2018-08-23 |
20180240807 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film. | 2018-08-23 |
20180240808 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode. | 2018-08-23 |
20180240809 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device. | 2018-08-23 |
20180240810 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device includes a pillar member, a plurality of insulating layers arranged on an outer peripheral surface of the pillar member, an electrode film arranged between the insulating layers adjacent in a height direction, and a second block insulating film arranged between the electrode film and the pillar member and between the electrode film and the insulating layers. The pillar member includes a first block insulating film, a memory film, and a channel semiconductor layer in order from a side at its outer peripheral surface. The first block insulating film and the second block insulating film are made of an insulating material having a relative dielectric constant larger than that of silicon oxide. A distance between the memory film and the electrode film is a sum of a thickness of the first block insulating film and a thickness of the second block insulating film. The thickness of the second block insulating film is equal to or larger than the thickness of the first block insulating film, and is twice or less the thickness of the first block insulating film. | 2018-08-23 |
20180240811 | VERTICAL SEMICONDUCTOR MEMORY DEVICE STRUCTURES INCLUDING VERTICAL CHANNEL STRUCTURES AND VERTICAL DUMMY STRUCTURES - A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure. | 2018-08-23 |
20180240812 | 3D MEMORY DEVICE - A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region. | 2018-08-23 |
20180240813 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer. | 2018-08-23 |
20180240814 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells. | 2018-08-23 |
20180240815 | FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS - A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage. | 2018-08-23 |
20180240816 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device are provided. The array substrate includes: a base substrate; and first leads, third leads, and second leads connecting the first leads and the third leads on the base substrate. The base substrate includes a second region corresponding to a sealing material, a sealed first region, and a third region provided on a side of the second region away from the first region. The first region includes the first leads; the second region includes the second leads; and the third region includes the third leads. The area ratio of two adjacent third leads is greater than that of corresponding two adjacent first leads. | 2018-08-23 |
20180240817 | Liquid Crystal Display Device and Electronic Device - To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed. | 2018-08-23 |
20180240818 | METHOD FOR MANUFACTURING TFT SUBSTRATE AND STRUCTURE THEREOF - The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate arranges a connection electrode ( | 2018-08-23 |
20180240819 | Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same - A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate. | 2018-08-23 |
20180240820 | ELECTRO-OPTICAL AND OPTOELECTRONIC DEVICES - The present invention is notably directed to an electro-optical device. The latter comprises a layer structure with: a silicon substrate; a buried oxide layer over the silicon substrate; a tapered silicon waveguide core over the buried oxide layer, the silicon waveguide core cladded by a first cladding structure; a bonding layer over the first cladding structure; and a stack of III-V semiconductor gain materials on the bonding layer, the stack of III-V semiconductor gain materials cladded by a second cladding structure. The layer structure is configured to optically couple radiation between the stack of III-V semiconductor gain materials and the tapered silicon waveguide core. The first cladding structure comprises a material having: a refractive index that is larger than 1.54 for said radiation; and a bandgap, which, in energy units, is larger than an average energy of said radiation. | 2018-08-23 |
20180240821 | INTEGRATION OF SILICON THIN-FILM TRANSISTORS AND METAL-OXIDE THIN FILM TRANSISTORS - This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the active layers. In one or more embodiments, an apparatus is provided that comprises a first transistor comprising a silicon active layer, and a second transistor comprising a metal oxide active layer. The second transistor is vertically stacked on the first transistor, and the first transistor and the second transistor share a gate electrode formed between the silicon active layer and the metal oxide active layer. With these embodiments, the gate electrode corresponds to a top gate of the first transistor and a bottom gate of the second transistor. | 2018-08-23 |
20180240822 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a substrate, a patterned layer, a light-shielding layer, a first electrode, a second electrode, an electroluminescent layer (EL), a first insulating layer (FIL), and a color filter (CF). The patterned layer is disposed on the substrate, and includes: first body portions, and a first opening between the first body portions. The light-shielding layer is disposed on the patterned layer, and includes: second body portions, and a second opening between the second body portions. The first electrode is disposed on the substrate, the first and second openings overlap the first electrode. The second electrode overlaps the first electrode. The EL is disposed between the first and second electrodes. The FIL is disposed on the second electrode. The CF is disposed on the FIL. The EL is at least disposed in the first opening, and the FIL and the CF are at least disposed in the second opening. | 2018-08-23 |
20180240823 | SOLID-STATE IMAGING ELEMENT AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging element and an electronic apparatus, in which the number of wires controlling readout can be reduced in a case where a pixel signal of each pixel is read out in a predetermined order for each unit pixel region. The unit pixel region is configured by a plurality of pixels arranged in an array. A readout circuit is provided for each unit pixel region and reads out, in a predetermined order, pixel signals of the plurality of pixels configuring the unit pixel regions. Pixel drive wires, which control readout of the pixels configuring the unit pixel regions adjacent in the vertical direction and having the same readout order, are shared. The present disclosure can be applied to, for example, a CMOS image sensor and the like. | 2018-08-23 |
20180240824 | OPTOELECTRONIC MODULE WITH CUSTOMIZABLE SPACERS - The disclosure describes customizable optoelectronic modules and methods for standardizing a plurality of the customizable optoelectronic modules. The customizable optoelectronic modules can be configured to mitigate dimensional variations and misalignments in a number of their respective constituent components such as optical assemblies and sensor covers. The customizable optoelectronic modules and methods for standardizing a plurality of the customizable optoelectronic modules can obviate the need for binning during manufacturing thereby saving considerable resources such as time and expense. | 2018-08-23 |
20180240825 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE - The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality. | 2018-08-23 |
20180240826 | IMAGE SENSOR - An image sensor device includes a photoelectric conversion element configured to receive incident light and generate photocharges in response to the received incident light; a floating diffusion coupled to the photoelectric conversion element to store the photocharges generated by the photoelectric conversion element, the floating diffusion having a first capacitance value; a conductive pattern electrically coupled to the floating diffusion; and a variable electrode located apart from the conductive pattern by a gap, wherein the conductive pattern and the variable electrode form a variable capacitor coupled to the floating diffusion and having a second capacitance value and operable to change an effective capacitance of the floating diffusion in response to a control signal applied to the variable electrode. | 2018-08-23 |
20180240827 | PACKAGE STRUCTURE AND PACKAGING METHOD - A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate, where a first surface of the upper cover plate is provided with a support structure, the upper cover plate covers the first surface of the chip unit, the support structure is located between the upper cover plate and the chip unit, the sensing region is located in a cavity enclosed by the support structure and the first surface of the chip unit, and the upper cover plate has a preset thickness, so that light reflected by a sidewall of the upper cover plate is not directly incident on the sensing region. | 2018-08-23 |
20180240828 | MOLDED IMAGE SENSOR CHIP SCALE PACKAGES AND RELATED METHODS - Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer. | 2018-08-23 |
20180240829 | SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE - The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device capable of further improving quality. A flattening film is formed so as to fill a recessed portion of a semiconductor substrate having a pixel region in which a plurality of pixels is arranged in an array, a recessed region is formed in the flattening film by hollowing out a region corresponding to the pixel region, and a color filter layer is formed in the recessed region. In addition, an on-chip lens layer is formed on a plane including the flattening film and the color filter layer. The present technology is applicable, for example, to a CMOS image sensor. | 2018-08-23 |
20180240830 | Surface Treatment for BSI Image Sensors - A method comprises forming an image sensor adjacent to a first side of a substrate, thinning a second side of the substrate, performing a halogen treatment on the second side of the substrate and forming a backside illumination layer on the second side of the substrate. | 2018-08-23 |
20180240831 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2018-08-23 |
20180240832 | SOLID STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD, SEMICONDUCTOR WAFER, AND ELECTRONIC APPARATUS - The present technology relates to a solid state image pickup device and a production method, a semiconductor wafer, and an electronic apparatus by which the yield can be improved. | 2018-08-23 |
20180240833 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH IMPROVED CONTACT AREA - An image sensor includes a semiconductor material having a front side and a back side opposite the front side. The image sensor also includes a shallow trench isolation (STI) structure, an interlayer dielectric, an intermetal dielectric, and a contact area. The STI structure extends from the front side of the semiconductor material into the semiconductor material. The interlayer dielectric is disposed between the front side of the semiconductor material and the intermetal dielectric. The contact area is disposed proximate to a lateral edge of the semiconductor material. The contact area includes a metal interconnect disposed within the intermetal dielectric and a plurality of contact plugs at least partially disposed within the interlayer dielectric. The contact area also includes a contact pad. The plurality of contact plugs is coupled between the contact pad and the metal interconnect. | 2018-08-23 |
20180240834 | SOLID-STATE IMAGE-CAPTURING ELEMENT AND ELECTRONIC DEVICE - The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode. | 2018-08-23 |
20180240835 | IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a method of manufacturing an image sensor device. The method comprises forming a first semiconductor chip including a matrix of image sensing cells and bonding a second semiconductor chip with the first semiconductor chip. A plurality of conductive vias are formed in the second semiconductor chip, where each of the plurality of conductive vias includes a first end substantially coplanar with a first surface of the first semiconductor chip and a second end in contact with a conductive trace in the second semiconductor chip. A first dielectric layer is formed over the plurality of conductive vias and a first conductive material is formed over the first dielectric layer. The first conductive material is etched to form a plurality of conductors coupled to ground and the plurality of conductors are electrically isolated from one another. | 2018-08-23 |
20180240836 | SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT, AND ELECTRONIC APPARATUS - The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 μm) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 μm and 2 μm respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device. | 2018-08-23 |
20180240837 | IMAGE SENSOR AND SENSING PIXEL ARRAY FOR READING OUT CHARGE OF SENSING SIGNAL AND CHARGE OF RESET SIGNAL OF ONE SENSING PIXEL UNIT AFTER ANOTHER - A sensing pixel array used in an image sensor includes sensing pixel units each including a photodiode, a row reset transistor, a buffer transistor, and a column control transistor at least. Photodiode converts light into a sensing signal. Row reset transistor is coupled to a reference reset signal and photodiode, and is controlled by a row reset signal. Buffer transistor is coupled to the output of photodiode to receive and buffer the sensing signal. Column control transistor is electrically connected to the control end or the output of the buffer transistor and is used as a switch which can be closed or open according to a column control signal to control whether to transfer charge of the reference reset signal to a capacitor when the row reset transistor becomes conductive. | 2018-08-23 |
20180240838 | CMOS IMAGE SENSOR WITH DUAL DAMASCENE GRID DESIGN HAVING ABSORPTION ENHANCEMENT STRUCTURE - The present disclosure, in some embodiments, relates to a method of forming an image sensor integrated chip. The method may be performed by forming an image sensing element within a substrate, and forming an absorption enhancement structure over a back-side of the substrate. The absorption enhancement structure is selectively etched to concurrently define a plurality of grid structure openings and a ground structure opening within the absorption enhancement structure. A grid structure is formed within the plurality of grid structure openings and a ground structure is formed within the ground structure opening. The grid structure extends from over the absorption enhancement structure to a location within the absorption enhancement structure. | 2018-08-23 |
20180240839 | OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME - An optical device includes a substrate, a semiconductor chip, a resin member, and a transparent plate. The semiconductor chip is provided on the substrate, and an optically functional layer is formed in a part of a top portion of the semiconductor chip. The resin member is provided on the substrate with a top surface and an inner side surface, and has a frame shape surrounding the optically functional layer. The resin member is integrally formed from a resin material, and includes a recessed portion provided at the intersection of the top surface and the inner side surface. The transparent plate is disposed in the recessed portion. The semiconductor chip, the resin member, and the transparent plate are arranged to define airspace. | 2018-08-23 |
20180240840 | SOLID-STATE IMAGING APPARATUS, AND ELECTRONIC APPARATUS - The present technology relates to a solid-state imaging apparatus and an electronic apparatus that makes it possible to improve coloration and improve image quality. The solid-state imaging apparatus is formed so that, in a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, a first electrical barrier formed between a first photoelectric conversion unit and a first unnecessary electric charge drain unit in the first pixel, and a second electrical barrier formed between a second photoelectric conversion unit and a second unnecessary electric charge drain unit in the second pixel have different heights, respectively. The present technology can be applied to, for example, a CMOS image sensor. | 2018-08-23 |
20180240841 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device including a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer. | 2018-08-23 |
20180240842 | PHOTON COUNTING CONE-BEAM CT APPARATUS WITH MONOLITHIC CMOS INTEGRATED PIXEL DETECTORS - CBCT including monolithic photon counting FPD for medical applications requiring real-time 3D imaging, like mammography, interventional guided procedures or external beam radiotherapy, includes CMOS processed readout electronics monolithically integrated with a single crystalline X-ray absorber by covalent wafer bonding near room temperature and adapted for single photon counting providing high energy, temporal and spatial resolution. | 2018-08-23 |
20180240843 | PRINT SENSOR WITH GALLIUM NITRIDE LED - A papillary print sensor is provided, including a light emitting device configured to emit light radiation towards the sensor; and a matrix photodetector configured to be sensitive to at least part of an emission spectrum of the light emitting device, the light emitting device and the matrix photodetector being distributed together in and/or above a same semiconducting substrate, the light emitting device being composed of at least one gallium nitride light emitting diode (LED) with a series of through openings. | 2018-08-23 |
20180240844 | Selector Device Having Asymmetric Conductance for Memory Applications - The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same. | 2018-08-23 |
20180240845 | Magnetic Memory Cell Including Two-Terminal Selector Device - The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes a plurality of metal-rich particles or clusters embedded in a matrix or at least one conductor layer interleaved with insulating layers. | 2018-08-23 |
20180240846 | NEUROMORPHIC DEVICE INCLUDING A SYNAPSE HAVING CARBON NANO-TUBES - A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes. | 2018-08-23 |
20180240847 | IMAGING ELEMENT AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - The present technology relates to a back surface irradiation type imaging element having an organic photoelectric conversion film capable of preventing color mixing and securing dynamic range, a method of manufacturing the same, and an electronic apparatus. An imaging element according to an aspect of the present technology includes a photoelectric conversion film provided on one side of a semiconductor substrate, a pixel separation section formed in an inter-pixel region, and a through electrode that transmits a signal, corresponding to an electric charge obtained by photoelectric conversion in the photoelectric conversion film, to a wiring layer formed on the other side of the semiconductor substrate, the through electrode being formed in the inter-pixel region. The present technology is applicable to a back surface irradiation type CMOS image sensor. | 2018-08-23 |
20180240848 | X-RAY DETECTOR - Disclosed is a direct-conversion-type X-ray detector, including a first electrode on a substrate, a semiconductor structure including a photoconductor using a perovskite material on the first electrode, and a second electrode on the semiconductor structure. | 2018-08-23 |
20180240849 | METHOD OF MANUFACTURING DISPLAY PANEL - The present disclosure discloses a method of manufacturing a display panel. The method includes: providing a first substrate, and forming a release layer on the first substrate; forming a thin film transistor driving layer on the first substrate; forming a display element on the first substrate, wherein a part of the display element forms above the release layer and another part of the display element forms above the thin film transistor driving layer; separating the release layer and the first substrate with a laser; removing the release layer and the display element above the release layer, and forming a hollow portion on the first substrate; packaging the display element to form a display panel, wherein the display panel at least includes a first packaging portion; and providing a through hole passing through the display panel at a region on the display panel corresponding to the hollow portion. | 2018-08-23 |
20180240850 | ORGANIC ELECTROLUMINESCENT DISPLAY PANEL AND DISPLAY DEVICE - The disclosure discloses an organic electroluminescent display panel and a display device. The display panel includes at least one touch sensing element located in a rounded corner display area of the display panel. An outline of the at least one touch sensing element includes an arc. The arc lies against an outline of the rounded corner of the rounded corner display area. In this way, difference between the outline of the touch pattern of the display panel and the outline of the abnormally shaped display panel can be minimized to reduce the size of parts of touch sensing element(s) going beyond the rounded corner display area that need to be cut off and integrity of the pattern of the touch sensing element(s) can be improved, thus improving quality of response signals and the touch performance at the abnormally shaped edge. | 2018-08-23 |
20180240851 | SILICON-BASED OLED IMAGE TRANSCEIVING DEVICE AND MANUFACTURE METHOD THEREOF - A silicon-based OLED image transceiving device includes a substrate, multiple photodiodes for sensing light, and multiple OLEDs for emitting light. The OLED includes a metal interconnect anode, a hole transport layer, an organic light emitting layer, an electronic transport layer, and a transparent cathode layer. The hole transport layer, the organic light emitting layer, the electronic transport layer, and the transparent cathode layer are sequentially formed on the metal interconnect anode. The organic light emitting layer is only located on an area corresponding to the metal interconnect anode, and does not extend to an area corresponding to the photodiode. The multiple photodiodes and organic light emitting layers of the multiple OLEDs are arranged to form a pixel matrix of the image transceiving device. The silicon-based OLED image transceiving device has relatively high sensitivity of the photodiode. | 2018-08-23 |
20180240852 | FLEXIBLE DISPLAY SCREEN AND MANUFACTURING METHOD THEREFOR - A flexible display screen and a method for manufacturing a flexible display screen are provided. The flexible display screen includes a flexible substrate, a thin-film transistor layer, an organic electroluminescent layer, and a flexible cover plate. The thin-film transistor layer is stacked on the flexible substrate and includes a driving section and a packaging section arranged around the driving section, where the packaging section is provided with at least one elongated groove, and at least two long protrusions corresponding to the groove. Two adjacent protrusions are located on both sides of the length direction of the groove. The organic electroluminescent layer is accordingly disposed on the driving section, and the flexible cover plate is stacked on a side of the organic electroluminescent layer that departs from the driving section and covers the organic electroluminescent layer and the packaging section. | 2018-08-23 |
20180240853 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Disclosed is an organic light emitting display device including a dam structure disposed in a non-display area of a substrate and an alignment mark disposed outside the dam structure. The alignment mark is not covered by, and does not overlap with, the dam structure, because the alignment mark is disposed outside the dame structure. Thus, a scribing process may be performed smoothly. | 2018-08-23 |