34th week of 2012 patent applcation highlights part 26 |
Patent application number | Title | Published |
20120212983 | METHOD FOR CONVERTING POWER FOR A HIGH-VOLTAGE DIRECT VOLTAGE CONNECTION - A method for converting a multi-phase alternating voltage into a high-voltage direct voltage and then into a second multi-phase alternating voltage. The method utilizes first and second cascades of power converter cells, with each individual cell having respective first and second current valves. The method includes offsetting the clocking of individual power converter cells by a predetermined factor; cyclically switching off the first current valves in counterpoint with the second current valves, so that only one set of current valves are “on” at any given time while the other set of current valves is “off” at that time; and, in response to a signal indicating that an individual power cell is malfunctioning, shunting out the individual malfunctioning power cell. | 2012-08-23 |
20120212984 | POWER SUPPLY DEVICE - A power supply device that is able to switch between rectifier circuits in accordance with the voltage of a multi-phase AC power supply, and able to accommodate different power supply voltages. The power supply device has rectifier circuits that include a first circuit that rectifies a line voltage of the AC power supply, converting it into a direct current voltage of a first predetermined value, when the voltage of the AC power supply is a predetermined value or less, and a second circuit that rectifies a phase voltage of the AC power supply, converting it into a direct current voltage of a second predetermined value, when the voltage of the alternating current power supply exceeds the predetermined value. The first and second circuits operate in such a way that the AC input current is of the same phase as the voltage of the AC power supply. | 2012-08-23 |
20120212985 | POWER CONVERSION APPARATUS - According to one embodiment, an apparatus includes a controller which outputs a signal for controlling ON and OFF of a switch which changes over connection between a second input terminal and the output end of a coil. The controller includes an MPPT control unit which follows a maximum power point with a period based on a zero-cross detection signal of a system voltage based on an input signal acquired by subtracting a value obtained by multiplying a droop gain simulating drooping characteristics, a control unit which outputs a direction value in such a manner that a difference between a reference output from the MPPT control unit and the input signal becomes zero, and a PWM comparator which outputs a PWM signal based on the direction value and a triangular wave voltage. | 2012-08-23 |
20120212986 | SWITCHING POWER SUPPLY APPARATUS - A switching power supply apparatus includes: an input part; an input filter provided for a power factor correction circuit, which includes at least a line capacitor; a bridgeless power factor correction circuit that is connected to the input part; and an inrush current suppression circuit to suppress inrush current, wherein the bridgeless power factor correction circuit comprises: a conversion unit, which has a boost inductor unit and a switching circuit connected to the boost inductor unit; and a smoothing unit that is connected to an output terminal side of the conversion unit, and wherein the inrush current suppression circuit is arranged at least one of: a path connecting between an end of the input filter and the boost inductor unit; a path connecting between the boost inductor unit and the switching circuit; and a path connecting between the switching circuit and the smoothing unit. | 2012-08-23 |
20120212987 | POWER SUPPLY AND POWER CONTROL CIRCUITRY - A power supply can include a storage component or a storage unit including a capacitive element. In an embodiment, the power supply can include an electrical energy storage unit, a transformer, switching elements, and a pulse width modulation unit. In a particular embodiment, the power supply can be configured to provide an output voltage different from the voltage supplied by the electrical energy power storage unit. In another embodiment, the power supply can include storage components having electrodes connect to different printed circuit boards. In still another embodiment, the power supply can include an output anode, an output cathode, and an input electrode connected to the storage component. In a further embodiment, the power supply circuitry can include a transformer, switching elements, a pulse width modulation unit, and an output control units coupled to an output electrode, the pulse width modulation unit, or any combination thereof. | 2012-08-23 |
20120212988 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. | 2012-08-23 |
20120212989 | MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors. | 2012-08-23 |
20120212990 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip. | 2012-08-23 |
20120212991 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode. | 2012-08-23 |
20120212992 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer. | 2012-08-23 |
20120212993 | ONE TIME PROGRAMMING BIT CELL - A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor has a second drain, a second source, and a second gate. The first source is coupled to the second drain. The second source is configured to detect data stored in the OTP memory cell. | 2012-08-23 |
20120212994 | MEMORY APPARATUS - A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element. | 2012-08-23 |
20120212995 | PROGRAMMABLE LSI - A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off. | 2012-08-23 |
20120212996 | MEMORY DEVICE HAVING MEMORY CELLS WITH WRITE ASSIST FUNCTIONALITY - A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device. | 2012-08-23 |
20120212997 | TEST STRUCTURE FOR CHARACTERIZING MULTI-PORT STATIC RANDOM ACCESS MEMORY AND REGISTER FILE ARRAYS - A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit. | 2012-08-23 |
20120212998 | Non-Volatile Perpendicular Magnetic Memory with Low Switching Current and High Thermal Stability - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer. | 2012-08-23 |
20120212999 | Methods Of Forming Programmed Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material. | 2012-08-23 |
20120213000 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4 F | 2012-08-23 |
20120213001 | RELIABILITY METRICS MANAGEMENT FOR SOFT DECODING - Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector. | 2012-08-23 |
20120213002 | SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS - In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories. | 2012-08-23 |
20120213003 | NON-VOLATILE MEMORY DEVICE AND RELATED READ METHOD - A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation. | 2012-08-23 |
20120213004 | NON-VOLATILE MEMORY DEVICE AND RELATED READ METHOD - A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor. | 2012-08-23 |
20120213005 | NON-VOLATILE MEMORY DEVICE, MEMORY CONTROLLER, AND METHODS THEREOF - The method includes receiving a block address and an erase command output from a controller, and changing, until an erase operation performed according to the erase command on a block corresponding to the block address is completed, a parameter value related to the erase operation. The method further includes storing information corresponding to a finally changed parameter value, and transmitting the information to the controller according to a command output from the controller. | 2012-08-23 |
20120213006 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor, | 2012-08-23 |
20120213007 | CONTROLLING A NON-VOLATILE MEMORY - Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of memory cells. Moreover, the non-volatile memory includes a counter-doped-gate device, coupled within the integrated circuit substrate, in power-transmissive communication between the high-voltage node and the intermediate-voltage node. | 2012-08-23 |
20120213008 | NONVOLATILE MEMORY DEVICE AND PROGRAM VERIFY METHOD THEREOF - A program verify method of the nonvolatile memory device includes supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array, sensing a voltage of a bit line coupled to the memory cells in response to a first sense signal, supplying a second program verify voltage higher than the first program verify voltage to the word line, and sensing a voltage of the bit line in response to a second sense signal having a lower voltage level than the first sense signal. | 2012-08-23 |
20120213009 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities. | 2012-08-23 |
20120213010 | Asymmetric Sense Amplifier Design - A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance. | 2012-08-23 |
20120213011 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal. | 2012-08-23 |
20120213012 | STROBE APPARATUS, SYSTEMS, AND METHODS - A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed. | 2012-08-23 |
20120213013 | MEMORY BUILDING BLOCKS AND MEMORY DESIGN USING AUTOMATIC DESIGN TOOLS - The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis. | 2012-08-23 |
20120213014 | WRITE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage. | 2012-08-23 |
20120213015 | SENSE AMPLIFIER - A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor form cross coupled sensing pairs. The third PMOS and the fourth PMOS transistors serve as compensation transistors. The third NMOS and the fourth NMOS transistors serve as sensing enabling transistors. | 2012-08-23 |
20120213016 | SEMICONDUCTOR MEMORY DEVICE - At a succeeding stage of a sense amplifier, a first data latch is provided which has the same bit number as the page length and is controlled to invariably hold the same data as that of the sense amplifier. When a column address strobe (CAS) access begins, data is transferred from the first data latch to an error checking and correcting circuit, and error correction and parity generation are performed in a pipeline process. As a result, the CAS access time and the CAS cycle time are reduced. | 2012-08-23 |
20120213017 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 2012-08-23 |
20120213018 | DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period. | 2012-08-23 |
20120213019 | SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF - A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line. | 2012-08-23 |
20120213020 | MEMORY CONTROLLER - A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal. | 2012-08-23 |
20120213021 | SEMICONDUCTOR DEVICE HAVING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE - Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated. | 2012-08-23 |
20120213022 | SIP SEMICONDUCTOR SYSTEM - A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system. | 2012-08-23 |
20120213023 | SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING - Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability. | 2012-08-23 |
20120213024 | MEMORY DEVICE WITH DATA PREDICTION BASED ACCESS TIME ACCELERATION - A memory device includes a memory array comprising a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle. By way of example, the different supplemental charging and discharging paths may comprise an additional pull-up path configured to supplement operation of a pull-up path of the given memory cell and an additional pull-down path configured to supplement operation of a pull-down path of the given memory cell. | 2012-08-23 |
20120213025 | SEMICONDUCTOR MEMORY DEVICE FOR MINIMIZING MISMATCH OF SENSE AMPLIFIER - A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized. | 2012-08-23 |
20120213026 | MEMORY DEVICE AND METHOD FOR SENSING A CONTENT OF A MEMORY CELL - A memory device and a method for sensing a content of a memory cell. The memory device includes: a pair of bit-lines; a memory cell coupled between the pair of bit-lines; a sensing circuit having at least two inputs for receiving respective currents from a current conveyor, said sensing circuit being arranged to sense, when operating in a sensing mode, a difference between said output currents, said difference between the output currents representing a content of the memory cell; and said sensing circuit comprising an output for outputting an output signal that represents the content of the memory cell; and a current conveyor, coupled to the pair of bit-lines and to the sensing circuit, for: isolating the sensing circuit from the bit-lines, when the current conveyor operated in an isolation mode; said current conveyor having at least two outputs for providing, to the sensing circuit when the sensing circuit operated in the sensing mode, output currents representing bit-lines currents; and equalizing the output currents before the current conveyor starts to operate in a current conveying mode. The sensing circuit enters the sensing mode after the current conveyor exits the current conveying mode. | 2012-08-23 |
20120213027 | METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY - A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's. | 2012-08-23 |
20120213028 | MEMORY CELL AND MEMORY ARRAY UTILIZING THE MEMORY CELL - A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel with the select line. The second switch device has: a first terminal, coupled to the second terminal of the first switch device; a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line. The capacitor has a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line. | 2012-08-23 |
20120213029 | APPARATUS AND METHOD FOR MIXING OF A MATERIAL TO BE MIXED - The invention relates to a device ( | 2012-08-23 |
20120213030 | MIXER FOR USE IN A MICROWAVE OVEN - A microwave oven food mixer comprises a body including a drive mechanism and a plurality of adjustable arms extending outwardly from the body. The body and arms are configured so that the body may engage the lip of a culinary vessel disposed on a turntable of a microwave oven, with the arms extended to engage walls of the oven. A mixing arrangement extends downwardly from the body and is arranged to be located in said vessel during use. The mixing arrangement includes a fixed stirrer and a rotatable stirrer. The fixed stirrer is secured to the body and arranged to pass adjacent an inner wall of the vessel. The rotatable stirrer is connected to the drive mechanism and arranged so that rotation of the vessel on the turntable with the arms engaging walls of the oven causes rotation of the rotatable stirrer. | 2012-08-23 |
20120213031 | NETWORKED SONAR OBSERVATION OF SELECTED SEABED ENVIRONMENTS - A sonar transducer network for observing a seabed includes a controller. A first transducer assembly includes a first acoustic transducer to convert a first ping to a first electrical signal; and a first transducer processor to receive a first electrical signal from the first acoustic transducer to generate the first transducer data. At least one second transducer assembly is spaced apart from the first transducer assembly. The second transducer assembly includes a second acoustic transducer to convert a second ping to a second electrical signal. The second transducer processor receives the second electrical signal from the second acoustical transducer to generate second transducer data. A network bus communicates first transducer data and second transducer data with the controller. | 2012-08-23 |
20120213032 | METHOD FOR PZ SUMMATION OF 3-DIMENSIONAL WIDE AZIMUTH RECEIVER GATHERS AND DEVICE - Apparatus, computer instructions and method for de-pegging seismic data related to a subsurface of a body of water. The method includes receiving as input recorded seismic data (H, G), wherein the recorded seismic data is recorded with a receiver having at least three components; extracting a three-dimensional (3D) gather from the recorded seismic data (H, G); separating up-going and down-going components (U, D) from the 3D gather using a 3D calibration operator (G | 2012-08-23 |
20120213033 | METHOD AND APPARATUS FOR DEGHOSTING SEISMIC DATA - Apparatus, computer instructions and method for deghosting seismic data related to a subsurface of a body of water. The method includes inputting data recorded by detectors that are towed by a vessel, the data being associated with waves travelling from the subsurface to the detectors; applying a migration procedure to the data to determine a first image of the subsurface; applying a mirror migration procedure to the data to determine a second image of the subsurface; joint deconvoluting the first image and the second image for deghosting a reflectivity of the subsurface; and generating a final image of the subsurface based on the deghosted reflectivity of the joint deconvoluting step. | 2012-08-23 |
20120213034 | APPARATUS, SYSTEM AND METHOD FOR UNDERWATER SIGNALING OF AUDIO MESSAGES TO A DIVER - Embodiments of the invention provide a system, apparatus and methods for underwater voice communication between a diver and an underwater electronic device. In many embodiments, the system includes a dive computer which generates audio signals corresponding to spoken messages and a mouthpiece apparatus having an acoustic transducer that conducts sound via conduction through the diver's teeth and skull to the cochlea so as to allow the diver to hear the messages and other sounds and a microphone for sensing the diver's voice. The mouthpiece is adapted to be easily attached to portions of a SCUBA or other underwater breathing apparatus. It may also be attached or integral to a snorkel or similar apparatus. | 2012-08-23 |
20120213035 | BOARD FOR SYNTHETIC APERTURE BEAMFORMING APPARTUS - The present invention relates to a board for a synthetic aperture ultrasound imaging apparatus which includes an analog to digital converter converting M analog channel data into M digital channel data; a partial beamformer unit including N partial beamformers generating N partial beams from the M digital channel data; and an adder adding a partial beam stored in a k-th synthetic aperture memory among a plurality of synthetic aperture memories and a partial beam outputted from a k+1-th partial beamformer to input the added partial beam to a k+1-th synthetic aperture memory. The present invention can facilitate an increase in the number of channels by adding a board without transmitting a lot of channel data between boards by exchanging and synthesizing a part of the scanline data between the boards at rear ends of the boards. | 2012-08-23 |
20120213036 | Electroacoustic Transducer, in Particular Transmitting Transducer - An electroacoustic transducer, in particular a transmitting transducer for sonar systems, is disclosed, comprising two end caps that are arranged at a fixed distance from each other, multiple bars which are braced between the two end caps and the ends of which are attached to the end caps next to each other in the peripheral direction, and an elastic shell that externally encloses the bars. In order to significantly reduce the weight of the transducer and simplify production, composite modules are attached to the bars so as to excite vibrations. Each composite module has electrode structures that include spaced-apart electrodes and are arranged on at least two film layers made of insulating material, and spaced-apart piezoceramic fibers which are arranged between the film layers and are contacted by the electrodes on opposite longitudinal sides. | 2012-08-23 |
20120213037 | PROGRAM WHEEL OF A CALENDAR MECHANISM - Calendar mechanism comprising a program wheel device | 2012-08-23 |
20120213038 | CALENDAR MECHANISM - Calendar mechanism comprising a day program wheel | 2012-08-23 |
20120213039 | ANTENNA DEVICE AND ELECTRONIC TIMEPIECE - An antenna device which is provided in an electronic timepiece, and receives positioning signals from satellites includes: a first electrode; a second electrode; and a dielectric layer arranged between the first electrode and the second electrode, wherein one electrode of the first electrode and the second electrode constitutes at least a part of a character plate of the electronic timepiece. | 2012-08-23 |
20120213040 | ELECTRONIC TIMEPIECE - An electronic timepiece includes: a timekeeping section which counts time; a time display section which displays time; an illuminating section which performs illumination; a wireless communication section which performs wireless communication by transmitting/receiving a wireless signal intermittently; and a drive control section which performs duty drive of the illuminating section when a period in which wireless communication is conducted by the wireless communication section and a period in which the illuminating section is driven overlap with each other. | 2012-08-23 |
20120213041 | HEAT-ASSISTED MAGNETIC WRITE HEAD, HEAD GIMBALS ASSEMBLY, HEAD ARM ASSEMBLY, AND MAGNETIC DISK DEVICE - A heat-assisted magnetic write head includes: a magnetic pole having an end surface exposed to an air bearing surface; a waveguide extending toward the air bearing surface to propagate light; a plasmon generator provided between the magnetic pole and the waveguide and generating near-field light from the air bearing surface, based on the light propagated through the waveguide; and a clad provided to surround both the waveguide and the plasmon generator collectively, the clad having a refractive index lower than that of the waveguide, and exhibiting a thermal conductivity higher than that of the waveguide. The clad may be provided to collectively surround the magnetic pole, as well. | 2012-08-23 |
20120213042 | HEAT-ASSISTED MAGNETIC WRITE HEAD, HEAD GIMBALS ASSEMBLY, HEAD ARM ASSEMBLY, AND MAGNETIC DISK DEVICE - A heat-assisted magnetic write head includes a magnetic pole having an end surface exposed at an air bearing surface, a waveguide extending toward the air bearing surface to propagate light, and a plasmon generator provided between the magnetic pole and the waveguide, and generating near-field light from the air bearing surface, based on the light propagated through the waveguide. The plasmon generator has an end portion exposed at the air bearing surface or located in close proximity to the air bearing surface, the end portion having a minimum thickness in a region close to the waveguide. | 2012-08-23 |
20120213043 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An acquisition section acquires image data having a plurality of frames. Table information is written into a store when the image data is acquired. The table information includes first position information representing absolute position information of each of the plurality of frames and second position information representing relative position information when a head frame of the image data is set as a reference. A specification section specifics the second position information of a frame corresponding to a frame reproduction instruction using the first position information. A reproduction section reproduces the reproduction frame corresponding to the specified second position information. Writing of the table information into the table store is restricted when there is an instruction to reproduce the frame. | 2012-08-23 |
20120213044 | MANUFACTURING METHOD FOR OPTICAL RECORDING MEDIUM, OPTICAL RECORDING MEDIUM, OPTICAL INFORMATION DEVICE, AND INFORMATION REPRODUCING METHOD - Shape-wise thicknesses of a cover layer and first through (N−1)th intermediate layers of an optical recording medium having refractive indexes nr | 2012-08-23 |
20120213045 | MANUFACTURING METHOD FOR OPTICAL RECORDING MEDIUM, OPTICAL RECORDING MEDIUM, OPTICAL INFORMATION DEVICE, AND INFORMATION REPRODUCING METHOD - Shape-wise thicknesses of a cover layer and first through (N−1)th intermediate layers of an optical recording medium having refractive indexes nr | 2012-08-23 |
20120213046 | OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS - In an optical pickup device for a simple optical system, a light beam emitted from a laser diode is split into first and second light beams by a polarized beam splitter, an optical disc is irradiated with the first light beam to obtain signal light, and the second beam is reflected by a reflection element to obtain reference light. Light beams of the signal light and the reference light are synthesized into one light beam, the synthesized light beam is separated into four light beams by a phase difference forming unit including a grating, a divided wave plate and a polarization grating, and different phase differences are afforded to the signal light and the reference light in each light beam. The four light beams are detected by one detector to generate the reproduction signal. | 2012-08-23 |
20120213047 | METHOD AND APPARATUS FOR MOUNTING A DISC - Aspects of the disclosure provide a method for mounting a storage disc. The method includes receiving data stored at a location on the storage disc. The location on the storage disc used for providing a structure of the storage disc as a result of a previous recording on the storage disc. Then, the method includes determining a medium type based on a parameter in the structure that is indicative of the medium type. | 2012-08-23 |
20120213048 | METHOD AND APPARATUS FOR DETECTING LAND PRE-PITS - Aspects of the disclosure provide a method for detecting land pre-pits. The method includes detecting, based on a land pre-pit threshold, a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium, comparing a characteristic of the detected land pre-pit data stream in a specific number of wobble periods with a pre-determined land pre-pit characteristic in the specific number of wobble periods, and adjusting the land pre-pit threshold based on the comparison. | 2012-08-23 |
20120213049 | READ SIGNAL EVALUATION METHOD, INFORMATION RECORDING AND READING METHOD, AND INFORMATION RECORDING AND READING APPARATUS - A read signal evaluating means for ensuring compatibility in an optical phase multilevel recording and reading system is provided. In addition, a decoding means not large in circuit scale is provided. An optical phase is modulated based on user data, and phase information thus obtained is recorded in a recording medium. Then, the phase information recorded in the recording medium is optically read, and is converted into an electric signal. The signal is subjected to adaptive equalization and to partial response most-likely decoding. A shift in a time axis direction from a target wave of a predetermined pattern is detected from the read phase information and a statistical average is calculated. Meanwhile, a value of the phase read from the predetermined pattern is extracted from the read phase information and a statistical average is calculated. | 2012-08-23 |
20120213050 | OPTICAL DISC DRIVE DEVICE AND INTERCONNECTION STRUCTURE - Disclosed is an optical disc drive device having a metallic exterior casing and an internal unit to be housed in the exterior casing, the internal unit further including an optical pickup unit for performing recording or reproduction of information signals on an optical disc, and a printed wiring substrate on which a connector electrically connected to the optical pickup unit and serving for transmission and reception of electrical signals from and to external electronic equipment is mounted, wherein the exterior casing has an opening for allowing the connector to be exposed outside, the printed wiring substrate has a ground pattern formed to surround the connector, and a fringe portion of the opening of the exterior casing and the ground pattern are in electrical contact with each other. Thus, radiation noise from around wiring lines contained in the optical disc drive device or the like is reduced. | 2012-08-23 |
20120213051 | OPTICAL PICKUP HEAD - An optical pickup head is provided, which includes a silicon substrate, in which an aperture and an objective lens are disposed on the silicon substrate; and a laser diode (LD), a 135-degree tilted reflector, and a 135-degree tilted holographic reflector are disposed on the silicon substrate. The two 135-degree tilted reflectors and a holographic optical element (HOE) are fabricated on a slant face structure of an optical platform using a semiconductor process, so all the elements are disposed at a straight zone, and then in combination with bonding of the LD and an optical sensor element, an miniaturization objective is achieved and an optical path is shortened. | 2012-08-23 |
20120213052 | OPTICAL HEAD, OPTICAL DISC DEVICE, INFORMATION PROCESSING DEVICE, AND OBJECTIVE LENS - Provided are an optical head capable of favorably recording or reproducing information to or from an information recording medium including a plurality of information recording surfaces, an optical disc device including the optical head, an information processing device including the optical disc, and an objective lens. The optical head ( | 2012-08-23 |
20120213053 | SINGLE-SIDED PRINTING PROVIDING DUAL-SIDED READING OF PRINT ON OPTICAL DISCS - Disclosed is an optical disc with a first area to store data for playback and that is reflective or opaque to visible light, and a second area that is transparent to visible light and includes first and second concentric rings. In one embodiment, a method of printing information on the optical disc includes: printing an inverse first text pattern in the first ring during a first printing on a first side, where the first text pattern is formed in reverse as viewed from the first side; printing a second text pattern in the second ring during a second printing on the first side, where the second text pattern is correctly visible from the first side; and printing, during the second printing, a first solid pattern to overlay at least a portion of the first text pattern, where the first text pattern is correctly visible as viewed from a second side. | 2012-08-23 |
20120213054 | RADIO COMMUNICATION METHOD, RADIO COMMUNICATION SYSTEM, AND RADIO TRANSMISSION APPARATUS - A transmission apparatus according to the present invention includes: an encoding section; a modulation section; a variable-SF spreading section that performs spreading with variable SF according to control information A from a control section; an IDFT section that performs IDFT on output from the spreading section; a GI inserting section; a parallel/serial conversion section that converts output from the GI inserting section into a serial data sequence; a digital/analog conversion section; and an RF section that transmits a signal from an antenna after converting the signal to a frequency band for analog signal transmission and controlling it to an appropriate transmission power. The control section is configured to generate control information A for determining the variable SF and input the information A to the variable-SF spreading section and the RF section. In control information A, SF is varied depending on transmission power required. | 2012-08-23 |
20120213055 | METHOD AND NODE FOR TRANSMITTING DATA OVER A COMMUNICATION NETWORK USING NEGATIVE ACKNOWLEDGMENT - A method of transmitting data over a communication network using negative acknowledgment is presented. In the method, a stream of data packets is transmitted from a first node of the network to a second node of the network. All but at least two of the stream of data packets is successfully received at the second node, wherein the data packets that are not successfully received are not located sequentially within the stream of data packets. A status packet is transmitted from the second node to the first node, wherein the status packet includes an indication of each of the data packets that were not successfully received. In response to receiving the status packet at the first node, the data packets that were not successfully received at the second node are retransmitted from the first node to the second node in response to receiving the status packet. | 2012-08-23 |
20120213056 | METHOD AND SYSTEM FOR A TRANSMITTING ANTENNA SELECTION FAILURE RECOVERY MODE - Aspects of a method and system for a transmitting antenna selection failure recover mode are presented. Aspects of the system may include a transmitting mobile terminal that enables selection of a sequence of protocol data units (PDU), for example a sequence of sounding frames, which may be transmitted during an antenna selection procedure. During transmission of the selected PDU sequence, the transmitting mobile terminal may receive an antenna selection failure indication frame. The transmitting mobile terminal may enable retransmission of at least one previously transmitted PDU in the PDU sequence based on the failure indication. Transmission of subsequent PDUs in the PDU sequence may resume after the retransmission. Alternatively, upon receipt of the failure indication frame the transmitting mobile terminal may restart the selected frame sequence from the beginning, or may select a subsequent PDU frame sequence. | 2012-08-23 |
20120213057 | Coordination Processing Method and Device for Self Organizing Operation and Communication System - A coordination processing method for a self organizing operation includes obtaining a preset coordination relationship between a first self organizing operation and a second self organizing operation before performing the first self organizing operation. If the second self organizing operation exists, the first self organizing operation and the second self organizing operation are performed according to the coordination relationship. If the second self organizing operation does not exist, performing the first self organizing operation is performed. | 2012-08-23 |
20120213058 | APPARATUS AND METHOD FOR FACILITATING FALLBACK ACCESS SCHEMES - Systems and methodologies are described that facilitate random access procedures using one or more fallback access schemes after initial access attempts have failed. UE equipped to determine failure of a first access request to a first base station due to interference from a second base station. Further, a UE equipped to determine the failure can do so and implement one or more fallback access schemes in response to the determination. In one example, a fallback access scheme allows the UE to select a secondary carrier frequency for communications with the first base station. In another example, a fallback access scheme allows the UE to designate the first base station as inaccessible and communicate with other base stations. | 2012-08-23 |
20120213059 | RELIABLE AND RESILIENT END-TO-END CONNECTIVITY FOR HETEROGENEOUS NETWORKS - Embodiments of the present invention address deficiencies of the art in respect to connectivity management in a heterogeneous network and provide a method, system and computer program product for resilient and reliable end-to-end connectivity in a heterogeneous network. In one embodiment of the invention, a method for resilient and reliable end-to-end connectivity in a heterogeneous network environment can be provided. The method can include creating an instance of an abstracted network resource model (NRM) for a heterogeneous network environment of different network resource nodes. The method further can include binding an application endpoint in the instance of the abstracted NRM with a connectivity endpoint for a first of the different network resource nodes. Finally, the method can include re-binding the application endpoint to a second of the different network resource nodes in response to detecting the outage. | 2012-08-23 |
20120213060 | SYSTEMS AND METHODS FOR SEAMLESS COMMUNICATIONS RECOVERY AND BACKUP - A recovery network may provide communication recovery and backup services to a carrier having a service area. The recovery network may be configured to communicatively couple the carrier to the public communication network (PCN) using one or more alternative communication paths, such as a satellite network. The alternative communication paths may couple the recovery network to the carrier independently of the PCN. When the carrier detects a failure in its uplink to the PCN, it may failover to the recovery network, which may service the communication requests using the alternative communication path(s). Similarly, the recovery network may be used to service inbound communication requests directed to the carrier or other organization, such as a Public Safety Answering Point (PSAP). When used with a PSAP, the recovery network may be configured to access and/or provide metadata related to inbound communication requests. | 2012-08-23 |
20120213061 | COGNITIVE RELAY TECHNIQUES - The subject specification comprises a cognitive relay communications management (CRCM) component associated with a primary communication system, wherein the CRCM component controls relaying at least a portion of transmitted communications from a secondary source device (SSD) transmitting data to a secondary destination device (SDD) associated with a secondary communication system, in accordance with a specified relay protocol, such as a buffered decode-and-forward protocol. The CRCM component identifies when the secondary relay station (SRS) is not transmitting on the relay-destination (R-D) link and the source-relay link is not blocked, and, in such instance, allows transmission of a packet from the SSD to the SRS. The SRS forwards the packet to the SDD when the CRCM component identifies when the R-D link is not blocked. The SRS and/or SSD remove the packet from their respective queues when an acknowledgement message(s) is received from the SDD and/or SRS, respectively. | 2012-08-23 |
20120213062 | METHOD OF TWO-STAGE ADAPTIVE FREQUENCY HOPPING FOR CLUSTERED WIRELESS SENSOR NETWORK - A method of two-stage adaptive frequency hopping for a clustered wireless sensor network, including: a) building a clustered wireless sensor network; b) defining a superframe structure based on IEEE 802.15.4 according to a topology of the clustered wireless sensor network; c) extending a beacon frame payload based on a beacon frame format of an IEEE 802.15.4 Media Access Control (MAC) layer; and d) performing a two-stage adaptive frequency hopping mechanism on nodes based on the above superframe structure and the extended beacon frame of the IEEE 802.15.4 MAC layer. | 2012-08-23 |
20120213063 | Disjoint Path Computation Algorithm - A network element implementing Multiprotocol Label Switching to automatically create an optimal deterministic back-up Label Switch Path (LSP) that is maximally disjointed from a primary LSP to provide a reliable back up to the primary LSP. The network element receives a request for a generation of an LSP, determines that the request for the generation of the LSP is for the back-up LSP, locates each link of the primary LSP in a traffic engineering database, modifies each link of the primary LSP to have a link cost significantly greater than an actual link cost to discourage use of each link of the primary LSP in the back-up LSP, executes a Constrained Shortest Path First algorithm to obtain the back-up LSP, wherein the back-up LSP has a maximum disjointedness from the primary LSP due to a modified cost of each link of the primary LSP, and returns the back-up LSP. | 2012-08-23 |
20120213064 | MONITORING RESOURCE CONGESTION IN A NETWORK PROCESSOR - Embodiments of the invention are directed to monitoring resources of a network processor to detect a condition of exhaustion in one or more of the resources over a predetermined time interval and to provide an indication of the condition. Some embodiments periodically sample various resources of a network processor and from the samples calculate utilization of the network processor's memory bus and core processor, and determine if an interworking FIFO packet queue error has occurred. Such information may help network operators and/or support engineers to quickly zero in on the root cause and take corrective actions for network failures which previously could have been attributed to many different causes and that would have required significant time and effort to troubleshoot. | 2012-08-23 |
20120213065 | MEDIA ACCESS CONTROL APPARATUS AND METHOD FOR GUARANTEEING QUALITY OF SERVICE IN WIRELESS LAN - A media access control (MAC) apparatus and corresponding methods for guaranteeing quality-of-service in a wireless local area network (LAN) are presented. The MAC method includes extracting, performing, determining, a first transmitting step, and a second transmitting step. The extracting includes extracting a user priority from a frame received from an upper layer and separately storing a voice frame and a non-voice frame according to an access category (AC). The performing includes independently performing backoff operations for the voice frame and the non-voice frame. The determining includes determining whether the backoff operations for the voice frame and the non-voice frame have simultaneously ended. The first transmitting includes transmitting the voice frame having a higher priority first and performing the backoff operation for the non-voice frame if the backoff operations have simultaneously ended. The second transmitting includes transmitting a frame whose backoff operation ends if the backoff operations have not simultaneously ended. | 2012-08-23 |
20120213066 | Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes - Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights. | 2012-08-23 |
20120213067 | RF-AWARE PACKET FILTERING IN RADIO ACCESS NETWORKS - Methods and systems are provided for filtering packets in a wireless communication system in the to-subscriber direction. This filtering is at least in part based on RF circuit state information. For example, a packet filter is used that either permits or denies packets from reaching a mobile subscriber based on whether there is already an established RF circuit to provide packets to the mobile subscriber. Alternatively, or in addition, the packet filter may consider the history of circuit state transitions associated with a particular mobile subscriber, the percentage (or aggregate number) of available airlink resources that are currently in use, and/or the length of time associated with the dormancy of a mobile subscriber's RF connection. In various embodiments, the packet filter may cause one or more packets to be sent to a mobile subscriber using a special data channel that does not require the establishment of an RF circuit. | 2012-08-23 |
20120213068 | METHODS OF DATA TRAFFIC SHAPING, APPARATUS AND WIRELESS DEVICE - Methods of data traffic shaping, an apparatus and a wireless device are provided. A method of data traffic shaping comprises receiving data packets, the data packets to be forwarded; storing at least one of the data packets in a buffer memory if the buffer memory has an available space for accommodating the at least one of the data packets; and discarding at least one other of the data packets if the buffer memory does not have an available space for accommodating the at least one other of the data packets. An apparatus is configured to carry out the method. A wireless device may include the apparatus. | 2012-08-23 |
20120213069 | TRANSMISSION CONTROL METHOD, TRANSMISSION CONTROL SYSTEM, COMMUNICATION DEVICE AND RECORDING MEDIUM OF TRANSMISSION CONTROL PROGRAM - A transmission control method includes performing communication between a transmission source communication device and a transmission destination communication device by using a transmission control protocol which includes a plurality of congestion control functions corresponding to a plurality of congestion control methods, respectively, and causing, when the transmission source communication device and the transmission destination communication device switch from a first congestion control function to a second congestion control function, at least one of a plurality of parameters for controlling operating states in the first congestion control function to be inherited by a parameter for controlling an operating state in the second congestion control function. | 2012-08-23 |
20120213070 | DYNAMIC SETTING OF OPTIMAL BUFFER SIZES IN IP NETWORKS - A communications system provides a dynamic setting of optimal buffer sizes in IP networks. A method for dynamically adjusting buffer capacities of a router may include steps of monitoring a number of incoming packets to the router, determining a packet arrival rate, and determining the buffer capacities based at least partially on the packet arrival rate. Router buffers are controlled to exhibit the determined buffer capacities, e.g. during writing packets into and reading packets from each of the buffers as part of a packet routing performed by the router. In the disclosed examples, buffer size may be based on the mean arrival rate and one or more of mean packet size and mean waiting time. | 2012-08-23 |
20120213071 | Method and Apparatus for Channel Traffic Congestion Avoidance in a Mobile Communication System - An apparatus, comprising at least one processor configured to receive and read a series of blocks on a first channel and determine whether there is congestion and if not transmitting a channel request on a second channel. | 2012-08-23 |
20120213072 | DATA RATE AWARE SCHEDULING IN ADVANCED WIRELESS NETWORKS - A base station for an Internet protocol (IP) wireless access network receives an initial attach request from a user device. Based on the initial attach request, a policy and charging rules function (PCRF) device provides to the base station, a subscriber bearer policy that includes a particular quality-of-service control indicator (QCI) value, an uplink data rate limit, and a downlink data rate limit. The base station calculates an uplink bandwidth allocation, based on the QCI value and the uplink data rate limit, that is proportionate to the total maximum data rate of all uplink traffic with the same QCI value. The base station also calculates a downlink bandwidth allocation, based on the QCI value and the downlink data rate limit, that is proportionate to the total maximum data rate of all downlink traffic with the same QCI value. | 2012-08-23 |
20120213073 | SYSTEMS, METHODS, AND COMPUTER READABLE MEDIA FOR MAINTAINING PACKET DATA PROTOCOL (PDP) CONTEXT WHILE PERFORMING DATA OFFLOAD - Systems, methods, and computer readable media for maintaining packet data protocol (PDP) context while performing data offload are disclosed. According to one aspect, a method for maintaining PDP context while performing data offload includes detecting a data offload condition wherein a UE for which a first network node is maintaining a PDP context is sending or receiving data using a data path that does not include the first network node. While the data offload condition exists, packets are sent from a source other than the UE to the first network node so as to cause the first network node to maintain the PDP context for the UE. In one embodiment, a node interposed between the UE and the first network node periodically sends dummy packets or heart beat packets to the first network node on behalf of the UE, which may include packets that appear to come from the UE. | 2012-08-23 |
20120213074 | SYSTEM AND METHOD FOR FLOW TABLE MANAGEMENT - Methods and systems for managing the actions that are applied to packet flows by packet processing systems. A packet processing system maintains a flow table, i.e., a list of active flows and respective actions to be applied to the flows. The system classifies each incoming packet into a respective flow, and processes the packet in accordance with the action that is specified for this flow in the flow table. Typically, the system deletes a packet flow from the flow table when it becomes inactive, e.g., when no packets belonging to the flow arrive within a certain time-out period. | 2012-08-23 |
20120213075 | PACKET TRANSFER DEVICE AND POWER SUPPLY CONTROL METHOD FOR QOS CONTROL CIRCUIT - It is intended to reduce a power consumption without degrading a communication quality of a packet transfer device. One or more of a receiver, a switch unit, and a transmitter include a QoS control circuit for applying QoS control to received packets. There is provided a power saving operation mode that enables power saving operation by changing a grain size of the QoS control according to a flow rate of the packets, and controlling whether or not to supply an electric power to the QoS control circuit or a part of the QoS control circuit, according to the flow rate of the packets. | 2012-08-23 |
20120213076 | CELL PROCESSING METHOD, SOURCE LINE CARD, AND NETWORK CARD IN SWITCHING NETWORK - The present invention provides a source line card. The source line card segments a data packet in a data stream into cells first, then inserts Time Stamps and Flow Identifications into cell headers, and sends the marked cell headers and cell payloads to the network card. The network card sends the cells to a destination line card or a lower-level network card in sequence according to the Time Stamps and the Flow Identifications, where the Time Stamps and the Flow Identifications are in the cell headers of the received cells. By inserting the Time Stamps and the Flow Identifications into the cell headers, it is ensured that an output sequence and an input sequence of cells that belong to a stream in the switching network are the same, so that the destination line card may reassembles a data packet easily according to a sequence in which the cells are received. | 2012-08-23 |
20120213077 | NETWORK BANDWIDTH DETECTION AND DISTRIBUTION - Prioritizing network traffic among two or more distinct channels of communication within a single application in a node configured to communicate with one or more other nodes over a network is disclosed. For a particular time quantum, a bandwidth quantum may be distributed amongst two or more communication channels according to priorities associated with those channels. Ready data for each channel may be transmitted over a network path up to the size of the reserved portion for that channel and not greater than a path maximum transmission unit (MTU) size for a network path. This abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2012-08-23 |
20120213078 | APPARATUS FOR PERFORMING PACKET-SHAPING ON A PACKET FLOW - A first apparatus receives, at a first transmission rate, packets belonging to a target packet flow on which packet-shaping processing for controlling network traffic is to be performed, and stores the received packets in a first packet buffer. Then, the first apparatus performs first packet-shaping processing on the target packet flow by transmitting, at a second transmission rate, packets that belong to the target packet flow and read out from the first packet buffer. A second apparatus stores packets received from the first apparatus in a second packet buffer. When a shortage of buffer resource for storing packets belonging to the target packet flow occurs in the first packet buffer, the second apparatus performs second packet-shaping processing on the target packet flow by transmitting, at a third transmission rate, packets that belong to the target packet flow and are read out from the second packet buffer. | 2012-08-23 |
20120213079 | TRAP-FREE SHORTEST LINK-DISJOINT PATHS - A method including receiving information corresponding to a network graph of a network; determining a maximum flow value of the network based on the network graph; selecting a value for a number of trap-free shortest link-disjoint paths to find between a source node and a destination node based on the maximum flow value; selecting a value for a minimum remaining flow value based on the value for the number of trap-free shortest link-disjoint paths; and selecting a trap-free shortest link-disjoint path in which a complementary part of the network supports at least the remaining minimum flow value. | 2012-08-23 |
20120213080 | TRAP-FREE SHORTEST LINK-AND-SHARED RISK LINK GROUP-DISJOINT PATHS - A method including receiving network graph information of a network, wherein the network graph information includes shared risk link group (SRLG) information; determining a maximum link-and-SRLG-disjoint flow value of the network based on the network graph information; selecting a value for a number of trap-free shortest link-and-SRLG-disjoint paths to find between a source node and a destination node based on the maximum link-and-SRLG-disjoint flow value; selecting a minimum remaining link-and-SRLG-disjoint flow value based on the value for the number of trap-free shortest link-and-SRLG-disjoint paths; and selecting a trap-free shortest link-and-SRLG-disjoint path in which a complementary part of the network supports at least the minimum remaining link-and-SRLG-disjoint-flow value. | 2012-08-23 |
20120213081 | NETWORK DESIGN SYSTEM - An operator sets a path demand to be accommodated, and sets information of a device candidate, the number of ports, a path route and the like, which are demanded for a network, in an objective function that indicates a total cost when the path demand to be accommodated is newly included in the network. A mathematical programming problem for minimizing the objective function under a constraint condition derived from a configuration of the network is set, and a solution is obtained by using a solver for solving the mathematical programming problem. A device is added or the like to the network based on the obtained solution, and the demanded path is added to the network. | 2012-08-23 |
20120213082 | PREVENTION OF CALL SPOOFING IN A VOICE OVER INTERNET PROTOCOL (VoIP) NETWORK - Call spoofing in a Voice over Internet Protocol (IP) system may be detected and/or prevented. A device may receive a call request to initiate a VoIP call. The device may analyze marker information in the call request to determine whether the call request is valid. The device may also analyze the call request, based on call pattern information of a quantity of other calls, to determine whether the call request is suspicious; and complete the call based on the determination of whether the call request is valid and the determination of whether the call request is suspicious. | 2012-08-23 |