34th week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120211783 | LIGHT-EMITTING-DIODE ARRAY WITH MICROSTRUCTURES IN GAP BETWEEN LIGHT-EMITTING-DIODES - A light-emitting-diode (LED) array includes a first LED device having a first electrode and a second LED device having a second electrode. The first LED device and the second LED device are positioned on a common substrate. At least one polymer material is between the first LED device and the second LED device. A plurality of microsctructures are in the at least one polymer material. An interconnect is formed on top of the at least one polymer material to electrically connect the first electrode and the second electrode. | 2012-08-23 |
20120211784 | NITRIDE SEMICONDUCTOR STACKED STRUCTURE AND METHOD FOR MANUFACTURING SAME AND NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor stacked structure having a first surface includes a substrate, a first buffer layer, a first crystal layer, a second buffer layer and a second crystal layer. A step portion is provided in the substrate and includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface. The first buffer layer includes In | 2012-08-23 |
20120211785 | HIGH POWER PLASTIC LEADED CHIP CARRIER WITH INTEGRATED METAL REFLECTOR CUP AND DIRECT HEAT SINK - A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package includes a lead frame with an integrated reflector cup. The reflector cup is directly connected to a heat sink, which improves the ability of the PLCC package to distribute heat away from the light source that is provided in the reflector cup. | 2012-08-23 |
20120211786 | LED PACKAGE STRUCTURE WITH A WIDE OPTICAL FIELD - An LED package structure with a wide optical field comprises a substrate, an LED chip, and an encapsulation. The substrate has at least two electrodes and a carrier. The carrier has a carrier surface. The carrier surface is higher than a top surface of the substrate and higher than the electrodes. The LED chip is mounted on the carrier surface. The LED chip electrically connects with the electrodes via wires. The encapsulation covers the LED chip. The LED chip has a wide light emitting angle. | 2012-08-23 |
20120211787 | Method for Fabricating a Semiconductor Component based on GaN - A semiconductor component has a plurality of GaN-based layers, which are preferably used to generate radiation, produced in a fabrication process. In the process, the plurality of GaN-based layers are applied to a composite substrate that includes a substrate body and an interlayer. A coefficient of thermal expansion of the substrate body is similar to or preferably greater than the coefficient of thermal expansion of the GaN-based layers, and the GaN-based layers are deposited on the interlayer. The interlayer and the substrate body are preferably joined by a wafer bonding process. | 2012-08-23 |
20120211788 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device having high optical extraction efficiency is provided. The semiconductor light-emitting device includes a substrate on which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are formed sequentially; an n electrode formed in an exposed part of the n-type semiconductor layer by removing parts of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer; a current spreading layer formed on the p-type semiconductor layer; a p electrode formed on the current spreading layer; and a current blocking layer formed between the p-type semiconductor layer and the current spreading layer to include a region corresponding to the p electrode. | 2012-08-23 |
20120211789 | LIGHT EMITTING DEVICE PACKAGE - There is provided a light emitting device package, including: a package body; a first lead frame coupled to the package body and including a first recess having an exposed side, the first recess having a chip mounting area formed to be downwardly recessed therein, wherein at least a part of a bottom surface of the chip mounting area is exposed to a bottom surface of the package body; a second lead frame coupled to the package body so as to have a predetermined distance from the first lead frame and including a second recess having an exposed side opposed to the exposed side of the first recess; and at least one light emitting device mounted on the chip mounting area of the first lead frame and electrically connected with the first and second lead frames. | 2012-08-23 |
20120211790 | OPTICAL DEVICE FOR SEMICONDUCTOR BASED LAMP - An optical device for a semiconductor based lamp includes a base and a semiconductor based light-emitting device mounted on the base. A transparent body encapsulates the semiconductor based light-emitting device. A reflective surface is in contact with the transparent body and covers a predetermined region on a top of the transparent body. The reflective surface has an opening. At least a portion of the transparent body protrudes through the opening in the reflective surface. Light emitted from the semiconductor based light-emitting device transmits upwardly through the opening in the reflective surface. | 2012-08-23 |
20120211791 | LED Packaging Structure and Fabricating Method Thereof - A light emitting diode (LED) packaging structure includes a base, a LED chip, a gel-blocking structure and a phosphor layer. The LED chip disposed on the base and electrically connected to the base. The LED chip having a substrate and a semiconductor layer formed on the substrate. The gel-blocking structure is disposed on the substrate of the LED chip and surrounding the semiconductor layer. The phosphor layer is filled within a space defined by the gel-blocking structure, the substrate and the semiconductor layer. The present invention also discloses a fabricating method of the LED packaging structure. | 2012-08-23 |
20120211792 | Package Substrate and Method for Forming the Same - A package substrate is disclosed. The package substrate includes a substrate body having a conductive portion, a plurality of insulation portions and two surfaces opposing to each other; and a plurality of bonding layers for heat dissipation formed on the two surfaces of the substrate body, conducted via the conductive portion and separated from one another by the insulation portions. A method for forming the package substrate is also disclosed. | 2012-08-23 |
20120211793 | Low Temperature High Strength Metal Stack for Die Attachment - A light emitting diode structure includes a diode region and a metal stack on the diode region. The metal stack includes a barrier layer on the diode region and a bonding layer on the barrier layer. The barrier layer is between the bonding layer and the diode region. The bonding layer includes gold, tin and nickel. A weight percentage of tin in the bonding layer is greater than 20 percent and a weight percentage of gold in the bonding layer is less than about 75 percent. A weight percentage of nickel in the bonding layer may be greater than 10 percent. | 2012-08-23 |
20120211794 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a light-emitting stack having an upper surface and a lower surface; a pad, arranged on the upper surface, comprising: a first bonding region; and a second bonding region physically connected to the first bonding region through a connecting region having a connecting width; a first electrode connected to the first bonding region; a second electrode connected to the second bonding region; and a third electrode extending from the pad and arranged between the first electrode and the second electrode. At least one of the first electrode, the second electrode, and the third electrode has a width smaller than the connecting width. | 2012-08-23 |
20120211795 | SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING SUBSTRATE HAVING PROTECTION LAYERS AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a compound semiconductor light emitting device including: an Si—Al substrate; protection layers formed on top and bottom surfaces of the Si—Al substrate; and a p-type semiconductor layer, an active layer, and an n-type semiconductor layer which are sequentially stacked on the protection layer formed on the top surface of the Si—Al substrate, and a method for manufacturing the same. | 2012-08-23 |
20120211796 | Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same - A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate. | 2012-08-23 |
20120211797 | HEAT-CURABLE SILICONE RESIN COMPOSITION FOR SEALING OPTICAL SEMICONDUCTORS, AND A SEALED OPTICAL SEMICONDUCTOR USING THE SAME - A heat-curable silicone resin composition for sealing optical semiconductors including: component (A): 100 parts by mass of a silicon compound expressed by Formula (1) below; and component (B): from 0.001 to 10 parts by mass of a condensation catalyst. | 2012-08-23 |
20120211798 | ADJUSTABLE FIELD EFFECT RECTIFIER - An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference. | 2012-08-23 |
20120211799 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A POWER SEMICONDUCTOR MODULE - A power semiconductor module including a semiconductor device (e.g., an insulated gate bipolar transistor (IGBT), a reverse conductive (RC IGBT), or a bi-mode insulated gate transistor (BIGT)) with an emitter electrode and a collector electrode is provided. An electrically conductive upper layer is sintered to the emitter electrode. The upper layer is capable of forming an eutecticum with the semiconductor of the semiconductor device, and has a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor in a range of ≦250%, for example ≦50%. An electrically conductive base plate is sintered to the collector electrode. The semiconductor module includes an electrically conductive area which is electrically isolated from the base plate and connected to the upper layer via a direct electrical connection. The semiconductor module is easy to prepare, has an improved reliability and exhibits short circuit failure mode capacity. | 2012-08-23 |
20120211800 | GaN HEMTs with a Back Gate Connected to the Source - The present invention reduces the dynamic on resistance in the channel layer of a GaN device by etching a void in the nucleation and buffer layers between the gate and the drain. This void and the underside of the device substrate may be plated to form a back gate metal layer. The present invention increases the device breakdown voltage by reducing the electric field strength from the gate to the drain of a HEMT. This electric field strength is reduced by placing a back gate metal layer below the active region of the channel. The back gate metal layer may be in electrical contact with the source or drain. | 2012-08-23 |
20120211801 | GROUP III NITRIDE LAMINATED SEMICONDUCTOR WAFER AND GROUP III NITRIDE SEMICONDUCTOR DEVICE - There is provided a normally-off group III nitride semiconductor device having a high breakdown field strength and minimal crystal defects, and a group III nitride laminated semiconductor wafer used to make the group III nitride semiconductor device. The group III nitride laminated semiconductor wafer | 2012-08-23 |
20120211802 | FIELD EFFECT TRANSISTOR, SEMICONDUCTOR SWITCH CIRCUIT, AND COMMUNICATION APPARATUS - A field effect transistor includes a source wiring that is formed on a compound semiconductor substrate, and has a plurality of source electrodes arranged in parallel to each other at predetermined intervals, a drain wiring that is formed on the compound semiconductor substrate, and has a plurality of drain electrodes arranged in parallel to each other at predetermined intervals and alternatively disposed in a parallel direction of the plurality of source electrodes, a gate wiring that is formed on the compound semiconductor substrate, and has a portion located between the source electrode and the drain electrode which are adjacent to each other at least in the parallel direction, and a plurality of buried gate layers that is formed under the gate wiring in a region in which the gate wiring is formed, and is independently provided between each electrode of the source electrodes and the drain electrodes. | 2012-08-23 |
20120211803 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES - Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing. | 2012-08-23 |
20120211804 | CHARGE TRANSFER PHOTOSITE - A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor. | 2012-08-23 |
20120211805 | CAVITY STRUCTURES FOR MEMS DEVICES - Embodiments relate to MEMS devices, particularly MEMS devices integrated with related electrical devices on a single wafer. Embodiments utilize a modular process flow concept as part of a MEMS-first approach, enabling use of a novel cavity sealing process. The impact and potential detrimental effects on the electrical devices by the MEMS processing are thereby reduced or eliminated. At the same time, a highly flexible solution is provided that enables implementation of a variety of measurement principles, including capacitive and piezoresistive. A variety of sensor applications can therefore be addressed with improved performance and quality while remaining cost-effective. | 2012-08-23 |
20120211806 | Normally-Off Semiconductor Switches and Normally-Off JFETS - A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided. | 2012-08-23 |
20120211807 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 2012-08-23 |
20120211808 | FIN-TRANSISTOR FORMED ON A PATTERNED STI REGION BY LATE FIN ETCH - When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach. | 2012-08-23 |
20120211809 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPLIANCE - Provided are a semiconductor device with less leakage current is reduced, a semiconductor device with both of high field effect mobility and low leakage current, an electronic appliance with low power consumption, and a manufacturing method of a semiconductor device in which leakage current can be reduced without an increase in the number of masks. The side surface of a semiconductor layer formed of a semiconductor film having high carrier mobility is not in contact with any of a source electrode and a drain electrode. Further, such a transistor structure is formed without an increase in the number of photomasks and can be applied to an electronic appliance. | 2012-08-23 |
20120211810 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 2012-08-23 |
20120211811 | MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - A magnetic memory has a magnetic recording layer, a reference layer connected via a non-magnetic layer to the magnetic recording layer, first and second magnetization pinning layers disposed below the magnetic recording layer. The magnetic recording layer and the reference layer have a perpendicular magnetic anisotropy. The magnetic recording layer has a magnetization reversal region having a reversible magnetization and overlapping the difference layer, a first magnetization pinned region connected to a first boundary of the magnetization reversal region with the direction of the magnetization being fixed in a first direction, and a second magnetization pinned region connected to a second boundary of the magnetization reversal region with the direction of magnetization being fixed in a second direction anti-parallel to the first direction. The first and the second magnetization pinning layers fix the magnetization of the first and the second magnetization pinned regions. | 2012-08-23 |
20120211812 | HIGH-SPEED HIGH-POWER SEMICONDUCTOR DEVICES - High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage. | 2012-08-23 |
20120211813 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode. | 2012-08-23 |
20120211814 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 2012-08-23 |
20120211815 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - In one embodiment, a semiconductor device includes a semiconductor substrate having a first groove; and a plurality of first pillars over the substrate. The plurality of first pillars is disposed beside the first groove. A first insulator is disposed in the first groove. A bit contact is disposed in the first groove and over the first insulator. The bit contact is coupled to side surfaces of the plurality of first pillars. | 2012-08-23 |
20120211816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; | 2012-08-23 |
20120211817 | Flash Memory Device - A flash memory device including a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers. | 2012-08-23 |
20120211818 | SEMICONDUCTOR DEVICES - In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness. | 2012-08-23 |
20120211819 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2012-08-23 |
20120211820 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films. | 2012-08-23 |
20120211821 | SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a first stacked body on a substrate by alternately stacking a first film and a second film, forming a second stacked body on the first stacked body by alternately stacking a third film and a fourth film, making a through-hole to pierce the second stacked body and the first stacked body by performing etching, an etching rate of the third film being lower than an etching rate of the first film in the etching, forming a charge storage film on an inner surface of the through-hole, and forming a semiconductor member in the through-hole. The first film and the second film are formed of mutually different materials. The third film and the fourth film are formed of mutually different materials. And, the first film and the third film are formed of mutually different materials. | 2012-08-23 |
20120211822 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 2012-08-23 |
20120211823 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a lower select transistor formed within a semiconductor substrate, memory cells stacked over the lower select transistors, and an upper select transistor formed over the memory cells. | 2012-08-23 |
20120211824 | VERTICAL TRANSISTOR HAVING A GATE STRUCTURE FORMED ON A BURIED DRAIN REGION AND A SOURCE REGION OVERLYING THE UPPER MOST LAYER OF THE GATE STRUCTURE - Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface. | 2012-08-23 |
20120211825 | Trench MOSFET and Method for Fabricating Same - According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode. | 2012-08-23 |
20120211826 | Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance - A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance. | 2012-08-23 |
20120211827 | METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE - In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor. | 2012-08-23 |
20120211828 | HYBRID SPLIT GATE SEMICONDUCTOR - In an embodiment in accordance with the present invention, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, a shield electrode at a second depth on the first side of the vertical channel region, and a hybrid gate at the first depth on a second side of the vertical channel region. The region below the hybrid gate on the second side of the vertical channel region is free of any electrodes. | 2012-08-23 |
20120211829 | FIELD-EFFECT TRANSISTOR AND METHOD OF CREATING SAME - A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate. | 2012-08-23 |
20120211830 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern. | 2012-08-23 |
20120211831 | TRENCH MOSFET WITH TRENCHED FLOATING GATES IN TERMINATION - A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprise an EPR surrounding outside the multiple trenched floating gates in the termination area. | 2012-08-23 |
20120211832 | SPLIT-GTE LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVISE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure. | 2012-08-23 |
20120211833 | SUPER-JUNCTION SEMICONDUCTOR DEVICE - A super-junction semiconductor device includes a drift layer including an alternating-conductivity-type layer that includes n-type region and p-type region arranged alternately in parallel to the first major surface of an n-type substrate. These alternating regions extend deep in a direction perpendicular to the first major surface. The first major surface includes a main device region with a gate electrode and a main source electrode and sensing device region with a gate electrode and a sensing source electrode. There is a common drain electrode on the second major surface of the substrate. There is a separation region between the main device region and the sensing device region. It includes an n-type region and p-type regions in the n-type region. The p-type regions are in an electrically floating state in the directions parallel and perpendicular to the first alternating-conductivity-type layer. | 2012-08-23 |
20120211834 | MULTI-LEVEL LATERAL FLOATING COUPLED CAPACITOR TRANSISTOR STRUCTURES - A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure. | 2012-08-23 |
20120211835 | SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE CONNECTION - Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region. | 2012-08-23 |
20120211836 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G | 2012-08-23 |
20120211837 | SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS - When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures. | 2012-08-23 |
20120211838 | Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas - When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for | 2012-08-23 |
20120211839 | METHODS OF CHANNEL STRESS ENGINEERING AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation. | 2012-08-23 |
20120211840 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines]. | 2012-08-23 |
20120211841 | OTP MEMORY CELL HAVING LOW CURRENT LEAKAGE - A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell | 2012-08-23 |
20120211842 | Semiconductor Body Having a Terminal Cell - A semiconductor body comprising a first connection for feeding an upper supply potential and a first and a second terminal cell, which are situated at a distance from each other. The semiconductor body further comprises an arrester structure, which is arranged between the first and second terminal cells in a p-doped substrate. The arrester structure comprises a first and a second p-channel field-effect transistor structure, each of which is set in a respective n-doped well substantially parallel to the first and second terminal cells, and a diode structure with a p-doped region set in a further n-doped well between the n-doped wells of the first and second p-channel field-effect transistor structures. The diode structure is designed to activate the first and second p-channel field-effect transistor structure as arrester elements during an electrostatic discharge in the semiconductor body. | 2012-08-23 |
20120211843 | OPTIMIZED CHANNEL IMPLANT FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion. | 2012-08-23 |
20120211844 | Semiconductor Device Comprising Self-Aligned Contact Elements and a Replacement Gate Electrode Structure - When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height. | 2012-08-23 |
20120211845 | Integrated Circuit with Sensor and Method of Manufacturing Such an Integrated Circuit - Disclosed is an integrated circuit comprising a substrate ( | 2012-08-23 |
20120211846 | MRAM DEVICE AND METHOD OF ASSEMBLING SAME - A method of assembling a magnetoresistive random access memory (MRAM) device includes providing a substrate having an opening. A tape is applied to a surface of the substrate and a first magnetic shield is placed onto the tape and within the substrate opening. An adhesive is applied between the first magnetic shield and the substrate to attach the first magnetic shield to the substrate. An MRAM die is attached to the first magnetic shield and bond pads of the MRAM die are connected to pads on the substrate with wires. A second magnetic shield is attached to a top surface of the MRAM die. An encapsulating material is dispensed onto the substrate, the MRAM die, the second magnetic shield and part of the first magnetic shield, cured, and then the tape is removed. Solder balls then may be attached to the substrate. | 2012-08-23 |
20120211847 | SEMICONDUCTOR DEVICE INCLUDING A MAGNETIC TUNNEL JUNCTION AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. | 2012-08-23 |
20120211848 | SPIN TRANSPORT TYPE MAGNETIC SENSOR - The magnetic sensor includes a base substrate having a magnetic shield layer; a single-domain semiconductor crystal layer attached via an insulating film on the magnetic shield layer of the base substrate; a first ferromagnetic layer formed on top of the semiconductor crystal layer on the opposite side of the semiconductor crystal layer to the insulating film, via a first tunnel barrier layer; and a second ferromagnetic layer formed, at a distance from the first ferromagnetic layer, on top of the semiconductor crystal layer on the opposite side of the semiconductor crystal layer to the insulating film, via a second tunnel barrier layer. | 2012-08-23 |
20120211849 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR LAMINATING SEMICONDUCTOR WAFERS, AND ELECTRONIC DEVICE - A method for manufacturing a semiconductor device including: forming a wiring layer on a surface side of a first semiconductor wafer; forming a buried film so as to fill in a level difference on the wiring layer, the level difference being formed at a boundary between a peripheral region of the first semiconductor wafer and an inside region being on an inside of the peripheral region, and the level difference being formed as a result of a surface over the wiring layer in the peripheral region being formed lower than a surface over the wiring layer in the inside region, and making the surfaces over the wiring layer in the peripheral region and the inside region substantially flush with each other; and opposing and laminating the surfaces over the wiring layer formed in the first semiconductor wafer to a desired surface of a second semiconductor wafer. | 2012-08-23 |
20120211850 | IMAGING ELEMENT, METHOD FOR MANUFACTURING IMAGING ELEMENT, PIXEL DESIGN METHOD, AND ELECTRONIC APPARATUS - An imaging element includes a plurality of pixels that are two-dimensionally arranged and each have a light receiving part including a photoelectric conversion element and a light collecting part that collects incident light toward the light receiving part. Each of the light collecting parts in the plurality of pixels includes an optical functional layer having, in a surface, a specific projection and depression structure depending on the pixel position. | 2012-08-23 |
20120211851 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes semiconductor substrate; a plurality of photoelectric conversion sections of n-type that are formed at an upper part of semiconductor substrate and arranged in a matrix; output circuit that is formed on a charge detection surface that is one surface of semiconductor substrate and detects charges stored in photoelectric conversion sections; a plurality of isolating diffusion layers of a p-type that are formed under output circuit and include high concentration p-type layers adjacent to respective photoelectric conversion sections; and color filters formed on a light incident surface that is the other surface opposing the one surface of semiconductor substrate and transmit light with different wavelengths. Shapes of respective photoelectric conversion sections correspond to color filters and differ depending on the high concentration p-type layer configuring isolating diffusion layer. | 2012-08-23 |
20120211852 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2012-08-23 |
20120211853 | SOLID-STATE IMAGING APPARATUS AND METHOD OF MANUFACTURING THE SAME - A solid-state imaging apparatus includes: an imaging section having a light-receiving portion for receiving light from an object to image the object; and a substrate on which the imaging section is disposed, wherein a predetermined member provided on the substrate in the neighborhood of the light receiving portion is partially or entirely coated in black. | 2012-08-23 |
20120211854 | PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE - Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage. | 2012-08-23 |
20120211855 | SEMICONDUCTOR APPARATUS, MANUFACTURING APPARATUS, AND MANUFACTURING METHOD - A semiconductor apparatus includes: a first sheet-like member having a light receiving surface of an imaging device and a first connection terminal disposed thereon, the imaging device generating an image by receiving incident light from a light collecting section for collecting external light disposed thereon; a second sheet-like member having a second connection terminal to be connected to the first connection terminal provided thereon; a conductive bonding portion made of a conductive material and bonded with the first connection terminal; and a bonding wire connecting the conductive bonding portion and the second connection terminal, wherein the bonding wire is disposed along the plane of the first sheet-like member such that reflected light from the bonding wire does not impinge on the light receiving surface. | 2012-08-23 |
20120211856 | PHOTOVOLTAIC CELL CONDUCTOR CONSISTING OF TWO, HIGH-TEMPERATURE AND LOW-TEMPERATURE, SCREEN-PRINTED PARTS - Method for formation of at least one electrical conductor on a semiconductor material ( | 2012-08-23 |
20120211857 | PYROELECTRIC DETECTOR, PYROELECTRIC DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A pyroelectric detector includes a substrate, a support member and a pyroelectric detection element, which includes a capacitor, first and second reducing gas barrier layers, an insulating layer, a plug and a second electrode wiring layer. The first reducing gas barrier layer covers at least a second electrode and a pyroelectric body of the capacitor, and has a first opening that overlaps the second electrode in plan view. The insulating layer covers at least the first reducing gas barrier layer, and has a second opening that overlaps the first opening in plan view. The plug is disposed in the first and second openings and connected to the second electrode. The second electrode wiring layer is formed on the insulating layer and connected to the plug. The second reducing gas barrier layer is formed on the insulating layer and the second electrode wiring layer and covers at least the plug. | 2012-08-23 |
20120211858 | THERMAL DETECTOR, THERMAL DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A thermal detector includes a substrate, a thermal detection element and a support member. The substrate has a recess part with a bottom surface of the recess part being a curved light-reflecting surface. The thermal detection element has a light-absorbing film. The support member supports the thermal detection element. The substrate and the support member are arranged to form a hollow part therebetween. The support member includes a light-absorbing part in which impurities are dispersed in polycrystalline silicon with the light-absorbing part being arranged in at least a part of a surface of the support member facing toward the hollow part so that the light-absorbing part being irradiated by light. | 2012-08-23 |
20120211859 | SCHOTTKY DIODE - A Schottky diode including a semiconductor region, a first terminal comprising a metal or a metal silicide or being metallic, and a second terminal comprising at least a portion of the semiconductor region. The diode further includes an at least partly conductive material or a material capable of holding a charge in close proximity to, or in contact with, or surrounding one of the first and second terminals, a field insulator located at least partly in the semiconductor region, a dielectric region located over the semiconductor region between the field insulator and the one of the first and second terminals for isolating the conductive or charge-holding material from the semiconductor region, and wherein the dielectric region comprises insulating regions of different thicknesses. | 2012-08-23 |
20120211860 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation. | 2012-08-23 |
20120211861 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators are formed in an upper layer portion of the semiconductor substrate. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess. | 2012-08-23 |
20120211862 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING SOI SUBSTRATE - The method for manufacturing an SOI substrate includes the following steps: forming an insulating film on a semiconductor substrate; exposing the semiconductor substrate to accelerated ions so that an embrittlement region is formed in the semiconductor substrate; bonding the semiconductor substrate to a base substrate with the insulating film interposed therebetween; separating the semiconductor substrate along the embrittlement region so that a semiconductor film is provided over the base substrate with the insulating film interposed therebetween; and forming a mask over the semiconductor film to etch part of the semiconductor film and part of the insulating film so that the periphery of the semiconductor film is on the inner side than the periphery of the insulating film. | 2012-08-23 |
20120211863 | METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH - A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide. | 2012-08-23 |
20120211864 | INDUCTOR - Parasitic capacitance between upper and lower adjacent wirings of an inductor using a multilayer wiring layer in an insulating film formed on a base substrate is reduced. An inductor is characterized by having one go-around of go-around wiring (A-B or B-C) formed in each of at least two of adjacent wiring layers of a plurality of wiring layers | 2012-08-23 |
20120211865 | DEEP TRENCH CAPACITOR WITH CONFORMALLY-DEPOSITED CONDUCTIVE LAYERS HAVING COMPRESSIVE STRESS - A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-Si | 2012-08-23 |
20120211866 | METAL-INSULATOR-METAL CAPACITOR AND A METHOD OF FABRICATING THE SAME - A metal-insulator-metal (MIM) capacitor and a method of fabricating the same. The MIM capacitor is in a memory area of a wafer and comprises a top electrode formed from the same metal layer as a point contact to a via in the logic area of the wafer. The method of fabricating the MIM capacitor in a memory area of a wafer comprises forming a point contact to a via in a logic area of the wafer from the same metal layer as a top electrode of the MIM capacitor. | 2012-08-23 |
20120211867 | SIDE-MOUNTED CONTROLLER AND METHODS FOR MAKING THE SAME - A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package. | 2012-08-23 |
20120211868 | ULTRA-LOW VOLTAGE COEFFICIENT CAPACITORS - A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor ( | 2012-08-23 |
20120211869 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 2012-08-23 |
20120211870 | III-V SEMICONDUCTOR STRUCTURES WITH DIMINISHED PIT DEFECTS AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime. | 2012-08-23 |
20120211871 | METHOD OF PRODUCING NANOPATTERNED ARTICLES, AND ARTICLES PRODUCED THEREBY - A nanopatterned surface is prepared by forming a block copolymer film on a miscut crystalline substrate, annealing the block copolymer film, then reconstructing the surface of the annealed block copolymer film The method creates a well-ordered array of voids in the block copolymer film that is maintained over a large area. The nanopatterned block copolymer films can be used in a variety of different applications, including the fabrication of high density data storage media. | 2012-08-23 |
20120211872 | SEMICONDUCTOR DEVICE - A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device | 2012-08-23 |
20120211873 | METHOD FOR FORMING A PATTERN AND SEMICONDUCTOR DEVICE - A method for forming a pattern includes: forming a resist film on an object and patterning the formed resist film; forming a spacer film to coat the object and the resist film, and forming a concave portion surrounded by the spacer film; forming a first opening from the concave portion by etching a portion of the spacer film so that the spacer film remains beside a side wall of the resist film while exposing the object under the concave portion and the top surface of the resist film; and forming a second opening by removing the resist film. | 2012-08-23 |
20120211874 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof. | 2012-08-23 |
20120211875 | SEMICONDUCTOR DEVICE WITH STACKED SEMICONDUCTOR CHIPS - A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip. | 2012-08-23 |
20120211876 | MODULE IC PACKAGE STRUCTURE - A module IC package structure includes a substrate unit, a radio frequency unit, an inner shielding unit, an insulative package unit, and an outer shielding unit. The substrate unit includes a circuit substrate. The radio frequency unit includes at least one radio frequency element disposed on and electrically connected to the circuit substrate. The inner shielding unit includes an inner metal shielding layer formed on a predetermined surface of the radio frequency element. The insulative package unit includes an insulative package resin body disposed on the circuit substrate to cover the radio frequency element. The outer shielding unit is formed on the outer surface of the insulative package resin body and electrically connected to the circuit substrate. The inner metal shielding layer is a radio frequency property maintaining layer disposed between the radio frequency element and one part of the outer shielding unit for shielding the radio frequency element. | 2012-08-23 |
20120211877 | Semiconductor Device And Method For Manufacturing Same - A semiconductor device includes (i) a tape base material, (ii) a wiring pattern, (iii) a semiconductor element which is electrically connected with the wiring pattern, (iv) a top-side insulating protective film which covers a top surface of the tape base material and has an top-side opening section provided in a region where the top-side insulating protective film faces the semiconductor element, and (v) a reverse-side insulating protective film which covers a reverse surface of the tape base material and has a reverse-side opening section provided on a reverse side below the top-side opening section. The top-side insulating protective film has a protruding opening section extending outwardly from the region. An opening of the reverse-side opening section is 1.00 time to 8.50 times larger in an area than the region. | 2012-08-23 |
20120211878 | CHIP PACKAGE WITH PLANK STACK OF SEMICONDUCTOR DIES - In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate. | 2012-08-23 |
20120211879 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer. | 2012-08-23 |
20120211880 | Flip Chip Interconnection Having Narrow Interconnection Sites on the Substrate - A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces. | 2012-08-23 |
20120211881 | Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process - A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer. | 2012-08-23 |
20120211882 | Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch - A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate. | 2012-08-23 |