34th week of 2013 patent applcation highlights part 64 |
Patent application number | Title | Published |
20130219073 | ADAPTIVE DISPLAY STREAMS - A transcoding device receives an input stream representing media information designated for display at a sink device. The transcoding device generates multiple display streams based on the input stream, wherein each of the display streams has a different transmission characteristic, such as a different bit rate or resolution. The transcoding device selects one of the generated display streams based on a network characteristic, such as a bandwidth or latency, and communicates the selected stream to the network for transmission to the sink device. In response to a change in the network characteristic, a different one of the generated display streams is selected and communicated to the network for transmission to the sink device. | 2013-08-22 |
20130219074 | SYSTEM AND METHOD FOR DYNAMIC FILE AVAILABILITY DURING ENCODING - A method for dynamic file availability during remote transfer and transcoding involves the conversion of a non-streamable media file to a streamable format prior to transcoding, and the streaming of the transcoded file before ingest and transcode is complete. A first portion of a non-streamable media file is received at an ingest server for transcoding. Upon determining that the first portion does not include a header, the probable location of the header in the media file is determined and a header portion of the file is received at the ingest server. The first portion is combined with at least part of the header to produce a first streamable segment. Prior to receiving the last portion of the media file at the ingest server, the first streamable segment is transcoded at a first transcode server to produce a first transcoded streamable segment. | 2013-08-22 |
20130219075 | SYSTEM AND METHOD FOR ROUTING MEDIA - The system and method for streaming media to a viewer and managing the media comprises an enhanced service routing processor (ESRP), a real time switch management system (RTSMS), a name routing processor (NRP), and a managed media switch (MMS). The RTSMS has a reservation system. The ESRP receives media from an owner, manages the media according to media rules and order rules defined by the owner, and distributes the media to one or more switches, such as the MMS, according to the media rules and the order rules. The RTSMS is configured to receive the media rules and to receive a viewer's media request via the reservation server. The reservation system of the RTSMS processes the media request according to the media rules and builds a reservation for the requested media. The RTSMS generates the reservation to the viewer and to the NRP. The NRP receives the reservation data from the viewer and from the RTSMS. The NRP processes the reservation data and locates an MMS that can stream the media to the viewer. The NRP transmits the IP address of the MMS to the viewer and transmits the reservation data to the MMS. The viewer initiates a session or connection with the MMS using the reservation number. If the reservation data from the viewer matches the reservation data from the NRP, the MMS streams the media to the viewer. | 2013-08-22 |
20130219076 | WIRELESS MULTIMEDIA BROKERAGE SERVICE FOR REAL TIME CONTENT PROVISIONING - A wireless multimedia brokerage service supports sharing of real-time multimedia content whereby a mobile device user can perceive real-time content from a device in visual proximity, such as a nearby display device, and share the content of the display device with another mobile terminal user without the need to download or otherwise directly access the real-time content. The brokerage service can handle the transactional details of obtaining rights to the real-time content and also manage establishing and terminating a real-time multimedia session with the device(s) of the recipient user(s). In some embodiments, the wireless multimedia content brokerage service can proactively obtain subscriptions to content providers based on the location of one or more users. The brokerage service can also proactively obtain and buffer real-time content after receiving a request to share the content, with the buffering allowing for content to be preserved while the recipient user or users are contacted. The content can then be pushed or otherwise provided to the recipient(s). | 2013-08-22 |
20130219077 | EMULATING FICON OVER IP - A Fibre Connection (FICON) information unit is received by a host processor executing a host internet protocol (IP) software library. The FICON information unit is written to a transport layer. Data including the FICON information unit is then transmitted to a storage control unit over an IP network. | 2013-08-22 |
20130219078 | TUNNEL CREATION - A non-transitory machine readable medium storing a program that configures managed forwarding elements to establish tunnels between the managed forwarding elements is described. From a particular managed forwarding element, the program receives information regarding coupling of a network element to the first managed forwarding element. Upon receiving the information, the program generates a set of universal flow entries for configuring another managed forwarding element to establish a tunnel to the particular managed forwarding element. | 2013-08-22 |
20130219079 | STORAGE AREA NETWORK MULTI-PATHING - Provided are a method, computer program product and system for network multi-pathing. Paths to a storage system are through a first network type and a second network type. The first network type has a higher Input/Output (I/O) per second performance characteristic than the second network type. A length is determined from a received I/O request. The I/O request is sent on one of the paths to the storage system through the first network type in response to determining that the length of the I/O request is below a threshold length. The I/O request is sent on one of the paths to the storage system through the second network type in response to determining that the length of the I/O request is above the threshold length. | 2013-08-22 |
20130219080 | METHOD FOR ROUTING AND ASSOCIATED ROUTING DEVICE AND DESTINATION DEVICE - A method for routing in a routing device includes receiving a plurality of data packets of a communication session, and consulting a set of routing rules for each data packet of the plurality of data packets. The set of routing rules indicates on which of at least two egress interfaces of said router each data packet of said plurality of data packets is to be forwarded. The method further includes forwarding each of the plurality of data packets on the respective egress interfaces, deriving information from the plurality of data packets, and deactivating at least one routing rule of the set of routing rules, at least based on whether the information meets predetermined criteria. | 2013-08-22 |
20130219081 | Method and Apparatus for Adaptive Forwarding Strategies in Content-Centric Networking - A named-data networking (NDN) node, comprising a plurality of faces each of which is coupled to a different node in a content-centric network, and a processor coupled to the faces, wherein the processor is configured to probe the performance of each of the faces for an interest, wherein the interest is associated with multiple ones of the faces, wherein a next-hop is identified by the face, wherein a one of the faces associated with the interest is used to forward the interest when the interest is received by the NDN node, and wherein the one of the faces used is determined based on a selection probability determined from feedback from the probe of the performance of the faces. | 2013-08-22 |
20130219082 | MOBILE ROUTER INFORMATION MANAGEMENT SERVER, MOBILE ROUTER, MOBILE ROUTER NETWORK, AND COMMUNICATION METHOD FOR SAME - With the object of enabling data transfer between mobile routers without going through a home agent and establishing a connection to a destination mobile router even when mobile communication terminals equipped in the destination mobile router are changed at the time of initiating connection to the destination mobile router, a mobile router information management server has a mobile router registration information table that registers, for each mobile router, mobile router information that is reported from the mobile routers and that includes identification information of the mobile routers and identification information of mobile communication terminals equipped in the mobile routers, in response to inquiry information from a mobile router that includes identification information of another mobile router that is to be a communication destination, searches the mobile router registration information table, based on the identification information of the other mobile router, for mobile router information that includes identification information of mobile communication terminals equipped in the other mobile router, and returns the searched mobile router information to the mobile router. | 2013-08-22 |
20130219083 | PERIPHERAL DEVICE, INFORMATION PROCESSING SYSTEM, CONTROL METHOD, AND STORAGE MEDIUM - An MFP sets an enterprise number that responds to an external device regardless of a specific rule corresponding to a request when the MFP receives the request for acquiring MIB information in which a specific object ID is designated from an external device. The MFP receives the request for acquiring MIB information from a PC and responds the set enterprise number to the request. | 2013-08-22 |
20130219084 | MULTI-STANDARD COMPATIBLE EV CHARGER - The present invention discloses a multi-standard compatible electrical vehicle charger, including a power converter having an interface compatible with messages or instructions of an internal protocol; when the electrical vehicle charger charges an electric vehicle, the power converter is adapted to output power to a battery of the electric vehicle; and a data transmission device having an internal interface compatible with messages or instructions of the internal protocol and an external interface compatible with messages or instructions of an external protocol; wherein when the electrical vehicle charger charges the electric vehicle, the data transmission device is adapted to communicate with a battery management system through the external interface according to the external protocol followed by the battery management system, and to communicate with the power converter through the internal interface according to the internal protocol followed by the power converter. This electrical vehicle charger improves the utilization rate of the electrical vehicle charger. | 2013-08-22 |
20130219085 | MULTI-DISK COMBINATION DEVICE AND METHOD FOR COMBINING A PLURALITY OF USB FLASH DRIVES - In a method for combining universal serial bus (USB) flash drives using a multi-disk combination device, the multi-disk combination device includes a USB input port and several USB output ports. The method sets an initialization voltage value of each of the USB output ports as a low voltage level, and detects a current voltage value of each of the USB output ports while the USB input port is plugged into a USB connection of an electronic device. The method determines whether any USB output port connects to a USB flash drive, builds a disk array mode for all USB flash drives connected to the USB output ports, and controls each of the USB flash drives to store data of the electronic device in the disk array mode through a USB output port corresponding to the USB flash drive. | 2013-08-22 |
20130219086 | ELECTRONIC DEVICE CAPABLE OF AUTOMATICALLY SWITCHING MODES OF A MEMORY MODULE AND RELATED METHOD - A method of automatically switching modes of a memory module is disclosed in the present invention. The method includes enabling an auto-switch program, reading an actuating value in database, triggering a sensor, comparing the actuating value and an environmental parameter sensed by the sensor, and switching the mode of the memory module when the environmental parameter corresponds to the actuating value. | 2013-08-22 |
20130219087 | HIGH-DEFINITION MULTIMEDIA INTERFACE (HDMI) RECEIVER APPARATUSES, HDMI SYSTEMS USING THE SAME, AND CONTROL METHODS THEREFOR - A high-definition multimedia interface (HDMI) receiver apparatus is provided. The HDMI receiver apparatus includes a pin, a control module, and an extended display identification data (EDID) module. The pin is used to receive an HDMI cable connection voltage in a first operation state and output a hot plug detection signal in a second operation state. The control module is connected with the pin. When the pin receives the HDMI cable connection voltage in the first operation state, the control module switches the pin to the second operation state from the first operation state and outputs the hot plug detection signal to an HDMI transmitter apparatus through the pin, such that the HDMI transmitter apparatus reads EDID information according to the hot plug detection signal. The EDID module is used to store the EDID information. | 2013-08-22 |
20130219088 | CONFIGURABLE PRIORITIZATION OF DATA TRANSMISSION IN A DATA STORAGE TOPOLOGY - Processing input/output requests may include: processing one or more input/output (IO) requests in a first IO queue associated with a first device group; detecting a queuing of one or more IO requests in a second IO queue associated with a second device group; pausing the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a detection of a queuing of one or more IO requests in a second IO queue associated with a second device group; processing the one or more IO requests in a second IO queue associated with a second device group; and resuming the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a completion of the processing the one or more IO requests in a second IO queue associated with a second device group. | 2013-08-22 |
20130219089 | Communication Processing Device that Stores Communication Data in Buffers, Image Forming Apparatus, and Method of Communication Processing - A communication processing device includes a communication data processing circuit that (i) issues an access request for a buffer specified by a descriptor, among a plurality of buffers in a first memory, and (ii) outputs a predetermined switching permission signal at a time when a data access for one of the plurality of buffers is completed. The communication processing device also includes a second memory and a transmission destination switching circuit. The second memory includes a plurality of alternative buffers corresponding to the plurality of buffers. The transmission destination switching circuit switches a transmission destination of the access request from one of the plurality of buffers in the first memory to one of the plurality of alternative buffers in the second memory, based on the switching permission signal. | 2013-08-22 |
20130219090 | SYSTEM AND METHOD FOR VIRTUALIZING THE PERIPHERALS IN A TERMINAL DEVICE TO ENABLE REMOTE MANAGEMENT VIA REMOVABLE PORTABLE MEDIA WITH PROCESSING CAPABILITY - Systems and methods for virtualizing the peripherals in a wireless device to enable remote management via removable portable media with processing capability are described. One aspect may include a system for virtualizing a peripheral device of a wireless device from a media device, the system comprising a media device, including a first memory; a processor coupled to said first memory; and a virtualization device controller interface remote layer adapted to run on said processor and first memory, wherein said virtualization device controller interface remote layer is adapted to communicate with a peripheral device of the wireless device. | 2013-08-22 |
20130219091 | Island-Based Network Flow Processor Integrated Circuit - A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks. | 2013-08-22 |
20130219092 | Global Event Chain In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information. | 2013-08-22 |
20130219093 | Electrically Configurable Option Board Interface - A Main Logic Board having an electrically configurable option board interface (ECOBI) to facilitate connection of option boards into apparatus for providing optional functions. Once connected to the host, an Option board provides identification (ID) data to the main logic board host processor. The host processor determines the interface configuration necessary to enable communication between the host and the option board based on the option board ID, then configures electrically configurable interface circuitry for operational compatibility. The option board may provide an interface driver directly to the host for configuration of the interface. The interface may comprise a standard interface protocol such as PCI or USB that the host configures through the same connection to the option board. | 2013-08-22 |
20130219094 | Commonality of Memory Island Interface and Structure - The functional circuitry of a network flow processor is partitioned into a number of rectangular islands. The islands are disposed in rows. A configurable mesh data bus extends through the islands. A first island includes a first memory and a first data bus interface. A second island includes a processor, a second memory, and a second data bus interface. The processor can issue a command for a target memory to do an action. If a field in the command has a first value then the target memory is the first memory, whereas if the field has a second value then the target memory is in the second memory. The command format is the same, regardless of whether the target memory is local or remote. If the target memory is remote, then a data bus bridge adds destination information before putting the command onto the global configurable mesh data bus. | 2013-08-22 |
20130219095 | CIRCUIT AND METHOD FOR PIPE ARBITRATION USING AVAILABLE STATE INFORMATION AND ARBITRATION - Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit. | 2013-08-22 |
20130219096 | PROGRAMMABLE EVENT DRIVEN YIELD MECHANISM WHICH MAY ACTIVATE OTHER THREADS - Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors. | 2013-08-22 |
20130219097 | MODULE ON BOARD FORM FACTOR FOR EXPANSION BOARDS - A new form factor for circuit boards can be employed for directly connecting an expansion board to a motherboard without the need for PCIe hardware such as sockets, retainers, screw and nut assemblies, and connectors. The module on board form factor for an expansion board comprises a first side of the expansion board and a second side of the expansion board located physically opposite to the first side of the expansion board. The first side of the expansion board comprises one or more components configured to provide functionality associated with the expansion board. The second side of the expansion board comprises a plurality of connection leads, such as solder connections, that directly couple the expansion board to the motherboard. | 2013-08-22 |
20130219098 | Mobile Device Docking Station - A docking station adapted to receive and communicate with one or more mobile device. An interchangeable docking module can be removably engaged on the docking station. The docking module is adapted to receive a mobile device. Once the mobile device is received (“docked”) in the docking module, the docking station may be operable to deliver an electric current to charge the mobile device. A communication link between the docking station and the mobile device may also be established. A user may configure various functions of the mobile device using the docking station. | 2013-08-22 |
20130219099 | Device Interface Module - A computer, such as a portable computer, can include a removable interface module. The module can contain a device having a computer interface. The device can be a radio or a fiber optic communications device, for example. The use of such a module can facilitate repair and reconfiguration of the portable computer in the field. Such computers can be used by military personnel, police, emergency medical personnel, fire fighters, and the like. | 2013-08-22 |
20130219100 | Staggered Island Structure In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another. | 2013-08-22 |
20130219101 | COMMUNICATION WITH TWO OR MORE STORAGE DEVICES VIA ONE SAS COMMUNICATION PORT - One or more techniques and/or systems are disclosed for enabling communication between a SAS communication port of a SAS communication component and multiple storage devices. In a first example, a first SAS to SATA bridge chip and a second SAS to SATA bridge chip may be configured to route data from a SAS communication component to multiple storage devices. In a second example, a SAS to SATA bridge chip and a port multiplier may be configured to route data from a SAS communication component to multiple storage devices. In a third example, a four port SAS to SATA bridge comprising two SAS ports and two SATA ports may be configured to route data from a SAS communication component to multiple storage devices. Supporting two or more storage devices with a single SAS communication port allows storage enclosures to increase storage capacity, while decreasing cost per slot. | 2013-08-22 |
20130219102 | Local Event Ring In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring provides a communication path along which an event packet is communicated to each rectangular island along the local event ring. The local event ring involves event ring circuits and event ring segments. Upon each transition of a clock signal, an event packet moves through the ring from event ring segment to event ring segment. Event information and not packet data travels through the ring. The local event ring functions as a source-release ring in that only the event ring circuit that inserted the event packet onto the ring can delete the event packet from the ring. | 2013-08-22 |
20130219103 | Configurable Mesh Data Bus In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. | 2013-08-22 |
20130219104 | METHOD AND APPARATUS FOR COMPRESSING DATA SECTORS IN STORAGE DRIVE - A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory. | 2013-08-22 |
20130219105 | METHOD, DEVICE AND SYSTEM FOR CACHING FOR NON-VOLATILE MEMORY DEVICE - Example embodiments described herein may relate to memory devices, and may relate more particularly to caching for non-volatile memory devices. | 2013-08-22 |
20130219106 | TRIM TOKEN JOURNALING - Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up. | 2013-08-22 |
20130219107 | WRITE ABORT RECOVERY THROUGH INTERMEDIATE STATE SHIFTING - A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page. | 2013-08-22 |
20130219108 | Method, Memory Controller and System for Reading Data Stored in Flash Memory - An exemplary method for reading data stored in a flash memory. The method includes: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates an uncorrectable result; and performing the error correction operation according to the second set of LLR mapping values. | 2013-08-22 |
20130219109 | MEMORY SYSTEM AND PROGRAM METHOD THEREOF - A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner. | 2013-08-22 |
20130219110 | ELECTRONIC APPARATUSES - Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event. | 2013-08-22 |
20130219111 | SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner. | 2013-08-22 |
20130219112 | MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components. | 2013-08-22 |
20130219113 | MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes. | 2013-08-22 |
20130219114 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 2013-08-22 |
20130219115 | DELAY CIRCUIT, DELAY CONTROLLER, MEMORY CONTROLLER, AND INFORMATION TERMINAL - A delay circuit of the present disclosure includes a first delay unit and a second delay unit which are connected in series and delay an input signal to generate a delayed signal. The first delay unit includes a first signaling pathway, and changes, based on a first delay control value, a first amount of delay to be provided to the input signal by switching signaling pathways for transmitting the input signal that are within the first pathway. The second delay unit includes a second signaling pathway, and changes, based on a second delay control value, a second amount of delay to be provided to the input signal without switching the second signaling pathway for transmitting the input signal. | 2013-08-22 |
20130219116 | DATA MIGRATION FOR COMPOSITE NON-VOLATILE STORAGE DEVICE - In one embodiment, a method for managing a composite storage device made up of fast non-volatile storage, such as a solid state device, and slower non-volatile storage, such as a traditional magnetic hard drive, can include maintaining a first data structure, which stores instances of recent access to each unit in a set of units in the fast non-volatile storage device, such as the SSD device and also maintaining a second data structure that indicates whether or not units in the slower storage device, such as the HDD, have been accessed at least a predetermined number of times. In one embodiment, the second data structure can be a probabilistic hash table, which has a low required memory overhead but is not guaranteed to always provide a correct answer with respect to whether a unit or block in the slower storage device has been referenced recently. | 2013-08-22 |
20130219117 | DATA MIGRATION FOR COMPOSITE NON-VOLATILE STORAGE DEVICE - Approaches to managing a composite, non-volatile data storage device are described. In one embodiment, a method for managing a composite storage device made up of fast non-volatile storage, such as a solid state device, and slower non-volatile storage, such as a traditional magnetic hard drive, can include maintaining a first data structure, which stores instances of recent access to each unit in a set of units in the fast non-volatile storage device, such as the SSD device and also maintaining a second data structure that indicates whether or not units in the slower storage device, such as the HDD, have been accessed at least a predetermined number of times. In one embodiment, the second data structure can be a queue of Bloom filters. | 2013-08-22 |
20130219118 | RESTORE IN CASCADED COPY ENVIRONMENT - In one aspect of the present description, handling multiple backup processes comprises detecting that a defined storage volume is present in a first cascade of storage volumes; detecting that the defined storage volume is present in a second cascade of storage volumes; receiving a data write for a last storage volume in the first cascade of storage volumes; and performing a cleaning data write on the defined storage volume in the second cascade of storage volumes, wherein the cleaning data write corresponds to the received data write. Other aspects may be utilized, depending upon the particular application. | 2013-08-22 |
20130219119 | WRITING NEW DATA OF A FIRST BLOCK SIZE TO A SECOND BLOCK SIZE USING A WRITE-WRITE MODE - Apparatuses and methods to write new data of a first block size are provided. A particular method may include writing old data from a destination block of a second block size of a data drive to a first buffer of the second block size. The old data may be written according to address information of the old data and without overwriting the new data in the first buffer. The method may further include writing zeros to a second buffer of the second block size according to the address information of the old data. The zeros written in the second buffer may correspond with the old data written in the first buffer. | 2013-08-22 |
20130219120 | METHOD AND SYSTEM FOR EXECUTION OF APPLICATIONS IN CONJUNCTION WITH RAID - Systems and methods are disclosed which allow various applications which may utilize a RAID system (or other types of applications) to be executed on the same set of computing devices which implement that RAID system. More particularly, in certain embodiments a virtualization layer may be executed on a data bank. A set of desired application programs may be executed using this virtualization layer, where the context for each instance of the applications executing on the virtualization layer may be stored in a volume kept utilizing the RAID system. | 2013-08-22 |
20130219121 | METHOD AND APPARATUS FOR IMPLEMENTING A TRANSACTIONAL STORE SYSTEM USING A HELPER THREAD - A method, apparatus, and computer readable article of manufacture for executing a transaction by a processor apparatus that includes a plurality of hardware threads. The method includes the steps of: executing, by the processor apparatus using the plurality of hardware threads, a main software thread for executing the transaction and a helper software thread for executing a barrier function; and deciding, by the processor apparatus, whether or not the barrier function is required to be executed when the main software thread encounters a transactional load or store operation that requires the main software thread to read or write data. | 2013-08-22 |
20130219122 | MULTI-STAGE CACHE DIRECTORY AND VARIABLE CACHE-LINE SIZE FOR TIERED STORAGE ARCHITECTURES - A method in accordance with the invention includes providing first, second, and third storage tiers, wherein the first storage tier acts as a cache for the second storage tier, and the second storage tier acts as a cache for the third storage tier. The first storage tier uses a first cache line size corresponding to an extent size of the second storage tier. The second storage tier uses a second cache line size corresponding to an extent size of the third storage tier. The second cache line size is significantly larger than the first cache line size. The method further maintains, in the first storage tier, a first cache directory indicating which extents from the second storage tier are cached in the first storage tier, and a second cache directory indicating which extents from the third storage tier are cached in the second storage tier. | 2013-08-22 |
20130219123 | MULTI-CORE PROCESSOR SHARING L1 CACHE - A multi-core processor comprises a level 1 (L1) cache and two independent processor cores each sharing the L1 cache. | 2013-08-22 |
20130219124 | EFFICIENT DISCARD SCANS - A plurality of tracks is examined for meeting criteria for a discard scan. In lieu of waiting for a completion of a track access operation, at least one of the plurality of tracks is marked for demotion. An additional discard scan may be subsequently performed for tracks not previously demoted. The discard and additional discard scans may proceed in two phases. | 2013-08-22 |
20130219125 | CACHE EMPLOYING MULTIPLE PAGE REPLACEMENT ALGORITHMS - The present invention extends to methods, systems, and computer program products for implementing a cache using multiple page replacement algorithms. An exemplary cache can include two logical portions where the first portion implements the least recently used (LRU) algorithm and the second portion implements the least recently used two (LRU2) algorithm to perform page replacement within the respective portion. By implementing multiple algorithms, a more efficient cache can be implemented where the pages most likely to be accessed again are retained in the cache. Multiple page replacement algorithms can be used in any cache including an operating system cache for caching pages accessed via buffered I/O, as well as a cache for caching pages accessed via unbuffered I/O such as accesses to virtual disks made by virtual machines. | 2013-08-22 |
20130219126 | Wait-Free Parallel Data Cache - A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue. | 2013-08-22 |
20130219127 | CACHING DATA OBJECTS ON A CLIENT SIDE USING A PROTOTYPE CHAIN - Provided are a computer implemented method, computer program product, and system for caching a data object. A copy of an original data object to a specified depth is obtained. The copy of the original data object to the specified depth is cached with reference to the original data object in a prototype chain. A change to a value of a property of the cached copy is received. A new property entry is created for the changed value of the property under the cached copy. A change flag is set to indicate that there is a changed value for the property. | 2013-08-22 |
20130219128 | METHODS AND APPARATUS FOR REUSING SNOOP RESPONSES AND DATA PHASE RESULTS IN A BUS CONTROLLER - Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR | 2013-08-22 |
20130219129 | METHODS AND APPARATUS FOR REUSING SNOOP RESPONSES AND DATA PHASE RESULTS IN A CACHE CONTROLLER - Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data. | 2013-08-22 |
20130219130 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR INTER-CORE COMMUNICATION IN MULTI-CORE PROCESSORS - Method, apparatus, and computer program product embodiments of the invention are disclosed for efficient communication between processor units in a multi-core processor integrated circuit architecture. In example embodiments of the invention, a method comprises: storing with a shared inter-core communication unit in a multi-core processor, first data produced by a producer processor core, in a first token memory located at a first memory address of a memory address space; and connecting with the shared inter-core communication unit, the first token memory to a consumer processor core of the multi-core processor, to load the first data from the first token memory into the consumer processor core, in response to a first-type command from the producer processor core. | 2013-08-22 |
20130219131 | LOW ACCESS TIME INDIRECT MEMORY ACCESSES - An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address. | 2013-08-22 |
20130219132 | STORAGE MEDIUM STORING INFORMATION PROCESSING PROGRAM, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus | 2013-08-22 |
20130219133 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING INFORMATION PROCESSING PROGRAM - An information processing apparatus includes a detecting unit that detects a capacity of a free space of a non-volatile storage device in an apparatus including the non-volatile storage device and a volatile storage device, a determining unit that determines whether the setting of notification destination information to the non-volatile storage device is available on the basis of the detected capacity, an information setting unit that sets the notification destination information to the volatile storage device when the determining unit determines that the setting of the notification destination information to the non-volatile storage device is not available, and an interval setting unit that sets an interval of communication for management with the apparatus to be shorter than that set when it is determined that the setting of the notification destination information is available, if the determining unit determines that the setting of the notification destination information is not available. | 2013-08-22 |
20130219134 | WRITE DATA MASK METHOD AND SYSTEM - A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command. | 2013-08-22 |
20130219135 | DYNAMIC TIME REVERSAL OF A TREE OF IMAGES OF A VIRTUAL HARD DISK - A technique manages a virtual hard disk tree in a computing system executing a hypervisor to provide a client virtualization environment. The technique involves linking, by a client executing within a control virtual machine of the client virtualization environment, a first delta image of a virtual hard disk generated later in time to a base image of the virtual hard disk. The technique further involves modifying contents of the first delta image, the base image, and a second delta image which is linked to the base image; and deleting the second delta image after modifying the contents of the first delta image, the base image, and the second delta image. The base image and the first delta image, together with additional delta images of the virtual hard disk comprise a tree of images of the virtual hard disk. | 2013-08-22 |
20130219136 | STORAGE APPARATUS AND METHOD FOR CONTROLLING STORAGE APPARATUS INVOLVING SNAPSHOTS - A drop in the access performance to a source volume is prevented by executing various control methods according to the snapshot usage method. A storage apparatus comprises one or more storage devices which provide storage areas; and a controller which creates a logical volume in the storage area provided by the one or more storage devices, and which reads and writes data from/to the logical volume according to a request from a host, wherein the controller acquires one or more snapshots which are data images at certain time points of the logical volume, wherein the controller determines whether the logical volume is subject to abrupt load fluctuations on the basis of performance information of the logical volume and the snapshots, and wherein, if the logical volume is subject to abrupt load fluctuations, the controller executes predetermined control processing according to usage cases of the snapshots. | 2013-08-22 |
20130219137 | REDUNDANCY LOADING EFFICIENCY - A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors. | 2013-08-22 |
20130219138 | STORAGE SYSTEM, MANAGEMENT SERVER, STORAGE APPARATUS, AND DATA MANAGEMENT METHOD - A snapshot volume is migrated by using a primary volume of a migration destination storage apparatus. | 2013-08-22 |
20130219139 | METHODS AND SYSTEMS FOR MAINTAINING A STORAGE VOLUME WITH HOLES AND FILLING HOLES - In one embodiment, a method for managing access to a fast non-volatile storage device, such as a solid state device, and a slower non-volatile storage device, such as a magnetic hard drive, can include a method of managing a sparse logical volume in which unmapped blocks of the logical volume are not allocated until use. In one embodiment, a method of sparse hole filling operates in which range locks are dynamically adjusted to perform allocations for sparse hole filling, and then re-adjusted to perform standard operations using a byte range lock. In one embodiment, a high level data structure can be used in the range lock service in the form of an ordered search tree, which could use any search tree algorithm, such as red-black tree, AVL tree, splay tree, etc. | 2013-08-22 |
20130219140 | PERMISSIONS OF OBJECTS IN HOSTED STORAGE - A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system. | 2013-08-22 |
20130219141 | CASCADED, POINT-IN-TIME-COPY ARCHITECTURE WITH DATA DEDUPLICATION - A method for performing a write to a volume x in a cascaded architecture is described. In one embodiment, such a method includes determining whether the volume x has a child volume, wherein each of the volume x and the child volume have a target bit map (TBM) associated therewith. The method then determines whether the TBMs of both the volume x and the child volume are set. If the TBMs are set, the method finds a higher source (HS) volume from which to copy the desired data to the child volume. Finding the HS volume includes travelling up the cascaded architecture until the source of the data is found. Once the HS volume is found, the method copies the data from the HS volume to the child volume and performs the write to the volume x. A method for performing a read is also disclosed herein. | 2013-08-22 |
20130219142 | DELETING RELATIONS IN MULTI-TARGET, POINT-IN-TIME-COPY ARCHITECTURES WITH DATA DEDUPLICATION - A method for deleting a relation between a source and a target in a multi-target architecture is described. The multi-target architecture includes a source and multiple targets mapped thereto. In one embodiment, such a method includes initially identifying a relation for deletion from the multi-target architecture. A target associated with the relation is then identified. The method then identifies a sibling target that inherits data from the target. Once the target and the sibling target are identified, the method copies the data from the target to the sibling target. The relation between the source and the target is then deleted. A corresponding computer program product is also disclosed and claimed herein. | 2013-08-22 |
20130219143 | VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM - A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine. | 2013-08-22 |
20130219144 | STORAGE APPARATUS, STORAGE SYSTEM, METHOD OF MANAGING STORAGE, AND COMPUTER-READABLE STORAGE MEDIUM HAVING STORAGE MANAGEMENT PROGRAM STORED THEREON - A storage apparatus is provided, including a first storage unit; a load information obtaining unit that obtains load information for each of a plurality of portions defined by dividing the first storage unit; a portion identifying unit that identifies a candidate portion that is to be relocated in the first storage unit based on the load information; a determining unit that determines whether or not data in the candidate portion is allowed to be migrated to a second storage unit, the second storage unit having a performance value higher than a performance value of the first storage unit; an adder that adds the second storage unit, when the determining unit determines that the data in the candidate portion is not allowed to be migrated; and a relocation unit that migrates the data in the candidate portion from the first storage unit to the added second storage unit. | 2013-08-22 |
20130219145 | Method and Apparatus for Ensuring Data Cache Coherency - A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality. | 2013-08-22 |
20130219146 | METHOD, DEVICE AND SYSTEM FOR A CONFIGURABLE ADDRESS SPACE FOR NON-VOLATILE MEMORY - Example embodiments described herein may relate to memory devices, and may relate more particularly to configurable address space for non-volatile memory devices. | 2013-08-22 |
20130219147 | Multi-Core Online Patching Method and Apparatus - A multi-core online patching method and an apparatus for mapping patch data to a patch area of a shared memory are disclosed. A method of the embodiment of the present invention includes: separating shared global variables and private global variables defined in a patch; mapping the shared global variables to a shared data segment in a patch area by using a mapping mode of a direct memory address, and mapping the private global variables to private data segments in the patch area by using a mapping mode of a variable address specified by a user. The embodiments of the present invention may be used in a multi-core DSP system of telecom-grade software. | 2013-08-22 |
20130219148 | NETWORK ON CHIP PROCESSOR WITH MULTIPLE CORES AND ROUTING METHOD THEREOF - An exemplary embodiment of the present disclosure illustrates a network on chip processor including multiple cores and a Kautz NoC. Each of the cores is assigned with an addressing string with L based-D words, and the addressing string does not have two neighboring identical words, wherein L present of an addressing string length is an integer larger than 1, D present of a word selection is an integer larger than 2. Each of the cores is unidirectionally link to other (D−1) cores through the Kautz NoC, and in the two connected cores, the last (L−1) words associated with the addressing string of one core are same as the first (L−1) words associated with the addressing string of the other core. | 2013-08-22 |
20130219149 | OPERAND SPECIAL CASE HANDLING FOR MULTI-LANE PROCESSING - A single instruction multiple data processing pipeline | 2013-08-22 |
20130219150 | Parsing Data Representative of a Hardware Design into Commands of a Hardware Design Environment - A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment. | 2013-08-22 |
20130219151 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 2013-08-22 |
20130219152 | INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE - A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode. | 2013-08-22 |
20130219153 | Load/Move and Duplicate Instructions for a Processor - A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register. | 2013-08-22 |
20130219154 | CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS - Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction. | 2013-08-22 |
20130219155 | Pre-installed Application Activation - Pre-installed application activation techniques are described in which live content for applications is activated before user interaction with the applications. Input indicative of an initial log-in of a user to access an operating system is detected. In response, configuration of an account for the user with the operating system may be initiated to set-up a device for first use by the user. During the configuration, notifications are activated through a notification system of the operating system to obtain live content for one or more pre-installed applications on the computing device. The activation occurs before interaction of the user with the pre-installed applications. Live content may then be incorporated with representations of the applications within a user interface for the operating system, such as displaying application tiles having corresponding live content in a start screen presented to the user after completion of the initial set-up. | 2013-08-22 |
20130219156 | COMPLIANCE AWARE CHANGE CONTROL - A Configuration Management System (or CMS) assists with ensuring compliance when changes are proposed to be made to the infrastructure elements of a data center. Configuration state information is collected and stored as a set of features and feature attributes. Specified actions that may be taken with the infrastructure elements are preferably stored in a library. Projected configuration snapshots are determined and compared against compliance policies associated with each infrastructure element. Compliance checks that fail are preferably presented to a user who may then implement additional actions to compensate for the failure and then again request compliance testing. Compliance checks that pass they be stored in a queue waiting to then be further implemented by a human the demonstrator for automated agent when appropriate. | 2013-08-22 |
20130219157 | MOBILE TERMINAL AND CONTROLLING METHOD THEREOF - A mobile terminal and controlling method thereof are disclosed, by which a setting of a low power wireless communication module can be automatically reseted if the mobile terminal is turned on. The present invention includes a power supply unit, an application processor, a low power wireless communication module configured to maintain an active state by being supplied with the power from the power supply unit despite that the mobile terminal is in an inactive state, the low power wireless communication module set to be cut off a signal inputted from the application processor if the application processor is in the inactive state, and a reset circuit receiving a trigger signal from the application processor after activation of the application processor, the reset circuit resetting a setting of the low power wireless communication module based on the trigger signal. | 2013-08-22 |
20130219158 | Method for Monitoring Changes of Configuration of a Control Device of an Automatic Machine - In an automatic machine controlled by a control device of its own having at least one non-volatile memory, in which a program for controlling the automatic machine can be installed, and at least one processing module for executing the control program installed, the control device is programmed with an operating system designed for implementing a method for monitoring the changes of configuration of the control device, in which each event of installation of a new control program in the memory is detected, execution of the control program installed last is enabled, and each new control program that is installed is saved, together with corresponding installation data, in at least one archive memory portion of the memory. | 2013-08-22 |
20130219159 | SINGLE-WIRE BOOTLOADER FOR TARGET DEVICE WITH SELF-PROGRAMMING CAPABILITY - A single-wire bootloader software architecture is disclosed that interfaces with any host device that has a serial port to program memory of a target device using only a single general-purpose I/O pin. The single-wire bootloader does not require any chip hardware resource modules. Instead, the single-wire bootloader implements a single-wire UART in software that monitors a single general-purpose I/O pin for commands from the host device. | 2013-08-22 |
20130219160 | SYSTEM AND METHOD FOR BOOTING UP A COMPUTER BASED ON DATA CAPTURED IN A NON-VOLATILE SEMICONDUCTOR MEMORY DURING A LEARN MODE - A system includes a timer and a control module. The control module: in response to a first request for first data, determines whether the first data is stored in a non-volatile semiconductor memory (NVSM); in response to the first data not being stored in the NVSM, (i) loads the first data from a hard disk drive (HDD) and boots up a computer a first time based on the first data, and (ii) while operating in a learn mode and while loading the first data from the HDD, captures a portion of the first data in the NVSM; in response to the timer indicating an end of a period during which the computer is booted up the first time, ceases the capturing of the first data; and based on the portion of the first data captured in the NVSM during the learn mode, boots up the computer a second time. | 2013-08-22 |
20130219161 | Direct Migration of Software Images with Streaming Technique - A mechanism is provided for migrating a software image installed on a source data-processing entity to a target data-processing entity. The target data-processing entity is booted from a preliminary bootstrap program. The software image is mounted as a remote mass memory on the target data-processing entity. A primary bootstrap program of the software image is copied onto a local mass memory of the target data-processing entity. The target data-processing entity is re-booted from the primary bootstrap program thereby loading a streaming function, and serving each request of accessing a memory block on the target data-processing entity by the streaming function. In response to the memory block missing from the local mass storage, the streaming function downloads the memory block from the software image and stores the memory block into the local mass memory. Otherwise, the streaming function retrieves the memory block from the local mass memory otherwise. | 2013-08-22 |
20130219162 | UNIFIED DESKTOP WAKE AND UNLOCK - Methods and devices for selectively presenting a user interface or “desktop” across two devices are provided. More particularly, a unified desktop is presented across a device and a computer system. The unified desktop acts as a single user interface that presents data and receives user interaction in a seamless environment that emulates a personal computing environment. To function within the personal computing environment, the unified desktop includes a sleep state where both the device and computer system become inactive. The unified desktop may be awakened by one of numerous actions by the unified system or the user. | 2013-08-22 |
20130219163 | SYSTEMS AND METHODS FOR SCHEDULING CHANGES - The present disclosure includes a system and method for scheduling changes. In an example of scheduling changes according to the present disclosure, a usage pattern of a number of services ( | 2013-08-22 |
20130219164 | CLOUD-BASED HARDWARE SECURITY MODULES - A cloud-based hardware security device (HSM) providing core security functions of a physically controlled HSM, such as a USB HSM, while allowing user access within the cloud and from a user device, including user devices without input ports capable of direct connection to the HSM. The HSMs can be connected to multi-HSM appliances on the organization or user side of the cloud network, or on the cloud provider side of the cloud network. HSMs can facilitate multiple users, and multi-HSM appliances can facilitate multiple organizations. | 2013-08-22 |
20130219165 | SYSTEM AND METHOD FOR PROCESSING FEEDBACK ENTRIES RECEIVED FROM SOFTWARE - A method and system for processing feedback entries received from software provided by a vendor to an end user machine. The end user machine includes the software, a feedback module, and a database. The feedback module: generates an encryption E | 2013-08-22 |
20130219166 | HARDWARE BASED IDENTITY MANAGER - A method for providing authentication credentials to a server over a communications network includes initiating communication with a server over a communications network. The communication is to be established using a secure connection. A message is received from the server over the communications network as well as a request for a digital certificate associated with a first user account accessible to the server. An encrypted private key is decrypted in a secure hardware module to obtain a decrypted private key. The decrypted private key is associated with the first user account. The message received from the server is passed to the secure hardware module. The message is digitally signed in the secure hardware module using the decrypted private key. The digital certificate and the digitally signed message are sent to the server over the communication network. | 2013-08-22 |
20130219167 | NETWORK NODE WITH NETWORK-ATTACHED STATELESS SECURITY OFFLOAD DEVICE EMPLOYING IN-BAND PROCESSING - A network node for communicating data packets secured with a security protocol over a communications network includes a host information handling system (IHS) and one or more external security offload devices coupled by a secure data link. The host IHS communicates state information about data packets, and the external offload security device provides stateless secure data encapsulation and decapsulation of packets using a security protocol. An external network interface controller or internal network interface controller communicates encapsulated data packets over the communications network to a final destination. Encapsulation and decapsulation of packets by the external security offload device reduces network latency and reduces the computational load on the processor in the host IHS. Maintaining state information in the host IHS allows hot-swapping of external security offload devices without information loss. The external security offload device may be included in a firewall, or intrusion detection device, and may implement IPsec protocol. | 2013-08-22 |
20130219168 | NETWORK NODE WITH NETWORK-ATTACHED STATELESS SECURITY OFFLOAD DEVICE EMPLOYING OUT-OF-BAND PROCESSING - A network node for communicating data packets secured with a security protocol over a communications network includes a host information handling system (IHS) and one or more external security offload devices coupled by a secure data link. The host IHS communicates state information about data packets, and the external offload security device provides stateless secure data encapsulation and decapsulation of packets using a security protocol. An external network interface controller or internal network interface controller communicates encapsulated data packets over the communications network to a final destination. Encapsulation and decapsulation of packets by the external security offload device reduces network latency and reduces the computational load on the processor in the host IHS. Maintaining state information in the host IHS allows hot-swapping of external security offload devices without information loss. The external security offload device may be included in a firewall, or intrusion detection device, and may implement IPsec protocol. | 2013-08-22 |
20130219169 | Public Cloud Data at Rest Security - An encryption switch which is used in a cloud environment to secure data on the LUNs used by the clients. A client provides a certificate to the cloud service. The encryption switch develops a cloud crypto domain (CCD) as a secure area, with the data at rest on the LUNs encrypted. The encryption switch develops a master key for client use in the CCD, which is provided to the client encrypted by the client's public key. Data encryption keys (DEKs) are created for each LUN and provided to the client. The DEKs are stored in a key vault by the client for use if needed. The cloud service provisions a client VM to be used with the encrypted LUN and develops a nexus between the LUN and the client VM for the encryption switch to use in data operations. The client communicates through the client VM to access the LUN. | 2013-08-22 |
20130219170 | DATA COMMUNICATION AUTHENTICATION SYSTEM FOR VEHICLE GATEWAY APPARATUS FOR VEHICLE DATA COMMUNICATION SYSTEM FOR VEHICLE AND DATA COMMUNICATION APPARATUS FOR VEHICLE - A vehicular data communication system is disclosed. The vehicular data communication system includes an authentication device for authenticating an external tool connected to a bus, an authentication control device for determining whether an external tool is authenticated by the authentication device and for setting an authenticated state to permit a data communication between the external tool and an access target ECU on the bus upon determining that the external tool is authenticated by the authentication device, and an authentication maintain device for maintaining the authenticated state within a predetermined period after the authenticated state is set by the authentication control device. | 2013-08-22 |
20130219171 | NETWORK NODE WITH NETWORK-ATTACHED STATELESS SECURITY OFFLOAD DEVICE EMPLOYING IN-BAND PROCESSING - A network node for communicating data packets secured with a security protocol over a communications network includes a host information handling system (IHS) and one or more external security offload devices coupled by a secure data link. The host IHS communicates state information about data packets, and the external offload security device provides stateless secure data encapsulation and decapsulation of packets using a security protocol. An external network interface controller or internal network interface controller communicates encapsulated data packets over the communications network to a final destination. Encapsulation and decapsulation of packets by the external security offload device reduces network latency and reduces the computational load on the processor in the host IHS. Maintaining state information in the host IHS allows hot-swapping of external security offload devices without information loss. The external security offload device may be included in a firewall, or intrusion detection device, and may implement IPsec protocol. | 2013-08-22 |
20130219172 | SYSTEM AND METHOD FOR PROVIDING A SECURE BOOK DEVICE USING CRYPTOGRAPHICALLY SECURE COMMUNICATIONS ACROSS SECURE NETWORKS - A gateway device is used to control the flow of data to and from a network. To ensure that a message is not transmitted beyond the edge of an intranet without authorization such as outside of a private network, or to a device within the private network without authorization, a gateway will only establish a communication session with a computing device within the private network that possess a requisite community-of-interest key. If either the gateway device or computing device does not possess a matching community-of-interest key then a communication session cannot be established between the computing device and gateway device. Other aspects include transmitting a message destined for another network by converting it into a format in which it can be received outside the private network without knowledge of the type of security measures used within the private network. | 2013-08-22 |