34th week of 2008 patent applcation highlights part 39 |
Patent application number | Title | Published |
20080199943 | Material Solubiliser Reactor For Hydrolysis and/or Wet Fermentation and Waste Treatment Plant With Such a Solubiliser and Reactor - The invention relates to a method for the treatment of waste with organic components, whereby in standardized method steps, various material solubilisers, for dissolving the organic material in a solvent and various reactors for carrying out a hydrolysis and/or a wet fermentation are used depending on the particle size and suitable solubilisers and reactors. A suitable waste treatment plant is also disclosed. | 2008-08-21 |
20080199944 | Pressure Controllable Incubation System - A pressure controllable incubation system is provided for constantly maintaining a concentration of carbon dioxide while keeping a pressure chamber, in which living organisms to be cultured are placed, at a pressure higher than atmospheric pressure. The pressure controllable incubation system comprise a bomb that stores air containing high-concentration carbon dioxide to be injected into a pressure chamber and supplies the air into the pressure chamber, and a heat controller that constantly maintains temperature in the pressure chamber. The pressure controllable incubation system constantly maintains culture conditions such as pressure, temperature, and concentration of carbon dioxide which the user wants for a long time, so that it can be effectively applied to the culture of various living organisms. | 2008-08-21 |
20080199945 | CANTILEVER FOR MEASURING INTRA-CELLULAR AND INTER-CELLULAR MICROSPACES - A cantilever for measuring intra-cellular and inter-cellular microspaces of the present invention includes a support portion, a lever portion provided to the support portion so as to protrude therefrom, and a probe portion provided near a free end of the lever portion. The probe portion includes a conductive probe made of a carbon-based material, and an insulating film to coat a periphery of the conductive probe. | 2008-08-21 |
20080199946 | Biochip - The present invention relates to a biochip for nucleic acid hybridization. The biochip of the present invention comprises a hybridization chamber which is in the form of a cavity, a porous matrix pressed in the hybridization chamber; and at least one first circulation hole and at least one second circulation hole which are communicated with the hybridization chamber so that the reaction solution flows in the at least one first circulation hole and flows out the at least one second circulation hole through the pores of the porous matrix. The hybridization reaction area is increased by flowing the reaction solution through the pores of the membrane, which enable the reaction sensitivity to be increased. The diffusion distance for the reaction molecules is decreased due to the limited inside space of the membrane, and thereby the hybridization time is shortened. | 2008-08-21 |
20080199947 | Blood cell analyzer, blood cell analyzing method, and computer program product - A blood cell analyzer is provided with a first detection unit for electrically detecting blood cells in blood sample; a second detection unit for optically detecting blood cells in blood sample; a volume information obtainer for obtaining volume information of red blood cells based on the electrically detected blood cells; a scattered light intensity information obtainer for obtaining a scattered light intensity of red blood cells based on the optically detected blood cells; a first histogram preparer for preparing a first histogram of the volume information of each of red blood cells; a second histogram preparer for preparing a second histogram of the scattered light intensity information of each of red blood cells; a display unit; and a data processor for preparing a screen for displaying on the display unit, the screen including the first and second histograms. | 2008-08-21 |
20080199948 | SYSTEM FOR DETECTING INFECTIOUS AGENTS USING COMPUTER-CONTROLLED AUTOMATED IMAGE ANALYSIS - A method for recognizing an object in an image is disclosed wherein a fractal map of the image is generated by estimating the fractal dimension of each pixel in the image. The fractal map may be segmented by thresholding and locations of candidate objects are determined. The pixel value of the image pixel corresponding to the same location where the candidate object is found in the fractal map may be compared to a threshold value. If the pixel value is greater than the threshold value, the candidate object is recognized as a valid object. | 2008-08-21 |
20080199949 | DEVICE FOR SAMPLING BLOOD DROPLETS UNDER VACUUM CONDITIONS - A blood extraction device ( | 2008-08-21 |
20080199950 | Enhanced Bio-Assays By Using Gradient Nanotopgraphy - ABSTRACT A system and method for using gradient nanotopography to increase mammalian cell attachment and cell confinement on surfaces. A surface platform consisting of a thin film of gold possessing a gradient of topography on the surface and self-assembled monolayers of alkanethiols presenting desired functional groups is formed. A gradient in the chemical properties is induced in the terminal groups of the monolayer because of the continuous increase in the surface area and the anisotropy of gold film structure. The gradient nanotopraphy provides simultaneous control of two key properties, the presentation of the terminal functional groups and a continuous increase in the surface density of functional groups on the surface. This control provides for drug screening assays using adherent cell-based experiments. | 2008-08-21 |
20080199951 | Device for the Storage and Treatment of Biodegradable Wet Solid Waste - The present invention relates to a device for the storage and treatment of biodegradable wet solid waste, especially for vegetarian household waste materials. The device consists of a bucket shaped container with a mesh bottom and a removable cover with a hole at the center. The container is provided with a leachate collection basket at the bottom, which is mounted on an iron stand to hold the device. Openings are provided on the lateral surface of the basket for ventilation. The waste is added to the container from the top by hand lifting the lid. The ventilation facilitates degradation of the material in side the container, reducing the release of odour and, leachate. The volume of the waste also gets reduced because of self-compaction. In one embodiment the storage and treatment device is provided in the form of a house hold kit. | 2008-08-21 |
20080199952 | COMPOSITIONS AND METHODS FOR TREATING OR PREVENTING PNEUMOCOCCAL INFECTION - The invention provides polypeptides, polysaccharide-polypeptide conjugates, and expression vectors for treating or preventing pneumococcal infection. The compositions induce an anti-pneumococcal immune response when administered to a mammal. The compositions can be used prophylactically to vaccinate an individual and/or therapeutically to induce a therapeutic immune response in an infected individual. | 2008-08-21 |
20080199953 | SYSTEM AND METHOD FOR FORMING A CONNECTIVE TISSUE CONSTRUCT - A system and method are provided for forming a connective tissue construct, such as a tendon construct, in vitro. A substrate is provided with at least two anchors secured thereto in spaced relationship. Fibroblast cells are provided on the substrate in the absence of a synthetic matrix, where at least some of the cells are in contact with the anchors. The cells are cultured in vitro under conditions to allow the cells to self-organize and become confluent between the anchors, where the anchors are receptive to the cells and allow the cells to attach thereto while permitting the cells to detach from the substrate to form a three-dimensional connective tissue construct. | 2008-08-21 |
20080199954 | METHODS FOR SORTING DIMORPHIC DAUGHTER CELLS - This invention relates to methods for distinguishing and sorting cells. In particular it includes methods for distinguishing and sorting post-mitotic and post-meiotic daughter cells into two classes according to differential cellular features. Labeling, tagging, or marking of the cells' chromatin proteins, RNA, or DNA may assist in distinguishing the daughter cells. In some embodiments, two cell classes may be studied and the cells' proteins, glycoproteins, and RNA may be identified and subset. Information from these subsets may then be used to distinguish and sort the two classes of cells from similar tissues according to protein, glycoprotein, and RNA makeup. | 2008-08-21 |
20080199955 | Tissue Infiltration Apparatus - A tissue infiltration apparatus ( | 2008-08-21 |
20080199956 | Storage Medium For Cells - The invention relates to a method for storages of human cells in particular, cell media for storage of cells and the use of such cell media for storage of cells, wherein the vitality of the cells is preserved during the storage. | 2008-08-21 |
20080199957 | ENHANCED TRANSPORT USING MEMBRANE DISRUPTIVE AGENTS - Compositions and methods for transport or release of therapeutic and diagnostic agents or metabolites or other analytes from cells, compartments within cells, or through cell layers or barriers are described. The compositions include a membrane barrier transport enhancing agent and are usually administered in combination with an enhancer and/or exposure to stimuli to effect disruption or altered permeability, transport or release. In a preferred embodiment, the compositions include compounds which disrupt endosomal membranes in response to the low pH in the endosomes but which are relatively inactive toward cell membranes, coupled directly or indirectly to a therapeutic or diagnostic agent. Other disruptive agents can also be used, responsive to stimuli and/or enhancers other than pH, such as light, electrical stimuli, electromagnetic stimuli, ultrasound, temperature, or combinations thereof. The compounds can be coupled by ionic, covalent or H bonds to an agent to be delivered or to a ligand which forms a complex with the agent to be delivered. Agents to be delivered can be therapeutic and/or diagnostic agents. Treatments which enhance delivery such as ultrasound, iontophoresis, and/or electrophoresis can also be used with the disrupting agents. | 2008-08-21 |
20080199958 | Suspension Culture Vessels - A cell culture vessel comprising a housing chamber which has an inverted frusto-conical bottom having a vertical axis. The culture vessel further comprises an upper and lower section which are concentric. The vessel requires little or no shear-force and less stress by shaking or impellor action. | 2008-08-21 |
20080199959 | Method For Cell Culture - The present invention relates to a method for cell culture, more precisely small scale cell culture. In the present invention a screening tool is used which comprises particulate matter or microcarriers, such as beads, attached to a solid support, such as a microtiter plate, for the cultivation of cells on said microcarriers. The microcarriers are preferably cultivation beads, such as CYTODEX™. According to the invention, this small scale format for cell cultivation may be used for any testing involving cells, for example testing of optimal growth conditions for a specific type of cell, such as stem cells. Another use is cell expansion. | 2008-08-21 |
20080199960 | Methods for the Delivery of Oligomeric Compounds - The presently disclosed subject matter relates to the delivery of oligonucleotides to cells through the delivery of a composition or reagent comprising a hybridization complex comprising a first antisense oligonucleotide which is modified to have a higher stability against degradation, and a second sense oligonucleotide which is prone to degradation. The presently disclosed subject matter furthermore relates to dendrimeric bioconjugates and compositions or reagents comprising them, wherein the bioconjugate comprises a conjugate moiety coupled to a dendrimeric structure and to their use to deliver oligomeric compounds including oligonucleotides or duplexes, as described above, to cells for modulation of gene expression (i.e. antisense or antigene therapy/research, RNA interference). | 2008-08-21 |
20080199961 | ANTISENSE COMPOSITION AND METHOD FOR INHIBITION OF miRNA BIOGENESIS - The present disclosure relates to compounds and methods for inhibiting the formation of miRNAs that inhibit translation of one or more identified proteins. The compounds comprise antisense oligonucleotides targeting the pri-miRNA precursor of miRNAs. | 2008-08-21 |
20080199962 | Qualitative Assay of Extra-Virgin Olive Oils - A methodology that enables introduction of an innovative assay for evaluating the extra-virgin olive oil (EOO), based upon the quantification of the main components of the saponifiable and non-saponifiable fractions of EOOs and upon its total antioxidizing power. | 2008-08-21 |
20080199963 | Method of Determining Acid Content - A method for determining the TAN value of a hydrocarbon-containing composition, in which the sample is cleared of free water, heated to an elevated temperature in an oxygen free environment, conditioned at the elevated temperature for an extended period of time, cooled down to a temperature near to room temperature, and titrated against alcoholic potassium hydroxide, whereby the TAN value may be calculated. | 2008-08-21 |
20080199964 | SITE-SPECIFIC INSTALLATION OF METHYL-LYSINE ANALOGUES INTO RECOMBINANT HISTONES - The present invention provides reagents and methods for the introduction of analogues of methyl or acetyl lysine into histone proteins. | 2008-08-21 |
20080199965 | Method For The Identification Of Proteins Folding Inhibitors - The present invention relates to a method for the identification of peptide inhibitors of the folding and thus of the biological function(s) of proteins which do not create resistance. In particular, the invention relates to inhibitors of viral enzymes with a high mutation rate. | 2008-08-21 |
20080199966 | Vitro Method For the Diagnosis of Neurodegenerative Diseases - An in vitro method for the detection, determination of severity and monitoring and prognosis of neurodegenerative diseases is disclosed. The presence and/or concentration of the physiologically inactive proadrenomedullin (proADM) partial peptide, in particular, the midregional proADM partial peptide, is determined in a biological fluid of a patient who is suffering from a neurodegenerative disease or is suspected of having such a disease. Conclusions about the presence, course, severity or success of a treatment of the neurodegenerative disease are drawn on the basis of the presence and/or concentration of the specific partial peptide in the biological sample. | 2008-08-21 |
20080199967 | System for Detection of S-Nitrosoproteins - The present invention describes a novel, simplified method for detecting and monitoring the presence of nitrosylated proteins, such as S-nitrosoproteins, in a biological sample using fluorescence detection. The present invention further describes a method which can both quantify and identify the nature of nitrosylated proteins, which method is useful for monitoring both normal and disease states, in the development and screening of potential therapeutic drug species. | 2008-08-21 |
20080199968 | Method of Forming Signal Probe-Polymer - To solve a problem occurring in the PALSAR method that a polymer would be formed in the state of unbound to a captured test gene and thus affect the quantitative characteristics as a nonspecific signal, it is intended to develop a technique whereby the polymer formation is controlled in the step of forming an assembly (polymer) of probes so that the polymer is formed exclusively on a test gene to thereby improve the sensitivity and quantitative characteristics. It is found that the polymer can be quantitatively formed and a nonspecific reaction can be inhibited by, in the step of forming a polymer by reacting plural kinds of probes having abilities to complementarily bind to each other, not adding or reacting these probes at once but starting with the reaction of a first probe in one group, and then reacting the second probe in the other group followed by the reactions of probes one by one (i.e., the first probe, the second probe, and so on). | 2008-08-21 |
20080199969 | METHOD OF MONITORING BULK (TOTAL) MICROBIOLOGICAL ACTIVITY IN PROCESS STREAMS - An apparatus and method for monitoring and controlling microbiological activity in a process stream by measuring dissolved oxygen is disclosed. | 2008-08-21 |
20080199970 | Chemical Sensing Device - This invention relates to a chemical sensing device for detecting an analyte. The device comprises a light source; at least one luminescent reagent which is capable of luminescing when irradiated by the light source wherein the luminescence of the luminescent reagent is modifiable by the analyte thereby changing the generation of heat, which change in heat generation is proportional to the concentration of the analyte, a transducer having a pyroelectric or piezoelectric element and electrodes which is capable of transducing the change in heat to an electrical signal, and a detector which is capable of converting the electrical signal into an indication of the concentration of the analyte. The invention also relates to a method for detecting an analyte. | 2008-08-21 |
20080199971 | Integrated Membrane Sensor - An integrated microelectronic sensor is provided in a disposable flow membrane sensing device. The integrated sensors detect electromagnetic effect labels in flow detection zones above the sensor in the membrane. The labels are small particles that give off a detectable electromagnetic signal. They are commonly used for isolating and quantifying biochemical targets of interest. The sensors are fabricated using planar integrated circuit technologies. Sensors can detect labels of several types including magnetic, electric, and photonic. These types all have in common the fact that the sensor detects the label at a distance. Magnetoresistive sensors for detecting magnetic labels, and photodiodes for detecting photonic labels are described. | 2008-08-21 |
20080199972 | Spectroscopic Method For the Detection of Analytes - The present invention relates to methods for the detection of one or more analytes, in particular pathogens, viruses, prions, bacteria, parasites, pharmaceuticals, antibiotics, cytostatics, psychoactive substances, narcotics, analgesics, cardiac drugs, metabolites, coagulation inhibitors, hormones, interleukins and cytokines, performance-enhancing drugs, drugs, toxins, noxious substances, pesticides, insecticides, wood preservatives, herbicides, fungicides, explosives, vitamins and flavors by providing a conjugate of the analyte and an europium cryptate fluorophore or respectively a terbium cryptate fluorophore together with an antibody which is specific for the analyte and an antibody which is specific for the europium cryptate fluorophore or respectively the terbium cryptate fluorophore and by spectroscopically determining the fluorescence quenching which occurs when the analyte is added. Furthermore the present invention relates to conjugates of the analyte and the europium cryptate fluorophore or respectively terbium cryptate fluorophore as well as to a kit for the detection of analytes. | 2008-08-21 |
20080199973 | HYDROPHILIC CHEMILUMINESCENT ACRIDINIUM LABELING REAGENTS - In accordance with the present invention, it has been discovered that introduction of hydrophilic sulfoalkyl substituents and/or hydrophilic linkers derived from homocysteic acid, cysteic acid, glycine peptides, tetraethylene oxide, and the like, offset the hydrophobicity of the acridinium ring system to produce a more soluble label which can be attached to an antibody at higher loading before precipitation and aggregation problems are encountered. Additional compounds described herein contain linkers derived from short peptides and tetraethylene oxide which increase aqueous solubility due to hydrogen bonding with water molecules. The present invention also embraces reagents for multiple acridinium labeling for signal amplification composed of a peptide bearing several acridinium esters with sulfonate groups at regularly spaced intervals for increased solubility. The invention also embraces assays employing the above-described compounds. | 2008-08-21 |
20080199974 | Method for Functionalizing Biosensor Chips - A met4hod is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies. | 2008-08-21 |
20080199975 | METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern. | 2008-08-21 |
20080199976 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device manufacturing method has a step forming a transistor layer portion on a semiconductor substrate, and a step forming a ferroelectric capacitor portion including a lower electrode, a ferroelectric substance and an upper electrode above the transistor layer portion, wherein the step forming the ferroelectric capacitor portion includes adjusting an area of the upper electrode on the basis of manufacturing parameters of the ferroelectric capacitor portion. | 2008-08-21 |
20080199977 | Activated Chemical Process for Enhancing Material Properties of Dielectric Films - A method for restoring a dielectric constant of a layer of a silicon-containing dielectric material having a first dielectric constant and at least one surface, wherein the first dielectric constant of the layer of silicon-containing dielectric material has increased to a second dielectric constant, the method comprising the steps of: contacting the at least one surface of the layer of silicon-containing dielectric material with a silicon-containing fluid; and exposing the at least one surface of the layer of silicon-containing dielectric material to an energy source selected from the group consisting of: UV radiation, heat, and an electron beam, wherein the layer of silicon-containing dielectric material has a third dielectric constant that is lower than the second dielectric constant after exposing the layer of silicon-containing dielectric material to the energy source. | 2008-08-21 |
20080199978 | System and method for film stress and curvature gradient mapping for screening problematic wafers - A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer. | 2008-08-21 |
20080199979 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Method of manufacturing a semiconductor device, including: preparing a TAB tape featuring an insulating tape having a device hole and a plurality of holes, a plurality of leads formed on a surface of the tape and extending at one end into the device hole and at the other end into the holes, slits provided inside arrangements of columns of holes, and a warp prevention reinforcement insulating film to hold the leads between it and the tape; connecting front ends of the leads to the electrodes of the chip; forming an encapsulant to enclose the chip, the leads and a portion of the tape; forming thick bump electrodes on that surface side of the leads running through the holes to which the semiconductor chip is connected; performing an electric characteristic test, using the bump electrodes as measuring terminals; and cutting the TAB tape to a predetermined shape. | 2008-08-21 |
20080199980 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. | 2008-08-21 |
20080199981 | METHOD FOR FORMING A FLUID EJECTION DEVICE - A method of forming a fluid ejection device includes forming a pair of first glass layers and forming a second glass layer. Each first glass layer includes a first side and a second side with the second side defining a first fluid flow structure. The second glass layer includes a first side and a second side opposite the first side, with each respective first side and second side defining a second fluid flow structure. The second glass layer is bonded in a sandwiched position between the respective first glass layers with each respective second fluid flow structure of the second glass layer in fluid communication with the respective first fluid flow structure of the respective first glass layers to define a fluid flow pathway for ejecting a fluid. | 2008-08-21 |
20080199982 | Fabrication Process for Package With Light Emitting Device On A Sub-Mount - A method of fabricating a package with a light emitting device includes depositing a first metallization to form a conductive pad on which the light emitting device is to be mounted and to form one or more feed-through interconnections extending through a semiconductor material that supports the conductive pad. Subsequently, a second metallization is deposited to form a reflective surface for reflecting light, emitted by the light emitting device, through a lid of the package. Deposition of the second metallization is de-coupled from deposition of the first metallization. | 2008-08-21 |
20080199983 | METHOD FOR MANUFACTURING A SEMICONDUCTOR LASER - A method of manufacturing semiconductor laser device including a GaN wafer includes forming a semiconductor layer on the GaN wafer and on which ridge portions are formed. Grooves are formed in the semiconductor layer such that each groove is disposed in line with the scribe marks, between each of the ridge portions and an upstream scribe mark. The grooves are curved and convex outwardly towards a downstream side, and each groove has an apex on a cleavage line. The side extending from the apex preferably does not form an angle of 60 degrees with respect to a cleavage direction or the cleavage line. | 2008-08-21 |
20080199984 | OLED PATTERNING METHOD - A method of forming a patterned, light-emitting device that includes mechanically locating a first masking film over a substrate; forming first openings in first locations in the masking film; and depositing first light-emissive materials over the substrate through the first openings in the first masking film. Subsequent steps include mechanically removing the first masking film; mechanically locating a second masking film over the substrate in a position that prevents particulate contamination in the first locations; and forming second openings in the second masking film. The second openings are in different locations over the substrate than the first openings. The first locations are protected from particulate contamination resulting from the formation of the second openings. Additional steps include depositing second light-emissive materials over the substrate through the second openings in the second masking film; and mechanically removing the second masking film. | 2008-08-21 |
20080199985 | LEADFRAME ENHANCEMENT AND METHOD OF PRODUCING A MULTI-ROW SEMICONDUCTOR PACKAGE - A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads. | 2008-08-21 |
20080199986 | METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP - A method (and apparatus) of assembling a die on an electronic substrate, includes processing an assembly including a substrate and a die, and during the processing, introducing a pre-stress to the assembly during a cure process. | 2008-08-21 |
20080199987 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF LEAD FRAME - Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented. | 2008-08-21 |
20080199988 | CONDUCTIVE PATTERN FORMATION METHOD - The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip. | 2008-08-21 |
20080199989 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein is a method of manufacturing a semiconductor device having a thyristor formed by joining a first p-type semiconductor layer, a first n-type semiconductor layer, a second p-type semiconductor layer, and a second n-type semiconductor layer in order, the method including the steps of: forming the second p-type semiconductor layer including a p-type impurity in a surface layer of a semiconductor substrate; forming the first n-type semiconductor layer including an n-type impurity on the semiconductor substrate including the second p-type semiconductor layer by epitaxial growth; forming a non-doped semiconductor layer on the first n-type semiconductor layer by epitaxial growth; and forming the first p-type semiconductor layer including a p-type impurity on the non-doped semiconductor layer by epitaxial growth. | 2008-08-21 |
20080199990 | Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material. | 2008-08-21 |
20080199991 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug. | 2008-08-21 |
20080199992 | DISPLAY DEVICE, MANUFACTURING METHOD THEREOF, AND TELEVISION RECEIVER - The present invention discloses a method for manufacturing a display device comprising the steps of forming a first film pattern using a photosensitive material over a substrate, forming a second film pattern in such a way that the first film pattern is exposed by being irradiated with a laser beam, modifying a surface of the second film pattern into a droplet-shedding surface, forming a source electrode and a drain electrode by discharging a conductive material to an outer edge of the droplet-shedding surface by a droplet-discharging method, and forming a semiconductor region, a gate-insulating film, and a gate electrode over the source electrode and the drain electrode. | 2008-08-21 |
20080199993 | Protective layer in device fabrication - An improved method for fabricating an HEMT device having active device layers deposited on a semiconductor substrate. In an embodiment, the improved method comprises the steps of depositing an AlN layer over the active device layers using a relatively low temperature vacuum process to form an amorphous layer protecting the active device layers from unnecessary exposure to fabrication processes, and selectively forming openings in the AlN layer to expose portions of the active device layers for imminent process steps. | 2008-08-21 |
20080199994 | Method of Producing Semiconductor Device and Semiconductor Device - A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films is kept thin. | 2008-08-21 |
20080199995 | Integrated Hydrogen Anneal and Gate Oxidation for Improved Gate Oxide Integrity - A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between annealing and forming the dielectric layer, the semiconductor substrate is maintained in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer. | 2008-08-21 |
20080199996 | METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE - A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters. | 2008-08-21 |
20080199997 | Methods of Forming Inter-poly Dielectric (IPD) Layers in Power Semiconductor Devices - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 2008-08-21 |
20080199998 | PRE-EPITAXIAL DISPOSABLE SPACER INTEGRATION SCHEME WITH VERY LOW TEMPERATURE SELECTIVE EPITAXY FOR ENHANCED DEVICE PERFORMANCE - The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses. | 2008-08-21 |
20080199999 | Formation of a Selective Carbon-Doped Epitaxial Cap Layer on Selective Epitaxial SiGe - A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region. | 2008-08-21 |
20080200000 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - After the formation of element isolation insulating films, an n-well, and a p-well on a Si substrate, the Si substrate is subjected to cleaning (step S | 2008-08-21 |
20080200001 | METHOD OF PRODUCING A TRANSISTOR - Method of producing a transistor, comprising in particular the steps of: | 2008-08-21 |
20080200002 | Plasma Sputtering Film Deposition Method and Equipment - A method for generating metal ions by sputtering a metal target ( | 2008-08-21 |
20080200003 | Method for Forming Multi-Layered Binary Oxide Film for Use in Resistance Random Access Memory - The invention relates to a method for forming a multi-layered binary oxide film for ReRAM. The method includes forming a lower electrode layer on a substrate; forming a metal layer on the lower electrode layer in a vacuum atmosphere; oxidizing the metal layer into a binary oxide film in a vacuum atmosphere; repeating the steps of forming and oxidizing the metal layer to form a desired thickness of the multi-layered binary oxide film; and forming an upper electrode layer on the multi-layered film. The method allows a nonvolatile memory device more efficient than the conventional perovskite structure in a simple process without concerns for surface contamination since the metal layer is formed and oxidized in a vacuum atmosphere. | 2008-08-21 |
20080200004 | Method of fabricating semiconductor optical device - In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure is formed on a primary surface of a first III-V semiconductor region. After forming the insulating structures, a second III-V semiconductor region is grown on the first III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second III-V semiconductor region. After forming the second III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer. | 2008-08-21 |
20080200005 | STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE - An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation. | 2008-08-21 |
20080200006 | Method for Forming Shallow Trench Isolation of Semiconductor Device - A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a vertical sidewall in a portion of the substrate predetermined to be a device isolation region, performing a plasma treatment process on the sidewall of the trench to form a plasma oxide film, forming an oxide film over the resulting structure to fill the trench, and performing a planarization process over the resulting structure. | 2008-08-21 |
20080200007 | Methods of forming semiconductor devices - A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern. | 2008-08-21 |
20080200008 | BONDING INTERFACE QUALITY BY COLD CLEANING AND HOT BONDING - The invention relates to improvements in a method for molecularly bonding first and second substrates together by placing them in surface to surface contact. The improvement includes, prior to placing the substrates in contact, cleaning the surface of one or both of the substrates in a manner to provide a cleaned surface that is slightly roughened compared to a conventionally polished surface, and heating at least one or both of the substrates prior to placing the substrates in contact while retaining the heating at least until the substrates are in surface to surface contact. | 2008-08-21 |
20080200009 | Methods of Forming Stacked Semiconductor Devices with Single-Crystal Semiconductor Regions - Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions. | 2008-08-21 |
20080200010 | Method for Manufacturing Bonded Wafer - A thickness of silicon oxide film of a wafer for active layer is controlled to be thinner than that of buried silicon oxide film. Consequently, uniformity in film thickness of the active layer of a bonded wafer is improved even if a variation in the in-plane thickness of the silicon oxide film is large at a time of ion implantation. Furthermore, since the silicon oxide film is rather thinner and thereby the ion implantation depth is relatively deeper, damages to the active layer and the buried silicon oxide film caused by the ion implantation can be reduced. | 2008-08-21 |
20080200011 | HIGH-TEMPERATURE, SPIN-ON, BONDING COMPOSITIONS FOR TEMPORARY WAFER BONDING USING SLIDING APPROACH - New compositions and methods of using those compositions as bonding compositions are provided. The compositions comprise a polymer dispersed or dissolved in a solvent system, and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the active wafer and its active sites during subsequent processing and handling. The compositions form bonding layers that are chemically and thermally resistant, but that can also be softened to allow the wafers to slide apart at the appropriate stage in the fabrication process. | 2008-08-21 |
20080200012 | Wafer processing method and laser processing apparatus - In a wafer processing method for penetrating a wafer by use of a laser processing apparatus including a chuck table for holding the wafer, laser beam irradiation means for irradiating the wafer held on the chuck table with a laser beam, and imaging means for imaging the wafer held on the chuck table, the chuck table includes a chuck table main body, a holding member disposed on an upper surface of the chuck table main body and having a holding surface for holding an entire surface of the wafer, the holding member comprising a transparent or translucent member, and a light emitting body disposed laterally of a side of the holding member opposite to the holding surface. The wafer processing method comprises irradiating a predetermined processing region of the wafer held on the chuck table with the laser beam to perform the penetration in a predetermined manner, then lighting the light emitting body, with the wafer being held on the chuck table, imaging the processing region by the imaging means, and determining acceptance or rejection of the penetration based on whether or not light has passed through the processing region. | 2008-08-21 |
20080200013 | GALLIUM NITRIDE MATERIALS AND METHODS ASSOCIATED WITH THE SAME - Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance. | 2008-08-21 |
20080200014 | METHOD OF FORMING A VERTICAL DIODE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved. | 2008-08-21 |
20080200015 | MULTI-STEP PLASMA DOPING WITH IMPROVED DOSE CONTROL - A method of multi-step plasma doping a substrate includes igniting a plasma from a process gas. A first plasma condition is established for performing a first plasma doping step. The substrate is biased so that ions in the plasma having the first plasma condition impact a surface of the substrate thereby exposing the substrate to a first dose. The first plasma condition transitions to a second plasma condition. The substrate is biased so that ions in the plasma having the second plasma condition impact the surface of the substrate thereby exposing the substrate to a second dose. The first and second plasma conditions are chosen so that the first and second doses combine to achieve a predetermined distribution of dose across at least a portion of the substrate. | 2008-08-21 |
20080200016 | Method of fabricating nonvolatile semiconductor memory device - A method of fabricating a nonvolatile semiconductor memory device includes the steps of: (a) forming a layered dielectric film on the semiconductor substrate; (b) forming a first conductive film on the layered dielectric film; (c) forming a first dielectric film on the first conductive film; (d) patterning the first dielectric film and the first conductive film to form a layered pattern composed of first dielectric films and first conductive films; and (e) implanting a first impurity along a direction having an inclination angle to a normal direction to a principal plane of the semiconductor substrate by using the layered pattern as a mask to form a first impurity diffusion layer being the same in conductivity type as the semiconductor substrate, wherein, step (d) includes patterning the first dielectric film to form the first dielectric films having a shape with a width narrower in an upper surface than in a lower surface. | 2008-08-21 |
20080200017 | Method of producing semiconductor device - A method of producing a semiconductor device includes the steps of: introducing a p-type impurity corresponding to a conductive type of a channel area into a channel forming area; introducing fluorine into the channel forming area at a low acceleration voltage; and thermally processing a substrate to increase a threshold voltage. In the method of the present invention, the step of thermally processing the substrate is performed after the steps of introducing the p-type impurity into the channel forming area and introducing fluorine into the channel forming area. Further, the steps of introducing the p-type impurity into the channel forming area and introducing fluorine into the channel forming area may be performed any order. | 2008-08-21 |
20080200018 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas. | 2008-08-21 |
20080200019 | Selective Deposition of Noble Metal Thin Films - Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode. | 2008-08-21 |
20080200020 | Semiconductor device and method of fabricating a semiconductor device - A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer. | 2008-08-21 |
20080200021 | SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK - A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO | 2008-08-21 |
20080200022 | POST-SEED DEPOSITION PROCESS - A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the photoresist and plated metal until all of the exposed seed layer has been removed. | 2008-08-21 |
20080200023 | METHOD OF FABRICATING MICRO CONNECTORS - A wafer is provided, and a first surface of the wafer is etched to form a plurality of through holes. A first surface conductive layer is formed on the first surface, and an internal conductive layer is formed to fill up each through hole. A first insulating layer is formed on the first surface conductive layer. A thinning process is performed to thin a second surface of the wafer so as to expose the internal conductive layer in the through holes. A second surface conductive layer is formed on the second surface, and the second surface conductive layer is electrically connected to the first surface conductive layer via the internal conductive layer. | 2008-08-21 |
20080200024 | Semiconductor device and method for fabricating the same - A method for fabricating a semiconductor device includes forming an interlayer insulating film over a semiconductor substrate. The interlayer insulating film is selectively etched to form a hole defining a storage node region. A lower electrode is formed in the hole. A support layer is formed over the lower electrode. The support layer fills an upper part of the hole and exposes the interlayer insulating film. A dip-out process is performed to remove the interlayer insulating film. The supporting layer is removed to expose the lower electrode. A dielectric film is formed over the semiconductor substrate including the lower electrode. A plate electrode is formed over the semiconductor substrate to fill the dielectric film and the lower electrode. | 2008-08-21 |
20080200025 | METHOD OF FORMING COMPOSITE OPENING AND METHOD OF DUAL DAMASCENE PROCESS USING THE SAME - A dual damascene process is provided. A dielectric layer is formed on a substrate and then a via opening is formed in the dielectric layer to expose a liner formed on the substrate. A gap fill (GF) layer is filled into the via opening and a resistant layer is formed on the substrate. A photolithographic process and an etching process are performed to form a trench in the dielectric layer and to remain the gap fill material having a top surface with a convex shape. In the etching process, an etching rate of the gap fill material layer is larger than that of the resistant layer. The gap fill material, the resistant layer, and the liner exposed by the via opening are removed. A conductive layer fills out the trench and the via opening. This invention is focusing on controlling etch-rate to avoid shielding effect when forming the composite opening. | 2008-08-21 |
20080200026 | Method of forming fine metal patterns for a semiconductor device using a damascene process - A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process. | 2008-08-21 |
20080200027 | METHOD OF FORMING METAL WIRE IN SEMICONDUCTOR DEVICE - The present invention discloses a method of forming a metal wire in a semiconductor device and comprises the steps of forming a first insulating layer, a conductive layer and a capping layer on a semiconductor substrate, forming hard mask patterns on the capping layer, etching the capping layer and the conductive layer through an etching process utilizing the hard mask patterns to form metal wires, removing the hard mask patterns and forming a second insulating layer on the semiconductor substrate including the metal wires to insulate the metal wires from each other. | 2008-08-21 |
20080200028 | METHODS OF POSITIONING AND/OR ORIENTING NANOSTRUCTURES - Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods. | 2008-08-21 |
20080200029 | Method of fabricating microstructures - Provided is a method of fabricating a microstructure, and more specifically, a method of fabricating a structure of a Micro Electro Mechanical System (MEMS), which includes the step of applying and patterning a material for the sacrificial layer on a silicon substrate, and forming a post with the same material as the sacrificial layer material, so that a stiction problem can be prevented in advance at the time of fabricating the microstructure, only one process needs to be added to simplify fabrication of a post, and the sacrificial layer can be formed in a desired shape because a photoresist is used as the sacrificial layer material. | 2008-08-21 |
20080200030 | Method For Producing an Electronic Component - The invention relates to a method for producing an electronic component on a surface of a substrate with the electronic component having, seen at right angles to the surface of the substrate, at least two electrical functional layers which are arranged one above the other and such that they overlap at least in a surface area F, with the at least two electrical functional layers on the substrate being structured directly or indirectly using a continuous process, with a first electrical functional layer of the at least two electrical functional layers being structured such that a first length/width dimension of the first electrical functional layer parallel to the surface of the substrate and in a relative movement direction of the substrate is at least 5 μm longer/wider, preferably more than 1 mm longer/wider, than a length/width dimension of the surface area F in the relative movement direction and parallel to the surface of the substrate. | 2008-08-21 |
20080200031 | Method of fabricating gate electrode having polysilicon film and wiring metal film - A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may include forming an interface metal film and nitriding an upper surface portion of the interface metal film to form an interface metal nitride film on an upper surface portion of the interface metal film. A wiring metal film may be formed on the interface control layer. | 2008-08-21 |
20080200032 | POLISHING METHOD OF SEMICONDUCTOR SUBSTRATE - The present invention relates to a method of polishing a semiconductor substrate, comprising pressing a semiconductor substrate having a film to be polished that is held by a carrier onto a polishing cloth fixed on a revolving polishing table and supplying a polishing slurry to the space between the polishing cloth and the semiconductor substrate, wherein the end point of polishing is determined according to the change in the friction coefficient while the friction coefficient between the semiconductor substrate and the polishing cloth is measured. According to the present invention it is possible to measure friction coefficient accurately in polishing a semiconductor substrate and use the change thereof to determine the end point of polishing. | 2008-08-21 |
20080200033 | POLISHING COMPOUND, METHOD FOR POLISHING SURFACE TO BE POLISHED, AND PROCESS FOR PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To provide a polishing compound which is capable of polishing SiC at a high removal rate, or capable of suppressing polishing of silicon dioxide in an insulating layer on the other hand, while polishing SiC at a high removal rate, in production of a semiconductor integrated circuit device, whereby it is possible to obtain a semiconductor integrated circuit device having a planarized multiplayer structure. | 2008-08-21 |
20080200034 | METHOD TO REMOVE BEOL SACRIFICIAL MATERIALS AND CHEMICAL RESIDUES BY IRRADIATION - A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability. | 2008-08-21 |
20080200035 | METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE - A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed on sidewalls of the first patterns using an amorphous carbon layer. Spaces between the first patterns including the spacers are gap filled to form second patterns. Accordingly, a contact hole having a pitch with exposure equipment resolution or less can be formed. | 2008-08-21 |
20080200036 | Printable Etching Media For Silicon Dioxide and Silicon Nitride Layers - The present invention relates to a novel printable etching medium having non-Newtonian flow behaviour for the etching of surfaces in the production of solar cells, and to the use thereof. The present invention furthermore also relates to etching and doping media which are suitable both for the etching of inorganic layers and also for the doping of underlying layers. In particular, they are corresponding particle-containing compositions by means of which extremely fine structures can be etched very selectively without damaging or attacking adjacent areas. | 2008-08-21 |
20080200037 | Method of thinning a wafer - A method of thinning wafer is disclosed. A wafer has an active surface and a back surface is provided. A plurality of protruding components may be disposed on the active surface. The wafer is placed in a mold and a polymeric material is formed in the mold to cover at least the active surface of the wafer. The polymeric material is cured and the mold is removed. The back surface of the wafer is ground to thin the wafer. The polymeric material is removed to expose the active surface of the wafer and the protruding components disposed on the active surface. The polymeric material is allowed to cover the active surface of the wafer and the protruding components through the mold; accordingly, the stress produced during the grinding can be distributed uniformly on the wafer, and the wafer warpage, breakage, or collapse, or the protruding component peeling can be avoided. | 2008-08-21 |
20080200038 | Heat processing method and apparatus for semiconductor process - A heat processing method for a semiconductor process includes placing a plurality of target substrates stacked at intervals in a vertical direction within a process field of a process container. Each of the target substrates includes a process object layer on its surface. Then, the method includes supplying an oxidizing gas and a deoxidizing gas to the process field while heating the process field, thereby causing the oxidizing gas and the deoxidizing gas to react with each other to generate oxygen radicals and hydroxyl group radicals, and performing oxidation on the process object layer of the target substrates by use of the oxygen radicals and the hydroxyl group radicals. Then, the method includes heating the process object layer processed by the oxidation, within an atmosphere of an annealing gas containing ozone or oxidizing radicals, thereby performing annealing on the process object layer. | 2008-08-21 |
20080200039 | NITRIDATION PROCESS - The invention is directed to a nitridation process for a wafer. The nitridation process comprises steps of disposing the wafer on a top surface of a chuck in a nitridation process tool, wherein a plurality of concentric pipe coils is disposed close to the bottom surface of the chuck. Then, the chuck is heated and the chuck is regionally cooling down by applying a coolant into the concentric pipe coils, wherein the flow rates of the coolant in the concentric pipe coils are different from each other. Furthermore, a plasma nitridation process is performed on the wafer. | 2008-08-21 |
20080200040 | Reconfigurable harness board - An apparatus including a harness board and a clamp removably connected to the harness board with a magnetic field. The magnetic field permits the clamp to be removed from the harness board. Also, a post is removably connected to the harness board using a magnetic field, and the magnetic field permits the post to be removed from the harness board. | 2008-08-21 |
20080200041 | STORAGE DEVICE - The present disclosure relates to a storage device. The storage device comprises a frame having a hole and a printed circuit board embedded in the frame, wherein the printed circuit board has an extended part for forming a connector. The connector may pass through the hole and is exposed out the frame for interfacing the storage device with a host device. At least one memory device is mounted to the printed circuit board and electrically connected to the printed circuit board. | 2008-08-21 |
20080200042 | Land grid array module with contact locating features - A land grid array module is provided that includes a land grid array interface. The interface includes a substrate having a mating face. A contact pad is provided on the mating face of the substrate. The contact pad has an exposed surface with a depression that is configured to restrain transverse movement of a mating contact tip when the mating contact tip is loaded against the contact pad. The substrate layer may include a via having a diameter such that the depression is formed in the contact pad when the contact pad is plated over the via. The depression may also be stamped in the exposed surface of the contact pad. Alternatively, the depression may be surrounded by a raised conductive perimeter that is configured to retain the mating contact tip. | 2008-08-21 |