34th week of 2008 patent applcation highlights part 14 |
Patent application number | Title | Published |
20080197438 | Sensor semiconductor device and manufacturing method thereof - This invention discloses a sensor semiconductor device and a manufacturing method thereof, including: providing a wafer having a plurality of sensor chips, forming a plurality of grooves between bond pads on active surfaces of the adjacent sensor chips; forming conductive traces in the grooves for electrically connecting the bond pads; mounting a transparent medium on the wafer for covering sensing areas of the sensor chips; thinning the sensor chips from the non-active surfaces down to the grooves, thereby exposing the conductive traces; cutting the wafer to separate the sensor chips; mounting the sensor chips on a substrate module having a plurality of substrates, electrically connecting the conductive traces to the substrates; providing an insulation material on the substrate module and between the sensor chips so as to encapsulate the sensor chips but expose the transparent medium; and cutting the substrate module to separate a plurality of resultant sensor semiconductor devices. | 2008-08-21 |
20080197439 | Semiconductor Device And Method For Manufacturing Same - A semiconductor device including a Schottky diode of the trench-junction-barrier type having an integrated PN diode, and a corresponding method for manufacturing the device, are provided. An n layer is provided on an n | 2008-08-21 |
20080197440 | Nonvolatile Memory - To provide a nonvolatile memory which realizes nonvolatile characteristic similar to a flash memory and a high-speed access equivalent to SRAM, has an integration degree exceeding that of DRAM, requires low voltage and low power consumption, and can be driven by a small-size battery, there are provided: (1) a non-volatile memory, including: a pair of metal electrodes; and a nano-hole-containing metal oxide film having a film thickness of 0.05 μm to 5 μm, which has a honeycomb structure and is provided between the pair of metal electrodes in a Schottky junction state, to use an interface state produced in a partition wall of the nano-hole-containing metal oxide film as a memory charge holder; and (2) a non-volatile memory, including: a substrate electrode; a nano-hole-containing metal oxide film formed by anodic oxidation of a surface of the substrate electrode; and a metal electrode formed to an upper end portion of a partition wall of the nano-hole-containing metal oxide film by Schottky junction, in which the nano-hole-containing metal oxide film has a structure in which a plurality of double Schottky barriers are formed in parallel. | 2008-08-21 |
20080197441 | SEMICONDUCTOR COMPONENT WITH VERTICAL STRUCTURES HAVING A HIGH ASPECT RATIO AND METHOD - A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric. | 2008-08-21 |
20080197442 | SEMICONDUCTOR COMPONENT WITH CELL STRUCTURE AND METHOD FOR PRODUCING THE SAME - A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode. | 2008-08-21 |
20080197443 | Semiconductor Substrate Comprising a Pn-Junction and Method For Producing Said Substrate - An SOI substrate comprising a carrier substrate, a dielectric layer and a semiconductor layer. A continuous pn junction is realized in the semiconductor layer, which pn junction can be produced by applying differently doped partial layers on the SOI substrate. In this way, it is possible to use an SOI substrate for producing semiconductor components and, in particular, rear side diodes. | 2008-08-21 |
20080197444 | INTEGRATED CIRCUIT AND METHOD INCLUDING AN ISOLATION ARRANGEMENT - An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the trenches and at least partially side walls of the auxiliary structure. A liner on the first isolation structure fills the trenches and gaps between the auxiliary structures with a second isolation structure; and the second isolation structure is pulled back, wherein upper sections of the liner are uncovered. | 2008-08-21 |
20080197445 | Isolation and termination structures for semiconductor die - Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 2008-08-21 |
20080197446 | Isolated diode - Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 2008-08-21 |
20080197447 | METHOD FOR MANUFACTURING A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer. | 2008-08-21 |
20080197448 | SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 - To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO | 2008-08-21 |
20080197449 | WIRING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD AND DEVICE FOR DESIGNING THE SAME - A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step. | 2008-08-21 |
20080197450 | AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS - A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising Si | 2008-08-21 |
20080197451 | High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications - Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV | 2008-08-21 |
20080197452 | Group III nitride semiconductor substrate - A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 μm. The substrate satisfies that a ratio of Δα/α is not more than 0.1, where α is a thermal expansion coefficient calculated from a temperature change in outside dimension of the substrate, and Δα is a difference (α−αL) between the thermal expansion coefficient α and a thermal expansion coefficient αL calculated from a temperature change in lattice constant of the substrate. | 2008-08-21 |
20080197453 | Semiconductor device and manufacturing method of the same - In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta | 2008-08-21 |
20080197454 | METHOD AND SYSTEM FOR REMOVING IMPURITIES FROM LOW-GRADE CRYSTALLINE SILICON WAFERS - Techniques are here disclosed for a solar cell pre-processing. The method and system remove impurities from low-grade crystalline semiconductor wafers and include forming a low-grade semiconductor wafer having a substrate having high impurity content. The process and system damage at least one surface of the semiconductor wafer either in the semiconductor wafer forming step or in a separate step to form a region on the surface that includes a plurality of gettering centers. The gettering centers attract impurities from the substrate during subsequent processing. The subsequent processes include diffusing impurities from the substrate using a phosphorus gettering process that includes impregnating the surface with a phosphorus material for facilitating the formation of impurity clusters associated with the gettering centers. Then, the process and system remove from the a portion having the impregnated phosphorus material and the impurity clusters, thereby yielding a semiconductor wafer having a substrate having a generally reduced impurity content. | 2008-08-21 |
20080197455 | Semiconductor device and manufacturing method therefor - A semiconductor device having a rectangular exterior appearance includes a substrate for arranging an integrated circuit on the surface thereof, at least one rewire electrically connected to the integrated circuit via at least one pad electrode, at least one electrode terminal formed on the rewire, and a resin layer for completely sealing the substrate including the rewire such that the electrode terminal be exposed to the exterior. Slopes are formed at the corners between the backside and the side faces of the resin layer; and other slopes are further formed at the corners between the surface and the side faces of the resin layer. Thus, it is possible to reliably prevent the semiconductor device sealed with the resin layer from chipping or peeling irrespective of an impact occurring at the corners of the resin layer. | 2008-08-21 |
20080197456 | Substrate polishing method, semiconductor device and fabrication method therefor - A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film. | 2008-08-21 |
20080197457 | SILICON WAFER AND ITS MANUFACTURING METHOD - A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90° light scattering method is formed in a region at a depth from the wafer surface of 25 μm or more but less than 100 μm, and a layer which has a light scattering defect density of 1×10 | 2008-08-21 |
20080197458 | Small Outline Package in Which Mosfet and Schottky Diode Being Co-Packaged - The present invention provides a thin small outline package in which MOSPET and Schottky diode being co-packaged, which comprises a electrode S of MOSFET, a electrode | 2008-08-21 |
20080197459 | ENCAPSULATED CHIP SCALE PACKAGE HAVING FLIP-CHIP ON LEAD FRAME STRUCTURE AND METHOD - In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects. | 2008-08-21 |
20080197460 | PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING SAME - A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material. | 2008-08-21 |
20080197461 | Apparatus for wire bonding and integrated circuit chip package - An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to the body, having a second internal channel of a second diameter for accommodating the flow of the conductive wire, wherein the first diameter is fixed and the second diameter is variable, the second diameter is not more than the first diameter and a diameter the conductive wire flowed through the compressible head is adjustable. An integrated circuit (IC) package is also provided. | 2008-08-21 |
20080197462 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided with a package main body including a base portion configured by joining thin plates integrally, and a semiconductor device accommodating portion provided on one surface of the base portion, electric terminals electrically connected to a semiconductor device in the accommodating portion and exposed to an outer surface of the accommodating portion, and a heat high-transfer element including at least one layer-like member provided in the base portion. The layer-like member is configured independent of the base portion by a material having a thermal conductivity higher than that of the base portion, and extends from a position corresponding to a heat-generation site of the semiconductor device to a position in an outside of the heat-generation site corresponding position. | 2008-08-21 |
20080197463 | Electronic Component And Method For Manufacturing An Electronic Component - An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead. | 2008-08-21 |
20080197464 | Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device - A semiconductor device package ( | 2008-08-21 |
20080197465 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Variations in fastening positions of semiconductor elements are eliminated by forming protrusions on a die pad so as to enclose the semiconductor elements before an adhesive that fastens the semiconductor elements to the die pad is wetted and spread. | 2008-08-21 |
20080197466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor chip; a plurality of pellet-like electrically conductive members connected to electrodes of the semiconductor chip; and an encapsulation resin that encapsulates the semiconductor chip and the electrically conductive members. The electrically conductive members are embedded into the encapsulation resin. Surfaces of the electrically conductive members are exposed from the encapsulation resin so that the electrically conductive members serve as external connection terminals of the semiconductor device. | 2008-08-21 |
20080197467 | Conductive structure for a semiconductor integrated circuit and method for forming the same - A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the pad via the first opening portion. The conductive structure comprises a support layer defining a second opening portion. A conductor is formed in the second opening portion to serve as a bump having a planar top surface. | 2008-08-21 |
20080197468 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a first chip, a cap structure, a second chip and a sealant. The first chip is disposed in an opening of the substrate and is electrically connected to the substrate. The cap structure is disposed on the substrate corresponding to the first chip. The second chip is disposed on the cap structure and is electrically connected to the substrate. The sealant encapsulates the first chip, the cap structure and the second chip. | 2008-08-21 |
20080197469 | Multi-chips package with reduced structure and method for forming the same - The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance. | 2008-08-21 |
20080197470 | Stacked electronic component and manufacturing method thereof - A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed. | 2008-08-21 |
20080197471 | SEMICONDUCTOR CHIP MOUNTING SUBSTRATE, SEMICONDUCTOR CHIP MOUNTING BODY, SEMICONDUCTOR CHIP STACKED MODULE, AND SEMICONDUCTOR CHIP MOUNTING SUBSTRATE MANUFACTURING METHOD - There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate. | 2008-08-21 |
20080197472 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE USING THE SAME - A semiconductor device includes a circuit board which has a first main surface having first connection pads, a second main surface having second connection pads, a first opening passing through a vicinity of the first connection pads, and a second opening passing through a vicinity of the second connection pads. A first semiconductor element is mounted in a face-down state on the first main surface of the circuit board. First electrode pads are exposed into the second opening and connected to the second connection pads through the second opening. A second semiconductor element is mounted in a face-up state on the second main surface of the circuit board. Second electrode pads are exposed into the first opening and connected to the first connection pads through the first opening. | 2008-08-21 |
20080197473 | CHIP HOLDER WITH WAFER LEVEL REDISTRIBUTION LAYER - A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip. | 2008-08-21 |
20080197474 | Semiconductor device package with multi-chips and method of the same - The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate. | 2008-08-21 |
20080197475 | Packaging conductive structure and method for forming the same - A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure. | 2008-08-21 |
20080197476 | SEMICONDUCTOR DEVICE - The bump diameter of a bump electrode is reduced. An external connection substrate is bonded to a semiconductor chip, and is provided with, at an edge portion thereof, an external connection electrode protruding from the semiconductor chip, and continuing on both principal surfaces of the external connection substrate. The external connection electrode on a principal surface side of the external connection substrate is connected to the bump electrode through an opening in a resin layer covering the external connection electrode. The external connection electrode on the other principal surface is connected to a conductive path of a mounting board. The chip and the external connection substrate are fixed together by an underfill material. The external connection electrode and the conductive path are fixed together by solder. The bonding strength can be improved even with a reduced bump diameter so that the chip can be reduced in size. | 2008-08-21 |
20080197477 | Flip-Chip Grid Ball Array Strip and Package - The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages. | 2008-08-21 |
20080197478 | SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND CONNECTING THROUGH-HOLE AND METHOD OF THE SAME - The present invention provides a semiconductor device package with the die receiving through hole and connecting through holes structure comprising a substrate with a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A die is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Further, a bonding wire is formed to couple and the bonding pads and the first contact pads. A dielectric layer is formed on the bonding wire, the die and the substrate. | 2008-08-21 |
20080197479 | SEMICONDUCTOR PACKAGE, INTEGRATED CIRCUIT CARDS INCORPORATING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAME - One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip. | 2008-08-21 |
20080197480 | Semiconductor device package with multi-chips and method of the same - The present invention provides a semiconductor device package with the multi-chips comprising a substrate with a die receiving through hole, a conductive connecting through holes structure and coupled the first contact pads on an upper surface and second contact pads on a lower surface of the substrate through a conductive connecting through holes. A first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though holes of the substrate. Then, a first conductive wire is formed to couple the first bonding pads and the first contact pads. Further, a second die having second bonding pads is attached on the first die. A second conductive wire is formed to couple the second bonding pads and the first contact pads. A plurality of dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate. | 2008-08-21 |
20080197481 | Semiconductor sensor having flat mounting plate - A semiconductor sensor for detecting a rotational speed of a rotor is contained in a cylindrical housing, an opening of which is closed with a cover member. The cover member includes a mounting plate integrally molded therewith. Components including a bare sensing chip and other circuit chips are directly mounted on a flat surface of the mounting plate. The components mounted on the flat surface are covered with gel having a high flowability. The gel is prevented from flowing out of the flat surface toward the cover member by banks formed at both sides of the flat surface. On an inner wall of the bank, curved surfaces and depressions are formed to surely suppress creeping up of the gel and to trap the gel therein if it creeps up the inner wall of the bank. Thus, the gel is surely prevented from flowing out even though the banks do not entirely surround the flat mounting surface. | 2008-08-21 |
20080197482 | SEMICONDUCTOR MODULE, PORTABLE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module is provided, which is capable of suppressing the deterioration of reliability and improving heat radiation. The semiconductor module includes: a semiconductor substrate in which electrodes of a circuit element are formed on its surface; a re-wiring pattern connected to the electrodes to ensure large pitch of the electrodes; an electrode integrally formed with the re-wiring pattern; an insulating layer formed on a rear surface of the semiconductor substrate; a radiator formed on the insulating layer; and projections integrally formed with the radiator and penetrating the insulating layer to connect to the rear surface of the semiconductor substrate. | 2008-08-21 |
20080197483 | Lidless semiconductor cooling - A system for cooling a semiconductor includes a heat sink in thermal contact with the semiconductor, a thermal interface material (TIM) layer disposed between the heat sink and the semiconductor, and a picture frame support disposed between a substrate of the semiconductor and the heat sink, wherein the picture frame support encloses at least a portion of the semiconductor in a plane between the substrate and the heat sink, and wherein the picture frame support has a height that is greater than a height of the semiconductor. | 2008-08-21 |
20080197484 | Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package - In a method of manufacturing an electronic component package, first, there is fabricated a wafer incorporating a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages, and a retainer for retaining the plurality of sets of external connecting terminals, the wafer including a plurality of pre-base portions that will be separated from one another later to be bases of the electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chips are connected to the external connecting terminals. Next, the electronic component chips are sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed. | 2008-08-21 |
20080197485 | Module comprising a semiconductor chip comprising a movable element - The invention relates to a module comprising a carrier, a first semiconductor chip applied to the carrier and having a movable element and a second semiconductor chip applied to the first semiconductor chip, wherein an active first main surface of the first semiconductor chip faces the carrier and a first cavity is formed between the two semiconductor chips. | 2008-08-21 |
20080197486 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode electrically connected to the integrated circuit; a first resin layer that is formed in a first region overlapping the integrated circuit over a surface of the semiconductor substrate where the electrode is formed; a wiring that is electrically connected to the electrode and is formed on the first resin layer; and a second resin layer that is formed on the surface of the semiconductor substrate in a second region surrounding the first region, is the second resin layer being spaced a distance from the first resin layer. | 2008-08-21 |
20080197487 | Semiconductor Device Including a Coupled Dielectric Layer and Metal Layer, Method of Fabrication Thereof, and Material for Coupling a Dielectric Layer and a Metal Layer in a Semiconductor Device - A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material. | 2008-08-21 |
20080197488 | BOWED WAFER HYBRIDIZATION COMPENSATION - A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane. | 2008-08-21 |
20080197489 | Packaging conductive structure and method for manufacturing the same - A packaging conductive structure for a semiconductor substrate and a method for manufacturing the structure are provided. The structure comprises an under bump metal (UBM) that overlays a pad of the semiconductor substrate. At least one auxiliary component is disposed on the UBM. Then, a bump conductive layer is disposed thereon and a bump is subsequently formed on the bump conductive layer. Thus, the bump can electrically connect to the pad of the semiconductor substrate through the UBM and the bump conductive layer and can provide better junction buffer capabilities and conductivity. | 2008-08-21 |
20080197490 | Conductive structure for a semiconductor integrated circuit and method for forming the same - A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially overlapping the pad to define the first lateral size of the first opening. The conductive structure electrically connects to the pad via the first opening. The conductive structure overlaps the first opening portion and parts of the passivation layer to provide a lower conductive resistance for the pad when connecting to a bump. Meanwhile, the conductive structure provides no discontinuity over the passivation layer in other places, thereby providing a stable conduction. | 2008-08-21 |
20080197491 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The semiconductor device includes a silicon interposer made of a semiconductor and a first semiconductor chip mounted on one surface of the silicon interposer. The semiconductor device is provided with a through electrode penetrating the silicon interposer and having a side surface insulated from the silicon interposer; and a wiring connecting one end of the through electrode and the silicon interposer. The through electrode is connected to a power supply wiring or a GND wiring provided on the first semiconductor chip. | 2008-08-21 |
20080197492 | Semiconductor device, connecting member, method for manufacturing a semiconductor device and method for manufacturing a connecting member - A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element. | 2008-08-21 |
20080197493 | Integrated circuit including conductive bumps - One embodiment provides an integrated circuit including an electrical contact and a conductive bump elongated via centrifugal forces. The conductive bump has a base and a top. The base is attached to the electrical contact and the top remains unattached. | 2008-08-21 |
20080197494 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same - A semiconductor device has an interconnect and a via material. The via material is provided under the interconnect and is in contact with an end portion of the interconnect. The interconnect and the via are made of copper as one piece. The via material has a top surface coupled to a bottom surface of the interconnect. The top surface has a first portion parallel with a longitudinal direction of the interconnect and a second portion parallel with a direction perpendicular to the longitudinal direction, and the first portion is larger than the second portion. | 2008-08-21 |
20080197495 | STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES - A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines. | 2008-08-21 |
20080197496 | Semiconductor device having at least two layers of wirings stacked therein and method of manufacturing the same - A semiconductor device according to the present invention is a semiconductor device having a first wiring formed in a first insulating layer and a second wiring formed in a second insulating layer formed on the first insulating layer and the first wiring. Here, at least one of the first wiring and the second wiring is a CuAl wiring. The second wiring is electrically connected to the first wiring at its via-plug portion, with a plurality of barrier layers interposed between the second wiring and the first wiring. In the barrier layers, a CuAl-contact barrier layer which is in contact with the CuAl wiring has a nitrogen atom content of less than 10 atomic %. Therefore, the present semiconductor device has high reliability and small variations in initial via resistance value. | 2008-08-21 |
20080197497 | BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS - A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad. | 2008-08-21 |
20080197498 | Gate Electrode Silicidation Process - A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process. | 2008-08-21 |
20080197499 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 2008-08-21 |
20080197500 | INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP - A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap. | 2008-08-21 |
20080197501 | INTERCONNECTION SUBSTRATE AND SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF INTERCONNECTION SUBSTRATE - An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the metal particles has a flat shape generally parallel to a plane of the resin layer. | 2008-08-21 |
20080197502 | SEMICONDUCTOR DEVICE HAVING METAL WIRINGS OF LAMINATED STRUCTURE - A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material. | 2008-08-21 |
20080197503 | CHIP PACKAGE - A chip package including a carrier, at least one chip disposed on the carrier, a plurality of wires electrically connecting the carrier and the chip, and an encapsulant wrapping the chip and the wires is provided. The chip has a semiconductor substrate, an interconnection structure, at least one first reference plane, at least one second reference plane, and at least one chip via, in which the first and second reference planes are respectively located on both sides of the semiconductor substrate, and the interconnection structure is located on the first reference plane and the semiconductor substrate. The chip via connects the first reference plane to the second reference plane. The chip package further includes at least one conductive bonding layer, which bonds the second reference plane to the carrier. | 2008-08-21 |
20080197504 | SINGLE-SIDED, FLAT, NO LEAD, INTEGRATED CIRCUIT PACKAGE - An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge). | 2008-08-21 |
20080197505 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first resin layer that is disposed on the passivation film; a second resin layer that covers the passivation film and the first resin layer; and a wiring that extends from the electrode to a first part of the second resin layer above the first resin layer, the electrode passing on a second part of the second resin layer above the passivation film. | 2008-08-21 |
20080197506 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER STRUCTURE - A semiconductor device manufacturing method, includes the steps of forming an insulating film over a semiconductor substrate, thinning selectively a thick portion, whose film thickness is thicker than a reference value, of the insulating film, forming contact holes in a thinned portion of the insulating film | 2008-08-21 |
20080197507 | Electronic package structure and method - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 2008-08-21 |
20080197508 | PLATED PILLAR PACKAGE FORMATION - A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package. | 2008-08-21 |
20080197509 | Semiconductor package having stacked semiconductor chips - A semiconductor package including: a package substrate on the surface of which plural connection terminals are provided; a semiconductor chip on the surface of which plural bonding pads are provided; plural bonding wires that connect between the plural connection terminals and the plural bonding pads; a resin formed to fill a gap between the bonding wires and the surface of the semiconductor chip; and a semiconductor chip provided on the bonding wires via a film-shaped resin, wherein at least three of the plural bonding wires are formed at substantially the same heights and higher than other bonding wires. | 2008-08-21 |
20080197510 | Semiconductor device and wire bonding method - A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion. | 2008-08-21 |
20080197511 | Bonding pad structure, electronic device having a bonding pad structure and methods of fabricating the same - An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads. | 2008-08-21 |
20080197512 | Process for manufacturing deep through vias in a semiconductor device, and semiconductor device made thereby - A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body having a structural layer, a substrate, and a dielectric layer set between the structural layer and the substrate; insulating a portion of the structural layer to form a front-side interconnection region; insulating a portion of the substrate to form a back-side interconnection region; and connecting the front-side interconnection region and the back-side interconnection region through the dielectric layer. | 2008-08-21 |
20080197513 | BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS - A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress. | 2008-08-21 |
20080197514 | DIE COAT PERIMETER TO ENHANCE SEMICONDUCTOR RELIABILITY - A semiconductor packaging stress relief technique with enhanced reliability. Reliability is enhanced over conventional post wirebond assembly die coating processes by forming a peripheral wall on the semiconductor die isolating the stress sensitive area from remaining area in the semiconductor die, and depositing die coat material constraining the flow of the die coat material in the stress sensitive area of the semiconductor die. The peripheral wall, by constraining flow of the die coat material, prevents stress on the package bond wires caused by mismatch in coefficient of thermal expansion between the die coat and the package bond wires which are encased in the plastic molding compound. | 2008-08-21 |
20080197515 | Cooling tower air inlet and drain pan - A mechanical draft cooling tower is provided. The cooling tower includes a direct cooling section having a plurality of fill sheets. Water is sprayed downwardly over the fill sheets and is collected in a collection sump. The collection sump is comprised of two end walls, two side walls, a floor and a drain. The end walls are sloped at the floor intersection. The floor is sloped to a center section where the drain is located. | 2008-08-21 |
20080197516 | Micro-Bubble Generator, Vortex Breakdown Nozzle for Micro-Bubble Generator, Vane Swirler for Micro-Bubble Generator, Micro-Bubble Generating Method, and Micro-Bubble Applying Device - There is provided a micro-bubble generator including a swirling-flow generating vane nozzle and vortex breakdown nozzle connected coaxially to each other. The swirling flow generating vane nozzle produces a swirling flow of a liquid having a gas introduced to the center thereof from a gas feeding unit. The swirling flow is supplied to a flow constricting section included in the vortex breakdown nozzle to provide micro bubbles from a vortex breakdown section also included in the vortex breakdown nozzle. | 2008-08-21 |
20080197517 | DEVICES AND METHODS FOR SELECTIVELY LYSING CELLS - A device for generating microbubbles in a gas and liquid mixture and injection device, the device comprising: a housing defining a mixing chamber; means for mixing solution contained in the mixing chamber to generate microbubbles in the solution; a needle array removably attached to the housing and in fluid connection with the mixing chamber, the needle array including at least one needle; and at least one pressure sensor for measuring tissue apposition pressure, the pressure sensor being mounted on one of the housing and the needle array. | 2008-08-21 |
20080197518 | Shaped article with polymer domains and process - A process for making a multiphase birefringent film and resulting shaped article comprise (a) a first polymeric material forming a continuous phase in all directions and (b) a second polymeric material that is continuous in only one direction disposed within the first phase, the second polymeric material being predominately curvilinear in shape and substantially extending the length of the film, at least one of the phases being birefringent and the two phases being substantially matched in refractive index in at least one direction | 2008-08-21 |
20080197519 | Strand Shaping Part and Method for Starting the Same - A strand shaping part for connecting an extruder ( | 2008-08-21 |
20080197520 | Method and Plant for Manufacturing Artilces in the Form of Sheets or Blocks of Conglomerate Stone or Stone-Like Material - In order to manufacture articles in the form of sheets or blocks of conglomerate stone or stone-like material, single mixes are prepared in mixers ( | 2008-08-21 |
20080197521 | METHOD OF INDICATING AN OPEN/CLOSE STATE OF A CHECK VALVE OF AN INJECTION MOLDING MACHINE - A method of indicating an open/close state of a check valve of an injection molding machine simply and more accurately. The method detects screw rotational force during injection and displays in wave form on the screen of a display device changes in detected rotational force. An open/close state of the check valve can be indicated based on the waveform pattern displayed on the display screen because the screw rotational force waveform pattern changes when the check valve closes. From the fact that the screw rotational force waveform pattern changes when the check valve closes, the open/close state of the check valve can be indicated from the displayed waveform. | 2008-08-21 |
20080197522 | DEVICE FOR PRODUCING A SPUN-BONDED NON-WOVEN - A device and method for producing a spun-bonded non-woven. A molten polymer supplied to a spinning beam from a melt source is extruded through a multiplicity of linearly arranged spinneret bores into filaments arranged in the form of a curtain. A tensile force is exerted on the filaments by means of a draw-off nozzle. The filaments are thereupon deposited on to a conveyer belt where they form a spun-bonded non-woven. At the draw-off nozzle, a monitoring means is provided which detects a characteristic quantity characteristic of the process. One or more structure-borne sound sensors are preferably used as monitoring means. The measurement result of the monitoring means, after a desired value comparison, is supplied to a signal means or is used for regulating the process. | 2008-08-21 |
20080197523 | SYSTEM AND METHOD FOR MANUFACTURING COMPOSITE MATERIALS HAVING SUBSTANTIALLY UNIFORM PROPERTIES - A system and method for manufacturing composite material components having substantially uniform properties comprising means to control the metering of constituent composite material components during manufacture. The resulting composite material components may, for example, be used in the construction of decking systems, railing, porches, fences, stairs, or other similar or suitable applications that may benefit from aesthetically pleasing appearances. | 2008-08-21 |
20080197524 | Thermoformable Melamine/Formaldehyde-Based Foams Exhibiting Low-Formeldehyde Emission - A process for the production of foams by heating with foaming and crosslinking of a mixture comprising a melamine/formaldehyde (MF) precondensate, a curing agent and a blowing agent, a formaldehyde scavenger being added prior to the heating, and foams based on melamine/formaldehyde resins having a low formaldehyde emission and the use thereof for the production of shaped articles by thermoforming. | 2008-08-21 |
20080197525 | Apparatus and Method for Supplying Powder Quantitatively and Material Supplying Apparatus Including the Apparatus for Supplying Powder - Provided are an apparatus and method for supplying powder quantitatively and a material supply apparatus including the apparatus for supplying powder quantitatively. The apparatus for supplying powder quantitatively to a place where required includes: a driving part generating a driving force using an external power; a powder supply part connected to the driving part, following the operation of the driving part, and transferring the powder according to a predetermined path; a chamber placed on the sides of the powder supply part and receiving the powder transferred by the powder supply part; a compression part compressing the transferred powder in the chamber; and a quantitative supply part separating a desired amount of powder from the compressed powder and discharging the separated powder from the chamber. The method of supplying powder quantitatively to a place where required includes: a preparation operation of receiving powder and preparing for the transfer of the powder; a powder transfer operation of transferring the powder to a chamber having a predetermined volume according to a predetermined path using a powder supply part that is driven by an external power and transfers the powder; a compressing operation of making the compressed bulk of powder by compressing the transferred powder in a compression part of the chamber; a separating operation of separating a desired amount of powder from the powder that is compressed and bridged in the chamber using a separating means; and a discharge operation of discharging the separated powder to the outside. | 2008-08-21 |
20080197526 | Process for Preparing Composites Using Epoxy Resin Formulations - Epoxy composites are prepared by separately preheating an epoxy resin and a hardener; mixing the preheated epoxy resin and preheated hardener to form a hot reaction mixture and curing the hot reaction mixture in the presence of a reinforcement until the mixture cures to form a composite having a polymer phase with a glass transition temperature of at least 150° C. | 2008-08-21 |
20080197527 | Method of feeding a rubber-consumer device with rubber, and an installation for feeding the rubber-consumer device with rubber - A method of the type in which a strip of rubber is moved continuously from a rubber-supplier device to a consumer device. During the continuous movement and prior to reaching the consumer device, a portion, referred to as the residue, is taken continuously from the strip of rubber. The residue is taken by continuously cutting the strip of rubber. For example, the supplier device includes upstream storage means for storing the strip of rubber from which the strip is moved toward the extruder, and downstream storage means in which the residue is stored. After the strip of rubber on the upstream storage means has been used up, the upstream and downstream storage means are swapped with each other. | 2008-08-21 |
20080197528 | Combination of Substituted Cyclodextrin Compound and Activated Carbon - The invention is a composition that can prevent formation in, or scavenge undesirable organic materials from, a polymer matrix. The composition contains cyclodextrin and particles of activated carbon. The composition can scavenge thermal decomposition products that can be produced during melt processing of a polymer, contaminants inherent in a polymer, or other types of impurities from a polymer matrix that otherwise may elute into the air, a water supply, or an ingestible material such as a food, a drug, or a beverage. Other aspects of the invention are blends of the composition with polymeric materials, methods of making blends, articles containing the composition, and methods of making articles containing the composition. | 2008-08-21 |
20080197529 | Production method for molding plastics on soft cloth - A production method for molding includes a. a first molding: depending on a shape to be molded, implementing a die feed-in on soft cloth, with the plastic that is injected in being fused and set with the cloth, for serving as a substrate layer; b. punching and trimming: punching and trimming the plastic that has been set to form a base; c. a second molding: implementing a second die feed-in on the base of a shaped product, with the injected-in plastic being fused and set with a surface of the base, to form the needed shape; d. tailoring and trimming: tailoring and trimming an edge interface between two layers of the assembled plastic to form a shaped product of a double-layer plastic on the soft cloth. | 2008-08-21 |
20080197530 | METHOD FOR FABRICATING A THREE DIMENSIONAL EMBLEM - A method for fabricating a three dimensional emblem is disclosed. An indentation is formed in the back surface of a piece of transparent material. Multiple colors are printed to form a pattern or emblem in the indentation. After printing, the indentation is filled with resin to make the back surface of the piece of transparent material flat. A second indentation is then formed in the filled indentation. When the front surface of the transparent material is viewed, the emblem appears as a three dimensional emblem. Since the emblem is under the front surface of the transparent material, the three dimensional emblem is protected and cannot be inadvertently dislodged from the transparent material. | 2008-08-21 |
20080197531 | Elastomeric Film With Anti-Skid Additive - The present invention provides an elastomeric film having anti-skid properties. The film comprises one or more layers, wherein at least one of the layers comprises from 0.1 to 10% (by weight) of an anti-skid additive, which does not melt, or has a melt temperature greater than 500° F., and has a particle size between 50 and 500 microns. Suitable anti-skid additives may be sand, clay, silica, crosslinked polyethylenes, other polymers or ultra high molecular weight polyethylene (UHMWPE). Also provided is a resin composition and a method for manufacturing an elastomeric film having anti-skid properties. | 2008-08-21 |
20080197532 | DENTURE FLASK MOULD PRESS AND METHOD OF USE - In preparing dentures, hardened mould material surrounds the denture. This mould material is adhered inside a denture flask with a housing having two separably matable portions. To remove the hardened mould material from the flask, the flask is mounted in a mould press having a shaft, with one of the portions is restrained against movement along an axis of travel of the shaft. A portion of the mould material at an end of the restrained flask portion is available for contact with the shaft along the axis of travel. A capped end of the shaft is forcefully advanced against the adhered mould material therein, thereby breaking the adhesion. After this is done, the denture flask is dismounted from the mould press and the hardened mould material is removed from the first flask portion. If necessary, the process is repeated with the other housing portion. | 2008-08-21 |
20080197533 | PAYMENT CARD MANUFACTURING TECHNOLOGY - A payment card manufacturing process glues a thin battery and an autonomously reprogrammable magnetic device to the inside surface of one of two outer front and rear laminate sheets. The magnetic device is pressed through a precisely cut rectangular hole provided for it in the rear laminate sheet, and is sealed with a gasket bead. Such magnetic device is critically placed flush in a magnetic stripe area, and the end gaps are such that they will minimize adverse magnetic transitions seen by a reader between the magnetic stripe field and the autonomously reprogrammable magnetic device. The surfaces of the battery, electronics, and laminate sheets, are plasma treated to promote adhesion. These are then all sandwiched together inside a heated mold that is tilted or vibrated just before a two-part polyurethane is injected. Each of the two polyurethane parts is temperature adjusted to match viscosities and thus improve mixing. The liquid polyurethane is injected through a nozzle and manifold to fill all the voids between the laminate sheets, and air escapes or is vacuumed out the top edge of the mold. The polyurethane sets quickly and sheets of sixteen or more payment cards can then be de-molded and singulated. | 2008-08-21 |
20080197534 | METHOD OF MANUFACTURING SEALED HONEYCOMB STRUCTURE - The manufacturing method of the plugged honeycomb structure for DPF wherein a plugging depth thereof can easily be made uniformly and briefly at low costs. In the method for manufacturing a plugged honeycomb structure having a plugging portion formed in one opening end portion of each of predetermined cells of a cylindrical honeycomb structure including a plurality of cells partitioned and formed into a honeycomb shape by porous partition walls to form fluid passages, holes | 2008-08-21 |
20080197535 | Apparatus for seamless applying to a bra a casing for housing a bra-cup supporting element - An apparatus for applying to the cups of a bra, or to the overall bra, a casing for housing therein a cup supporting element, comprises at least two bobbins, one supporting a resilient element or casing, and the other supporting an adhesive having a protective silicone processed paper, a first hot-applying device for binding the casing to the adhesive material, and a programmable tensioning device, applying to the adhesive processed casing an adjustable pulling force. | 2008-08-21 |
20080197536 | Dry-Forming Three Dimensional Wood Fiber Webs - A method for the dry-formation of a deep drawn, three-dimensional wood fiber structural core is provided. The method comprises providing a preformed, substantially flat, dry-formed mat of wood fibers, providing a three-dimensional mold, introducing the dry-formed mat of wood fibers into the three-dimensional mold, and drawing and molding the mat of wood fibers into said three-dimensional wood fiber structural core. | 2008-08-21 |
20080197537 | Closed Cooling System For Tools of Plastic Processing Machines - Tools of plastics processing machines are cooled over their surface and/or at particular points as soon as compound supply is finished. Heat is thus suitably withdrawn from the shaped compound, ensuring the fastest possible cooling and shortening cycle times. The invention relates to a closed, coolant-filled cooling system for tools of plastics processing machines having at least one compressor, a supply pipe, a tool region to be cooled and a discharge pipe, the supply pipe being connected to the outlet of the compressor and the discharge pipe being connected to the inlet of the compressor, while at least one open end of the supply pipe plunges into at least one bore arranged in the tool region to be cooled, and an open end of the discharge pipe is sealed to this bore. The supply pipe and the discharge pipe may be combined in a coaxial pipe with the supply pipe arranged in the centre and the discharge pipe enveloping the supply pipe. | 2008-08-21 |