34th week of 2020 patent applcation highlights part 57 |
Patent application number | Title | Published |
20200266246 | DISPLAY DEVICE - A display device is provided. The display device includes a substrate including an active region in which a plurality of pixels are arranged; a first electrode layer disposed on the substrate and including a first electrode disposed in each pixel and an auxiliary electrode spaced apart from the first electrode and disposed along a boundary of each pixel; an intermediate layer disposed on the first electrode and including a light emitting layer; and a second electrode disposed on the intermediate layer, disposed in each pixel, and electrically connected to the auxiliary electrode; wherein a plurality of unit pixel groups, each including one or more pixels, are defined on the substrate, the respective second electrodes of the pixels belonging to each unit pixel group are electrically connected to each other by the auxiliary electrode, and the auxiliary electrodes belonging to different unit pixel groups are electrically separated from each other. | 2020-08-20 |
20200266247 | MOTHER BOARD, AND METHOD FOR MANUFACTURING LIGHTING DEVICE - A mother board includes a plurality of organic EL elements, each of the plurality of organic EL elements includes a first positive electrode terminal and a second positive electrode terminal that are electrically connected to the first electrode layer and a first negative electrode terminal and a second negative electrode terminal that are electrically connected to the second electrode layer, neighboring organic EL elements are arranged so that the first positive electrode terminal or the second positive electrode terminal and the first negative electrode terminal or the second negative electrode terminal face each other, and predetermined ones of the first positive electrode terminals or the second positive electrode terminals and the first negative electrode terminals or the second negative electrode terminals are electrically connected to each other by a connecting member so that the plurality of organic EL elements constitute a lighting unit. | 2020-08-20 |
20200266248 | ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF, AND DISPLAY DEVICE - An array substrate includes a back plate including planar and curved portions; a light emitting layer at the back plate including first and second light emitting units that are spaced apart from each other, and a wavelength of a light emitted by the first light emitting unit being greater than a wavelength of a light emitted by the second light emitting unit; a pixel defining layer at a first side of the back plate and between the first light emitting unit and the second light emitting unit, the pixel defining layer including a first pixel defining region on the curved portion and adjacent to the first light emitting unit and close to the planar portion; and a correction layer at a side of the first pixel defining region away from the back plate for absorbing and reflecting the light emitted by the first light emitting unit. | 2020-08-20 |
20200266249 | DISPLAY PANEL AND DISPLAY DEVICE - The present application provides a display panel and a display device. The display panel includes a substrate; an active switch, which is disposed on the substrate and includes a first active switch, a second active switch, and an indium gallium zinc oxide layer; a pixel, which is disposed on the substrate and coupled to the first active switch and includes a quantum dot light-emitting diode; and a light sensor, which is disposed on the substrate and coupled to the second active switch and includes a quantum dot light sensing layer; where the active switch includes a gate layer, a gate insulating layer, the indium gallium zinc oxide layer, an etch stop layer, a metal layer, and a pixel electrode layer which are sequentially arranged on the substrate. | 2020-08-20 |
20200266250 | DISPLAY DEVICE - A display device, an electronic device, or a lighting device that is unlikely to be broken is provided. A flexible first substrate and a flexible second substrate overlap with each other with a display element provided therebetween. A flexible third substrate is bonded on the outer surface of the first substrate, and a flexible fourth substrate is bonded on the outer surface of the second substrate. The third substrate is formed using a material softer than the first substrate, and the fourth substrate is formed using a material softer than the second substrate. | 2020-08-20 |
20200266251 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a first substrate and a second substrate opposing to the first substrate. The first substrate includes a transmission area in which a shutter unit is disposed and an emission area in which an organic light emitting diode is disposed. The shutter unit includes a first shutter electrode, a second shutter electrode, and a shutter layer interposed between the first and second shutter electrodes. The organic light emitting diode includes a pixel electrode, a common electrode, and a light-emitting layer interposed between the pixel and common electrodes. At least one of the first and second shutter electrodes is connected to the common electrode of the organic light emitting diode. | 2020-08-20 |
20200266252 | IN-DISPLAY SENSORS AND VIEWING ANGLE ADJUSTMENT MICROASSEMBLIES - Cameras are located within the display area of a display. In-display cameras allow for thinner display bezels. In-display cameras allow for the creation of ultra-high resolution images. The ability to capture an object from multiple perspectives allows for holographic image recording and playback. Multiple views of an image can be captured with varying depths of focus, allowing an image's depth of field to be adjusted during post processing. In-display cameras can also be used for user authentication, touch detection and three-dimensional gesture recognition. Thermal sensors located within the display area allow for control of the display temperature, improved control over system performance, and compensation for micro-LED degradation that can occur due to aging or increased temperature. Microlens assemblies located above pixels can adjust the viewing cone angle of the display or a portion of the display and microassemblies located under individual pixels or pixel arrays can adjust a viewing angle. | 2020-08-20 |
20200266253 | DISPLAY DEVICE - A display device that includes a plurality of pixels arranged in a row direction and a column direction crossing the row direction. The display device includes a first substrate including light-emitting elements each disposed in the respective pixels. A second substrate faces the first substrate. A plurality of optical patterns are disposed on the second substrate in pixel columns, respectively, and extend along the column direction. Light-blocking patterns are disposed on the second substrate. The light-blocking patterns include a main light-blocking pattern extending along pixel column boundaries and fill spaces between adjacent optical patterns, and a subsidiary light-blocking pattern disposed on the optical patterns at pixel row boundaries and having a thickness smaller than a thickness of the main light-blocking pattern. | 2020-08-20 |
20200266254 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display panel including a first electrode, a second electrode on the first electrode, an organic layer between the first electrode and the second electrode and including at least one light emitting layer, an organic cover layer disposed on the second electrode, a lower layer between the organic cover layer and the second electrode and including a first layer, a second layer, and a third layer, which are different from each other and are sequentially stacked, and an upper layer on the organic cover layer. The first layer contacts the second electrode. The second layer and the third layer each include a silicon compound. | 2020-08-20 |
20200266255 | DISPLAY DEVICE - A display device includes hole patterns of upper and lower conductive layers that are disposed in a peripheral area of the display device and are asymmetric with respect to an opening of an insulating layer of the display device. A first one of the hole patterns may coincide with a second one of the hole patterns in a part of the peripheral area, while the first one of the hole patterns may cross the second one of the hole patterns in another part of the peripheral area. | 2020-08-20 |
20200266256 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - The present disclosure relates to an array substrate, manufacturing method thereof, and a display panel. The array substrate includes a substrate, at least a first top gate TFT and at least a first bottom gate TFT disposed on the substrate and located in each sub-pixel region; a gate of the first top gate TFT and a gate of the first bottom gate TFT are formed in a same layer with same material, an active layer pattern of the first top gate TFT and an active layer pattern of the first bottom gate TFT are respectively arranged on two sides of the gate, and orthographic projections of the active layer pattern of the first top gate TFT and the active layer pattern of the first bottom gate TFT on the substrate are spaced from each other in a first direction. | 2020-08-20 |
20200266257 | ARRAY SUBSTRATE, DISPLAY DEVICE AND PEEP PREVENTION METHOD THEREOF - A display substrate, a display device, and a peep prevention method thereof. The display substrate includes: a base substrate; a plurality of pixel units on the base substrate and including a plurality of first pixel units; and a light shielding portion positioned between two adjacent first pixel units. | 2020-08-20 |
20200266258 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a substrate having first regions for forming pixels and second regions located between the first regions, light shielding portions located within portions of the second regions adjacent to the first regions on the substrate, and pixel defining portions located within the second regions. At least a side surface of the light shielding portion adjacent to the first region is not covered by the pixel defining portion. | 2020-08-20 |
20200266259 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE - A display device includes a first signal line including a first layer disposed on a substrate and containing aluminum (Al), a second layer disposed on the first layer and containing titanium nitride (TiN | 2020-08-20 |
20200266260 | DISPLAY DEVICE - A display device includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps a first channel region included in the first active pattern, the lower pattern overlaps the first active pattern, and the first active pattern does not cross an edge of the lower pattern. | 2020-08-20 |
20200266261 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL, TRACE STRUCTURE AND ORGANIC LIGHT EMITTING DIODE DISPLAY APPARATUS - Disclosed is a trace structure of an organic light emitting diode display panel, including an array substrate, wherein the trace structure of the organic light emitting diode display panel includes an outer lead region disposed on a substrate of the array substrate. Two metal trace layers which are mutually insulated are disposed on the outer lead region. A bending region is configured to the outer lead region. Traces of the two metal trace layers and a center line of the bending region are arranged with a non-orthogonal included angle and the metal trace layers connect the organic light emitting diode display panel with external electrical signals. | 2020-08-20 |
20200266262 | SEMICONDUCTOR DEVICE HAVING 3D INDUCTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor. | 2020-08-20 |
20200266263 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity. | 2020-08-20 |
20200266264 | SINGLE CRYSTAL MATERIAL AND METHOD OF FORMING THE SAME AND STACKED STRUCTURE AND CERAMIC ELECTRONIC COMPONENT AND DEVICE - A stacked structure including: a single crystal substrate and, single crystal material on the single crystal substrate, wherein the single crystal material has a same crystallographic orientation as a crystallographic orientation of the single crystal substrate. Also a method of forming the stacked structure, a ceramic electronic component, and a device. | 2020-08-20 |
20200266265 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part. | 2020-08-20 |
20200266266 | SEMICONDUCTOR DEVICE WITH HIGH CHARGE CARRIER MOBILITY MATERIALS ON POROUS SILICON - A semiconductor device includes a porous silicon layer on a silicon substrate. The semiconductor device also includes a seal layer on the porous silicon layer. The semiconductor device further includes a high charge carrier mobility material layer on the seal layer. The semiconductor device may further include a strain balancing intermediate layer between the seal layer and the high charge carrier mobility material layer. Different high charge carrier mobility materials can be used in the high charge carrier mobility material layer to form different semiconductor devices. | 2020-08-20 |
20200266267 | METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches. | 2020-08-20 |
20200266268 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1>L2 and R1≥L2 are satisfied. | 2020-08-20 |
20200266269 | Power Semiconductor Device and Method of Processing a Power Semiconductor Device - A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion. | 2020-08-20 |
20200266270 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductivity type semiconductor layer having a first surface and a second surface opposite to the first surface and having an element portion formed in the first surface and an outer peripheral portion surrounding the element portion, a semiconductor element structure formed in the element portion, multiple guard ring trenches formed in the outer peripheral portion and each formed in the first surface of the semiconductor layer, and a second conductivity type outer peripheral portion impurity region formed in the outer peripheral portion, in which the multiple guard ring trenches include a first unit consisting of multiple guard ring trenches and a second unit consisting of multiple guard ring trenches arranged on the outside of the semiconductor layer relative to the multiple guard ring trenches belonging to the first unit, and in which the outer peripheral portion impurity region includes a first portion arranged below the multiple guard ring trenches belonging to the first unit and having a first depth with respect to the first surface of the semiconductor layer and a second portion arranged below the multiple guard ring trenches belonging to the second unit and having a second depth smaller than the first depth with respect to the first surface of the semiconductor layer. | 2020-08-20 |
20200266271 | SEMICONDUCTOR STRUCTURE WITH EXTENDED CONTACT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench. | 2020-08-20 |
20200266272 | FEEDER DESIGN WITH HIGH CURRENT CAPABILITY - Amendments to the Abstract | 2020-08-20 |
20200266273 | SOLID POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE - The present invention discloses a rugged power semiconductor field effect transistor structure, and through a special design, it solves the problem that the activation under a transient condition may result in failures on the device, so that there is no parasitic BJT, and thus the device is more rugged. | 2020-08-20 |
20200266274 | In-Situ Straining Epitaxial Process - A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate. | 2020-08-20 |
20200266275 | METHOD FOR MANUFACTURING SEMICONDCUTOR DEVICE AND SEMICONDUCTOR DEVICE - Disclosure is a method for manufacturing a semiconductor device. The method includes forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate, forming a gate electrode having a laminated structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer and forming a first metal film having the same laminated structure as the gate electrode in a region adjacent to the source electrode with an interval therebetween, forming a second metal film to contact with the source electrode and the first metal film, forming a hole being continuous with the first metal film from a back surface of the SiC substrate, and forming a metal via being continuous with the first metal film from the back surface in the hole. | 2020-08-20 |
20200266276 | Pnictide Nanocomposite Structure for Lattice Stabilization - A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters. | 2020-08-20 |
20200266277 | FIELD-EFFECT TRANSISTOR WITH A TOTAL CONTROL OF THE ELECTRICAL CONDUCTIVITY ON ITS CHANNEL - The first object of the invention is directed to field-effect gate transistor comprising (a) a substrate, (b) a source terminal, (c) a drain terminal, and (d) a channel between the source terminal and the drain terminal, the channel being a layer of Cu | 2020-08-20 |
20200266278 | GATE STRUCTURES RESISTANT TO VOLTAGE BREAKDOWN - A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption. | 2020-08-20 |
20200266279 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a gate electrode, a first conductive layer, and a second electrode. The gate electrode opposes, with a gate insulating portion interposed, a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a first direction. The first direction is perpendicular to a second direction. The second direction is from the first semiconductor region toward the second semiconductor region. The first conductive layer is provided inside the first semiconductor region with a first insulating layer interposed. Another portion of the first semiconductor region is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the gate electrode. | 2020-08-20 |
20200266280 | DEVICES AND METHODS INCLUDING AN ETCH STOP PROTECTION MATERIAL - Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess. | 2020-08-20 |
20200266281 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device is provided. The semiconductor device includes a first insulator; a first oxide provided over the first insulator; a second oxide provided over the first oxide; a first conductor and a second conductor provided apart from each other over the second oxide; a third oxide provided over the second oxide, the first conductor, and the second conductor; a second insulating film provided over the third oxide; and a third conductor provided over the second oxide with the third oxide and the second insulating film positioned therebetween. The third oxide contains a metal element and nitrogen, and the metal element is bonded to nitrogen. | 2020-08-20 |
20200266282 | Metal Gates and Manufacturing Methods Thereof - A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG. | 2020-08-20 |
20200266283 | PROCESS OF MAKING A SHORT-CIRCUITED DIODE THAT PREVENTS ELECTROCUTION - A process of making a short-circuited diode that changes the properties of an electric current that passes through the short-circuited diode so that the current does not harm a human that contacts the current after it passes through the diode. | 2020-08-20 |
20200266284 | NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION - A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate. | 2020-08-20 |
20200266285 | METHOD OF FORMING GATE - A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers. | 2020-08-20 |
20200266286 | GATE CUT FIRST ISOLATION FORMATION WITH CONTACT FORMING PROCESS MASK PROTECTION - A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner. | 2020-08-20 |
20200266287 | SEMICONDUCTOR DEVICE COMPRISING COUNTER-DOPED REGIONS - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate with a well region and a drift region in the semiconductor substrate; one or more counter-doped regions in the drift region, the plurality of counter-doped regions being directly below the second insulating structure and aligned along a direction vertical to a surface of the semiconductor substrate to divide the drift region into a plurality of parts and the plurality of counter-doped regions in the drift region being separated by the drift region. The semiconductor device further includes a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure. | 2020-08-20 |
20200266288 | VERTICAL FIELD EFFECT TRANSISTOR HAVING IMPROVED UNIFORMITY - A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins. | 2020-08-20 |
20200266289 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with favorable electrical characteristics and reliability is provided. A first insulator is formed. A second insulator is formed over the first insulator. An island-shaped oxide is formed over the second insulator. A stacked body of a third insulator and a conductor is formed over the oxide. The resistance of the oxide is selectively reduced by forming a film containing a metal element over the oxide and the stacked body. After a fourth insulator is formed over the second insulator, the oxide, and the stacked body, an opening portion exposing the second insulator is formed in the fourth insulator. A fifth insulator is formed over the second insulator and the fourth insulator. Oxygen introduction treatment is performed on the fifth insulator. | 2020-08-20 |
20200266290 | MONOLITHIC SELF-ALIGNED HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) AND COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) - Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region and a collector region. The collector region may include a proton implant region having an edge aligned with an edge of the emitter region. In certain aspects, the HBT device also includes a base region disposed between the emitter region and the collector region. | 2020-08-20 |
20200266291 | TRANSISTORS WITH BACKSIDE FIELD PLATE STRUCTURES - Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering. | 2020-08-20 |
20200266292 | COMPOSITE SUBSTRATES OF CONDUCTIVE AND INSULATING OR SEMI-INSULATING SILICON CARBIDE FOR GALLIUM NITRIDE DEVICES - In one aspect, a semiconductor device comprising an electronic conductive Silicon Carbide (SiC) substrate; a semi-insulating or insulating SiC epitaxial layer formed on the electronic conductive SiC substrate; and a Gallium Nitride (GaN) device formed on the semi-insulating or insulating SiC epitaxial layer. In one embodiment, the semi-insulating or insulating SiC epitaxial layer is grown directly on the SiC substrate through chemical vapor deposition (CVD). In another embodiment, the GaN device is a high electron mobility transistor (HEMT). | 2020-08-20 |
20200266293 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body, first and second electrodes, and first and second control electrodes. The first and second electrodes are provided on the semiconductor body. The first and second control electrodes each include a first portion positioned between the semiconductor body and the first electrode, a second portion positioned between the semiconductor body and the second electrode, and a third portion linked to the first and second portions. The semiconductor body includes first to fourth semiconductor layers. The second semiconductor layer is provided on the first semiconductor layer, and extends along the first to third portions. The fourth semiconductor layer is provided selectively on the second semiconductor layer, and extends along the second and third portions. The fourth semiconductor layer includes second conductivity-type impurities with a higher concentration than a concentration of second conductivity-type impurities in the second semiconductor layer. | 2020-08-20 |
20200266294 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region of a second conductivity type and a first base region of a second conductivity type that are respectively selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench that penetrates the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench via a gate insulating film, an interlayer insulating film provided on the gate electrode, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on a back surface of the semiconductor substrate. | 2020-08-20 |
20200266295 | HIGH VOLTAGE LDMOS TRANSISTOR AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region. | 2020-08-20 |
20200266296 | REDUCING BAND-TO-BAND TUNNELING IN SEMICONDUCTOR DEVICES - Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials. | 2020-08-20 |
20200266297 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer. | 2020-08-20 |
20200266298 | NANOSHEET TRANSISTOR WITH STABLE STRUCTURE - Sacrificial gate structures are simultaneously formed in isolation regions that are wider than the sacrificial gate structures formed in the active region. The wider sacrificial gate structures are formed by taking advantage of a smaller lateral etch of p-type silicon than undoped or n-type doped silicon during reactive ion etching. Amorphous or polycrystalline silicon is used as a sacrificial pattern transfer patterning layer in the gate patterning process. The p-type amorphous or polycrystalline silicon increases the sacrificial gate structure length in the isolation region and thus reduces spacing between the sacrificial gate structures in the isolation region. During inner spacer formation, the inner spacers pinch-off all sacrificial gate structures in the isolation region preventing the shallow trench isolation structure to be undercut and thus preventing the collapsing of the sacrificial gate structures in the isolation region. | 2020-08-20 |
20200266299 | FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH LOW RESISTANCE CONTACT - A method for forming a semiconductor device structure is provided. The method includes forming an epitaxial structure over a semiconductor substrate. The method also includes generating and applying plasma on an entire exposed surface of the epitaxial structure to form a modified region in the epitaxial structure. The plasma is directly applied on the source/drain structure without being filtered out, and the plasma includes ions with different charges. The method further includes forming a metal layer on the modified region and heating the metal layer and the modified region to form a metal-semiconductor compound region. | 2020-08-20 |
20200266300 | SEMICONDUCTOR DEVICE AND DISPLAY - A semiconductor device includes a semiconductor film, an interlayer insulating film, a source-drain electrode, and a semiconductor auxiliary film. The semiconductor film includes an oxide semiconductor material and has a channel region and a low-resistance region. The low-resistance region has an electric resistance lower than an electric resistance of the channel region. The interlayer insulating film covers the semiconductor film and has a through-hole opposed to the low-resistance region. The source-drain electrode includes a source electrode and a drain electrode and is electrically coupled to the semiconductor film through the through-hole. The semiconductor auxiliary film is in contact with the low-resistance region of the semiconductor film, reduces an electric resistance of the semiconductor film, and has a first opening at least on a part of a portion opposed to the through-hole. | 2020-08-20 |
20200266301 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present invention provides an array substrate and a display panel. The array substrate includes a first metal layer and an active layer. The first metal layer includes a first metal unit at the middle and a second metal unit and a third metal unit at two sides of the first metal unit. The active layer includes a channel region at the middle and a doped source region and a doped drain region at two sides of the channel region. The first metal unit is arranged corresponding to the channel region. The second metal unit and the third metal unit are connected to the doped source region and the doped drain region, respectively. | 2020-08-20 |
20200266302 | DETECTION APPARATUS, FABRICATION METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY APPARATUS - The present disclosure is related to a detection apparatus. The detection apparatus may include a gate insulating layer. The gate insulating layer may include at least a first layer and a second layer opposite the first layer. A plurality of protruding structures may be provided on a surface of the first layer facing the second layer and/or a surface of the second layer facing the first layer. The first layer and the second layer of the gate insulating layer may be connected through the protruding structures. | 2020-08-20 |
20200266303 | SEMICONDUCTOR DEVICE - A semiconductor device according to as embodiment includes a semiconductor layer that has first and second plane and includes first-conductivity-tom e first semiconductor region, second-conductivity-tom e second semiconductor region between the first semiconductor region and the first plane, first-conductivity-type third semiconductor region between the second semiconductor region and the first plane and has a lower first-conducivity type impurity concentration than the first semiconductor region, and second-conductivity-type fourth semiconductor region between the third semiconductor region. and the first plane and has a higher second-conductivity-type impurity concentration than the second semiconductor region; a first electrode on a side of the first plane of the semiconductor layer and is electrically connected to the third semiconductor region and the fourth semiconductor region; and a second electrode on a side of the second plane of the semiconductor layer, is electrically connected to the first semiconductor region, and is not electrically connected. to the second semiconductor region. | 2020-08-20 |
20200266304 | LAMINATED BODY - A laminated body comprising a substrate, one or more layers selected from a contact resistance reducing layer and a reduction suppressing layer, a Schottky electrode layer and a metal oxide semiconductor layer in this order. | 2020-08-20 |
20200266305 | OPTICAL SENSOR AND METHOD FOR FORMING THE SAME - An optical sensor includes pixels disposed in a substrate and a light collimating layer disposed on the substrate. The light collimating layer includes a first light-shielding layer, first transparent pillars, a second light-shielding layer, and second transparent pillars. The first light-shielding layer is disposed on the substrate. The first transparent pillars through the first light-shielding layer are correspondingly disposed on the pixels. The second light-shielding layer is disposed on the first light-shielding layer and the first transparent pillars. The second transparent pillars through the second light-shielding layer are correspondingly disposed on the first transparent pillars. The top surface area of each of the first transparent pillars is not equal to the bottom surface area of each of the second transparent pillars. | 2020-08-20 |
20200266306 | OPTICAL SENSOR WITH INTEGRATED PINHOLE - An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole. | 2020-08-20 |
20200266307 | HIGH EFFICIENCY SOLAR CELL WITH LIGHTWEIGHT SUPPORT STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A solar cell with lightweight support structure and a method of manufacturing the same are provided. The solar cell includes: a composite substrate; a photoelectric conversion structure disposed on the composite substrate, and including a light receiving side and a back side which is opposite the light receiving side; a front electrode formed on the light receiving side; and a back electrode formed on the back side, where the composite substrate includes an optical reflective layer which is connected with the back side of the photoelectric conversion structure; and where the photoelectric conversion structure includes at least one Group III-V compound semiconductor layer. | 2020-08-20 |
20200266308 | SOLAR CELL - A composition for solar cell electrodes, an electrode formed of the same, and a method of forming an electrode, the composition including a conductive powder; a glass frit; at least one of a cyclosiloxane compound and a silsesquioxane compound; and an organic vehicle. | 2020-08-20 |
20200266309 | IMAGING ELEMENT, SOLID STATE IMAGING DEVICE, AND ELECTRONIC DEVICE - There is provided imaging devices and methods of forming the same, including a stacked structure body including a first electrode, a light-receiving layer formed on the first electrode, and a second electrode formed on the light-receiving layer, where the second electrode comprises an amorphous oxide comprising at least one of zinc and tungsten, and where the second electrode is transparent and electrically conductive and has absorption characteristics of 20% or more at a wavelength of 300 nm. | 2020-08-20 |
20200266310 | PHOTODIODE - A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length. | 2020-08-20 |
20200266311 | SOLAR CELL HERMETIC PACKAGE STRUCTURE - A solar cell hermetic package structure includes a lower-cover plate, a conductive layer, a photovoltaic layer, a lower-electrode lead, an upper-electrode lead, an upper-cover plate, a border and dividers. The conductive layer and the photovoltaic layer are orderly arranged on one side of the lower-cover plate. The upper-electrode lead and the lower-electrode lead are arranged on the lower-cover plate and electrically connected to the photovoltaic layer and the conductive layer. The border is arranged on corresponding side edges of the lower-cover plate and the upper-cover plate. After the upper-cover plate and the lower-cover plate are combined, the photovoltaic layer is arranged in a hermetic package structure between the upper-cover plate and the lower-cover plate. A hermetic area accommodating the photovoltaic layer is formed by the border. The dividers are arranged in gaps of photovoltaic components and used as supports between the upper-cover plate and the lower-cover plate. | 2020-08-20 |
20200266312 | A BACKSHEET FOR A SOLAR CELL MODULE - A backsheet for a photovoltaic module includes a support, an adhesive layer provided on one side of the support, and an outer layer provided on the other side of the support, characterized in that at least one of the adhesive layer and the outer layer is coated from an aqueous composition, and the aqueous composition includes a water soluble or dispersible binder and a water dispersible core/shell polyisocyanate. | 2020-08-20 |
20200266313 | SEMITRANSPARENT THIN-FILM SOLAR MODULE - A thin-film solar module with a substrate and a layer structure applied thereon comprising a rear electrode layer, a front electrode layer, and an absorber layer arranged between the back electrode layer and the front electrode layer. Serially connected solar cells are formed in the layer region by patterning zones, having a rear electrode layer section. The layer region has at least one linear decoating region. The decoating region has an alternating sequence of optically transparent zones and electrode zones. The optically transparent zones are rear-electrode-layer-free and the electrode zones are absorber-layer-free and have a rear electrode layer section. The rear-electrode-layer-sections of at least one pair made up of one solar cell of one solar cell string and one solar cell of the other solar cell string are areally connected to one another by the rear-electrode-layer-section of at least one electrode zone. | 2020-08-20 |
20200266314 | MICRO-SCALE CONCENTRATED PHOTOVOLTAIC MODULE - A photovoltaic (“PV”) module may comprise an array of freeform micro-optics and an array of PV cells. The PV module may be a flat panel with a nominal thickness smaller than the length and width of the flat panel. An array of lenses may be embedded in an array substrate. The lenses may be coupled to light pipes. The lenses may concentrate light through the light pipes to multi junction cells. Diffuse light may be transferred through the array substrate to a silicon cell. The lenses and light pipes may be manufactured using a molding and drawing process. | 2020-08-20 |
20200266315 | SOLAR CELL SEALING MATERIAL AND SOLAR CELL MODULE - A solar cell sealing material of the present invention is a solar cell sealing material that is used to seal a solar cell element and includes an ethylene.α-olefin copolymer, an organic peroxide (A) having a one-hour half-life temperature in a range of equal to or higher than 100° C. and equal to or lower than 130° C., and an organic peroxide (B) having a one-hour half-life temperature in a range of higher than 130° C. and equal to or lower than 160° C., and a ratio (X | 2020-08-20 |
20200266316 | IMAGE SENSOR - An image sensor is disclosed which includes a substrate, a pixel array, a peripheral circuit, an SPAD detector and a VCSEL integrated in the substrate. The peripheral circuit is configured to process an electrical signal obtained from photoelectric conversion in the pixel array, the SPAD detector is configured to convert a first external optical pulse into an electrical pulse to provide a clock signal to the peripheral circuit. The VCSEL is driven by the peripheral circuit and configured to output a second optical pulse. The number of electrical connection terminals in the image sensor is reduced to only two, which is favorable to the miniaturization of the image sensor and simplifies the design of the mating device while allowing the inputting of a first optical pulse and outputting of a second optical pulse. By using these optical signals, extremely high speed and high bandwidth data transmission can be achieved. | 2020-08-20 |
20200266317 | METHOD FOR PRODUCING MODULES OF THIN FILM PHOTOVOLTAIC CELLS IN A ROLL-TO-ROLL PROCESS AND APPARATUS CONFIGURED FOR USING SUCH A METHOD - A method for producing in a roll-to-roll process modules of thin film photovoltaic cells in a substrate film, the modules including the substrate with a photovoltaic layer inbetween a lower and upper electrode layer, by using an apparatus including a belt conveyor, and scribe and print stations arranged at respective positions along a transport direction of the belt conveyor to create an interconnection structure between the photovoltaic cells including an arrangement of structural elements having one or more conductive and isolating scribe lines and a conductive body connecting adjacent thin film photovoltaic cells. The method includes: creating by the processing stations, the interconnection structure in the moving substrate film; measuring the structural elements and determining parameters of each structural element; based on the parameters establishing a positioning error, associated with a functional defect; based on the error, correcting settings of one or more processing stations and/or the belt conveyor. | 2020-08-20 |
20200266318 | METHOD OF TRANSFERRING LIGHT EMITTING DEVICE FOR DISPLAY AND DISPLAY APPARATUS - A method of transferring a light emitting device including the steps of preparing a wafer including a substrate, semiconductor layers disposed on the substrate, and bump pads disposed on the semiconductor layers and arranged in a plurality of light emitting device regions, dividing the wafer into a plurality of light emitting devices, attaching the light emitting devices to a transfer tape disposed on a supporting substrate, such that the substrate contacts the transfer tape, preparing a circuit board including pads arranged thereon, adjoining the supporting substrate with the circuit board, so that the bump pads of at least one light emitting device contact the pads of the circuit board, bonding the at least one light emitting device to the pads by applying heat to the bump pads and the pads, and separating the at least one light emitting device bonded to the pads from the transfer tape. | 2020-08-20 |
20200266319 | DRIVING BACKPLANE, METHOD FOR PRODUCING THE SAME, AND DISPLAY DEVICE - The present application discloses a driving backplane, a method for producing the same and a display device. The driving backplane includes: a substrate; a first insulating film layer disposed on the substrate and including a first region and a second region; an extended anode disposed on a side of the first region of the first insulating film layer, a height of the extended anode matching a height of a cathode of a light-emitting chip; and an extended cathode disposed on a side of the second region of the first insulating film layer, a height of the extended cathode matching a height of an anode of the light-emitting chip. | 2020-08-20 |
20200266320 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes: an n-type clad layer of an n-type aluminum gallium nitride (AlGaN)-based semiconductor material; an active layer of an AlGaN-based semiconductor material provided on a first top surface of the n-type clad layer; and an n-side electrode provided on a second top surface of the n-type clad layer adjacent to the first top surface. The n-side electrode includes a first metal layer on the second top surface containing titanium (Ti) and a second metal layer on the first metal layer containing aluminum (Al). A root-mean-square roughness (Rq) of a top surface of the second metal layer is 5 nm or less. | 2020-08-20 |
20200266321 | METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR DEVICES AND OPTOELECTRONIC SEMICONDUCTOR DEVICE - The invention relates to a method for producing a plurality of optoelectronic semiconductor components, comprising the following steps: preparing a plurality of semiconductor chips spaced in a lateral direction to one another; forming a housing body assembly, at least one region of which is arranged between the semiconductor chips; forming a plurality of fillets, each adjoining a semiconductor chip and being bordered in a lateral direction by a side surface of each semiconductor chip and the housing body assembly; and separating the housing body assembly into a plurality of optoelectronic components, each component having at least one semiconductor chip and a portion of the housing body assembly as a housing body, and each semiconductor chip not being covered by material of the housing body on a radiation emission surface of the semiconductor component, which surface is located opposite a mounting surface. The invention also relates to a semiconductor component. | 2020-08-20 |
20200266322 | SILICONE RESIN COMPOSITION AND USE OF THE SAME - A silicone resin composition useful for producing a cured product which shows high thermal shock resistance is provided. The composition contains a silicone resin containing silicon atoms selected from A1 silicon atoms and A2 silicon atoms, and A3 silicon atoms, in which the ratio of the content of the A3 silicon atoms to the total content of the A1 silicon atoms, the A2 silicon atoms, and the A3 silicon atoms is 50 mol % or more and 99 mol % or less. Side chains bonded to the silicon atoms include an alkyl group having 1 to 3 carbons and an alkoxy group having 1 or 2 carbons, and the molar ratio of alkoxy groups of alkyl groups is 5 or more to 100. | 2020-08-20 |
20200266323 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A display device includes a substrate and a light emitting layer on the substrate. The display device further includes a sealing portion on the light emitting layer. The sealing portion comprises a first inorganic layer. The first inorganic layer comprises at least one layer including silicon, oxygen, nitrogen and hydrogen. The at least one layer of the first inorganic layer includes a content of silicon of about 30-40 (at %), a content of oxygen of about 15-35 at %, a content of nitrogen of about 10-20 at %, a content of hydrogen of about 20-30 at %. | 2020-08-20 |
20200266324 | METHOD AND STRUCTURE OF BONDING A LED WITH A SUBSTRATE - A method of bonding a light-emitting diode (LED) with a substrate includes providing a LED disposed on a bottom surface of a LED substrate; forming a first isolating layer entirely on a substrate; forming a second isolating layer on the first isolating layer within a first area corresponding to an N-type contact pad of the LED; forming a first conductive layer on the second isolating layer within the first area; forming a second conductive layer on the first isolating layer within a second area corresponding to a P-type contact pad of the LED; and bonding the LED to the substrate by connecting the N-type contact pad to the first conductive layer within the first area, and connecting the P-type contact pad to the second conductive layer within the second area. | 2020-08-20 |
20200266325 | LED PRECISION ASSEMBLY METHOD - System and methods to enable integration of electronic components to form LED assembly with a high accuracy (0.1 mm or better) and high process capability (Cpk of 1.67 or higher) for realizing precision electro-mechanical device. The system and methods use through holes that connect a printed circuit board to a housing as fiducial marks and LED emitter center as a reference point for alignment in order to improve the efficacy and accuracy of assembling of the LED assembly. The through holes are drilled by using laser drilling or milling machine, Use of adhesive to anchor the LED component down prior to reflow process i.e. to avoid self alignment characteristic of component on solder paste during reflow process. | 2020-08-20 |
20200266326 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE - A method of manufacturing a display device | 2020-08-20 |
20200266327 | THERMOELECTRIC MODULE WITH INTEGRATED PRINTED CIRCUIT BOARD - A thermoelectric module assembly for thermally conditioning a component is includes first and second heat spreaders spaced apart from one another and at least one thermoelectric sub-assembly between and in thermal communication with the first and second heat spreaders. The at least one thermoelectric sub-assembly includes a plurality of thermoelectric devices and a printed circuit board having a plurality of electrical conduits. Each of the thermoelectric devices has a first end portion and a second end portion, the second end portion opposite from the first end portion, the first end portion mechanically coupled to the printed circuit board and in electrical communication with the plurality of electrical conduits, and the second end portion spaced from the printed circuit board. | 2020-08-20 |
20200266328 | THERMOELECTRIC MODULE - The present invention relates to a thermoelectric module, and a thermoelectric module according to an exemplary embodiment of the present invention includes: a plurality of thermoelectric elements that are disposed between a heat transmission member and a cooling member; and a first electrode layer and a second electrode layer that are respectively disposed between the heat transmission member and the plurality of thermoelectric elements and between the cooling member and the plurality of thermoelectric elements, wherein the plurality of thermoelectric elements may include P-type thermoelectric elements and N-type thermoelectric elements, and a P-type thermoelectric element and an N-type thermoelectric element that neighbor each other may have different heights, and one electrode layer selected from among the first electrode layer and the second electrode layer formed throughout the P-type thermoelectric element and the N-type thermoelectric element that neighbor each other may have at least two bent portions. | 2020-08-20 |
20200266329 | THERMOELECTRIC CONVERSION MODULE AND VEHICLE INCLUDING THE SAME - A thermoelectric conversion module may include a plurality of n type thermoelectric conversion materials and a plurality of p type thermoelectric conversion materials that are disposed alternately, and a plurality of electrodes that connects the plurality of thermoelectric conversion material disposed alternately on one side and on an opposite side alternately, wherein the plurality of electrodes includes a first electrode configured to electrically connect the n type thermoelectric conversion material and the p type thermoelectric conversion material by penetrating the n type thermoelectric conversion material and the p type thermoelectric conversion material to transfer heat obtained from a heat source to the plurality of thermoelectric conversion materials. | 2020-08-20 |
20200266330 | THERMOELECTRIC CONVERSION UNIT, THERMOELECTRIC CONVERSION MODULE, AND EXHAUST-GAS ELECTRICITY GENERATION UNIT - An exhaust-gas electricity generation unit is provided between an engine unit and a discharge unit. The exhaust-gas electricity generation unit includes a connecting pipe connecting the engine unit to the discharge unit and defining an exhaust-gas flow passage in which exhaust gas expelled from the engine unit flows, a plurality of thermoelectric conversion modules provided on an inner surface of the connecting pipe, along flow of heat, near the engine unit and near the discharge unit, and a flow-velocity increasing mechanism for causing the exhaust gas in the connecting pipe to have an increased flow velocity near the discharge unit than near the engine unit. | 2020-08-20 |
20200266331 | DISPLACEMENT MAGNIFICATION DEVICE - A displacement magnification device has a first link portion including a first rigid body and a first plate spring that couples the first rigid body to a supporting portion and a movable portion. A second link portion includes a first rigid body and a second plate spring that couples the first rigid body to the supporting portion and the movable portion. In this structure, the first rigid body and the second rigid body play roles to suppress the bending of the first plate spring and the second plate spring. In addition, a connection portion between the first plate spring and the supporting portion, a connection portion between the second plate spring and the supporting portion, a connection portion between the first plate spring and the movable portion, and a connection portion between the second plate spring and the movable portion play roles of elastic hinges. | 2020-08-20 |
20200266332 | Method and Apparatus for Poling Polymer Thin Films - A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has multiple grounding electrodes, grounding pads located at its edges, and a polymer thin film including multiple areas each covering only one grounding electrode. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a shadow mask below the poling source, and a Z-elevator to raise the workpiece carrier toward the shadow mask and poling source. When the workpiece in the workpiece carrier is raised to contact the underside of the shadow mask, multiple openings of the shadow mask expose only the corresponding multiple thin film areas of the workpiece to the plasma; meanwhile, conductive grounding terminals on the underside of the shadow mask electrically connect the grounding pads of the workpiece with carrier electrodes on the workpiece carrier, to ground the workpiece. | 2020-08-20 |
20200266333 | MEMORY DEVICE - The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more. | 2020-08-20 |
20200266334 | Nitride Diffusion Barrier Structure for Spintronic Applications - A magnetic tunnel junction (MTJ) is disclosed wherein a nitride diffusion barrier (NDB) has a L2/L1/NL or NL/L1/L2 configuration wherein NL is a metal nitride or metal oxynitride layer, L2 blocks oxygen diffusion from an adjoining Hk enhancing layer, and L1 prevents nitrogen diffusion from NL to the free layer (FL) thereby enhancing magnetoresistive ratio and FL thermal stability, and minimizing resistance x area product for the MTJ. NL is the uppermost layer in a bottom spin valve configuration, or is formed on a seed layer in a top spin valve configuration such that L2 and L1 are always between NL and the FL or pinned layer, respectively. In other embodiments, one or both of L1 and L2 are partially oxidized. Moreover, either L2 or L1 may be omitted when the other of L1 and L2 is partially oxidized. A spacer between the FL and L2 is optional. | 2020-08-20 |
20200266335 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor. | 2020-08-20 |
20200266336 | SPIN-ORBIT-TORQUE MAGNETIZATION ROTATING ELEMENT, SPIN-ORBIT-TORQUE MAGNETORESISTANCE EFFECT ELEMENT, AND MAGNETIC MEMORY - This spin-orbit-torque magnetization rotating element includes a spin-orbit torque wiring extending in a first direction and a first ferromagnetic layer laminated on the spin-orbit torque wiring, wherein the spin-orbit torque wiring includes a compound represented by XYZ or X | 2020-08-20 |
20200266337 | Electronic Circuit Structure and Method of Fabricating Electronic Circuit Structure Having Magnetoresistance Element with Improved Electrical Contacts - A manufacturing method results in a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate. | 2020-08-20 |
20200266338 | METHOD FOR FABRICATING MEMORY DEVICE - A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer. | 2020-08-20 |
20200266339 | MEMORY DEVICE - A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer. | 2020-08-20 |
20200266340 | INTEGRATED CIRCUIT - An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer. | 2020-08-20 |
20200266341 | Magnetoresistive Random Access Memory Cell and Fabricating the Same - A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer. | 2020-08-20 |
20200266342 | SELF-ALIGNED AND MISALIGNMENT-TOLERANT LANDING PAD FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer. | 2020-08-20 |
20200266343 | CROSS-POINT MEMORY AND METHODS FOR FORMING OF THE SAME - The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements. | 2020-08-20 |
20200266344 | RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer. | 2020-08-20 |
20200266345 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate a substrate, a first electrode structure on the substrate, the first electrode structure including first insulating patterns and first electrode patterns, the first insulating patterns alternately stacked with the first electrode patterns, a second electrode pattern on a sidewall of the first electrode structure, and a data storage film on a sidewall of the second electrode pattern. The data storage film has a variable resistance. | 2020-08-20 |