34th week of 2020 patent applcation highlights part 56 |
Patent application number | Title | Published |
20200266146 | BONDED ASSEMBLY INCLUDING A SEMICONDUCTOR-ON-INSULATOR DIE AND METHODS FOR MAKING THE SAME - A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices. | 2020-08-20 |
20200266147 | METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF - Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer. | 2020-08-20 |
20200266148 | Semiconductor Structure and Manufacturing Method Thereof - A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure. | 2020-08-20 |
20200266149 | GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES - Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure. | 2020-08-20 |
20200266150 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip. | 2020-08-20 |
20200266151 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure includes a first printed circuit board, a second printed circuit board and first space columns. The first printed circuit board has a first surface and a through hole. The second printed circuit board has a second surface facing the first surface. Each first space column is interconnected between the first surface and the second surface. An encapsulation layer is filled between the first and second printed circuit boards and among the first space columns so as to define a hollow chamber. A MEMS microphone component located within the hollow chamber is located on the first surface and aligned with the through hole. A sensing component is located within the hollow chamber. | 2020-08-20 |
20200266152 | Method and device for the integration of semiconductor wafers - A method for the integration of semiconductor components in a confined space, in particular for 3D integration, in which, after positioning relative to a carrier substrate and/or a redistribution layer, the semiconductor components are protected and fixed in their relative position by introduction of a potting compound, characterized in that before the introduction of the potting compound, a glass substrate having a multiplicity of cutouts separated by partition walls and serving to receive a semiconductor component, is positioned in such a way that the semiconductor component is enclosed by the sidewall surfaces—facing it—of the respective partition walls of the glass substrate. | 2020-08-20 |
20200266153 | LAYER STRUCTURE INCLUDING DIFFUSION BARRIER LAYER AND METHOD OF MANUFACTURING THE SAME - Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer. | 2020-08-20 |
20200266154 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame having a die pad; a semiconductor chip having a front surface in which an integrated circuit is formed, and a back surface that is die-bonded onto the die pad through intermediation of an interposing film and an adhesive layer; and an encapsulating resin for encapsulating the lead frame, the adhesive layer, the interposing film, and the semiconductor chip. The interposing film has a first opening which forms a space between a part of the back surface of the semiconductor chip and the adhesive layer. | 2020-08-20 |
20200266155 | PACKAGE STRUCTURE WITH STRUCTURE REINFORCING ELEMENT AND MANUFACTURING METHOD THEREOF - A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element. | 2020-08-20 |
20200266156 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having first and second surfaces, first and second pads disposed on the first and second surfaces respectively and electrically connected to each other, a semiconductor chip disposed on the first surface and connected to the first pads, a dummy chip disposed on the first surface, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate, an underfill between the semiconductor chip and the first surface of the substrate with an extension portion extended along facing side surfaces of the semiconductor chip and the dummy chip in the perpendicular direction, an upper end of the extension portion lower than the upper surface of the semiconductor chip, and a sealing material on the first surface to seal the semiconductor chip and the dummy chip. | 2020-08-20 |
20200266157 | SEMICONDUCTOR INTEGRATED CIRCUIT AND WITHSTAND VOLTAGE TEST METHOD - A voltage application region and a voltage applying pad form withstand voltage measuring wiring lines insulated from each other and different from each other by connecting a seal ring and a relay region through a via, and the withstand voltage measuring wiring lines different from each other are configured to apply a voltage between insulated seal rings provided on wiring layers adjacent to each other by applying a voltage between the voltage application region and the voltage applying pad. | 2020-08-20 |
20200266158 | HIGH PERFORMANCE THREE-DIMENSIONAL INTEGRATED CIRCUITS - Disclosed are systems and methods to enable multi-layered integrated circuits having two or more layers, capable of communicating via capacitive link coupling. In some embodiments, the layers which include the electrodes of capacitive links can be stacked in face-to-face or face-to-back configuration. | 2020-08-20 |
20200266159 | METHOD OF MAKING A STACKED INDUCTOR-ELECTRONIC PACKAGE - An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor. | 2020-08-20 |
20200266160 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound. | 2020-08-20 |
20200266161 | DETACHABLE BONDING STRUCTURE AND METHOD OF FORMING THEREOF - A detachable bonding structure for performing a device picked-up operation is provided. The detachable bonding structure includes a carrier substrate, a composite glue layer, a metal layer, and a device. The composite glue layer is present on the carrier substrate. The composite glue layer includes an ultraviolet glue and a photolysis material therein. The metal layer is present on the composite glue layer. The device is present on the metal layer. | 2020-08-20 |
20200266162 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view. | 2020-08-20 |
20200266163 | BUMP STRUCTURE MANUFACTURING METHOD - Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips. | 2020-08-20 |
20200266164 | METHOD FOR MANUFACTURING COMPLIANT BUMP - Provided is a method of manufacturing compliant bumps, the method including preparing an electronic device including at least one conductive pad, forming an elastic resin layer on the electronic device, forming a photoresist layer on the elastic resin layer, forming a first photoresist pattern on a region spaced apart from a region where the conductive pad is located, forming a second photoresist pattern having a lower cross-sectional area greater than an upper cross-sectional area, forming an elastic resin pattern having a lower cross-sectional area greater than an upper cross-sectional area, on a region spaced apart from a region where the conductive pad is located, and forming a conductive wiring pattern covering at least a part of the elastic resin pattern and extending to the conductive pad. | 2020-08-20 |
20200266165 | COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME - The copper pillars have improved integrity such that they can readily withstand the harsh reflow conditions of post solder bump application without readily failing. The method of making the copper pillars having the improved integrity involves a two-step electroplating process of varying current densities. | 2020-08-20 |
20200266166 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element. | 2020-08-20 |
20200266167 | SEMICONDUCTOR PACKAGE - The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer. | 2020-08-20 |
20200266168 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide. | 2020-08-20 |
20200266169 | REPLACEMENT BURIED POWER RAIL IN BACKSIDE POWER DELIVERY - Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate. | 2020-08-20 |
20200266170 | RESIN COMPOSITION, CONDUCTIVE COPPER PASTE, AND SEMICONDUCTOR DEVICE - An object of the present invention is to provide: a resin composition in which the specific resistance after curing is low regardless of the type of a thermosetting resin, and furthermore, the specific resistance after curing does not significantly change depending on the content of a copper powder; and a conductive copper paste including the resin composition. There are provided a resin composition including (A) a copper powder having an oxygen content of 0.3% by mass or less, (B) a thermosetting resin, (C) a fatty acid, and (D) an amine or an amine compound, as well as a conductive copper paste containing the resin composition. The (A) component has an average particle size of preferably 1 to 10 μm. | 2020-08-20 |
20200266171 | Semiconductor Arrangement and Method for Producing the Same - A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm. | 2020-08-20 |
20200266172 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction. | 2020-08-20 |
20200266173 | METHODS FOR FABRICATING 3D SEMICONDUCTOR DEVICE PACKAGES, RESULTING PACKAGES AND SYSTEMS INCORPORATING SUCH PACKAGES - Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed. | 2020-08-20 |
20200266174 | Die Stack Assembly Using An Edge Separation Structure For Connectivity Through A Die Of The Stack - A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die. | 2020-08-20 |
20200266175 | LIGHT EMITTING DIODE PANEL AND MANUFACTURING METHOD THEREOF - A light emitting diode panel including a first substrate, a second substrate and a plurality of display units is provided. The display units are disposed between the first substrate and the second substrate. One display unit has multiple first regions and a second region surrounded by the first regions and includes multiple first light emitting diodes, multiple control signal lines and a second light emitting diode. Every N first light emitting diodes construct one pixel unit located within one of the first regions, wherein N is an integer greater than 1. The control signal lines are disposed on the first substrate and each extends toward one first light emitting diode. The second light emitting diode is disposed on the first substrate, located within the second region, and surrounded by the first regions. The second light emitting diode is electrically connected to one of the control signal lines. | 2020-08-20 |
20200266176 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE - A method of manufacturing a display device | 2020-08-20 |
20200266177 | LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF AND DISPLAY MODULE USING THE SAME - A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150. | 2020-08-20 |
20200266178 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first connection structure having a first surface and a second surface and including one or more first redistribution layers, a first semiconductor chip disposed on the first surface, a second semiconductor chip disposed on the second surface, a third semiconductor chip disposed on the second surface, and at least one first passive component disposed between the second and third semiconductor chips on the second surface. The first connection structure may include a first region including a region overlapping the first passive component, and a second region including regions respectively overlapping at least portions of the second and third semiconductor chips, when viewed from above. The first region may be disposed between second regions. The first redistribution may include at least one of a power pattern and a ground pattern in the first region and include a signal pattern in the second region. | 2020-08-20 |
20200266179 | OPTOELECTRONIC DEVICE WITH AN ACTIVE ELEMENT - An optoelectronic device is specified, with
| 2020-08-20 |
20200266180 | INTEGRATED DISPLAY DEVICES - An IC chip comprises LED devices exposed on a front side of the IC chip, I/O bumps on a back side of the IC chip, a first die forming a stack with the LED devices and comprising driver circuits electrically connected to the LED devices, a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps, a second die including pipelining circuits and control circuits for the driver circuits, a second circuit that extends from the second die, and a circuit board electrically connected to the I/O bumps and to a power system. | 2020-08-20 |
20200266181 | MANUFACTURING METHOD OF LIGHT-EMITTING DIODE PACKAGE STRUCTURE - A manufacturing method of the light-emitting diode package structure is provided. A carrier is formed. The carrier comprises a first build-up circuit. At least one self-assembled material layer is formed on the first build-up circuit. A first solder mask layer is formed on the first build-up circuit. The first solder mask layer has at least one opening to expose a portion of the at least one self-assembled material layer. At least one light-emitting diode is disposed on the first build-up circuit. The at least one light-emitting diode has a self-assembled pattern, and the at least one light-emitting diode is self-assembled into the at least one opening of the first solder mask layer through a force between the self-assembled pattern and the at least one self-assembled material layer. | 2020-08-20 |
20200266182 | BONDED ASSEMBLY CONTAINING MULTIPLE MEMORY DIES SHARING PERIPHERAL CIRCUITRY ON A SUPPORT DIE AND METHODS FOR MAKING THE SAME - A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die. | 2020-08-20 |
20200266183 | DISPLAY DEVICE WITH A CHIP ON FILM - A display device including a display panel including a substrate, pixels provided on the substrate, and first lines connected to the pixels, the display device having a bending area where the display panel is bent. The display panel also includes a chip on film overlapping with a portion of the display panel and having second lines, an anisotropic conductive film provided between the chip on film and the display panel connecting the first lines and the second lines, and a coating layer covering the bending area and one end of the chip on film. In such a device, lines of the chip on film may be prevented from being corroded as they may be spaced apart from an edge of an insulating film. | 2020-08-20 |
20200266184 | PATCH ACCOMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES - Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness. | 2020-08-20 |
20200266185 | AREA AND POWER EFFICIENT CIRCUITS FOR HIGH-DENSITY STANDARD CELL LIBRARIES - Example embodiments provide a four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC) and a method for reducing area and power of an integrated circuit (IC) using a MXT4, the MXT4 including a complementary signal generator circuit configured to receive first and second selection signals and to generate first and second complementary selection signals based on respective ones of the first and the second selection signals; and a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) stack switch circuit configured to transmit at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals. | 2020-08-20 |
20200266186 | CHIP, MANUFACTURING METHOD, AND MOBILE TERMINAL - In a chip, a manufacturing method, and a mobile terminal, the chip includes a first region and a second region. The first region is formed by at least one first circuit unit set. The second region is formed by a second circuit unit set. The at least one first circuit unit set includes a plurality of identical circuit units. A number of circuit units in the first region determines a specification of the chip and a size of the first region of the chip. | 2020-08-20 |
20200266187 | ESD PROTECTION CIRCUIT PROVIDING MULTIPLE DETECTION SIGNALS - An ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors each for providing two detection signals. The ESD protection circuit includes driver circuitry that produces trigger signals to clamp circuits that make conductive the clamp circuits in response to an ESD event based on the detection signals from the current mirrors. | 2020-08-20 |
20200266188 | SEMICONDUCTOR DEVICE, AND HIGH VOLTAGE DEVICE WITH SELF-ELECTROSTATIC DISCHARGE PROTECTION - A high voltage device with self-electrostatic discharge protection. The device comprises: a semiconductor substrate; a first N-well ( | 2020-08-20 |
20200266189 | APPARATUS CONTAINING CIRCUIT-PROTECTION DEVICES - Apparatus having an array of memory cells might include a first transistor having a control gate, a first source/drain connected to a first contact for connection to peripheral circuitry, and a second source/drain connected to a second contact for connection to a data line selectively connected to a respective set of strings of series-connected memory cells of the array of memory cells; and a second transistor having a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the data line. | 2020-08-20 |
20200266190 | LOGIC CIRCUIT WITH INDIUM NITRIDE QUANTUM WELL - An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen. | 2020-08-20 |
20200266191 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material. | 2020-08-20 |
20200266192 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure. | 2020-08-20 |
20200266193 | COMPOSITE TRANSISTOR - Disclosed herein is a composite transistor which includes a first transistor TR | 2020-08-20 |
20200266194 | METAL FUSE AND SELF-ALIGNED GATE EDGE (SAGE) ARCHITECTURE HAVING A METAL FUSE - Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure. | 2020-08-20 |
20200266195 | FABRICATION OF FIN FIELD EFFECT TRANSISTORS UTILIZING DIFFERENT FIN CHANNEL MATERIALS WHILE MAINTAINING CONSISTENT FIN WIDTHS - A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar. | 2020-08-20 |
20200266196 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well. | 2020-08-20 |
20200266197 | Integrated Circuitry Comprising An Array, Method Of Forming An Array, Method Of Forming DRAM Circuitry, And Method Used In The Fabrication Of Integrated Circuitry - Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed. | 2020-08-20 |
20200266198 | SEMICONDUCTOR DEVICE INCLUDING ULTRA LOW-K SPACER AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer. | 2020-08-20 |
20200266199 | SEMICONDUCTOR STRUCTURE FOR PREVENTING ROW HAMMERING ISSUE IN DRAM CELL AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench. | 2020-08-20 |
20200266200 | SEMICONDUCTOR DEVICE HAVING STRAP CELL - A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions. | 2020-08-20 |
20200266201 | SEMICONDUCTOR STRUCTURE, STATIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A semiconductor structure and a static random access memory are provided. The semiconductor structure includes a base substrate. The base substrate includes a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The semiconductor structure further includes a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin, and pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions on one side of the gate structure is a non-epitaxial layer doped region in the fin. | 2020-08-20 |
20200266202 | 3-D NAND Control Gate Enhancement - Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. | 2020-08-20 |
20200266203 | Memory Arrays And Methods Used In Forming A Memory Array - A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed. | 2020-08-20 |
20200266204 | Memory Arrays And Methods Used In Forming A Memory Array - A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed. | 2020-08-20 |
20200266205 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2020-08-20 |
20200266206 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BIT LINES BETWEEN MEMORY ELEMENTS AND AN UNDERLYING PERIPHERAL CIRCUIT AND METHODS OF MAKING THE SAME - A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced. | 2020-08-20 |
20200266207 | CHANNEL HOLE AND BITLINE ARCHITECTURE AND METHOD TO IMPROVE PAGE OR BLOCK SIZE AND PERFORMANCE OF 3D NAND - Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate, the alternating layer stack including a plurality of conductor/dielectric layer pairs. The memory device further includes a first column of vertical memory strings extending through the alternating layer stack, and a first plurality of bitlines displaced along a first direction and extending along a second direction. The first column of vertical memory strings is disposed at a first angle relative to the second direction. Each of the first plurality of bitlines is connected to an individual vertical memory string in the first column. | 2020-08-20 |
20200266208 | APPARATUS AND METHODS FOR PLUG FILL DEPOSITION IN 3-D NAND APPLICATIONS - An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers. | 2020-08-20 |
20200266209 | METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions. | 2020-08-20 |
20200266210 | Assemblies Having Vertically-Extending Structures, and Methods of Forming Assemblies Having Vertically-Extending Channel Material Pillars - Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings. | 2020-08-20 |
20200266211 | THROUGH ARRAY CONTACT (TAC) FOR THREE-DIMENSIONAL MEMORY DEVICES - Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack. | 2020-08-20 |
20200266212 | VERTICAL MEMORY DEVICE AND METHOD OF FABRICATION THE SAME - A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate. | 2020-08-20 |
20200266213 | SEMICONDUCTOR DEVICE INCLUDING DIELECTRIC LAYER - A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion. | 2020-08-20 |
20200266214 | Display Panel, Method for Manufacturing the Same, and Display Device - The present disclosure provides a display panel, a method for manufacturing the same, and a display device. The insulation layer is provided above the first conductive electrodes in the bonding area of the display panel, the insulation layer covers the first conductive electrodes, and the insulation layer is capable of being pierced by ACF particles. When the display panel is bound to an FPC by an ACF, second conductive electrodes on the FPC can be electrically coupled to the first conductive electrodes on the display panel through the ACF particles, thereby achieving the bonding connection between the display panel and the FPC, even if a conductive foreign object falls into the area where the first conductive electrodes are located, short circuit cannot be caused, thereby improving the product yield. | 2020-08-20 |
20200266215 | ARRAY SUBSTRATE AND DISPLAY APPARATUS - An array substrate and display apparatus, the array substrate comprising a base substrate ( | 2020-08-20 |
20200266216 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a base substrate, an active layer on the base substrate and including a first active pattern, a first insulating layer on the active layer, a first gate conductive layer on the first insulating layer, a second insulating layer on the first gate conductive layer, and a third gate conductive layer on the second insulating layer, and including a third-a gate pattern. The third gate conductive layer is not directly connected to the first gate conductive layer. | 2020-08-20 |
20200266217 | FABRICATION OF THIN-FILM ELECTRONIC DEVICES WITH NON-DESTRUCTIVE WAFER REUSE - Thin-film electronic devices such as LED devices and field effect transistor devices are fabricated using a non-destructive epitaxial lift-off technique that allows indefinite reuse of a growth substrate. The method includes providing an epitaxial protective layer on the growth substrate and a sacrificial release layer between the protective layer and an active device layer. After the device layer is released from the growth substrate, the protective layer is selectively etched to provide a newly exposed surface suitable for epitaxial growth of another device layer. The entire thickness of the growth substrate is preserved, enabling continued reuse. Inorganic thin-film device layers can be transferred to a flexible secondary substrate, enabling formation of curved inorganic optoelectronic devices. | 2020-08-20 |
20200266218 | STACKED TRANSISTORS WITH DIELECTRIC BETWEEN CHANNELS OF DIFFERENT DEVICE STRATA - Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric. | 2020-08-20 |
20200266219 | SEMICONDUCTOR DEVICE AND DISPLAY - A semiconductor device includes a semiconductor film, a semiconductor auxiliary film, a wiring line, a first metal film, and an interlayer insulating film. The semiconductor film includes a channel region and a low-resistance region. The semiconductor film includes indium and oxygen. The semiconductor auxiliary film is in contact with the low-resistance region of the semiconductor film and reduces the electric resistance of the semiconductor film. The wiring line is electrically coupled to the low-resistance region of the semiconductor film. The first metal film covers the wiring line and has a higher standard electrode potential than the indium. The interlayer insulating film covers the semiconductor film with the first metal film interposed therebetween. The interlayer insulating film has a first hole and a second hole. The first hole is provided at a position opposed to the low-resistance region of the semiconductor film. The second hole reaches the first metal film. | 2020-08-20 |
20200266220 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An array substrate and a method of manufacturing the same are provided. The method of manufacturing an array substrate includes: forming a black matrix and an organic insulating pattern on a base substrate with a thin film transistor formed thereon, wherein the black matrix and the organic material pattern are formed by using an identical mask. | 2020-08-20 |
20200266221 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The present invention is provided with: a photoelectric conversion section that performs photoelectric conversion; a charge retaining section that temporarily retains electric charge converted by the photoelectric conversion section; and a first trench formed in a semiconductor substrate between the photoelectric conversion section and the charge retaining section, the first trench being higher than the photoelectric conversion section in a depth direction of the semiconductor substrate. Alternatively, the first trench is lower than the photoelectric conversion section and higher than the charge retaining section in the depth direction of the semiconductor substrate. The present technology can be applied to, for example, a back-illuminated CMOS image sensor. | 2020-08-20 |
20200266222 | HIGH-SPEED IMAGE SENSOR - A backside-illuminated multi-collection-gate image sensor is expected to achieve ultra-high-speed imaging. Signal electrons generated by incident light are collected to the pixel center of the front side and distributed to multiple collection gates placed around the center at a very short time interval. The temporal resolution is measured by the spread of arrival times of signal electrons to a collection gate. The major cause of the spread is mixing of signal electrons generated near the pixel border travelling a longer horizontal distance to the pixel center and those generated near the pixel center. Suppression of the horizontal travel time effectively decreases the standard deviation of the distribution of the arrival time. Therefore, devices to suppress the effects of the horizontal motion are introduced, such as a pipe-like photoelectron conversion layer with a much narrower cross section than the pixel area and a funnel-like photoelectron conversion layer. | 2020-08-20 |
20200266223 | LOW NOISE VERTICAL GATE DEVICE STRUCTURE - Various embodiments of the present disclosure are directed towards an image sensor including a photodetector disposed in a semiconductor substrate. A floating diffusion node is disposed in the semiconductor substrate and is above the photodetector. A transfer gate electrode overlies the photodetector. The transfer gate electrode has a top conductive body overlying a top surface of the semiconductor substrate and a bottom conductive body extending from the top conductive body to below the floating diffusion node. A portion of the top conductive body directly overlies the floating diffusion node. A first sidewall of the top conductive body directly overlies the bottom conductive body. | 2020-08-20 |
20200266224 | IMAGE SENSOR PACKAGE AND IMAGE SENSING MODULE - An image sensor package includes a substrate, an image sensor chip disposed on the substrate, and an external force absorbing layer disposed between the substrate and the image sensor chip and having a first surface and a second surface opposite to the first surface. The image sensor package further includes an adhesive layer configured to bond the second surface of the external force absorbing layer to the substrate. The adhesive layer has a first modulus, and the external force absorbing layer has a second modulus different from the first modulus. | 2020-08-20 |
20200266225 | FORMATION METHOD OF LIGHT SENSING DEVICE - A method for forming a light sensing device is provided. The method includes forming a light sensing region in a semiconductor substrate and forming a light shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the light shielding layer and partially removing the light shielding layer and the dielectric layer to form a light shielding element and a dielectric element. A top width of the light shielding element is greater than a bottom width of the dielectric element. The light shielding element and the dielectric element surround a recess, and the recess is aligned with the light sensing region. The method further includes forming a filter element in the recess. | 2020-08-20 |
20200266226 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate. The substrate includes a plurality of pixels. The semiconductor device also includes a light collimator layer disposed on the substrate. The light collimator layer includes a transparent connection feature disposed on the substrate, and a plurality of transparent pillars disposed on the transparent connection feature. The plurality of transparent pillars cover the plurality of pixels, and the transparent connection feature connects to the plurality of transparent pillars. The plurality of transparent pillars and the transparent connection feature are made of a first material which includes a transparent material. The light collimator layer also includes a plurality of first light-shielding features disposed on the transparent connection feature. The top surface of one of the transparent pillars is level with the top surface of one of the first light-shielding features. | 2020-08-20 |
20200266227 | SENSING MODULE AND IMAGE CAPTURING APPARATUS - A sensing module including a sensing array, a first shielding layer, a second shielding layer, and a reflective layer is provided. The sensing array includes a plurality of light passing regions and a light receiving surface facing away from an object, and the sensing array is located between the first shielding layer having a plurality of first openings and the second shielding layer having a plurality of second openings. The second shielding layer is located between the sensing array and the reflective layer. The light beams reflected by the object sequentially pass through the first openings, the light passing regions, the second openings, and are then transmitted to the reflective layer. The light beams are reflected by the reflective layer and then pass through the second openings again to be transmitted to the light receiving surface of the sensing array. An image capturing apparatus is also provided. | 2020-08-20 |
20200266228 | CONCAVE REFLECTOR FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR (CIS) - In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall. | 2020-08-20 |
20200266229 | LOW-NOISE IMAGE SENSOR HAVING STACKED SEMICONDUCTOR SUBSTRATES - Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface. | 2020-08-20 |
20200266230 | COLOR IMAGE-CAPTURE ELEMENT AND IMAGE CAPTURE DEVICE - Provided is a highly-sensitive color image-capture element and an image capture device that can be simply manufactured, have little polarization dependency, and have micro-spectroscopic elements capable of separating incident light into three wavelength ranges integrated facing a two-dimensional pixel array. An image capture element | 2020-08-20 |
20200266231 | IMAGE SENSOR WITH IMPROVED QUANTUM EFFICIENCY SURFACE STRUCTURE - The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer. | 2020-08-20 |
20200266232 | IMAGE SENSOR WITH IMPROVED QUANTUM EFFICIENCY SURFACE STRUCTURE - The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer. | 2020-08-20 |
20200266233 | MICRO LIGHT-EMITTING DIODE AND MANUFACTURING METHOD OF MICRO LIGHT-EMITTING DIODE - A micro light-emitting diode includes a first micro light-emitting diode including a first light-emitting layer and emitting light at a first wavelength, and a second micro light-emitting diode including the first light-emitting layer and a second light-emitting layer emitting light at a second wavelength longer than the first wavelength, in which the second light-emitting layer is a nitride semiconductor layer doped with a second rare earth element, and a nitride semiconductor of the first micro light-emitting diode and the nitride semiconductor of the second micro light-emitting diode are separated from each other. | 2020-08-20 |
20200266234 | SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING DEVICES - Apparatus and methods advantageously provide parallel-plate capacitors in superconducting integrated circuits. A method may include forming a metal-oxide layer to overlie at least a portion of a first capacitor plate, the first capacitor plate comprising a superconductive material, and depositing a second capacitor plate to overlie at least a portion of the metal-oxide layer, the second capacitor plate comprising a superconductive material. The method may include depositing a base electrode of superconductive material to overlie at least a portion of a substrate, depositing the first capacitor plate to overlie at least a portion of the base electrode, and superconductingly electrically coupled to the base electrode, and depositing a counter electrode of superconductive material to overlie at least a portion of the second capacitor plate, the counter electrode superconductingly electrically coupled to the second capacitor plate. The superconducting integrated circuit may include a parallel-plate capacitor and a Josephson junction. | 2020-08-20 |
20200266235 | MAGNETORESISTIVE STACK WITH SEED REGION AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%). | 2020-08-20 |
20200266236 | TOP PINNED MTJ STACK WITH SYNTHETIC ANTI-FERROMAGNETIC FREE LAYER AND ALN SEED LAYER - A top pinned magnetic tunnel junction (MTJ) stack for use in spin-transfer torque magnetoresistive random access memory (STT MRAM) is provided. The top pinned MTJ stack contains a synthetic anti-ferromagnetic magnetic free layer stack that is formed on an insulating aluminum nitride (AlN) seed layer having hexagonal symmetry. For such a top pinned MTJ stack, the symmetry requirements for the tunnel barrier layer do not conflict anymore with the symmetry requirements for strong anti-ferromagnetic exchange. Further, and compared to using only a metallic seed, the insulating AlN seed layer limits spin pumping from the magnetic free layer into the metallic seed layer and therefore lowers the switching current, while only making a small contribution to the resistance of a STT MRAM. | 2020-08-20 |
20200266237 | METHOD OF FABRICATING INTEGRATED CIRCUIT - An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided. | 2020-08-20 |
20200266238 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A resistive random access memory including a stacked structure, at least one vertical electrode, a selector element, and a plurality of resistance changeable structures is provided. The stacked structure is formed by a plurality of horizontal electrodes and a plurality of first dielectric layers stacked alternately, wherein the stacked structure has at least one channel hole extending through the horizontal electrodes and the first dielectric layers. The vertical electrode is formed in the at least one channel hole. The selector element is formed in the channel hole between the vertical electrode and the stacked structure. The resistance changeable structures are disposed on the surface of each of the horizontal electrodes and are in contact with the selector element in the channel hole. | 2020-08-20 |
20200266239 | RESISTIVE RANDOM ACCESS MEMORY CIRCUIT - An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line. | 2020-08-20 |
20200266240 | SEMICONDUCTOR MODULE AND POWER CONVERSION APPARATUS - An emitter interconnection connecting the emitter of a semiconductor switching element to a negative electrode is different in one or both of length and width from an emitter interconnection connecting the emitter of a semiconductor switching element to the negative electrode. At the time of switching, an induced electromotive force is generated at a gate control wire, or at a gate pattern, or at an emitter wire, by at least one of a current flowing through a positive electrode and a current flowing through the negative electrode, so as to reduce the difference between the emitter potential of the semiconductor switching element and the emitter potential of the semiconductor switching element caused by the difference. | 2020-08-20 |
20200266241 | IMAGING ELEMENT, METHOD OF MANUFACTURING IMAGING ELEMENT, AND IMAGING DEVICE - An imaging element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer including a p-type semiconductor and an n-type semiconductor, and provided between the first electrode and the second electrode, in which the photoelectric conversion layer has an exciton charge separation rate of 1×10 | 2020-08-20 |
20200266242 | Array Substrate, Display Device and Spatial Positioning Method of Display Device - Embodiments of the present disclosure provide an array substrate, a display device and a spatial positioning method of a display device. The display device includes a base substrate, a pixel layer arranged at a side of the base substrate, a light source structure having a same light exit direction as the pixel layer, a processing element. The light source structure to emits collimation invisible light, the pixel layer includes a plurality of sub-pixels and at least one sensing pixel arranged between the sub-pixels, the at least one sensing pixel receives reflected light of the collimation invisible light emitted by the light source structure and reflected by an object to be positioned, the processing element is coupled with the sensing pixel and the light source structure, a distance from the object to the display device is calculated according to relevant data information of the collimation invisible light and the reflected light. | 2020-08-20 |
20200266243 | LIGHT CONVERSION SUBSTRATE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE - A light conversion substrate includes a first substrate having a first region, a second region, and a third region. A first light conversion pattern is disposed on the first region and includes first wavelength conversion particles. A second light conversion pattern is disposed on the second region and is spaced apart from the first light conversion pattern and includes second wavelength conversion particles. A first scattering pattern is disposed on the third region to fill a space between the first light conversion pattern and the second light conversion pattern and includes first scattering particles. The first scattering pattern overlaps a portion of the first light conversion pattern and a portion of the second light conversion pattern in a direction of the thickness of the first substrate. | 2020-08-20 |
20200266244 | DISPLAY APPARATUS AND METHOD OF FABRICATING THE SAME - A display apparatus includes a display panel including a plurality of pixels, and a cover panel including a window layer, an optical filter layer, a color filter layer and a bezel layer. The window layer includes a transmission region and a bezel region adjacent to the transmission region. The optical filter layer is disposed on the transmission region of the rear surface of the window layer. The color filter layer is disposed on the optical filter layer and includes a quantum dot. The bezel layer is disposed on the bezel region of the rear surface. The optical filter layer includes a partition wall layer, in which an opening is defined, a light-blocking layer disposed on the partition wall layer, and a reflection layer disposed in the opening. The bezel layer has a same color as the light-blocking layer. | 2020-08-20 |
20200266245 | DISPLAY SCREEN, MOBILE TERMINAL AND DISPLAY METHOD - A display screen, a mobile terminal and a display method are provided. The display screen includes an OLED display screen and an optical fingerprint module arranged in the OLED display screen. The OLED display screen includes a light-emitting layer and a touch screen. The light-emitting layer includes a first light-emitting region and a second light-emitting region. The first light-emitting region is arranged at a position corresponding to the optical fingerprint module and configured to, when the region of the touch screen, which corresponds to the first light-emitting region, is not touched, emit light at a first preset brightness value, and when the region of the touch screen, which corresponds to the first light-emitting region, is touched, emit light at a second preset brightness value, the first preset brightness value is smaller than the second preset brightness value. | 2020-08-20 |