34th week of 2015 patent applcation highlights part 55 |
Patent application number | Title | Published |
20150235798 | FUSE - A fuse includes a pair of terminals and a fusible part that is provided between the pair of terminals, makes conductive connection between both of the pair of terminals, and is fused when an overcurrent flows. At least the fusible part is manufactured by a stereoscopic modeling method. | 2015-08-20 |
20150235799 | VERSATILE SPIN-POLARIZED ELECTRON SOURCE - One or more embodiments relate generally to the field of photoelectron spin and, more specifically, to a method and system for creating a controllable spin-polarized electron source. One preferred embodiment of the invention generally comprises: method for creating a controllable spin-polarized electron source comprising the following steps: providing one or more materials, the one or more materials having at least one surface and a material layer adjacent to said surface, wherein said surface comprises highly spin-polarized surface electrons, wherein the direction and spin of the surface electrons are locked together; providing at least one incident light capable of stimulating photoemission of said surface electrons; wherein the photon polarization of said incident light is tunable; and inducing photoemission of the surface electron states. | 2015-08-20 |
20150235800 | High-Speed Multiframe Dynamic Transmission Electron Microscope Image Acquisition System With Arbitrary Timing - An electron microscope is disclosed which has a laser-driven photocathode and an arbitrary waveform generator (AWG) laser system (“laser”). The laser produces a train of temporally-shaped laser pulses of a predefined pulse duration and waveform, and directs the laser pulses to the laser-driven photocathode to produce a train of electron pulses. An image sensor is used along with a deflector subsystem. The deflector subsystem is arranged downstream of the target but upstream of the image sensor, and has two pairs of plates arranged perpendicular to one another. A control system controls the laser and a plurality of switching components synchronized with the laser, to independently control excitation of each one of the deflector plates. This allows each electron pulse to be directed to a different portion of the image sensor, as well as to be provided with an independently set duration and independently set inter-pulse spacings. | 2015-08-20 |
20150235801 | CHARGED-PARTICLE-BEAM DEVICE AND METHOD FOR CORRECTING ABERRATION - In aberration measurement, a focus or an inclination angle of a beam is changed to extract a characteristic amount from plural images of an electron microscope, so that an aberration coefficient indicating the size and direction of aberration is obtained. However, when the aberration is extremely large, the electron microscope images are greatly distorted, which causes difficulties in extraction of the feature amount. | 2015-08-20 |
20150235802 | HOLDER DEVICE FOR ELECTRON MICROSCOPE - Disclosed is a holder device for an electron microscope, which efficiently collects light emitted when electrons collide with a sample inside the electron microscope and is selectively usable in various electron microscopes since it can be easily attached to and detached from the electron microscopes. The holder device includes a frame; a sample support block configured to be supported on the frame and comprising a sample mounting portion to support an edge of a sample; a mirror unit configured to comprise an upper mirror and a lower mirror respectively arranged above and below the sample and reflect light radiating from the sample, which is mounted to the sample mounting portion and to which an electron beam is emitted, in a predetermined direction; a condensing lens configured to condense light from the mirror unit on a predetermined target; and an optical fiber configured to collect light from the condensing lens. | 2015-08-20 |
20150235803 | Charged Particle Beam Device and Sample Observation Method - All of the conventional charged particle beam devices are designed only for the observation at atmospheric pressure or in gas atmosphere at a pressure substantially equal to the atmospheric pressure, and there is no device enabling easy observation using a typical high-vacuum charged particle microscope at atmospheric pressure or in gas atmosphere at a pressure substantially equal to the atmospheric pressure. Such a conventional technique has another problem that the distance between the diaphragm and a sample cannot be controlled, and so it has a high risk of breakage of the diaphragm. Then, the device of the present invention includes a diaphragm configured to separate a space to place a sample therein so that pressure of the space to place the sample therein is kept larger than pressure of the interior of the enclosure, the diaphragm letting the primary charged particle beam transmit or pass therethrough and being removable; a contact prevention member configured to prevent a contact between the sample and the diaphragm; and an adjustment mechanism configured to let at least a part of the contact prevention member in an optical axis direction of the charged particle optic column. | 2015-08-20 |
20150235804 | Charged Particle Microscope System and Measurement Method Using Same - A charged particle microscope system with a charged particle microscope including an irradiation unit that irradiates a subject to be inspected with a charged particle beam and a detection unit having a detector that detects a charged particle signal from the subject to be inspected irradiated by the irradiation unit; a signal processing unit that converts the charged particle signal detected by the detector of the charged particle microscope into an image signal; and an arithmetic processing unit that corrects the image signal converted by the signal processing unit with the use of signal conversion characteristics. | 2015-08-20 |
20150235805 | METHOD FOR MONITORING ENVIRONMENTAL STATES OF A MICROSCOPE SAMPLE WITH AN ELECTRON MICROSCOPE SAMPLE HOLDER - An apparatus and a method for measuring and monitoring the properties of a fluid, for example, pressure, temperature, and chemical properties, within a sample holder for an electron microscope. The apparatus includes at least one fiber optic sensor used for measuring temperature and/or pressure and/or pH positioned in proximity of the sample. | 2015-08-20 |
20150235806 | INTERFACE, A METHOD FOR OBSERVING AN OBJECT WITHIN A NON-VACUUM ENVIRONMENT AND A SCANNING ELECTRON MICROSCOPE - An interface, a scanning electron microscope and a method for observing an object that is positioned in a non-vacuum environment. The method includes: passing at least one electron beam that is generated in a vacuum environment through at least one aperture out of an aperture array and through at least one ultra thin membrane that seals the at least one aperture; wherein the at least one electron beam is directed towards the object; wherein the at least one ultra thin membrane withstands a pressure difference between the vacuum environment and the non-vacuum environment; and detecting particles generated in response to an interaction between the at least one electron beam and the object. | 2015-08-20 |
20150235807 | MULTI CHARGED PARTICLE BEAM WRITING APPARATUS AND MULTI CHARGED PARTICLE BEAM WRITING METHOD - A multi charged particle beam writing apparatus of the present invention includes an aperture member to form multiple beams, a plurality of first deflectors to respectively perform blanking deflection of a corresponding beam, a second deflector to collectively deflect the multiple beams having passed through the plurality of openings of the aperture member so that the multiple beams do not reach the target object, a blanking aperture member to block each beam that has been deflected to be in the off state by the plurality of first deflectors, and a current detector, arranged at the blanking aperture member, to detect a current value of all beams in the on state in the multiple beams that have been deflected by the second deflector. | 2015-08-20 |
20150235808 | SYSTEMS AND METHODS FOR IMPROVING WAFER ETCH NON-UNIFORMITY WHEN USING TRANSFORMER-COUPLED PLASMA - A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one. | 2015-08-20 |
20150235809 | PLASMA PROCESSING APPARATUS AND FILTER UNIT - Provided is a plasma processing apparatus in which an external circuit is electrically connected, via a line, to a predetermined electric member within a processing container thereof, and noises of first and second high frequency waves are attenuated or blocked by a filter provided on the line when the noises enter the line from the electric member toward the external circuit. The filter includes: an air core coil provided at a first stage when viewed from the electric member side; a toroidal coil connected in series with the air core coil; an electroconductive casing configured to accommodate or enclose the air core coil and the toroidal coil; a first condenser electrically connected between a connection point between the air core coil and the toroidal coil and the casing; and a second condenser connected between a terminal of the toroidal coil at the external circuit side and the casing. | 2015-08-20 |
20150235810 | TCCT MATCH CIRCUIT FOR PLASMA ETCH CHAMBERS - A match circuit includes the following: a power input circuit coupled to an RF source; an inner coil input circuit coupled between the power input circuit and an input terminal of an inner coil, the inner coil input circuit including an inductor and a capacitor coupled in series to the inductor, the inductor connecting to the power input circuit, and the capacitor connecting to the input terminal of the inner coil, a first node being defined between the power input circuit and the inner coil input circuit; an inner coil output circuit coupled between an output terminal of the inner coil and ground, the inner coil output circuit defining a direct pass-through connection to ground; an outer coil input circuit coupled between the first node and an input terminal of an outer coil; and an outer coil output circuit coupled between an output terminal of the outer coil and ground. | 2015-08-20 |
20150235811 | TUNABLE MULTI-ZONE GAS INJECTION SYSTEM - A tunable multi-zone injection system for a plasma processing system for plasma processing of substrates such as semiconductor wafers. The injector can include an on-axis outlet supplying process gas at a first flow rate to a central zone and off-axis outlets supplying the same process gas at a second flow rate to an annular zone surrounding the central zone. The arrangement permits modification of gas delivery to meet the needs of a particular processing regime by allowing independent adjustment of the gas flow to multiple zones in the chamber. In addition, compared to consumable showerhead arrangements, a removably mounted gas injector can be replaced more easily and economically. | 2015-08-20 |
20150235812 | SUBSTRATE PROCESSING DEVICE AND SUBSTRATE PROCESSING METHOD - Disclosed is an apparatus and method of processing substrate, wherein the apparatus comprises a process chamber; a substrate supporter for supporting at least one of substrates, wherein the substrate supporter is provided in the process chamber, and is rotated at a predetermined direction; a chamber lid confronting with the substrate supporter, the chamber lid for covering the process chamber; and a gas distributor having a plurality of gas distribution modules for distributing gas to the substrate, wherein the plurality of gas distribution modules are connected to the chamber lid, wherein each of the gas distribution modules includes a power source electrode and a ground electrode confronting each other, a plasma discharge space is formed between the power source electrode and the ground electrode, and the plasma discharge space is not overlapped with a thin film formation region of the substrate supported by the substrate supporter. | 2015-08-20 |
20150235813 | PLASMA PROCESSING DEVICE AND OPERATION METHOD - An operation method of a plasma processing device, includes performing a plasma process on a workpiece by supplying first high frequency power of a predetermined output to an electrode and generating plasma; and performing a charge storage process before the plasma process when a time interval from an end of a previous operation of the plasma processing device exceeds a predetermined interval, the charge storage process including supplying, to the electrode, second high frequency power of a lower output than the predetermined output. | 2015-08-20 |
20150235814 | PLASMA SOURCE FOR A PLASMA CVD APPARATUS AND A MANUFACTURING METHOD OF AN ARTICLE USING THE PLASMA SOURCE - A plasma source for a plasma CVD apparatus that includes an electrode group including four electrodes, which are a first electrode, a second electrode, a third electrode and a fourth electrode arranged in a row. The electrode group is connected to at least one AC power supply. A voltage supplied to two of the four electrodes is shifted in phase from a voltage supplied to the remaining two electrodes. A space to which a source gas is supplied is provided between the adjacent electrodes, and voltages applied to at least one set among the adjacent two electrodes are in the same phase. | 2015-08-20 |
20150235815 | SUBSTRATE PROCESSING APPARATUS - An apparatus includes a row of substrate transfer devices | 2015-08-20 |
20150235816 | APPARATUS FOR MONITORING GAS AND PLASMA PROCESS EQUIPMENT INCLUDING THE SAME - Provided is an apparatus for monitoring a gas and plasma process equipment including the same. The apparatus includes: a housing including a gas inflow hole, a gas discharge hole, and windows; a light source disposed adjacent to one of the windows outside the housing to provide source light to a gas supplied between the gas inflow hole and the gas discharge hole; a sensor disposed adjacent to the other of the windows outside the housing to detect fluorescence emitted from the gas by the source light; and a coil disposed in the housing between the gas inflow hole and the gas discharge hole to heat and decompose the gas between the light source and the sensor, thereby increasing the fluorescence emitted from the gas. | 2015-08-20 |
20150235817 | MAGNETRON SPUTTERING APPARATUS AND MAGNETRON SPUTTERING METHOD - A magnetron sputtering apparatus including a first magnet array arranged helically, a second magnet array arranged side by side with the first magnet array, a stationary magnet disposed in the circumference of the first and second magnet arrays, a magnet rotation mechanism causing the first and second magnet arrays to rotate around a rotation axis, and a plurality of magnetic induction members which is disposed between the outer perimeter of the first and second magnet arrays and the stationary magnet in a direction crossing the rotation axis direction and arranged in the rotation axis direction when viewed from the side of a target, and attracts magnetic force lines coming out from the first magnet array to guide the magnetic force lines to the side of the target or attracts magnetic force lines coming in from the side of the target to guide the magnetic force lines to the second magnet array. | 2015-08-20 |
20150235818 | MAGNETRON SPUTTERING COATING DEVICE, A NANO-MULTILAYER FILM, AND THE PREPARATION METHOD THEREOF - A magnetron sputtering coating device includes a deposition chamber, sputtering cathodes, a rotating stand within the deposition chamber, a support platform on the rotating stand, a first rotation system for driving the rotating stand to rotate around a central axis of the rotating stand, and a baffle fixed on the rotating stand. The sputtering cathodes are arranged around and perpendicular to the rotating stand. | 2015-08-20 |
20150235819 | OXIDE SINTERED BODY AND SPUTTERING TARGET - An oxide sintered body is obtained by mixing and sintering a zinc oxide, an indium oxide, a gallium oxide and a tin oxide. The oxide sintered body has a relative density of 85% or more, and has volume ratios satisfying the following expressions (1) to (3), respectively, as determined by X•ray diffractometry: (1) (Zn | 2015-08-20 |
20150235820 | OXIDE SINTERED BODY, PRODUCTION METHOD THEREFOR, TARGET, AND TRANSPARENT CONDUCTIVE FILM - A target for sputtering which enables to attain high rate film-formation of a transparent conductive film suitable for a blue LED or a solar cell. A oxide sintered body includes an indium oxide and a cerium oxide, and one or more oxide of titanium, zirconium, hafnium, molybdenum and tungsten. The cerium content is 0.3 to 9% by atom, as an atomicity ratio of Ce/(In+Ce), and the content of cerium is equal to or lower than 9% by atom, as an atomicity ratio of Ce/(In+Ce). The oxide sintered body has an In | 2015-08-20 |
20150235821 | UNIFORM FORCE FLANGE CLAMP - A clamp is provided that incorporates a plurality of flexible links with V flexures between the links to maintain even spacing of the links before and during installation. Each link has multiple segments joined around at least one flexure point, and a floating band surrounding the links to distribute clamping pressure that is produced along a circumference of contact points. The clamp provides evenly distributed clamping pressure by increasing the number of clamping contact points between the clamp and articles being joined. The clamp has non-limiting applications for clamping target tubes or as a vacuum flange for ISO fittings. A clamp can produce a vacuum tight seal between a target tube and end block or end support flange of a rotary magnetron without resort to tools, and as such is rapidly secured in place. | 2015-08-20 |
20150235822 | PROCESSING APPARATUS - The present invention provides a processing apparatus including a supply source including a first supply source and a second supply source arranged to respectively face a first surface of a substrate and a second surface on an opposite side to the first surface and configured to supply a material to apply a process to the substrate, a shield member including a first shield provided around the first supply source and a second shield provided around the second supply source, the first shield and the second shield being arranged to sandwich the substrate, and a moving device configured to move the first shield and the second shield to set one of a close state in which the first shield and the second shield are close to each other and a separate state in which the first shield and the second shield are separate from each other. | 2015-08-20 |
20150235823 | PLASMA APPARATUS, MAGNETIC-FIELD CONTROLLING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD - Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process. | 2015-08-20 |
20150235824 | SPUTTERING SYSTEM AND METHOD FOR HIGHLY MAGNETIC MATERIALS - A system for depositing material from a target onto substrates, comprising a processing chamber; a sputtering target having length L and having highly magnetic sputtering material provided on front surface thereof a magnet assembly operable to reciprocally scan across the length L in close proximity to rear surface of the target and the magnet assembly comprises: a back plate made of magnetic material; a first group of magnets arranged in a single line central to the back plate and having a first pole positioned to face the rear surface of the target; and, a second group of magnets provided around periphery of the back plate so as to surround the first group of magnets, the second group of magnets having a second pole, opposite the first pole, positioned to face the rear surface of the target. | 2015-08-20 |
20150235825 | ELECTRON TUBE - In an electron tube, an electrical resistance film having a stacked structure of electrically insulating layers and electrically conductive layers is formed on holding surfaces of bases in insulating substrates. This electrical resistance film is made as a firm and fine film with a desired resistance by use of an atomic layer deposition method, which can suppress electrification of the bases comprised of an insulating material. This makes it feasible to stably maintain withstand voltage characteristics. | 2015-08-20 |
20150235826 | SYSTEMS AND METHODS FOR CALIBRATING MASS SPECTROMETERS - Systems and methods are disclosed for calibrating mass spectrometers. In accordance with one implementation, a system comprises a calibrant chamber within a housing of a mass spectrometer. The system also comprises a permeation tube enclosed within the calibrant chamber, wherein the tube contains a calibrant chemical that continuously outgasses the calibrant chemical. The outgassed calibrant chemical may be introduced to the mass spectrometer for analysis. The system may also comprise a heating block to control the temperature of the calibrant chemical. The system may further comprise a valve that introduces a known amount of the calibrant chemical into the calibrant chamber. In accordance with the present disclosure, systems and methods are provided for calibrating a mass spectrometer abundance scale. | 2015-08-20 |
20150235827 | SYSTEMS AND METHODS FOR AUTOMATED OPTIMIZATION OF A MULTI-MODE INDUCTIVELY COUPLED PLASMA MASS SPECTROMETER - The present disclosure provides methods and systems for automated tuning of multimode inductively coupled plasma mass spectrometers (ICP-MS). In certain embodiments, a ‘single click’ optimization method is provided for a multi-mode ICP-MS system that automates tuning of the system in one or more modes selected from among the multiple modes, e.g., a vented cell mode, a reaction cell mode (e.g., dynamic reaction cell mode), and a collision cell mode (e.g., kinetic energy discrimination mode). Workflows and computational routines, including a dynamic range optimization technique, are presented that provide faster, more efficient, and more accurate tuning. | 2015-08-20 |
20150235828 | METHOD AND SYSTEM FOR QUANTITATIVE AND QUALITATIVE ANALYSIS USING MASS SPECTROMETRY - In some embodiments, a quantitative analysis of at least one ion signal associated with a sample, which is detected by a mass spectrometer having at least two tandem quadrupole instruments, is employed to select one of the following operational modes for further mass analysis of the sample: (a) utilizing both quadrupole instruments as mass resolving filters, and (b) utilizing one quadrupole instrument as a mass resolving filter and utilizing the other as a linear ion trap. In some embodiments, the quantitative analysis of the ion signal comprises comparing the ion signal intensity with a predefined threshold. | 2015-08-20 |
20150235829 | METHOD FOR MASS SPECTROMETRIC EXAMINATION OF GAS MIXTURES AND MASS SPECTROMETER THEREFOR - A method includes parallel or serial ionization of a gas mixture by activating at least two ionization devices operating using different ionization procedures, and/or by ionizing the gas mixture in a detector to which the gas mixture and ions and/or metastable particles of an ionization gas are fed. The method also includes detecting the ionized gas mixture in the detector for the mass spectrometric examination thereof. A mass spectrometer for mass spectrometric examination of gas mixtures includes an ionization unit for ionizing a gas mixture and a detector for detecting the ionized gas mixture. | 2015-08-20 |
20150235830 | ION TRAP MASS SPECTROMETER AND ION TRAP MASS SPECTROMETRY METHOD - There are provided an ion trap mass spectrometer and an ion trap mass spectrometry method which can realize reduction of the number of times that a sample is ionized, and shortening of the measurement time. Ions corresponding to a plurality of peaks P | 2015-08-20 |
20150235831 | ANALYSIS DEVICE AND ANALYSIS METHOD - Provided is a technique of analyzing particles in real time while collecting and condensing the particles continuously. Gas and/or particles as a detection target substance that are attached to an authentication target | 2015-08-20 |
20150235832 | Ion Guiding Device - An ion guiding device is disclosed comprising a first ion guide which is conjoined with a second ion guide. Ions are urged across a radial pseudo-potential barrier which separates the two guiding regions by a DC potential gradient. Ions may be transferred from an ion guide which has a relatively large cross-sectional profile to an ion guide which has a relatively small cross-sectional profile in order to improve the subsequent ion confinement of the ions. | 2015-08-20 |
20150235833 | Systems and Methods for Automated Analysis of Output In Single Particle Inductively Coupled Plasma Mass Spectrometry and Similar Data Sets - The present disclosure provides methods and systems for automated analysis of spectrometry data corresponding to particles of a sample, such as large data sets obtained during single particle mode analysis of an inductively coupled plasma mass spectrometer (SP-ICP-MS). Techniques are presented herein that provide appropriate smoothing for rapid data processing without an accompanying reduction (or with an acceptably negligible reduction) in accuracy and/or precision. | 2015-08-20 |
20150235834 | METHOD FOR MANUFACTURING SILICON-CONTAINING THIN FILM - The present invention relates to a method for forming a silicon-containing thin film using a chlorosilane compound represented by Si | 2015-08-20 |
20150235835 | HIGH GROWTH RATE PROCESS FOR CONFORMAL ALUMINUM NITRIDE - Methods of depositing conformal aluminum nitride films on semiconductor substrates are provided. Disclosed methods involve (a) exposing a substrate to an aluminum-containing precursor, (b) purging the aluminum-containing precursor for a duration insufficient to remove substantially all of the aluminum-containing precursor in gas phase, (c) exposing the substrate to a nitrogen-containing precursor to form aluminum nitride, (d) purging the nitrogen-containing precursor, and (e) repeating (a) through (d). Increased growth rate and 100% step coverage and conformality are attained. | 2015-08-20 |
20150235836 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING AN OXIDE LAYER - In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer. | 2015-08-20 |
20150235837 | METHOD FOR GROWING ALUMINUM INDIUM NITRIDE FILMS ON SILICON SUBSTRATE - A method for growing aluminum indium nitride (AlInN) films on silicon substrates comprises several steps: firstly, arranging a silicon substrate in a reaction chamber; secondly, providing multiple reaction gases in the reaction chamber, wherein the reaction gases include aluminum precursors, indium precursors and nitrogen-containing gases; finally, dynamically adjusting flow rates of the reaction gases and directly growing an AlInN layer on the silicon substrate via a crystal growth process. By directly forming an AlInN layer on the silicon substrate, lattice matching is increased, residual thermal stress is reduced and film quality is improved. In addition, fabrication process is simplified and thus cost is reduced. | 2015-08-20 |
20150235838 | HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS - Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a ( | 2015-08-20 |
20150235839 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY INCLUDING LITHOGRAPHICALLY-PRINTABLE ASSIST FEATURES - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well. | 2015-08-20 |
20150235840 | APPARATUS AND METHOD FOR IRRADIATING - A method irradiates a wafer and an apparatus provides for a wafer to be irradiated. A plurality of radiation emitters emit radiation. A mask permits a portion of the electromagnetic radiation from the plurality of radiation emitters to pass and blocks a further portion of said electromagnetic radiation from passing. | 2015-08-20 |
20150235841 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING ALUMINUM OXIDE - A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. The aluminum oxide overlies the dielectric material in a first region of the structure. A second region of the structure includes a first titanium nitride portion overlying the dielectric material, magnesium over the first titanium nitride portion, and a second titanium nitride portion over the magnesium. Methods of forming the semiconductor structure including aluminum oxide are also disclosed. | 2015-08-20 |
20150235842 | TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a transistor includes irradiating an oxygen gas cluster ion beam onto a surface layer of a substrate which is made of silicon carbide and includes a channel area to become a channel to form a thin interface oxide film. | 2015-08-20 |
20150235843 | Method of Manufacturing Semiconductor Device and Substrate Processing Method - A method of manufacturing a semiconductor device is provided. The method includes: forming a film containing a predetermined element, oxygen, carbon and nitrogen on a substrate by repeating a cycle. The cycle includes: (a) supplying a source gas containing the predetermined element and a halogen element to the substrate; (b) supplying a first reactive gas containing three elements including carbon, nitrogen and hydrogen to the substrate; (c) supplying a nitriding gas as a second reactive gas to the substrate; (d) supplying an oxidizing gas as a third reactive gas to the substrate; and (e) supplying an hydrogen-containing gas as a fourth reactive gas to the substrate, wherein (a) through (e) are non-simultanelously performed. | 2015-08-20 |
20150235844 | HERMETIC CVD-CAP WITH IMPROVED STEP COVERAGE IN HIGH ASPECT RATIO STRUCTURES - Implementations described herein generally relate to methods for forming dielectric films in high aspect ratio features. In one implementation, a method for forming a silicon oxide layer is provided. A silicon-containing precursor gas is flown into a processing chamber having a substrate having a high aspect ratio feature disposed therein. Then a high frequency plasma is applied to the silicon-containing precursor gas to deposit a silicon-containing layer over the surface of the high aspect ratio feature. The processing chamber is purged to remove by-products from the silicon-containing layer deposition process. An oxygen-containing precursor gas is flown into the processing chamber. A high frequency plasma and a low frequency plasma are applied to the oxygen-containing precursor gas to form the silicon oxide layer. | 2015-08-20 |
20150235845 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device, includes preparing a semiconductor substrate includes a connection pad to electrically connect to a circuit element formed on a main surface, or a rewiring line connected to the connection pad, forming an insulating photosensitive resin film on the substrate with the exclusion of at least an edge portion of the substrate by inkjet, patterning the photosensitive resin film by photolithography, and forming a rewiring line, UBM or an electrode for external connection on the substrate on which the patterned photosensitive resin film is formed. | 2015-08-20 |
20150235846 | METHOD AND APPARATUS FOR FORMING SILICON OXIDE FILM - A silicon oxide film forming method includes: forming an amorphous silicon film, including: adsorbing an adsorbate containing silicon to a workpiece by supplying a source gas containing chlorine and silicon into a reaction chamber accommodating the workpiece, activating the source gas, and reacting the activated source gas with the workpiece; and removing chlorine contained in the adsorbate by supplying hydrogen gas into the reaction chamber and activating the hydrogen gas, and reacting the activated hydrogen gas with the adsorbate, wherein removing the chlorine is performed after adsorbing the adsorbate is performed, thereby forming the amorphous silicon film on the workpiece; and forming a silicon oxide film on the workpiece by supplying an oxidizing gas into the reaction chamber and oxidizing the amorphous silicon film, wherein forming the amorphous silicon film and forming the silicon oxide film are repeated in this order plural times. | 2015-08-20 |
20150235847 | GROWING GRAPHENE ON SUBSTRATES - Embodiments described herein provide methods and apparatus for forming graphitic carbon such as graphene on a substrate. The method includes providing a precursor comprising a linear conjugated hydrocarbon, depositing a hydrocarbon layer from the precursor on the substrate, and forming graphene from the hydrocarbon layer by applying energy to the substrate. The precursor may include template molecules such as polynuclear aromatics, and may be deposited on the substrate by spinning on, by spraying, by flowing, by dipping, or by condensing. The energy may be applied as radiant energy, thermal energy, or plasma energy. | 2015-08-20 |
20150235848 | Ultra Long Lifetime Gallium Arsenide - A novel bulk GaAs with an increased carrier lifetime of at least 10 microseconds has been produced. This novel GaAs has many uses to improve optical and electrical devices. The method of producing the GaAs crystal involves using a technique called low pressure hydride phase epitaxy (LP-HVPE). In this technique, a gas containing Ga (typically GaCl) is reacted with a gas containing As (typically AsH | 2015-08-20 |
20150235849 | SELF-FORMATION OF HIGH-DENSITY ARRAYS OF NANOSTRUCTURES - A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer. | 2015-08-20 |
20150235850 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A semiconductor device manufacturing method of the present invention includes forming a base film having a water-repellent surface on a substrate; forming a photosensitive film having a water-repellent surface on the base film; developing the photosensitive film to expose the base film, thereby forming a photosensitive film pattern; supplying a first spacer material on the photosensitive film and on the exposed base film; and removing at least a part of the first spacer material formed on a top surface of the photosensitive film and a top surface of the base film. | 2015-08-20 |
20150235851 | METHOD FOR BONDING BY MEANS OF MOLECULAR ADHESION - The disclosure relates to a method of bonding by molecular adhesion comprising the positioning of a first wafer and of a second wafer within a hermetically sealed vessel, the evacuation of the vessel to a first pressure lower than or equal to 400 hPa, the adjustment of the pressure in the vessel to a second pressure higher than the first pressure by introduction of a dry gas, and bringing the first and second wafers into contact, followed by the initiation of the propagation of a bonding wave between the two wafers, while maintaining the vessel at the second pressure. | 2015-08-20 |
20150235852 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate. | 2015-08-20 |
20150235853 | INCREASING THE DOPING EFFICIENCY DURING PROTON IRRADIATION - A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion. | 2015-08-20 |
20150235854 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device is disclosed. The method comprises forming a etch stop layer and a dummy gate layer on a substrate; forming a dummy gate pattern by wet etching the dummy gate layer; forming a gate spacer around said dummy gate pattern; removing said dummy gate pattern by wet etching to form a gate trench; and forming a gate stack in the gate trench. In the method for manufacturing a semiconductor device according to the invention, epitaxial monocrystalline thin film is used as the dummy gate and the stop layer for wet etching the dummy gate. As a result, the verticality of the gate profile is improved, erosion of substrate at corner of the bottom is avoided, and therefore performance and reliability of the device is effectively improved. | 2015-08-20 |
20150235855 | Metal Deposition with Reduced Stress - Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer. | 2015-08-20 |
20150235856 | SEMICONDUCTOR STRUCTURES HAVING T-SHAPED ELECTRODES - A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid, dielectric, such as air. | 2015-08-20 |
20150235857 | METHOD OF FORMING SUBSTRATE PATTERN - According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region. | 2015-08-20 |
20150235858 | WAFER BACK-SIDE POLISHING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING PROCESSES - A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads. | 2015-08-20 |
20150235859 | METHOD FOR STRUCTURING A LAYERED STRUCTURE FROM TWO SEMICONDUCTOR LAYERS, AND MICROMECHANICAL COMPONENT - A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch stop layer is situated includes forming a first etching mask on a first side of the first semiconductor layer, carrying out a first etching step, starting from a first outer side, for structuring the first semiconductor layer, forming a second etching mask on a second side of the second semiconductor layer, and carrying out a second etching step, starting from the second outer side, for structuring the second semiconductor layer. After carrying out the first etching step and prior to carrying out the second etching step, at least one etching protection material is deposited on at least one trench wall of at least one first trench, which is etched in the first etching step. | 2015-08-20 |
20150235860 | ETCHING METHOD AND PLASMA PROCESSING APPARATUS - An etching method of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride includes: a process (a) and a process (b). In the process (a), a target object is exposed to plasma of a fluorocarbon gas and a thickness of a protective film on the second region is larger than a thickness of a protective film formed on the first region. In the process (b), the first region is etched by plasma of a fluorocarbon gas. In the process (a), a temperature of the target object is set to 60° C. or more to 250° C. or less. | 2015-08-20 |
20150235861 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - A plasma etching method includes a first process and a second process. In the first process, a hole is formed in a processing target film formed on a substrate accommodated within a processing chamber by performing an etching process of etching the processing target film. In the second process, a removing process, a deposition process and an extending process are repeatedly performed. In the removing process, a reaction product adhering to an inlet portion of the hole which is formed through the etching process is removed. In the deposition process, a deposit is deposited on a sidewall of the hole from which the reaction product is removed through the removing process. In the extending process, the hole, in which the deposit is deposited on the sidewall thereof through the deposition process, is deeply etched by performing the etching process. | 2015-08-20 |
20150235862 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method for etching a multilayer film using a mask is provided. The method includes (a) supplying a first gas containing hydrogen, hydrogen bromide, nitrogen trifluoride and at least one of hydrocarbon, fluorocarbon and fluorohydrocarbon into the processing chamber and exciting the first gas to etch the multilayer film from a top surface of the multilayer film to a predetermined position in a stacked direction of the multilayer film; and (b) supplying a second gas that does not substantially contain hydrogen bromide and contains hydrogen and nitrogen trifluoride and at least one of Thydrocarbon, fluorocarbon and fluorohydrocarbon into the processing chamber and exciting the second gas to etch the multilayer film from the predetermined position of the multilayer film to a top surface of the etching stop layer. | 2015-08-20 |
20150235863 | RADICAL-COMPONENT OXIDE ETCH - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride. | 2015-08-20 |
20150235864 | METHOD FOR PROCESSING A LAYER AND A METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - A method for processing a layer may include: providing a patterned carbon layer over a layer or over a carrier; and carrying out an ion implantation through the patterned carbon layer into the layer or into the carrier. | 2015-08-20 |
20150235865 | PROCESSING SYSTEMS AND METHODS FOR HALIDE SCAVENGING - Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools. | 2015-08-20 |
20150235866 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: | 2015-08-20 |
20150235867 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a surface and a rising surface that protrudes upward from the surface, on a semiconductor substrate; forming a conductive layer to cover the insulation layer having the protruding portion; and removing a predetermined region of the conductive layer by patterning the predetermined region according to an etching process using microwave plasma, which uses a microwave as a plasma source, while applying bias power of 70 mW/cm | 2015-08-20 |
20150235868 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE - A method for manufacturing a non-volatile memory includes depositing a first conductive film and a protective film on a substrate including a logic area and a cell area, patterning the protective film, depositing a hard mask layer on the first conductive film and the patterned protective film to pattern the hard mask layer, using the patterned hard mask layer to form a logic gate on the logic area, exposing a surface of the first conductive film in the cell area and forming a control gate on the cell area. | 2015-08-20 |
20150235869 | GLASSWORK COMPONENT, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - A manufacturing method of a glasswork component, includes: forming a compressive stress layer which ranges from one main surface to the other main surface of a glass substrate, along a scheduled cutting line, so as to be adjacent to the scheduled cutting line of the glass substrate; and cutting the glass substrate in the scheduled cutting line. | 2015-08-20 |
20150235870 | WAFER-LEVEL PACKAGED OPTICAL SUBASSEMBLY AND TRANSCEIVER MODULE HAVING SAME - A wafer-level packaged optical subassembly includes: a substrate element, the substrate element including a top layer and a base layer being bonded with the top layer; a top window cover being bonded with the top layer of the substrate element; and a plurality of active optoelectronic elements disposed within the substrate element. At least one primary cavity is defined in the substrate element by the top layer and the base layer, and configured for accommodating the active optoelectronic elements. A plurality of peripheral cavities are defined around the at least one primary cavity as alignment features for external opto-mechanical parts. | 2015-08-20 |
20150235871 | VACUUM LAMINATING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A vacuum laminating apparatus for use in manufacturing a semiconductor apparatus, including a frame mechanism to surround at least a side face of a support-base attached encapsulant including a thermosetting resin layer stacked as an encapsulant on a support base, the frame mechanism including a holding unit to hold a substrate on which semiconductor devices are mounted or a wafer on which semiconductor devices are formed with the substrate or the wafer facing and spaced apart from the thermosetting resin layer of the support-base attached encapsulant, the vacuum laminating apparatus capable of vacuum laminating the support-base attached encapsulant surrounded by the frame mechanism together with the substrate or wafer. The vacuum laminating apparatus inhibit the occurrence of voids in resin layer and warp of a substrate or wafer and manufacture a semiconductor apparatus having a precisely formed resin layer, even when the substrate or wafer used has a large area. | 2015-08-20 |
20150235872 | Curable Silicone Composition, Method For Producing Semiconductor Device, And Semiconductor Device - The present invention relates to a curable silicone composition comprising: (A) an organopolysiloxane composed of: (A-1) a linear organopolysiloxane having at least two silicon-bonded alkenyl groups in a molecule, and (A-2) a resin-like organopolysiloxane including 1.5 to 5.0% by weight alkenyl groups; (B) an organopolysiloxane having at least two silicon-bonded hydrogen atoms in a molecule; (C) a linear dialkyl polysiloxane having a viscosity at 25° C. of 2 to 10 mm | 2015-08-20 |
20150235873 | METHOD OF MANUFACTURING PACKAGE SYSTEM - A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps. | 2015-08-20 |
20150235874 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch. | 2015-08-20 |
20150235875 | Modular Flow Cell and Adjustment System - A combinatorial processing system having modular dispense heads is provided. The modular dispense heads are disposed on a rail system enabling an adjustable pitch of the modular dispense heads for the combinatorial processing. The modular dispense heads are configured so that sections of the modular dispense heads are detachable in order to accommodate various processes through a first section without having to completely disconnect and re-connect facilities to a second section. | 2015-08-20 |
20150235876 | METHOD AND APPARATUS FOR PROCESSING WAFER-SHAPED ARTICLES - A method and device for processing wafer-shaped articles includes a spin chuck for holding and rotating a wafer-shaped article about a rotation axis, and at least one dispenser for dispensing a fluid onto at least one surface of a wafer-shaped article. A collector surrounds the spin chuck for collecting process fluids, with at least two collector levels for separately collecting fluids in different collector levels. Each collector level comprises an exhaust gas collecting chamber leading to a respective exhaust gas conduit. At least one of the exhaust gas conduits comprises a valve mechanism that reciprocally restricts exhaust gas flow from its associated exhaust gas conduit while opening the exhaust gas conduit to an ambient environment outside the collector, and vice-versa. | 2015-08-20 |
20150235877 | TARGET DIMENSION UNIFORMITY FOR SEMICONDUCTOR WAFERS - One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions. | 2015-08-20 |
20150235878 | Semiconductor Manufacturing Apparatus and Method of Manufacturing Semiconductor Device - In one embodiment, a semiconductor manufacturing apparatus includes a support module configured to support a wafer having first and second faces. The apparatus further includes a chamber configured to contain the support module. The apparatus further includes a microwave generator configured to generate a microwave. The apparatus further includes a waveguide configured to emit the microwave into the chamber to irradiate the first or second face of the wafer with the microwave, the waveguide being provided to the chamber such that an incidence direction of the microwave emitted from the waveguide onto the first or second face is non-vertical to the first or second face. | 2015-08-20 |
20150235879 | DEVICE AND METHOD FOR WAFER TAPING - In accordance with some embodiments, a wafer taping device is provided. The wafer taping device includes a tape delivering along a first direction. The wafer taping device also includes a wafer mount unit disposed below the tape. The wafer mount unit has an upper surface for supporting a wafer and having a notch for allowing a cut mark of the wafer to align with it. The notch is staggered with a second direction in the upper surface, and the second direction is substantially perpendicular to the first direction. In addition, the wafer taping device includes a laminating roller disposed above the wafer mount unit and having a long axis elongated in the second direction. The laminating roller is configured to reciprocate along the first direction for pressing the tape to the wafer. | 2015-08-20 |
20150235880 | DETECTION APPARATUS, IMPRINT APPARATUS, AND METHOD OF MANUFACTURING PRODUCTS - This disclosure provides a detection apparatus configured to detect a moire pattern generated by grid patterns having grid pitches different from each other including: an image-pickup unit configured to pick up an image of the moire pattern; an imaging optical system configured to cause the image-pickup unit to image the moire pattern; and a processing unit configured to process an image-pickup result of the moire pattern imaged by the image-pickup unit, wherein a mark including a plurality of patterns having a width not larger than the resolving power of the imaging optical system arranged in a measuring direction and changed in duty ratio between the widths and intervals of the plurality of patterns is imaged by the image-pickup unit, and the processing unit evaluates the detection apparatus by processing the image-pickup result of the mark picked up by the image-pickup unit. | 2015-08-20 |
20150235881 | Apparatus and Method for Centering Substrates on a Chuck - An apparatus and method for centering substrates determining on a chuck. The apparatus includes a chuck in a process chamber, the chuck configured to removeably hold a substrate for processing; an array of two or more ultrasonic sensors arranged in the process chamber, each ultrasonic sensor arranged relative to the chuck so as to send a respective ultrasonic sound wave to a respective preselected region of the substrate and receive a respective return ultrasonic sound wave from the preselected region of the substrate; and a controller connected to each ultrasonic sensor and configured to compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave from each ultrasonic sensor. | 2015-08-20 |
20150235882 | DEVICES AND METHODS FOR HANDLING MICROELECTRONICS ASSEMBLIES - The disclosure relates to trays for the handling and shipping of computer chips, or similar microelectronic devices. The tray include a series of channels, each extending along a width of the tray. The channels include such devices as pins and clips for securing a thermoformed tape. The thermoformed tape includes pockets for storing the various computer chips, or similar microelectronic devices. | 2015-08-20 |
20150235883 | Semiconductor Wafer Transportation - A wafer transportation pod includes a body, a main compartment enclosed by the body, the main compartment to provide a controlled environment, a holding device within the main compartment, the holding device to hold a plurality of semiconductor wafers, a top latching mechanism configured to connect to another pod or a carrier mechanism of an overhead hoist transfer (OHT) system, a bottom latching mechanism configured to connect to another pod, the bottom latching mechanism being similar to the latching mechanism on the carrier. | 2015-08-20 |
20150235884 | CEILING STORAGE DEVICE CAPABLE OF WAFER PURGING - The invention provides an apparatus for stocking and purging a wafer at a ceiling. The apparatus includes: a rail that is formed so as to be installed on a ceiling to guide a vehicle; a stock system that is formed so as to be installed on the ceiling and is formed so as to receive a container, which contains wafers, from the vehicle and stock the container; and a purge assembly that is installed so as to communicate with the container through the stock system and is formed so as to purge the wafers, which are contained in the container, with gas. | 2015-08-20 |
20150235885 | PURGE SYSTEM, POD USED WITH PURGE SYSTEM, AND LOAD PORT APPARATUS - A system prevents oxidative gases in a FOUP which is fixed to an FIMS system in an open state from increasing over time. A tower type gas supply port extending from the bottom of the FOUP to inside is provided. Nitrogen can be supplied into the FOUP through the gas supply port in addition to nitrogen purge through the pod opening, when the pod is mounted on the FIMS. Two gas flows thus formed cooperate to create a gas flow flowing along the side of the FOUP opposite to the opening and to the opening. Thus, the gas in the interior of the FOUP is remounted with nitrogen uniformly. | 2015-08-20 |
20150235886 | PROCESSING METHOD AND PROCESSING APPARATUS - A method of processing an object to by using a processing apparatus is provided. The apparatus includes a plurality of containers to contain the object, a plurality of process chambers to perform a desired process on the object, a temporary storage chamber to temporarily store the object, and a transfer device to transfer the object. The method includes a first step of transferring an unprocessed object from the containers to the process chambers, and a second step of transferring a processed object from the process chambers to the temporary storage chamber. The method further includes a third step of collecting the processed object into one of the containers starting a collection of the processed object from the temporary storage chamber depending on a timing of processing a last object of the one of the containers prior to collecting the processed object into the other containers from the temporary storage chamber. | 2015-08-20 |
20150235887 | POSITIONING DEVICE, CONTROL DEVICE AND CONTROL METHOD - The present invention relates to a positioning device, e.g. for use as a wafer stage, having a very stable temperature, a very low power consumption and a uniform temperature distribution. A long stroke stage ( | 2015-08-20 |
20150235888 | SUBSTRATE PROCESSING APPARATUS, METHOD FOR CORRECTING POSITIONAL DISPLACEMENT, AND STORAGE MEDIUM - A substrate processing apparatus includes: first and second places in which a substrate can be placed; a substrate transfer device having a substrate holder that holds the substrate to transfer the substrate between the first and second places; and a substrate position measuring unit that detects a position of the substrate held by the substrate holder. The substrate position measuring unit, disposed independently of the substrate transfer device, is arranged at a position where the substrate held by the substrate holder of the substrate transfer device can be placed. | 2015-08-20 |
20150235889 | SYSTEM AND METHOD FOR PERFORMING HOT WATER SEAL ON ELECTROSTATIC CHUCK - A method is provided for treating a bipolar ESC having a front surface and a back surface, the front surface including an anodized layer. The method includes eliminating the anodized layer, disposing a new anodized layer onto the front surface, and treating the new anodized layer with water to seal the new anodized layer. | 2015-08-20 |
20150235890 | SEMICONDUCTOR DEVICE INCLUDING A DIELECTRIC MATERIAL - A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material. | 2015-08-20 |
20150235891 | WAFER HANDLER AND METHODS OF MANUFACTURE - A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler. | 2015-08-20 |
20150235892 | WAFER CLAMP FOR CONTROLLING WAFER BOWING AND FILM STRESS - A wafer clamp according to one embodiment includes an outer ring, and at least three members extending inwardly from the outer ring, each of the members having a contact area for engaging a wafer. A system includes a structure having at least one ring, each ring being for receiving a wafer, and a wafer clamp configured to clamp a wafer to each ring, the wafer clamp having an outer ring, and at least three members extending inwardly from the outer ring, each of the members having a contact area for engaging a wafer. | 2015-08-20 |
20150235893 | FABRICATING METHOD OF NON-VOLATILE MEMORY DEVICE - Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate, wherein the first word lines and the second word lines are arranged periodically and extend in a first direction. Bit lines are formed over the first and second word lines, wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate. | 2015-08-20 |
20150235894 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound. | 2015-08-20 |
20150235895 | Spacer Enabled Active Isolation for an Integrated Circuit Device - A method for forming an active isolation structure in a semiconductor integrated circuit die is disclosed. A first hard mask layer is deposited over a semiconductor substrate. Portions of the first hard mask layer are removed to form at least one trench. A spacer layer is deposited over the first hard mask and extends into each trench to cover exposed portions of the semiconductor substrate surface in each trench. Portions of the spacer layer are removed such that remaining portions define spacer layer walls covering the side walls of each trench. A second hard mask layer is deposited and extends into each trench between opposing spacer layer walls. The spacer layer walls are removed such that remaining portions of the first and second hard mask layers define a mask pattern, which is then transferred to the substrate to form openings in the substrate, which are filled with an isolation material. | 2015-08-20 |
20150235896 | METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer. | 2015-08-20 |
20150235897 | Reverse Tone Self-Aligned Contact - Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact. | 2015-08-20 |