33rd week of 2021 patent applcation highlights part 63 |
Patent application number | Title | Published |
20210257339 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided. | 2021-08-19 |
20210257340 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes: a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first bonding dielectric layer over the first die; a first active bonding via in the first bonding dielectric layer, electrically connected to the first interconnect structure; and a plurality of first dummy bonding vias in the first bonding dielectric layer, wherein the first dummy bonding vias laterally surround the first active bonding via and are electrically floating. | 2021-08-19 |
20210257341 | OFFSET PADS OVER TSV - Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV. | 2021-08-19 |
20210257342 | POWER SEMICONDUCTOR MODULE AND COMPOSITE MODULE - An uneven current distribution among a plurality of provided power semiconductor chips is to be suppressed. A power semiconductor module includes a module main body, a plurality of power semiconductor chips arranged on an upper surface of the module main body, and peripheral structures being insulating ferromagnets surrounding parts of a periphery of the module main body in a plan view, in which the plurality of power semiconductor chips are arranged in a vertical direction and a horizontal direction in a plan view, and at least one of the plurality of power semiconductor chips is arranged so as to be surrounded by other power semiconductor chips. | 2021-08-19 |
20210257343 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device is provided in an embodiment in the disclosure, including a subpixel region, a spacer, a light-emitting element, and a driving circuit. The spacer separates the subpixel region into a first region and a second region. The light-emitting element is located in at least one of the first region or the second region. The driving circuit is electrically connected to the first region and the second region, so as to drive the light-emitting element. A manufacturing method of the display device is also disclosed. | 2021-08-19 |
20210257344 | Apparatus and Method for Forming a Layer of a Material Provided in a Flowable State on an Optoelectronic Light-Emitting Device - In an embodiment an apparatus includes a delimiting device and a holding device configured to hold the delimiting device at a distance above an optoelectronic light-emitting device and form a layer of a material provided in a flowable state between the delimiting device and the light-emitting device, wherein a bottom side of the delimiting device, which faces the light-emitting device, has a structuring so that a structure complementary to the structuring is producible on an upper side of the layer. | 2021-08-19 |
20210257345 | LIGHT-EMITTING DIODES WITH LIGHT COUPLING AND CONVERSION LAYERS - Light-emitting sub-pixels and pixels for micro-light-emitting diode-based displays are provided. Also provided are methods of fabricating individual sub-pixels, pixels, and arrays of the pixels. The sub-pixels include a double-layered film that includes a coupling layer disposed over a light-emitting diode and a light-emission layer disposed over the coupling layer. | 2021-08-19 |
20210257346 | SEMICONDUCTOR DEVICE WITH INTEGRATED HEAT DISTRIBUTION AND MANUFACTURING METHOD THEREOF - A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die. | 2021-08-19 |
20210257347 | DISPLAY PANEL AND TILED DISPLAY DEVICE - The disclosure provides a display panel and a tiled display device. The display panel has a tiling edge and includes a non-transparent part and a transparent part. The transparent part has a peripheral edge. At least a portion of the peripheral edge of the transparent part is overlapped with the tiling edge. The tiled display device includes a plurality of display panels tiled together by the tiling edges thereof. | 2021-08-19 |
20210257348 | LIGHT EMITTING DIODE PACKAGE HAVING BACK-TO-BACK COMPARTMENT CONFIGURATION - A light emitting diode package, including: a housing, wherein the housing includes a top compartment having an aperture and a bottom compartment having an aperture; a lead frame, wherein the lead frame includes a first electrode and a second electrode, and wherein the lead frame is positioned between the top compartment and the bottom compartment of the housing; at least one light emitting diode light source, wherein the at least one light emitting diode light source is associated with the aperture of the top compartment of the housing; a light emitting diode driver, wherein the light emitting diode driver is associated with the aperture of the bottom compartment of the housing; and wherein the aperture of the top compartment of the housing and the aperture of the bottom compartment of the housing are positioned in a back-to-back configuration. | 2021-08-19 |
20210257349 | DISPLAY DEVICE - A display device includes: a substrate; a first bank on the substrate, at least portions of the first bank being spaced apart from each other; a plurality of first electrodes on the substrate, at least portions of the first electrodes being on portions of the first bank; a second electrode on the substrate, the second electrode being spaced apart from and between adjacent ones of the first electrodes; and a plurality of light emitting elements on the first electrodes and the second electrode. | 2021-08-19 |
20210257350 | DISPLAY WITH EMBEDDED PIXEL DRIVER CHIPS - Embodiments describe a display integration scheme in which an array of pixel driver chips embedded front side up in an insulator layer. A front side redistribution layer (RDL) spans across and is in electrical connection with the front sides of the array of pixel driver chips, and an array of light emitting diodes (LEDs) is bonded to the front side RDL. The pixel driver chips may be located directly beneath the display area of the display panel. | 2021-08-19 |
20210257351 | DUMMY POLY LAYOUT FOR HIGH DENSITY DEVICES - An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip. | 2021-08-19 |
20210257352 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPARATUS - To prevent an electrostatic damage on a display device formed with a driving circuit. Protective circuits are provided not only at input terminal parts, but also at intermediate parts of a circuit or at the ends of wiring lines. Otherwise, the protective circuits are provided at the ends of the wiring lines and at the places immediately before and after the input terminals, respectively, and then the circuit is interposed therebetween. Further, the protective circuits are provided around a circuit with a large current consumption. | 2021-08-19 |
20210257353 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR CMOS CIRCUITS - A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors. | 2021-08-19 |
20210257354 | IC Package Having a Metal Die for ESD Protection - An IC package having a metal die for ESD protection includes: a printed circuit board having power connections and ground connections; a function die; and a metal die adhered unto the function die and electrically insulated from the function die, wherein the metal die comprises a metal layer and a dummy die underlying the metal layer, and the metal layer is electrically coupled to one or more of the power connections and ground connections of the printed circuit board to provide package level electrostatic discharge (ESD) protection; and an encapsulant covering the metal die, the function die and a surface of the printed circuit board supporting the metal die and function die. | 2021-08-19 |
20210257355 | A POWER SEMICONDUCTOR DEVICE WITH A TEMPERATURE SENSOR - We describe herein a high voltage semiconductor device comprising a power semiconductor device portion ( | 2021-08-19 |
20210257356 | INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES - Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer. | 2021-08-19 |
20210257357 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device including: a first level, where the first level includes a first layer and first transistors, and where the first level includes a second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon; and where the second level includes at least one SerDes circuit. | 2021-08-19 |
20210257358 | SEMICONDUCTOR DEVICE - A semiconductor device is described including a substrate and a plurality of layers. The semiconductor device includes a cascode arrangement of a first bipolar transistor and a second bipolar transistor. A first-bipolar-transistor-collector of the first bipolar transistor and a second-bipolar-transistor-emitter of the second bipolar transistor are at least partially located in a common region in the same layer of the semiconductor device. | 2021-08-19 |
20210257359 | Transistor Gate Profile Optimization - A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction. | 2021-08-19 |
20210257360 | Bent Fin Devices - Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction. | 2021-08-19 |
20210257361 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin. | 2021-08-19 |
20210257362 | Enlarging Spacer Thickness by Forming a Dielectric Layer Over a Recessed Interlayer Dielectric - An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region. | 2021-08-19 |
20210257363 | CHIP AND METHOD FOR MANUFACTURING A CHIP - A chip is described including a semiconductor layer including doped regions; a metallization layer on the semiconductor layer and at least one cell row including p-channel field effect transistors and n-channel field effect transistors, wherein the doped regions form source regions and drain regions of the p-channel field effect transistors and the n-channel field effect transistors; contacts extending from the source regions, the drain regions and gate regions of the p-channel field effect transistors and the n-channel field effect transistors to the metallization layer, wherein the metallization layer is structured in accordance with a metallization grid such that the p-channel field effect transistors and the n-channel field effect transistors are connected to form one or more logic gates. | 2021-08-19 |
20210257364 | DISTRIBUTED ELECTRICAL OVERSTRESS PROTECTION FOR LARGE DENSITY AND HIGH DATA RATE COMMUNICATION APPLICATIONS - Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit. The method also includes choosing a device type of the selected segmented overstress protection devices from amongst two or more different device types providing complementary protection characteristics and protecting a core circuit from electrical overstress using the selected segmented overstress protection devices, the core circuit electrically connected to at least the signal pad, the power high pad, and the power low pad. | 2021-08-19 |
20210257365 | Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle - Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state. | 2021-08-19 |
20210257366 | MEMORY DEVICE - A memory cell includes: a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor including an active layer, the active layer being laterally oriented in a second direction, intersecting with the bit line; a capacitor laterally oriented in the second direction between the active layer and the plate line; and a word line laterally oriented in a third direction, intersecting with the bit line and the active layer, wherein the word line is embedded in the active layer. | 2021-08-19 |
20210257367 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a capacitor on a substrate. The capacitor includes a first electrode, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The second electrode includes a first layer, a second layer, and a third layer. The first layer is adjacent to the dielectric layer, and the third layer is spaced apart from the first layer with the second layer interposed therebetween. A concentration of nickel in the third layer is higher than a concentration of nickel in the first layer. | 2021-08-19 |
20210257368 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode. | 2021-08-19 |
20210257369 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact. | 2021-08-19 |
20210257370 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode. | 2021-08-19 |
20210257371 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a memory cell storing data. The memory cell capacitor includes a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate, an upper support pattern on upper lateral surfaces of the plurality of bottom electrodes, and a lower support pattern on lower lateral surfaces of the plurality of bottom electrodes. The lower support pattern is disposed between the substrate and the upper support pattern, and a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern. | 2021-08-19 |
20210257372 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer. | 2021-08-19 |
20210257373 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first region having a first trench and a second region having a second trench. A first buried insulation layer pattern is disposed in the first trench. The second trench includes the first buried insulation layer pattern, a second buried insulation layer pattern, and a third buried insulation layer pattern sequentially stacked therein. A first buffer insulation layer is disposed on the substrate in the first and second regions and has a flat upper surface. A second buffer insulation layer is disposed on the first buffer insulation layer. A bit line structure is disposed on the first and second regions. A first portion of the bit line structure is disposed on the second buffer insulation layer and has a flat lower surface. A second portion of the bit line structure directly contacts a surface of the substrate in the first region. | 2021-08-19 |
20210257374 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part. | 2021-08-19 |
20210257375 | METHODS AND APPARATUS FOR THREE DIMENSIONAL NAND STRUCTURE FABRICATION - Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces. | 2021-08-19 |
20210257376 | MEMORY CELL, NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory. | 2021-08-19 |
20210257377 | SEMICONDUCTOR NON-VOLATILE MEMORY DEVICES - A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells. | 2021-08-19 |
20210257378 | THREE-DIMENSIONAL MEMORY DEVICE WITH COMPOSITE CHARGE STORAGE STRUCTURES AND METHODS FOR FORMING THE SAME - A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner. | 2021-08-19 |
20210257379 | THREE-DIMENSIONAL MEMORY DEVICE WITH COMPOSITE CHARGE STORAGE STRUCTURES AND METHODS FOR FORMING THE SAME - A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner. | 2021-08-19 |
20210257380 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF - Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion. | 2021-08-19 |
20210257381 | METHODS FOR FORMING CHANNEL STRUCTURES IN THREE-DIMENSIONAL MEMORY DEVICES - Methods for forming channel structures in 3D memory devices are disclosed. In one example, a memory film and a sacrificial layer are subsequently formed along a sidewall and a bottom of a channel hole. A protective structure covering a portion of the sacrificial layer along the sidewall of the channel hole is formed. A portion of the sacrificial layer at the bottom of the channel hole that is not covered by the protective structure is selectively removed. A portion of the memory film at the bottom of the channel hole that is not covered by a remainder of the sacrificial layer is selectively removed. | 2021-08-19 |
20210257382 | MULTI-DIVISION STAIRCASE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of structure and methods for forming a staircase structure of a memory device are disclosed. In an example, a memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of stairs each has a first number of divisions at different depths along a first direction. The plurality of stairs extend along a second direction perpendicular to the first direction. Each of the first number of divisions of a respective stair includes a conductor portion on the top surface of the respective division and a second number of non-conductor portions under the conductor portion. The conductor portion and the non-conductor portions are insulated from one another by one or more dielectric layers. | 2021-08-19 |
20210257383 | SEMICONDUCTOR MEMORY DEVICE - A device includes conductor layers and a first pillar, extending through the conductor layers, that includes a first columnar portion, a second columnar portion, and a middle portion between the first and second columnar portions. A diameter of the middle portion is larger than a diameter of the first columnar portion and larger than a diameter of the second columnar portion. The first columnar portion includes a first semiconductor layer and a first charge storage layer. The second columnar portion includes a second semiconductor layer and a second charge storage layer. The middle portion includes a third semiconductor layer. The first and second semiconductor layers are in contact with the third semiconductor layer on a first side and a second side of the third semiconductor layer, respectively. The first charge storage layer is spaced from the second charge storage layer. | 2021-08-19 |
20210257384 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME - A three-dimensional nonvolatile memory device includes: a substrate including a cell area and an extension area having a staircase structure; a vertical structure on the substrate; a stacking structure having electrode layers and interlayer insulating layers on the substrate; a separation insulating layer on the substrate and separating the electrode layers; and a through-via wiring area adjacent to the cell or extension area and having through-vias passing through the substrate, wherein the cell area includes a main cell area in which normal cells are arranged and an edge cell area, the separation insulating layer includes a main separation insulating layer in the main cell area and an edge separation insulating layer in the edge cell area, and a lower surface of the main separation insulating layer is higher than the upper surface of the substrate and has a different depth than a lower surface of the edge separation insulating layer. | 2021-08-19 |
20210257385 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias - A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed. | 2021-08-19 |
20210257386 | VERTICAL MEMORY DEVICES - Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first stack of layers including a source connection layer and a second stack of layers including gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatively upon the first stack of layers. Further, the semiconductor device includes channel structures that are formed along the first direction in the first stack of layers and the second stack of layers, and a gate line cut structure having a trench that cuts through the first stack of layers and the second stack of layers. The trench is filled with at least an insulating layer. The semiconductor device includes a support structure having a first portion that is disposed at a side of the gate line cut structure and extended from the side of the gate line cut structure and underneath the second stack of layers. | 2021-08-19 |
20210257387 | Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures - Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures. | 2021-08-19 |
20210257388 | SEMICONDUCTOR DEVICE INCLUDING STANDARD CELLS - A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction. | 2021-08-19 |
20210257389 | ARRAY SUBSTRATE, DISPLAY PANEL, DISPLAY DEVICE AND METHOD OF MANUFACTURING AN ARRAY SUBSTRATE - An array substrate, includes: a substrate, three metal layers stacked on the substrate, and a plurality of signal line leads disposed in a peripheral area of the array substrate. The plurality of signal line leads are distributed in at least two of the three metal layers. | 2021-08-19 |
20210257390 | MOBILE TERMINAL - In order to minimize an additional non-output region that is generated when a wire bypasses a non-output region of a display, a mobile terminal is provided which comprises: a display panel including the non-output region; a TFT substrate included in the display panel; a TFT wire that is provided on a front surface of the TFT substrate to form an output region and is isolated in the non-output region; a via hole formed at the isolated point of the TFT substrate; and a bypass wire for connecting the isolated TFT wire through the via hole. | 2021-08-19 |
20210257391 | Array Substrate and Manufacturing Method Thereof - An array substrate and a manufacturing method thereof are disclosed. The method includes: forming a first thin film transistor which includes a first semiconductor layer, a first gate electrode, a first drain electrode and a first source electrode; forming a second thin film transistor which includes a second semiconductor layer, a second gate electrode, a second drain electrode and a second source electrode; and forming a dielectric layer which spaces the first semiconductor layer apart from the second semiconductor layer; the method further includes: processing the same layer to form at least one selected from the group consisting of the first gate electrode, the first drain electrode and the first source electrode, at least one selected from the group consisting of the second gate electrode, the second drain electrode and the second source electrode, and the dielectric layer by the same layer. | 2021-08-19 |
20210257392 | DRIVE BACKPLANE AND DISPLAY PANEL - A drive backplane and a display panel are provided, the drive backplane includes: a substrate; and an oxide thin film transistor arranged on the substrate, wherein the oxide thin film transistor includes: an oxide active layer; a first gate structure disposed on a side of the oxide active layer away from the substrate; and a second gate structure disposed between the oxide active layer and the substrate; wherein at least one of the first gate structure and the second gate structure comprises a plurality of gate electrodes spaced apart along a direction in which the oxide active layer extends. | 2021-08-19 |
20210257393 | THIN FILM TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF, CIRCUIT STRUCTURE, DISPLAY SUBSTRATE AND DISPLAY DEVICE - A thin film transistor structure and a manufacturing method thereof, a circuit structure, a display substrate and a display device are provided. The thin film transistor structure includes: a base plate, and a first thin film transistor and a second thin film transistor stacked on the base plate. The first thin film transistor and the second thin film transistor share a same active layer. | 2021-08-19 |
20210257394 | DISPLAY DEVICE, MANUFACTURING METHOD OF DISPLAY DEVICE, AND ELECTRONIC DEVICE - A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate. | 2021-08-19 |
20210257395 | METHOD FOR SILICON NANOSENSOR MANUFACTURING AND INTEGRATION WITH CMOS PROCESS - A method for producing a silicon nanosensor integrated with advanced complementary metal oxide semiconductor (CMOS) logic circuit having gate length (Lg) of less than 0.25 μm, comprising the steps of: allocating a silicon nanosensor region and a CMOS logic circuit region on one bulk silicon substrate; forming silicon nanowires at the allocated nanosensor region while shielding the CMOS logic circuit region; applying a layer of protecting hardmask on the substrate such that the hardmask acts as an extra protection layer to the nanosensor region while acting as a hardmask for CMOS logic circuit formation process thereinafter; subjecting the substrate to selective etching to form trenches, filling the trenches with silicon oxide and subjecting the substrate to chemical mechanical planarization; and removing the hardmask from the substrate in a region-by-region manner, in which the nanosensor region remains unexposed while removing hardmark from the CMOS logic circuit region, and vice versa. | 2021-08-19 |
20210257396 | BACKSIDE ILLUMINATION ARCHITECTURES FOR INTEGRATED PHOTONIC LIDAR - A single and dual path light detection and ranging (LiDAR) system can transmit and receive light through a silicon substrate backside of a photonic integrated circuit (PIC). The PIC can be interface with an electrical integrated circuit (EIC) using a front side that connects to the EIC using electrical contacts and a backside that faces away from the EIC. High density coupler elements (e.g., pixels, gratings) can emit and receive infrared light that propagates through the PIC layers and the backside towards objects to detection. | 2021-08-19 |
20210257397 | IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS - The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate. The signal output external terminal is electrically connected to the first through-via via a first rewiring line, the signal input external terminal is electrically connected to the second through-via via a second rewiring line, and a third rewiring line being electrically independent is arranged in a layer in which the first rewiring line and the second rewiring line are arranged. The present disclosure can be applied to, for example, the image pickup device, and the like. | 2021-08-19 |
20210257398 | SPECTRAL SENSORS - The present invention relates to a spectral sensor. The spectral sensor comprising: a light detecting element; a microlens; and an interference filter arranged between the light detecting element and the microlens, and configured to transmit light in one or more spectral bands; wherein the microlens has an effective focal length (F) exceeding a distance (D) between the microlens and the light detecting element. The microlens may be configured such that light refracted by the microlens, to be transmitted through the interference filter, converges towards a position (P) behind the light detecting element. The present invention further relates to an image sensor comprising a plurality of spectral sensors. | 2021-08-19 |
20210257399 | PHOTOELECTRIC CONVERSION DEVICE, IMAGING SYSTEM, AND MOVING BODY - A photoelectric conversion device including an effective pixel region including a plurality of effective pixels and a peripheral region provided outside the effective pixel region, the photoelectric conversion device comprising: a wiring layer; an upper electrode; and a photoelectric conversion film provided extensively over the effective pixel region and the peripheral region, wherein each of the plurality of effective pixels includes a pixel electrode disposed between the wiring layer and the photoelectric conversion film in a depth direction, the peripheral region includes a conductive layer disposed between the wiring layer and the photoelectric conversion film in the depth direction, and the upper electrode and the conductive layer are at a same potential. | 2021-08-19 |
20210257400 | IMAGE PICKUP APPARATUS FOR ENDOSCOPE AND ENDOSCOPE - An image pickup apparatus for endoscope includes a resin member in which an outer dimension of a third main surface is equal to an outer dimension of a second main surface, an image pickup member having a light receiving surface smaller than the second main surface, and having a first external electrode on a back surface covered by the resin member, a fan-out wiring provided to extend between an inside and an outside of an extension space, the extension space being an extension of the image pickup member in an optical axis direction, a first through wiring penetrating through the resin member, and provided in the inside of the extension space, a first bonding electrode connected with the external electrode through the first through wiring and the fan-out wiring and forming the fan-out wiring provided on the third main surface, and an electric cable bonded to the first bonding electrode. | 2021-08-19 |
20210257401 | IMAGING DEVICE, STACKED IMAGING DEVICE, AND SOLID-STATE IMAGING APPARATUS - An imaging device includes a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked. In the imaging device, an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, and the inorganic oxide semiconductor material layer contains indium (In) atoms, gallium (Ga) atoms, and tin (Sn) atoms. | 2021-08-19 |
20210257402 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P | 2021-08-19 |
20210257403 | X-RAY DETECTOR, METHOD FOR MANUFACTURING X-RAY DETECTOR, AND MEDICAL EQUIPMENT - Disclosed are an X-ray detector, a method for manufacturing an X-ray detector and a medical equipment. The X-ray detector includes a scintillator ( | 2021-08-19 |
20210257404 | EMBEDDED DEVICE AND METHOD OF MANUFACTURING THE SAME - An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height. | 2021-08-19 |
20210257405 | MULTI-LEVEL MEMRISTOR ELEMENTS - There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element. | 2021-08-19 |
20210257406 | REIMAGING IN A LIDAR SYSTEM - A light detection and ranging (LIDAR) system is provided that includes an optical a scanning mirror to steer a laser beam emitted from the tip of an optical fiber to scan a scene, and collect light incident upon any objects in the scene that is returned to the fiber tip. The LIDAR system further includes a re-imaging lens located between the optical fiber and scanning mirror, and an optic located between the scanning mirror and the scene. The re-imaging lens focuses the laser beam emitted from the optical fiber on or close to the first scanning mirror's center of rotation and thereby re-image the fiber tip at or close to the center of rotation, from which the laser beam is reflected as a divergent laser beam. And the optic is configured to collimate or focus the divergent laser beam from the first scanning mirror that is launched toward the scene. | 2021-08-19 |
20210257407 | NONVOLATILE MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE - A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer. | 2021-08-19 |
20210257408 | THREE DIMENSIONAL MEMORY ARRAYS - The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines. | 2021-08-19 |
20210257409 | NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE LAYER AND METHOD OF OPERATING THE SAME - A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions. | 2021-08-19 |
20210257410 | INTEGRATED REACTIVE MATERIAL ERASURE ELEMENT WITH PHASE CHANGE MEMORY - A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells. | 2021-08-19 |
20210257411 | MEMRISTIVE DEVICE - A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nanowire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes. | 2021-08-19 |
20210257412 | THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT - A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements. | 2021-08-19 |
20210257413 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a first wiring extending in a first direction and a second wiring extending in a second direction. The first and second wirings are spaced from each other in a third direction. The second wiring has a first recess facing the first wiring. A resistance change memory element is connected between the first and second wirings. A conductive layer is between the resistance change memory element and the second wiring and includes a first protrusion facing the second wiring, A switching portion is between the conductive layer and the second wiring and includes a second recess facing the conductive layer and a second protrusion facing the second wiring. The first protrusion is in the second recess. The second protrusion is in the first recess. The switching portion is configured to switch conductivity state according to voltage between the first wiring and the second wiring. | 2021-08-19 |
20210257414 | IMAGING DEVICE - An imaging device includes: an effective pixel region that includes a plurality of imaging elements-A, amplifies signal charges generated by photoelectric conversion, and reads the signal charges into a drive circuit; and an optical black region that includes a plurality of imaging elements-B, surrounds the effective pixel region, and outputs optical black that serves as the reference for black level. In the imaging device, the photoelectric conversion layer forming the plurality of imaging elements-A and the plurality of imaging elements-B is a common photoelectric conversion layer, the common photoelectric conversion layer is located on an outer side of the optical black region, and extends toward an outer edge region surrounding the optical black region, and an outer edge electrode is disposed in the outer edge region. | 2021-08-19 |
20210257415 | IMAGING DEVICE AND SOLID-STATE IMAGE SENSOR - An imaging device includes a first electrode, a charge accumulating electrode arranged with a space from the first electrode, an isolation electrode arranged with a space from the first electrode and the charge accumulating electrode and surrounding the charge accumulating electrode, a photoelectric conversion layer formed in contact with the first electrode and above the charge accumulating electrode with an insulating layer interposed therebetween, and a second electrode formed on the photoelectric conversion layer. The isolation electrode includes a first isolation electrode and a second isolation electrode arranged with a space from the first isolation electrode, and the first isolation electrode is positioned between the first electrode and the second isolation electrode. | 2021-08-19 |
20210257416 | SUBSTRATE AND PREPARATION METHOD THEREOF, DISPLAY PANEL AND PREPARATION METHOD THEREOF, AND DISPLAY DEVICE - A substrate and a preparation method thereof, a display panel and a preparation method thereof, and a display device are provided. The substrate includes a display region and a peripheral region positioned in a periphery of the display region and used for sealing, the substrate includes: a base substrate; an insulating layer, arranged on a side of the base substrate and positioned in the display region and the peripheral region for sealing; and a plurality of pixel units, positioned on the insulating layer corresponding to the display region, and in the peripheral region, at least one groove is disposed on a side of the insulating layer which faces away from the base substrate, a side of the groove which is away from the base substrate is open, and a depth direction of the groove is perpendicular to the base substrate. | 2021-08-19 |
20210257417 | Display Substrate and Manufacturing Method Thereof, Display Panel and Display Device - A display substrate and a fabrication method thereof, a display panel and a display device are provided. The display substrate includes pixels. Each of the pixels includes sub-pixels that emit light of different colors, each of the sub-pixels includes a light emitting element, and at least one of the sub-pixels further includes a color filter. The color filter of the at least one of the sub-pixels covers a portion of a light emitting region of the light emitting element of the at least one of the sub-pixels, and a color of the color filter of the at least one of the sub-pixels is the same as a color of light emitted by the light emitting element of the at least one of the sub-pixels. | 2021-08-19 |
20210257418 | DISPLAY DEVICE - A display device including a pixel includes: a substrate; a first pattern disposed on the substrate; a conductive, second pattern disposed on the first pattern and partially overlapping the first pattern; a conductive, third pattern disposed on the second pattern and partially overlapping the second pattern; a conductive, fourth pattern disposed on the third pattern and partially overlapping the third pattern, wherein the first pattern, the second pattern, the third pattern, and the fourth pattern overlap each other in a first area of the pixel; a pixel defining layer disposed on the fourth pattern and including a first opening overlapping a second area of the pixel without overlapping the first area; and a first emission layer to emit light having a blue color, the first emission layer disposed in the first opening. | 2021-08-19 |
20210257419 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device includes: a display panel having a first display area and a second display area, the first and second display areas having different light transmittances from each other in a unit area, wherein the display panel includes a plurality of organic light-emitting diodes disposed in the first display area and the second display area, wherein a first organic light-emitting diode disposed in the first display area and a second organic light-emitting diode disposed in the second display area each include at least one light emitter, and the number of the light emitter included in the second organic light-emitting diode is greater than the number of the light emitter included in the first organic light-emitting diode. | 2021-08-19 |
20210257420 | VISIBLE LIGHT SENSOR EMBEDDED ORGANIC LIGHT EMITTING DIODE DISPLAY PANELS AND DISPLAY DEVICES INCLUDING THE SAME - An OLED display panel may include a substrate, an OLED light emitter on the substrate and configured to emit light, and a visible light sensor on the substrate and configured to detect at least a portion of the emitted light based on reflection of the portion of the emitted light from a recognition target. The visible light sensor is in a non-light emitting region adjacent to the OLED light emitter so as to be horizontally aligned with the OLED light emitter in a horizontal direction extending parallel to an upper surface of the substrate, or between the substrate and a non-light emitting region adjacent to the OLED light emitter such that the visible light sensor is vertically aligned with the non-light emitting region in a vertical direction extending perpendicular to the upper surface of the substrate. | 2021-08-19 |
20210257421 | DISPLAY DEVICE, FLEXIBLE DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR - The present disclosure relates to the technical field of display, and provided thereby are a display device, a flexible display panel and a manufacturing method therefor. The flexible display panel comprises a flexible substrate and a plurality of pixel islands arranged in an array on the flexible substrate; the pixel islands have a display region and a peripheral region surrounding the display region, and each pixel island comprises a driving layer, a first electrode layer, a light emitting layer and a second electrode layer that are sequentially stacked on the flexible substrate; the first electrode layer comprises a first electrode located in the display region and a peripheral electrode located in the peripheral region; the peripheral electrode surrounds the display region, and a surface of the peripheral electrode away from the flexible substrate is provided with a barrier structure surrounding the display region, a preset spacing being present between the barrier structure and the display region; and the light emitting layer is intermittently provided in a region directly opposite to the barrier structure and a region located within a range of the preset spacing. | 2021-08-19 |
20210257422 | DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL - The present disclosure relates to an organic light emitting diode display panel and a method of manufacturing the organic light emitting diode display panel. A display panel, including: a plurality of first light emitting layers configured to emit a light of a first color when excited, the first light emitting layers are arranged in an array in a first direction and a second direction intersecting the first direction, each first light emitting layer includes a shaded region, the shaded region is a peripheral region of the first light emitting layer and has a thickness less than a first thickness threshold; and a pixel defining layer including a plurality of first openings covered by corresponding first light emitting layers, the plurality of first openings defining respective first light emitting zones of the plurality of first light emitting layers. | 2021-08-19 |
20210257423 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - In a display device in which an OLED is formed by a separate coating method, improving the accuracy of vapor deposition position and reducing display defects are established. In the array substrate, a display unit that displays an image configured with a plurality of pixels is formed. A first convex portion and a second convex portion are provided on a surface of a boundary region between the pixels of the array substrate. A first organic layer including a layer exhibiting a first emission color is stacked on the pixel electrode of the pixel, and second organic layers including a layer exhibiting a second emission color are stacked on the pixel electrode of the pixels. The first organic layer is provided to cover only the first convex portion. The second organic layers are provided not to cover any one of the first convex portion and the second convex portion. | 2021-08-19 |
20210257424 | DISPLAY DEVICE HAVING A POWER SUPPLY ELECTRODE LAYER INCLUDING A PLURALITY OF HOLES - A display device including: a substrate; a plurality of display elements defining a display area on the substrate and each including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; a power supply wiring disposed outside the display area; an organic insulating layer on the power supply wiring and having an opening exposing the power supply wiring; a power supply electrode layer partially disposed on the organic insulating layer and including a plurality of holes over the organic insulating layer. A first portion of the power supply electrode layer overlaps the power supply wiring and a second portion of the power supply electrode layer overlaps the opposite electrode; a plurality of protrusions spaced apart from each other and respectively covering at least some of the plurality of holes; and an encapsulation layer covering the plurality of display elements. | 2021-08-19 |
20210257425 | DISPLAY DEVICE, ELECTRONIC APPARATUS, AND METHOD OF FABRICATING THE DISPLAY DEVICE - It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured. | 2021-08-19 |
20210257426 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers lire first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 Å to about 400 Å. A gate insulation layer covers the active pattern A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern. | 2021-08-19 |
20210257427 | METHOD FOR MANUFACTURING DISPLAY DEVICE, AND DISPLAY DEVICE - A display device ( | 2021-08-19 |
20210257428 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display substrate and a manufacturing method thereof, and a display device, and relates to the field of display technology. The display substrate includes a base substrate and a thin film transistor array. The thin film transistor array includes a plurality of thin film transistors. A first electrode in each thin film transistor includes a first portion and a second portion having a height difference therebetween, and a height of the second portion is greater than a height of the first portion in a direction perpendicular to the base substrate. | 2021-08-19 |
20210257429 | DISPLAY PANEL AND DISPLAY DEVICE - Provided are a display panel and a display device. The display panel includes a base substrate; a first transistor and a second transistor, where the first transistor and the second transistor are formed on the base substrate, the first transistor includes a first active layer, a first gate, a first source, and a first drain, the first active layer contains silicon, the second transistor includes a second active layer, a second gate, a second source, and a second drain; and a first insulating layer and a second insulating layer, where the first insulating layer is located on a side of the second active layer facing away from the base substrate and between the second gate and the second active layer, the second insulating layer is located on a side of the second active layer facing towards the base substrate. | 2021-08-19 |
20210257430 | ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE - An organic light-emitting display device comprises a first thin-film transistor disposed on a substrate; and a second thin-film transistor disposed on the substrate and spaced apart from the first thin-film transistor. The first thin-film transistor comprises a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and that overlaps the first semiconductor layer, and a first insulating layer disposed between the first semiconductor layer and the first conductive layer. The second thin-film transistor comprises a second semiconductor layer, and a second conductive layer disposed on the second semiconductor layer and that overlaps the second semiconductor layer. The first semiconductor layer is disposed on a layer higher than the second semiconductor layer, the first semiconductor layer comprises an oxide semiconductor, the second semiconductor layer comprises low temperature polycrystalline silicon (LTPS), and the first insulating layer covers the entire first semiconductor layer. | 2021-08-19 |
20210257431 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display (OLED) device includes an organic light emitting diode having an anode and a cathode. The organic light emitting diode is configured to receive a reference voltage. A control transistor includes a first control electrode and a first semiconductor active layer. The control transistor is configured to receive a control signal. A driving transistor includes a second control electrode that is electrically connected to the control transistor, an input electrode that is configured to receive a power voltage, an output electrode that is electrically connected to the anode of the organic light emitting diode, and a second semiconductor active layer that includes a different material from that of the first semiconductor active laver. A shielding electrode is disposed on the second semiconductor active layer, overlapping the driving transistor, and configured to receive the power voltage. | 2021-08-19 |
20210257432 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer. | 2021-08-19 |
20210257433 | DISPLAY DEVICE - A display device includes: a substrate; a first restriction dam in a non-display area of the substrate and surrounding a display area of the substrate; a second restriction dam in the non-display area and surrounding the display area between the display area and the first restriction dam; a bank surrounding the display area outside the first restriction dam; and a voltage line configured to supply a voltage to a display element inside the display area, wherein the first restriction dam and the second restriction dam are on the voltage line between the display area and a pad area on one side of the non-display area, and the voltage line extends to the bank beyond the first restriction dam. | 2021-08-19 |
20210257434 | Display Substrate and Preparation Method Thereof, and Display Apparatus - Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a base substrate, a plurality of pixel island regions distributed in an array and spaced apart from each other, a plurality of aperture regions, and connection bridge regions located between pixel island regions and aperture regions, which are disposed on the base substrate, wherein the connection bridge region is provided with an isolation structure layer for cutting off an organic emitting layer and a cathode in the connection bridge region. | 2021-08-19 |
20210257435 | DISPLAY DEVICE - A display device includes an active area including pixels arranged in a matrix shape, a non-active area disposed at one side of the active area in a first direction and including a pad unit, non-active fanout wirings disposed in the non-active area and connected to the pad unit, signal wirings extending in the first direction to traverse the active area and connected to the pixels, and connection wirings, each at least partially passing through the active area and connecting some of the non-active fanout wirings and some of the signal wirings. Each of the connection wirings include first and third extension portion extending in the first direction, and a second extension portion extending in a second direction, and at least two of the pixels are disposed between corresponding extension portions of two adjacent connection wirings along a direction in which the corresponding extension portions are spaced apart from each other. | 2021-08-19 |
20210257436 | DISPLAY DEVICE - A display device includes a substrate, a pixel structure, a lighting circuit part, a driving integrated circuit part, a first lighting wire, a second lighting wire, and a connection electrode. The substrate includes a display area and a pad area. The pixel structure is on the substrate in the display area to emit light. The lighting circuit part is on the substrate in the pad area, and is electrically coupled to the pixel structure. The first lighting wire is spaced apart from a first side of the driving integrated circuit part in a first direction, and is coupled to the lighting circuit part. The second lighting wire is spaced apart from a second side facing the first side of the driving integrated circuit part in a second direction opposite to the first direction. The connection electrode electrically couples the first lighting wire and the second lighting wire to each other. | 2021-08-19 |
20210257437 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area around the display area. A pixel is disposed on the display area. A first dam is disposed on the non-display area. The first dam includes a first sub-dam and a second sub-dam disposed on the first sub-dam. A first power line is disposed on the non-display area and passes between the first sub-dam and the second sub-dam. The first power line is connected to the pixel. A bridge pattern is disposed under the first sub-dam. The bridge pattern is connected to the first power line. | 2021-08-19 |
20210257438 | DISPLAY DEVICE - A display device includes an active region including pixels receiving data signals through data lines, and a non-active region on a side of the active region in a first direction and including a pad portion. The display device includes non-active fan-out wirings in the non-active region and connected to the pad portion, signal wirings extending in the first direction across the active region and connected to the pixels, and connection wirings passing through the active region and connecting some of the non-active fan-out wirings and some of the signal wirings. Each of the connection wirings includes first and second extension portions made of a first conductive layer, and a third extension portion made of a second conductive layer different from the first conductive layer. The first and second extension portions extend in the first direction, and the third extension portion extends in a second direction intersecting the first direction. | 2021-08-19 |