| 33rd week of 2010 patent applcation highlights part 8 |
| Patent application number | Title | Published |
|---|
| 20100207119 | SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR, AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided. | 2010-08-19 |
| 20100207120 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The present invention provides a production method of a semiconductor device and a semiconductor device that permits suppression of a leakage current. A production method of a semiconductor device includes a structure in which a semiconductor layer, an insulating film, and a gate electrode are stacked on a main surface of a substrate in this order,
| 2010-08-19 |
| 20100207121 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE - A substrate supporting thin film transistors thereon, each including a semiconductor layer and source-drain electrodes, wherein the source-drain electrodes are formed from a nitrogen-containing layer or oxygen/nitrogen-containing layer and a thin film of pure copper or copper alloy. The nitrogen-containing layer or oxygen/nitrogen-containing layer has respectively part or all of its nitrogen or part or all of its oxygen or nitrogen connected to silicon in the semiconductor layer of the thin film transistor, and the thin film of pure copper or copper alloy is connected to the semiconductor layer of said thin film transistor through the nitrogen-containing layer or oxygen/nitrogen-containing layer. | 2010-08-19 |
| 20100207122 | Thin film transistor array substrate and manufacturing method thereof - A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring. Also, the data linker includes the gate pattern connected to the data pad, the data pattern formed opposite to the gate pattern in the center of the gate insulation film, and the connection wiring configured to connect the gate pattern with the data pattern through a first contact hole which exposes the data pattern and the gate pattern by penetrating through the passivation film and the gate insulation film. | 2010-08-19 |
| 20100207123 | LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device may include a plurality of light emitting elements formed on a first common electrode, each light emitting element having a first conductive layer formed over the first common electrode. The light emitting device may also include an active layer formed over the first conductive layer, a second conductive layer formed over the active layer, and an insulator formed between adjacent light emitting elements. A plurality of electrodes may be respectively formed on the plurality of light emitting elements, and a second common electrode may couple the plurality electrodes. Such a light emitting structure may improve emission characteristics, heat dissipation and high temperature reliability. | 2010-08-19 |
| 20100207124 | COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive. | 2010-08-19 |
| 20100207127 | LIGHT EMITTING DIODE WITH A TEMPERATURE DETECTING PATTERN AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate, a temperature detecting pattern, and a semiconductor structure. The temperature detecting pattern is formed on the substrate. Then the semiconductor structure is formed on the temperature detecting pattern and the substrate. The semiconductor structure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer. Per above-mentioned structural design, the temperature detecting pattern directly integrated into the LED can measure the actual temperature of PN junction with high precision. | 2010-08-19 |
| 20100207128 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a plurality of isolation layers formed along an outer peripheral portion of the light emitting structure below the light emitting structure, a metal layer interposed between the isolation layers, and a second electrode layer formed below the light emitting structure. | 2010-08-19 |
| 20100207129 | LIGHT EMITTING DIODE LIGHT SOURCE FOR EMITTING POLARIZED LIGHT - An exemplary light emitting diode (LED) light source includes a frame and light emitting units. The frame includes a supporting surface having a curved surface and one or more receiving holes configured in the curved surface. Each of the light emitting units is received in a respective receiving hole. Each of the light emitting units includes an LED die for generating light of two polarization states, a reflective polarizer for preferentially reflects one polarization state back into the LED die and preferentially transmitting the other polarization state out of the light emitting unit, a polarization converting film for converting the reflected light of the first polarization state into light of the second polarization state, and a reflective film for reflecting light of the converted second polarization state to the reflective polarizer. | 2010-08-19 |
| 20100207130 | ACTIVE MATRIX SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE - An active matrix substrate | 2010-08-19 |
| 20100207133 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light emitting device (A) includes an elongated substrate ( | 2010-08-19 |
| 20100207134 | LED LIGHTING DEVICE - An LED lighting device comprises a plurality of light emitting units which is configured to emit visible light having different colors which are mixed with each other to produce a white light. Each the light emitting units is composed of an LED chip and a phosphor. The LED chip is configured to generate light. The phosphor has a property of giving off a light of a predetermined color when the phosphor is excited by the light from the LED chip. The LED chip is selected from a group consisting of a blue LED chip, a UV LED chip, ad a violet LED chip. Each the phosphor is selected to give off the light of a predetermined color different from one another. | 2010-08-19 |
| 20100207139 | PHOTONIC MATERIAL HAVING REGULARLY ARRANGED CAVITIES - The invention relates to photonic materials having regularly arranged cavities containing at least one colorant, where the wall material of the photonic material has dielectric properties and as such is essentially non-absorbent for the wavelength of an absorption band of the respective colorant and is essentially transparent for the wavelength of a colorant emission which can be stimulated by the absorption wavelength, and the cavities are shaped in such a way that radiation having the wavelength of the weak absorption band of the colorant is stored in the photonic material, to the use thereof as phosphor system in an illuminant, to corresponding illuminants and production processes. | 2010-08-19 |
| 20100207140 | COMPACT MOLDED LED MODULE - A method of forming a light emitting diode (LED) module molds an array of lens support frames over an array of connected lead frames. LEDs are bonded to the lead frame contacts within the support frames. Molded lenses are then affixed over each support frame, and the lead frames are diced to create individual LED modules. In another embodiment, the lenses are molded along with the support frames to create unitary pieces, and the support frames are affixed to the lead frames in the array of connected lead frames. In another embodiment, no lenses are used, and cups are molded with the lead frames so that the LED module is formed solely of the unitary lead frame/cup and the LED. Since each LED enclosure is formed of only one or two separate pieces, and the modules are fabricated on an array scale, the modules can be made very small and simply. | 2010-08-19 |
| 20100207143 | LIGHT EMITTING DEVICE - A light emitting device includes a carrier, a light emitting element disposed and electrically connected to the carrier, and a transparent plate disposed on the carrier and including a flat-portion and a lens-portion. The lens-portion covers the light emitting element and has a light incident surface, a light emitting surface, a first side surface and a second side surface. The light emitting element is suitable for emitting a light beam. A first partial beam of the light beam passes through the light incident surface and leaves from the light emitting surface. A second partial beam of the light beam passes through the light incident surface and is transmitted to the first side surface or the second side surface, and the first side surface or the second side surface reflects at least a part of the second partial beam of the light beam to be passed through the light emitting surface. | 2010-08-19 |
| 20100207144 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package including a package body including a plurality of discrete and separated three-dimensional-shaped indentations formed in an undersurface of the package body and configured to dissipate heat generated in the package body, a cavity in the package body, and a light emitting device including at least one emitting diode in the cavity of the package body and configured to emit light. | 2010-08-19 |
| 20100207145 | Thin film light emitting diode - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition. | 2010-08-19 |
| 20100207146 | Light emitting element - A light emitting element includes a semiconductor laminated structure including a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type different from the first conductivity type, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, a surface electrode including a center electrode disposed on one surface of the semiconductor laminated structure and a thin wire electrode extending from a periphery of the center electrode, and a contact part disposed on a part of another surface of the semiconductor laminated structure extruding a part located directly below the surface electrode, in parallel along the thin wire electrode, and including a plurality of first regions forming the shortest current pathway between the thin wire electrode and a second region allowing the plural first regions to be connected. The surface electrode has an arrangement that the shortest current pathway between the center electrode and the contact part is longer than the shortest current pathway between the thin wire electrode and the first region, and the shortest current pathway between an end part of the thin wire electrode and the contact part is not shorter than the shortest current pathway between the thin wire electrode and the first region. | 2010-08-19 |
| 20100207149 | ORGANIC LIGHT-EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode (OLED) including: a substrate; a reflection layer on the substrate and including metal; a first electrode on the reflection layer and including a light transparent aluminum zinc oxide (AZO); an organic layer on the first electrode and including an emitting layer; and a second electrode on the organic layer and including a semi-permeable reflection layer. | 2010-08-19 |
| 20100207150 | Light Emitting Diode Assembly and Methods - Exemplary systems and methods for LED light engines include an LED package with electrical leads, each lead forming a compliant portion for making electrical and mechanical connection upon insertion into a receptacle of a circuit substrate. In an illustrative example, the electrical and mechanical connections may be formed upon the insertion of the compliant portion into the receptacle and without further process steps involving solder. Various examples may further include an elongated thermal dissipation member extending from a bottom of a package that contains the LED, where the elongated thermal member (e.g., tab) may be in substantial thermal communication with the LED die. As an example, the tab may provide a substantially reduced thermal impedance for dissipating heat from the LED die. Upon insertion into a circuit substrate, the LED package may be releasable by mechanical extraction without applied heat to facilitate repair or replacement, for example. | 2010-08-19 |
| 20100207155 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a substrate including a plurality of discrete and separated protruding reflective patterns protruding from the substrate and including a valley; a first semiconductor layer on the substrate and covering the reflective patterns; a gap formed in the valley of a corresponding reflective pattern between the substrate and the first semiconductor layer; an active layer on the first semiconductor layer; and a second semiconductor layer on the active layer. | 2010-08-19 |
| 20100207156 | Light emitting device package - Provided is a light emitting device package. The light emitting device package comprises a first conductive type package body, an insulating layer comprising an opening on the package body, a plurality of compound semiconductor layers disposed on the package body through the opening of the insulating layer, an electrode electrically connected to the plurality of compound semiconductor layers, a first metal layer electrically connected to the package body and disposed on a part of the insulating layer, and a second metal layer electrically connected to the electrode and disposed on the other part of the insulating layer. | 2010-08-19 |
| 20100207161 | Device and Method for Coupling First and Second Device Portions - This disclosure relates to devices and methods relating to coupled first and second device portions. | 2010-08-19 |
| 20100207162 | VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE - A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n | 2010-08-19 |
| 20100207163 | SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC-DISCHARGE PROTECTION CIRCUIT - A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells. | 2010-08-19 |
| 20100207164 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a first nitride semiconductor layer | 2010-08-19 |
| 20100207167 | COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive. | 2010-08-19 |
| 20100207168 | Cross-Point Memory Structures, And Methods Of Forming Memory Arrays - Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction. | 2010-08-19 |
| 20100207175 | SEMICONDUCTOR TRANSISTOR DEVICE HAVING AN ASYMMETRIC EMBEDDED STRESSOR CONFIGURATION, AND RELATED MANUFACTURING METHOD - A semiconductor transistor device is provided. The transistor device includes a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, and a drain region in the layer of semiconductor material. The source region has a stress-inducing semiconductor material located therein, while the drain region is free of any stress-inducing semiconductor material. This asymmetric arrangement of stress-inducing elements results in relatively high source-body leakage, and relatively low drain-body leakage, which is beneficial in analog circuit applications. | 2010-08-19 |
| 20100207176 | Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same - Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer. | 2010-08-19 |
| 20100207179 | DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING AN ASYMMETRIC TRANSISTOR AND A COLUMNAR CAPACITOR - A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell. | 2010-08-19 |
| 20100207180 | HIGH-PERFORMANCE ONE-TRANSISTOR FLOATING-BODY DRAM CELL DEVICE - Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased. | 2010-08-19 |
| 20100207181 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 2010-08-19 |
| 20100207182 | Implementing Variable Threshold Voltage Transistors - A circuit and method for implementing variable threshold voltage transistors in a complementary metal oxide semiconductor (CMOS) semiconductor chip, and a design structure on which the subject circuit resides are provided. Variable threshold voltage transistors are provided utilizing the NWELL and PWELL proximity effects of the CMOS semiconductor chip without any additional mask steps. A distance between an adjacent field effect transistor (FET) and an NWELL edge or PWELL edge is adjusted to selectively provide a needed threshold voltage for the FET. | 2010-08-19 |
| 20100207187 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation. | 2010-08-19 |
| 20100207188 | Semiconductor device and method of fabricating the same - A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film. | 2010-08-19 |
| 20100207189 | NON-VOLATILE MEMORY DEVICE WITH REDUCED WRITE-ERASE CYCLE TIME - A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region. | 2010-08-19 |
| 20100207190 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes. | 2010-08-19 |
| 20100207191 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 2010-08-19 |
| 20100207192 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor memory device capable of more efficiently trapping charges in a charge storage layer without increasing the thickness of the charge storage layer, as well as a manufacturing method thereof. In the non-volatile semiconductor memory device a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode are disposed successively between a first source/drain region and a second source/drain region above a semiconductor substrate. The charge storage layer has a first layer and second layers, the first layer has a first nitrogen atom concentration, each of the second layers has a second nitrogen atom concentration, higher than the first nitrogen atom concentration and faces one of the tunnel insulating film and the block insulator. | 2010-08-19 |
| 20100207195 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers functions as gate electrodes of the memory cells. | 2010-08-19 |
| 20100207196 | SEMICONDUCTOR DEVICE HAVING INTERNAL GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a main gate formed on a semiconductor substrate and a source region and a drain region formed in a surface of the semiconductor substrate on opposite sides of the main gate. An internal gate formed within a portion of the main gate that adjoins the source region. | 2010-08-19 |
| 20100207197 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented. | 2010-08-19 |
| 20100207198 | METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FACILITATING FORMATION OF FLOATING ISLANDS - A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween. | 2010-08-19 |
| 20100207201 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region and a source region of a second MOS transistor. The semiconductor device comprises: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric film, wherein: the first MOS transistor includes a first drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed in such a manner that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film; and the second MOS transistor includes a third drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed in such a manner that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film, and wherein a first silicide layer is formed to connect at least a part of a surface of the first drain or source region and at least a part of a surface of the third drain or source region, wherein the first silicide layer is formed in an area other than an area in which a contact for at least the first drain or source region and the third drain or source region is formed. | 2010-08-19 |
| 20100207202 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first insulating film, a second insulating film, and a conductive layer. The semiconductor substrate includes a pillar portion extending from a main surface of the semiconductor substrate. The first insulating film covers a side surface of the pillar portion. The second insulating film covers the main surface of the semiconductor substrate. The second insulating film is thicker than the first insulating film. The conductive layer extends along the first insulating film. | 2010-08-19 |
| 20100207203 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A Semiconductor device includes a substrate having an active region defined by a device isolation layer, a trench formed by etching the active region and the device isolation layer, a buried gate filling a portion of the trench, an interlayer insulation layer formed over the buried gate and filling a remainder of the trench, and an oxidation protecting layer formed between the buried gate and the device isolation layer. | 2010-08-19 |
| 20100207204 | Semiconductor device and method of fabricating the same - A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer. | 2010-08-19 |
| 20100207207 | SEMICONDUCTOR STRUCTURE - The invention provides a semiconductor structure. A first type body doped region is deposited on a first type substrate. A first type heavily-doped region having a finger portion with an enlarged end region is deposited on the first type body doped region. A second type well region is deposited on the first type substrate. A second type heavily-doped region is deposited on the second type well region. An isolation structure is deposited between the first type heavily-doped region and the second type heavily-doped region. A gate structure is deposited on the first type substrate between the first type heavily-doped region and the isolation structure. | 2010-08-19 |
| 20100207208 | NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME - A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region. | 2010-08-19 |
| 20100207209 | SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF - A semiconductor device having a small parasitic resistance and a high driving current is provided. The semiconductor device includes a fin portion that includes a pair of source/drain regions located on both end sides and a channel region sandwiched between the pair of source/drain regions; films that are formed on both sides in a channel-width direction of the fin portion; a gate electrode that is provided so as to stride across the channel region of the fin portion; a gate insulating film that is interposed between the gate electrode and the channel region; and a stress applying layer that applies a stress to the channel region of the fin portion, an upper surface and side surfaces of the source/drain region being coated with the stress applying layer in the fin portion, a lower end surface of the stress applying layer being in contact with the film with no gap. | 2010-08-19 |
| 20100207210 | Semiconductor devices - A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern. | 2010-08-19 |
| 20100207211 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a fin-type semiconductor region ( | 2010-08-19 |
| 20100207212 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCED BY SAME METHOD - To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer | 2010-08-19 |
| 20100207217 | Micro-Electro-Mechanical System Having Movable Element Integrated into Substrate-Based Package - Semiconductor-centered MEMS ( | 2010-08-19 |
| 20100207218 | ELECTRONIC COMPONENT DEVICE, AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an electronic component device, includes the steps of preparing a wiring substrate, which includes a silicon substrate, a concave portion provided on its upper surface side, a through hole formed to penetrate the silicon substrate on a bottom surface side of the concave portion, an insulating layer formed on the silicon substrate, a penetration electrode constructed by a lower conductor portion formed to a halfway position of a height direction from a bottom portion of the through hole and a connection metal member (indium layer) formed on the lower conductor portion in the through hole, and an electronic component having a terminal metal member (gold bump) on a lower surface side, and softening the connection metal member of the wiring substrate in a heating atmosphere and then sticking the terminal metal member of the electronic component into the connection metal member and connecting thereto. | 2010-08-19 |
| 20100207221 | Magnetic Random Access Memory - A device includes a magnetic tunnel junction (MTJ) structure and a cap layer in contact with the MTJ structure. The device also includes a spin-on material layer in contact with a sidewall portion of the cap layer and a conducting layer in contact with at least the spin-on material layer and a portion of the MTJ structure. The cap layer has been etched to expose a portion of an electrode contact layer of the MTJ structure. The conducting layer is in electrical contact with the exposed portion of the electrode contact layer of the MTJ structure. | 2010-08-19 |
| 20100207222 | Hall Effect Element Having a Hall Plate with a Perimeter Having Indented Regions - A Hall effect element includes a Hall plate with an outer perimeter. The outer perimeter includes four corner regions, each tangential to two sides of a square outer boundary associated with the Hall plate, and each extending along two sides of the square outer boundary by a corner extent. The outer perimeter also includes four indented regions. Each one of the four indented regions deviates inward toward a center of the Hall plate. The Hall plate further includes a square core region centered with and smaller than the square outer boundary. A portion of each one of the four indented regions is tangential to a respective side of the square core region. Each side of the square core region has a length greater than twice the corner extent and less than a length of each side of the square outer boundary. | 2010-08-19 |
| 20100207225 | Solid-state imaging device, electronic apparatus, and method for manufacturing the same - A solid-state imaging device includes: photoelectric conversion elements disposed on an imaging surface of a substrate, receiving light incident on a light receiving surface and performing photoelectric conversion to produce a signal charge; electrodes interposed between the photoelectric conversion elements; and light blocking portions provided above the electrodes and interposed between the photoelectric conversion elements. The light blocking portions include an electrode light blocking portion formed to cover the corresponding electrode, and a pixel isolation and light blocking portion protruding convexly from the upper surface of the electrode light blocking portion. The photoelectric conversion elements are arranged at first pitches on the imaging surface. The electrode light blocking portions and the pixel isolation and light blocking portions in the light blocking portions are arranged at second and third pitches, respectively, on the imaging surface. At least the third pitch increases with distance from the center toward the periphery of the imaging surface. | 2010-08-19 |
| 20100207226 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer. | 2010-08-19 |
| 20100207231 | SOLID-STATE IMAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - Photoelectric conversion regions ( | 2010-08-19 |
| 20100207232 | Gallium Nitride Semiconductor Device With Improved Forward Conduction - A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and Ohmic contacts. A first metal pad is formed in a third metal layer and over vias to the Schottky contacts to form an anode electrode. A second metal pad is formed in the third metal layer and over vias to the ohmic contacts to form a cathode electrode. | 2010-08-19 |
| 20100207235 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation structure formed in a semiconductor substrate to delimit an active region. The active region includes a gate forming area. Spacers are formed on the side surfaces of the active region excluding portions of the side surfaces of the active region at the gate forming area, such that side surfaces of the gate forming area of the active region are exposed. A gate is formed to cover the exposed gate forming area of the active region. | 2010-08-19 |
| 20100207236 | METHOD FOR MAKING A SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH AN INTEGRATED GROUND PLANE - A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane. | 2010-08-19 |
| 20100207237 | Crack stop structure enhancement of the integrated circuit seal ring - An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate. | 2010-08-19 |
| 20100207238 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer. | 2010-08-19 |
| 20100207247 | Semiconductor Integrated Circuit Device and Method of Fabricating the Same - A semiconductor integrated circuit device includes a lower electrode formed on a substrate, a first dielectric layer formed of a metal nitride layer, a metal oxynitride layer, or a combination thereof, on the lower electrode, a second dielectric layer formed on the first dielectric layer that includes a zirconium oxide layer, and an upper electrode formed on the second dielectric layer. | 2010-08-19 |
| 20100207248 | Patterns of Semiconductor Device and Method of Forming the Same - A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns. | 2010-08-19 |
| 20100207251 | Scribe Line Metal Structure - A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers. | 2010-08-19 |
| 20100207252 | Manufacturing method of semiconductor device - An adhesive layer of which thickness is over 25 μm and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board. | 2010-08-19 |
| 20100207255 | Shield for an intergrated circuit - A shield for an integrated circuit comprising an upper wall and a side wall assembly. The upper wall includes a top surface, a bottom surface and a perimeter. The side wall assembly depends from the perimeter of the upper wall. The side wall assembly has a proximal end, a distal end, an inner surface and an outer surface. The distal end defines a lower edge. At least a portion of the side wall assembly includes a plurality of surface variations along a length thereof, to, in turn, define a lower edge of the side wall assembly having a non-linear configuration. Such a non-linear configuration increases the rigidity of the shield. | 2010-08-19 |
| 20100207256 | SECURITY CHIP - A security chip is disclosed. The security chip includes: a substrate; an integrated circuit disposed on the substrate, the integrated circuit including circuit elements, circuit interconnect layers connecting the circuit elements together, and interlayer contacts supporting the circuit interconnect layers; a shield to at least partially shield the integrated circuit; and at least one lightwell in the shield and the integrated circuit, wherein each lightwell has a closed shape formed from parts of the circuit interconnect layers and interlayer contacts, wherein no exploitable voltage can be measured on the parts of the circuit interconnect layers and interlayer contacts, and wherein each lightwell forms a path for light to penetrate to the substrate preventing the light from reaching the circuit elements. Related apparatus and methods are also disclosed. | 2010-08-19 |
| 20100207259 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element. | 2010-08-19 |
| 20100207260 | QUAD FLAT PACKAGE WITH EXPOSED COMMON ELECTRODE BARS - An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed. | 2010-08-19 |
| 20100207261 | CHIP ATTACH ADHESIVE TO FACILITATE EMBEDDED CHIP BUILD UP AND RELATED SYSTEMS AND METHODS - Present embodiments are directed to an adhesive and method for assembling a chip package. The adhesive may be used to couple a chip to a substrate, and the adhesive may include an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator. | 2010-08-19 |
| 20100207262 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings. | 2010-08-19 |
| 20100207263 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first chip coupled to an electrical insulator, and a sintered heat conducting layer disposed between the electrical insulator and the first chip. | 2010-08-19 |
| 20100207264 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTED STRUCTURE - A module substrate has an interconnection electrode that is exposed at a side end face thereof. A semiconductor component including an IC chip is mounted on the module substrate. A molded part comprising a resin is formed so as to cover at least a part of the semiconductor component. A coating with higher heat conductivity than the molded part is formed on the surface of the molded part by applying a paste made of material with higher heat conductivity than the molded part. This improves heat dissipation. The coating can be formed such that it extends to the surface of the main substrate on which the module substrate with the semiconductor component is mounted and comes into contact with the interconnection electrode on the surface of the main substrate. This further improves heat dissipation. | 2010-08-19 |
| 20100207269 | Integrated Circuit Nanowires - Implementations of encapsulated nanowires are disclosed. | 2010-08-19 |
| 20100207270 | SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE DEVICE - A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes. | 2010-08-19 |
| 20100207273 | Micro Ball Feeding Method - Provided is a feeding method for feeding conductive balls to the insides of through holes of a mask reliably and efficiently so as to match a fine pitch. In the feeding method, a head ( | 2010-08-19 |
| 20100207274 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of suppressing surface scattering of electrons and reduction in electrical conductivity thereof. | 2010-08-19 |
| 20100207275 | HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals. | 2010-08-19 |
| 20100207276 | SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES - The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate. The inorganic ARC is liquid deposited and comprises a polymer that has at least one monomer unit comprising the formula M-R | 2010-08-19 |
| 20100207277 | SEMICONDUCTOR COMPONENT HAVING A STACK OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING THE SAME - A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another. | 2010-08-19 |
| 20100207278 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias. | 2010-08-19 |
| 20100207279 | SEMICONDUCTOR PACKAGE WITH RIBBON WITH METAL LAYERS - A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a ribbon. The ribbon includes a first metal layer and a second metal layer. The first metal layer is welded to the first chip and the second metal layer is attached to the second chip. | 2010-08-19 |
| 20100207280 | Wire bonding method and semiconductor device - After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead. | 2010-08-19 |
| 20100207287 | METHOD AND DEVICE FOR EXPLOSION FORMING - With the invention, a method and a device for explosive forming of work pieces, in which at least one work piece is arranged in at least one die and there deformed by means of an explosive to be ignited, is to be improved, in that an ignition mechanism that is technically easy to handle is produced with the shortest possible setup times, which permits the most precise possible ignition of the explosive with time-repeatable accuracy. This task is solved by a method and device, in which at least one work piece is arranged in at least one die and deformed there by means of an explosive being ignited, in which the explosive is ignited by means of at least one energy beam. | 2010-08-19 |
| 20100207288 | METHOD FOR AUTOMATICALLY PRODUCING A CONGLOMERATE STRUCTURE AND APPARATUS THEREFOR - A method and an apparatus for automatically making conglomerated structures ( | 2010-08-19 |
| 20100207293 | PROCESS OF PRODUCING POLYIMIDE FILM AND POLYAMIC ACID SOLUTION COMPOSITION - A process of producing a polyimide film including applying a polyamic acid solution composition to a substrate to form a coating layer and heating the coating layer, wherein the polyamic acid solution composition contains a mixed solvent system of at least two solvents selected from N-methyl-2-pyrrolidone, N-ethyl-2-pyrrolidone, and 1,3-dimethyl-2-imidazolidinone, each solvent being present in a proportion ranging from 7% to 93% based on the total mixed solvent system, and a polyamic acid composed mainly of s-BPDA and PPD. The process enables a film with a thickness exceeding 40 μm to be formed without involving bubble formation. | 2010-08-19 |
| 20100207294 | MULTI-WALLED GELASTIC MATERIAL - The present invention is directed to a gelastic cushion. The gelastic cushion is made from a conventional gelastic composition. The gelastic cushion has a structure having a first wall that defines an opening area and buckles when a force is applied to the first wall. When the first wall buckles a predetermined amount, a second wall, interconnected to the first wall, also buckles. The second wall decreases the chance that the first wall bottoms out. Bottoming out increases the pressure on the patient (a.k.a., the force) overlying the gelastic cushion. That increased pressure is undesirable. | 2010-08-19 |
| 20100207299 | METHODS OF FABRICATING STRUCTURAL ELEMENTS - A method of fabricating structural elements on the surface of a component is provided. The structural elements are configured to modify flow of a fluid passing over the surface. Conveniently, the fabrication is performed using a Direct Write technique. A three dimensional element is formed by depositing material on the surface, and subsequently curing the deposited material. | 2010-08-19 |
| 20100207300 | MOULDING OF ARTICLES - A moulding machine for paper fibre articles has a mould ( | 2010-08-19 |
| 20100207301 | METHOD OF FORMING FINE CHANNEL USING ELECTROSTATIC ATTRACTION AND METHOD OF FORMING FINE STRUCTURE USING THE SAME - A method of forming micro/nano channels and a method of forming micro/nano structures are provided which can easily form micro- and nano-sized channels and structures through simple processes. UV curable polymer patterns are formed on a first substrate, and the UV curable polymer patterns and a second substrate are sealed together by an electrostatic attraction. Then, a channel is formed by irradiating UV light. Also, after reversibly sealing the polymer patterns and a third substrate, prepolymer patterns are formed on the third substrate by flowing prepolymer. Then, the third is removed to form a fine structure. The nano-sized channels as well as the micro-sized channels can be formed through the substantially equal processes. Also, the reversible sealing or the irreversible sealing can be freely selected according to the coating of the curable polymer and UV irradiation time. | 2010-08-19 |
| 20100207302 | STAMPER MOLDING DIE AND METHOD FOR MOLDING STAMPER USING THE SAME - According to one embodiment, in a die for manufacturing a resin stamper, the following are defined the sizes of a resin injection hole and a cut punch receiving portion of a fixed-side template, areas in which a vacuum suction hole and an air-blow hole, respectively, are formed, the diameter of a cut punch on a moving-side template, and the taper angle of the peripheral portion of a cavity. | 2010-08-19 |
| 20100207303 | PROCESS FOR THE PRODUCTION OF FIBERS - A process is provided for producing fibers which includes forming a plurality of bubbles on the surface of a fiber spinning solution, applying a voltage between the solution and a counter-electrode spaced apart therefrom to cause jets to extend from the bubbles to the counter-electrode, and treating the solution with a surfactant to stabilize the bubbles. | 2010-08-19 |
| 20100207304 | APPARATUS FOR FORMING FLANGES ON COMPONENTS - An apparatus for forming a flange on a component is provided. The apparatus comprises a mold disposed for placement of the component thereon, a forming element configured to hold the component on the mold to facilitate formation of the flange, and a pressure element configured to cooperate with the mold to define a space therebetween. The apparatus further comprises a bladder disposed in the space and configured to impart a forming force to a portion of the component to form the flange on the component when the bladder is inflated. A method for forming a flange on a component is also presented. | 2010-08-19 |
| 20100207305 | System for cooling shape-rolled rails - A system for cooling a hot rail of rail steel to a fine perlitic or ferritic or perlitic/ferritic structure has a plurality of separate cooling modules with independently adjustable cooling parameters. The rail is guided downstream through the modules of the cooling stretch and through intermediate zones between the modules so as to cool the surface of the rail in each of the modules and to subject the rail to destressing or stress relief between the modules. Sensors in each of the intermediate zones detect the actual surface temperature of the rail in the respective zones, and a controller connected to the modules and to the sensors varies the cooling parameters of the cooling modules in dependence on the detected temperatures in the respective upstream zones to ensure a defined temperature in the rail that lies above a critical temperature at which bainitic structure components are formed. | 2010-08-19 |
| 20100207306 | TEMPERATURE MEASURING DEVICE - A temperature measuring device for molten metal includes a porous plug with a first end and an opposed second end, an outer protective sheath with a closed end, an inner protective tube with a closed end, and a thermocouple arranged within an interior of the inner protective tube. The outer protective sheath extends away from the first end of the plug and the inner protective tube is arranged within an interior of the outer protective sheath. The porous plug comprises a substantially refractory material and the outer protective sheath consists essentially of substantially refractory metal oxide and graphite. A junction of the thermocouple is proximate to the closed end of the inner protective tube. | 2010-08-19 |
