33rd week of 2022 patent applcation highlights part 68 |
Patent application number | Title | Published |
20220263472 | LOW POWER RECEIVER AND RELATED CIRCUITS - Low power radio frequency (RF) receivers and related circuits are described. | 2022-08-18 |
20220263473 | METHOD FOR CONTROLLING A DRIVER CIRCUIT, DRIVER CIRCUIT, SYSTEM COMPRISING A DRIVER CIRCUIT AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - The invention relates to a method for controlling a driver circuit. The method comprises operating an amplifier for providing an output signal, for example an electronic signal for driving or controlling a load, for example a voltage or a current, based on a control signal. The method further comprises operating a comparator for providing the control signal by comparing an input signal, for example an electronic signal with a lower level or a lower amplitude than the output signal, to a feedback signal, wherein the feedback signal is based on the output signal. The method further comprises providing a first supply voltage to the comparator, and providing a second supply voltage to the amplifier, wherein the second supply voltage is higher than the first supply voltage. | 2022-08-18 |
20220263474 | POWER AMPLIFIER SYSTEM - A power amplifier system having a carrier amplifier having a first supply node, a peaking amplifier having a second supply node, and envelope tracking (ET) circuitry is disclosed. The ET circuitry has a first tracking amplifier that generates a first voltage signal at the first supply node, a second tracking amplifier that generates a second voltage signal at the second supply node, and a transistor coupled between the first supply node and the second supply node. A control circuit has a first input coupled to an output of both or either of the first tracking amplifier and the second tracking amplifier and a control output terminal coupled to a control input terminal of the transistor, wherein the control circuit is configured to progressively turn on the transistor to pass current from the first supply node to the second supply node as the peaking amplifier progressively becomes active. | 2022-08-18 |
20220263475 | METHOD FOR ENHANCING POWER AMPLIFIER EFFICIENCY AND LINEARITY AND POWER AMPLIFIER - A method for power amplification uses circuitry including a main amplifier and an auxiliary amplifier that are constructed and operate such that an input is applied to the main and auxiliary amplifiers via an input network. At low power levels, the auxiliary amplifier is off and the main amplifier sees a large impedance. At maximum power level, both the auxiliary and main amplifiers operate at full power and there is a constant phase shift between them. While transitioning from low to maximum power, systematic AM-AM and AM-PM variations generated due to the phase shift provided by the input network, bias differences between the main and auxiliary amplifiers, and nature of the output combiner to compensate device related distortions. | 2022-08-18 |
20220263476 | CASCODE COMMON SOURCE TRANSIMPEDANCE AMPLIFIERS FOR ANALYTE MONITORING SYSTEMS - A biosensor for an analyte monitoring system. In one embodiment, the biosensor includes a cascode common source transimpedance amplifier circuit, an analog to digital converter, and an output circuit. The cascode common source transimpedance amplifier circuit is configured to receive an electrical current generated by an electrochemical reaction of an analyte on a test strip. The cascode common source transimpedance amplifier circuit is also configured to convert the electrical current to an analog voltage signal. The analog to digital converter is configured to convert the analog voltage signal to a digital voltage signal. The output circuit is configured to transmit a signal indicating a measured level of the analyte based on the digital voltage signal. | 2022-08-18 |
20220263477 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit includes a first transistor having the base coupled to an input terminal, the collector coupled to an output terminal, and the emitter coupled to ground, a first bias circuit coupled to the base of the first transistor via the first resistance element, a second transistor having the base coupled to the input terminal, the collector coupled to the output terminal, and the emitter coupled to ground, a second bias circuit coupled to the base of the second transistor via the second resistance element, and a first impedance circuit having a first end coupled between the base of the first transistor and the input terminal and a second end coupled between the first bias circuit and the first resistance element and being configured to be opened for a direct-current component and to be closed for an alternating-current component. | 2022-08-18 |
20220263478 | MAXIMUM POWER DETECTION AND AUTOMATIC GAIN CONTROL FOR CAPACITIVE CLASS-D AMPLIFIERS - A system includes a charge pump having an input coupled to a first voltage and an output at a second voltage, the second voltage greater than the first voltage. The system also includes an amplifier having a first input, a second input, and a third input, the first input coupled to the output of the charge pump, the second input coupled to the first voltage, the third input coupled to an input signal, the amplifier having an amplified output signal. The system also includes a maximum power detector coupled to the amplifier, the maximum power detector operable to determine whether the amplified output signal has reached a threshold output level and to reduce a power of the amplified output signal responsive to the determination. | 2022-08-18 |
20220263479 | HIGH GAIN-BANDWIDTH PRODUCT (GBW) AMPLIFIER WITH PASSIVE FEEDFORWARD COMPENSATION - Certain aspects of the present disclosure provide methods and apparatus for amplifying an input signal. One example apparatus is a differential amplifier that includes a positive input node, a negative input node, a positive output node, a negative output node, a positive input transistor having a gate coupled to the positive input node and having a drain coupled to the negative output node, a negative input transistor having a gate coupled to the negative input node and having a drain coupled to the positive output node, a first common-gate amplifier having an output coupled to the negative output node, a second common-gate amplifier having an output coupled to the positive output node, a first capacitive element coupled between the negative input node and an input of the first common-gate amplifier, and a second capacitive element coupled between the positive input node and an input of the second common-gate amplifier. | 2022-08-18 |
20220263480 | OPERATIONAL AMPLIFIER USING SINGLE-STAGE AMPLIFIER WITH SLEW-RATE ENHANCEMENT AND ASSOCIATED METHOD - An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier. | 2022-08-18 |
20220263481 | MULTI-STAGE AMPLIFIER CIRCUITS AND METHODS - A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes. | 2022-08-18 |
20220263482 | RF AMPLIFIERS HAVING SHIELDED TRANSMISSION LINE STRUCTURES - RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure. | 2022-08-18 |
20220263483 | CRYOGENIC PARAMETRIC AMPLIFIER CONTROL APPARATUS - A cryogenic parametric amplifier control apparatus is disclosed. Methods of implementation and devices incorporated within the whole of the apparatus are disclosed. Methods of reducing the number of signal lines necessary to control a parametric amplifier are disclosed. Schema allowing for control of multiple parametric amplifiers with a single apparatus are disclosed. | 2022-08-18 |
20220263484 | PIEZOELECTRIC ACOUSTIC RESONATOR WITH IMPROVED TCF MANUFACTURED WITH PIEZOELECTRIC THIN FILM TRANSFER PROCESS - A method and structure for a transfer process for an acoustic resonator device. In an example, a bulk acoustic wave resonator (BAWR) with an air reflection cavity is formed. A piezoelectric thin film is grown on a crystalline substrate. Patterned electrodes are deposited on the surface of the piezoelectric film. An etched sacrificial layer is deposited over the electrodes and a planarized support layer is deposited over the sacrificial layer. The device can include temperature compensation layers (TCL) that improve the device TCF. These layers can be thin layers of oxide type materials and can be configured between the top electrode and the piezoelectric layer, between the bottom electrode and the piezoelectric layer, between two or more piezoelectric layers, and any combination thereof. In an example, the TCLs can be configured from thick passivation layers overlying the top electrode and/or underlying the bottom electrode. | 2022-08-18 |
20220263485 | BANDPASS FILTER CIRCUIT AND MULTIPLEXER - Provided by a bandpass filter circuit and a multiplexer. The bandpass filter circuit includes at least one electromagnetic LC filter circuit and at least one acoustic wave resonance unit. The at least one acoustic wave resonance unit includes an input port, an output port, at least one circuit element and at least three resonators. The at least one electromagnetic LC filter circuit is electrically connected to the at least one acoustic wave resonance unit, and the at least three resonators include at least one first resonator and at least one second resonator. In a case where the at least one first resonator includes one first resonator, the first resonator is connected in series between the input port and the output port. | 2022-08-18 |
20220263486 | ELECTROMAGNETIC INTERFERENCE FILTER HAVING CONTROLLED IMPEDANCE MAGNITUDE - Electromagnetic interference filter for suppressing interferences in DC network, the network comprising a source device powering a load device via a bus connectable to the source device at an input side and to the load device at an output side. | 2022-08-18 |
20220263487 | PIEZOELECTRIC DEVICE AND MANUFACTURING METHOD OF THE SAME - A piezoelectric device includes a conductive adhesive, a container, and an AT-cut crystal element. The AT-cut crystal element has at least one side surface intersecting with a Z′-axis of the crystallographic axis of the crystal constituted of three surfaces. When a dimension of a straight-line portion along the Z′-axis of a second side opposed to the first side is expressed as W | 2022-08-18 |
20220263488 | BAW RESONATOR WITH REDUCED LATERAL MODES - A BAW resonator (RN) with reduced lateral modes is provided. The resonator has an active stack of bottom electrode (BE), piezoelectric material (PM) and top electrode (TE) and at least one element of this active stack has a curved side wall (CSW). Two or more curved side walls may be arranged on spheres, on cylinders or prisms with an elliptical footprint with different radii. | 2022-08-18 |
20220263489 | ELECTRODE-DEFINED UNSUSPENDED ACOUSTIC RESONATOR - A bulk acoustic resonator operable in a bulk acoustic mode includes a resonator body mounted to a separate carrier that is not part of the resonator body. The resonator body includes a piezoelectric layer, a device layer, and a top conductive layer on the piezoelectric layer opposite the device layer. The piezoelectric layer is a single crystal of LiNbO | 2022-08-18 |
20220263490 | SYMMETRIC TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH REDUCED SPURIOUS MODES - Acoustic resonators and filters are disclosed. An acoustic resonator includes a substrate and a piezoelectric plate. A back surface of the piezoelectric plate is attached to the substrate except for a portion of the piezoelectric plate forming a diaphragm spanning a cavity in the substrate. A conductor pattern including an interdigital transducer (IDT) is formed on a front surface of the piezoelectric plate, interleaved fingers of the IDT disposed on the diaphragm. A front-side dielectric layer is formed on the front surface of the piezoelectric plate between, but not over, the IDT fingers. A back-side dielectric layer is formed on a back surface of the diaphragm. Thicknesses of the IDT fingers and the front-side dielectric layer are substantially equal. An acoustic impedance Zm of the IDT fingers and an acoustic impedance Zfd of the front-side dielectric layer satisfy the relationship 0.8Zm≤Zfd≤1.25Zm. | 2022-08-18 |
20220263491 | ACOUSTIC WAVE DEVICE AND COMMUNICATION APPARATUS - An acoustic wave device includes a substrate, a multilayer film disposed on the substrate, a piezoelectric film disposed on the multilayer film, and a first excitation electrode and a second excitation electrode disposed on the piezoelectric film. The first excitation electrode has a plurality of first electrode fingers arranged with a first pitch p1 in a propagation direction of an acoustic wave. The second excitation electrode has a plurality of second electrode fingers arranged with a second pitch p2 in the propagation direction. The piezoelectric film is formed of a single crystal of LiTaO | 2022-08-18 |
20220263492 | TUNING FORK-TYPE VIBRATING REED, TUNING FORK-TYPE VIBRATOR AND MANUFACTURING METHOD THEREFOR - When a thick frequency adjustment metal film of a tuning fork-type vibration piece is irradiated with a beam on a wafer for frequency coarse adjustment, projections are possibly formed on a roughened end of the frequency adjustment metal film. Such projections are pressurized and pushed down not to chip off under any impact, so that the risk of frequency fluctuations is suppressed. | 2022-08-18 |
20220263493 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes a supporting substrate, a piezoelectric layer, and an IDT electrode. The piezoelectric layer is on the supporting substrate. The IDT electrode is on the piezoelectric layer. The supporting substrate is a silicon carbide substrate, which has a hexagonal crystal structure. The acoustic wave device uses an SH wave as a main mode. | 2022-08-18 |
20220263494 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH NARROW GAPS BETWEEN BUSBARS AND ENDS OF INTERDIGITAL TRANSDUCER FINGERS - An acoustic resonator has a piezoelectric plate attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm spanning a cavity in the substrate. An interdigital transducer (IDT) formed on the plate has interleaved fingers on the diaphragm with first parallel fingers extending from a first busbar and second parallel fingers extending from a second busbar of the IDT. A distance between the interleaved fingers defines an IDT pitch. The IDT has a gap distance between the ends of the first plurality of parallel fingers and the second busbar, and between the ends of the second plurality of parallel fingers and the first busbar; and the gap distance is less than ⅔ times the IDT pitch. | 2022-08-18 |
20220263495 | ACOUSTIC WAVE DEVICE WITH OVERTONE MODE - Aspects of this disclosure relate to an acoustic wave device having an overtone mode as a main mode. The acoustic wave device is sufficiently asymmetric on opposing sides of a piezoelectric layer over an acoustic reflector such that the main mode of the acoustic wave device is the overtone mode. | 2022-08-18 |
20220263496 | MULTISTAGE ACTIVE FILTER FOR AUTOMOTIVE APPLICATIONS - An active filter for suppressing an unwanted noise component from an electric supply line connecting a noise source and a load device, the active filter comprising a first active stage and a second active stage on the supply line, wherein the first active stage is between the noise source and the second active stage, wherein the first active stage has a first attenuation, and the second active stage has a second attenuation, characterized in that the first attenuation is lower than the second attenuation. | 2022-08-18 |
20220263497 | HIGH-FREQUENCY SEMICONDUCTOR DEVICE - The present invention relates to a high-frequency semiconductor device. A conventional high-frequency semiconductor device including an input second-order harmonic matching circuit has such a problem that gain decrease occurs. In a high-frequency semiconductor device ( | 2022-08-18 |
20220263498 | CIRCUIT AND ELECTRONIC DEVICE - A circuit, including a synchronizer register and a level shifter. The synchronizer register is electrically connected to the level shifter, the level shifter is powered by a dual-rail power supply, and a high-voltage power supply in the dual-rail power supply supplies power to the synchronizer register. A metastable state elimination capability of the synchronizer register can be improved by using the circuit. | 2022-08-18 |
20220263499 | SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD - The disclosure relates to a scan chain circuit comprising cascaded flip-flops having a functional input node and a test input node configured to be selectively coupled to logic circuitry at a clock edge time. A clock line is provided configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have active clock edges applied thereto at respective clock edge times. The chain of flip-flops comprise a set of flip-flops configured to receive an edge inversion signal and to selectively invert their active clock edges in response to the edge inversion signal being asserted. | 2022-08-18 |
20220263500 | Glitch Filter System - One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state. | 2022-08-18 |
20220263501 | DYNAMIC BALANCING OF TRANSISTORS - The present disclosure provides a cascode switching element comprising two or more electronic switching devices connected in series. The devices having an input terminal, an output terminal, and a control terminal that operates between a closed N state and an open state. The cascode switching element also includes a voltage balancing circuit connected to the at least two electronic switching devices and operative to limit cause the two or more electronic switching devices to share a line voltage across the switching element when in an open state in a manner that a nominal maximum voltage across a first one of the switching devices is not exceeded when said line voltage exceeds said nominal maximum voltage with a remaining portion of said line voltage being present across a remainder of said at least two electronic switching devices. | 2022-08-18 |
20220263502 | DC OUTPUT SOLID STATECONTACTOR ASSEMBLY - In one embodiment, there is provided a DC output solid contactor assembly having a housing enclosure and a cavity within the enclosure; one or more SOT-227 isolated semiconductor modules and its variants in a stand-alone, parallel or series configuration; a novel drive circuit board mounted on at least one of the modules with input power terminals for coupling to an input control source; and gate impulse output terminals coupling to one or more semiconductor's gate electrodes. The drive circuit includes a voltage priming system that converts input control signal to an isolated and optimal gate driving voltage level; and positive and negative output power terminals for coupling to the electrical load side. | 2022-08-18 |
20220263503 | SUPPLY VOLTAGE DETECTING CIRCUIT AND CIRCUIT SYSTEM USING THE SAME - A supply voltage detecting circuit has a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives and detects a supply voltage and is used to detect to generate a low-voltage detection signal. When the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and a transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is higher than or equal to the set level, the low voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a constant current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the constant current. | 2022-08-18 |
20220263504 | CURRENT DRIVING CIRCUIT - The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturation region; and a control unit for controlling the field effect transistor to operate in the saturation region, by activating the current supply source, if the field effect transistor operates in a region lower than a threshold voltage. | 2022-08-18 |
20220263505 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor base body including: a p-type substrate; and an n-type first semiconductor layer; a first electrode; a second electrode; an isolation film; an insulation film; and a third electrode disposed over the insulation film. The first electrode is electrically connected to a first circuit C | 2022-08-18 |
20220263506 | RADIO FREQUENCY COMMUNICATION SYSTEM AND RADIO FREQUENCY SWITCH THEREOF - Disclosed is a radio frequency switch and its radio frequency communication system. The RF switch comprises: N switch transistors Q | 2022-08-18 |
20220263507 | SEMICONDUCTOR APPARATUS PERFORMING CALIBRATION OPERATION AND A SEMICONDUCTOR SYSTEM USING THE SEMICONDUCTOR APPARATUS - A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver. | 2022-08-18 |
20220263508 | THRESHOLD LOGIC GATES USING FLASH TRANSISTORS - Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm. | 2022-08-18 |
20220263509 | SYSTEM AND METHOD FOR SELECTING AN OPERATING MODE, SUCH AS A BOOT MODE, OF A MICRO-CONTROLLER UNIT - A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values. | 2022-08-18 |
20220263510 | STACKED INTEGRATED PLATFORM ARCHITECTURE - A system comprising (1) a microelectrode array (MEA) component comprising an integrated multiplexed (MUX) logic circuit; and (2) a microprocessor, e.g., MOSFET, such as a CMOS, wherein the MEA is in electrical communication with the microprocessor such that signals produced by the microelectrodes are transmitted to the processor through the MUX. The use of a MUX reduces the number of outputs used to communicate signals from multiple microelectrodes to the microprocessor. The two components are removably engageable with each other such that after one or more uses, the engaged MEA can be removed and replaced with a new MEA, without the necessity of disposing the microprocessor. | 2022-08-18 |
20220263511 | DATA MUTEX FILTER CIRCUIT AND DATA MUTEX FILTERING METHOD - The present disclosure provides a data mutex filter circuit and a data mutex filtering method. The data mutex filter circuit has a main input terminal and a main output terminal and including a preprocessing sub-circuit and a 1st-stage filter sub-circuit to an Nth-stage filter sub-circuit which are cascaded, N being an integer greater than or equal to 2. The 1st-stage filter sub-circuit has an input terminal coupled to the preprocessing sub-circuit, and the Nth-stage filter sub-circuit has an output terminal coupled to the main output terminal. Each stage of filter sub-circuit is configured to compare whether input data currently received at the main input terminal is the same as history data stored therein, and feed back a comparison result to the preprocessing sub-circuit; the preprocessing sub-circuit outputs corresponding data to the 1st-stage filter sub-circuit according to the comparison result fed back by each stage of filter sub-circuit. | 2022-08-18 |
20220263512 | ANALOG PHASE LOCKED LOOP - An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage. | 2022-08-18 |
20220263513 | PHASE CORRECTING DEVICE, DISTANCE MEASURING DEVICE, PHASE FLUCTUATION DETECTING DEVICE AND PHASE CORRECTION METHOD - A phase correcting device includes a local oscillator configured to give a local oscillation signal to a device configured to detect a phase of an inputted signal, a first phase detector configured to detect a phase of the local oscillation signal to output the phase of the local oscillation signal, a reference phase device configured to generate a quasi-reference phase corresponding to a reference phase of the local oscillation signal at a time of an initial setting of the local oscillator to output the quasi-reference phase, based on a reference clock, a second phase detector configured to detect, a fluctuation amount of a phase of the local oscillator, based on the phase detected by the first phase detector and the quasi-reference phase, and a correction circuit configured to correct the phase of the inputted signal by using a detection result of the second phase detector. | 2022-08-18 |
20220263514 | FIRMWARE-BASED INTERLEAVED-ADC GAIN CALIBRATION AND HARDWARE-THRESHOLDING ENHANCEMENTS - The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started. | 2022-08-18 |
20220263515 | CIRCUIT FOR CONVERTING A SIGNAL BETWEEN DIGITAL AND ANALOG - An electronic circuit for converting a signal between digital and analog in a burst mode, including a processor configured to utilize a synchronizing clock signal, a converter configured to convert a signal data between digital and analog using a converter clock signal, a phase comparator configured to determine a phase relationship between the synchronizing clock signal and the converter clock signal, and a digital signal processor coupled to the phase comparator and configured to receive an information about the phase relationship, wherein the digital signal processor is configured to apply a delay to the signal data being exchanged between the processor and. The synchronizing clock signal and the converter clock signal have a predetermined frequency relationship. | 2022-08-18 |
20220263516 | MEASUREMENT UNIT CONFIGURED TO PROVIDE A MEASUREMENT RESULT VALUE USING CALCULATED VALUES - A measurement unit comprising a converter unit and a processing unit and configured to provide a measurement result value, based on a first input signal. The converter unit is configured to provide first digital, quantized values based on the first input signal. The measurement unit is further configured to calculate second values, which represents a reference quantity or a reference value, for a plurality of quantization step sizes associated with different values of the control signal. The measurement unit is configured to change the control signal of the converter unit between determination of different first values and/or a determination of the different second values, such that different first values and/or different second values are provided using different converter quantization step sizes. The processing unit is configured to provide a measurement result value from a predefined number of first values and a predefined number of second values. | 2022-08-18 |
20220263517 | MEASUREMENT UNIT CONFIGURED TO PROVIDE A MEASUREMENT RESULT VALUE - A measurement unit comprising a converter unit and a processing unit is configured to provide a measurement result value, based on a first input signal and a second input signal. | 2022-08-18 |
20220263518 | CONTROL DEVICE, SWITCHING CONVERTER AND METHOD FOR CONTROLLING AN OUTPUT VARIABLE - A digital closed loop control system. An output signal is detected with the aid of an analog-to-digital converter. A correction value is subtracted from the output signal prior to the analog-to-digital conversion and this correction value is added up again after the analog-to-digital conversion. The correction value in this case may be dynamically adapted. In this way, the analog-to-digital converter may be operated in a narrow conversion range. | 2022-08-18 |
20220263519 | SIGMA-DELTA MODULATOR WITH RESIDUE CONVERTER FOR LOW-OFFSET MEASUREMENT SYSTEM - A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal. | 2022-08-18 |
20220263520 | SYSTEM-LEVEL CHOPPING IN COULOMB COUNTER CIRCUIT - A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity, the sensor readout channel comprising an analog-to-digital converter (ADC) having an input and an output, first outside chopping switches located at the input of the ADC, and second outside chopping switches located at the output of the ADC. The ADC may comprise a memory element, first inside chopping switches located at the input of the memory element, and second inside chopping switches located at the output of the memory element. The first outside chopping switches, the second outside chopping switches, the first inside chopping switches, and the second inside chopping switches may be switched at the same frequency such that the memory element is swapped periodically in synchronization with the first outside chopping switches and second outside chopping switches. | 2022-08-18 |
20220263521 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. | 2022-08-18 |
20220263522 | OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING AND RATE (DE-)MATCHING FOR 3GPP NEW RADIO - Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory. | 2022-08-18 |
20220263523 | PARALLEL BIT INTERLEAVER - A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. | 2022-08-18 |
20220263524 | ELECTRONIC DEVICE - Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network. | 2022-08-18 |
20220263525 | COMPUTATIONAL MEMORY WITH ZERO DISABLE AND ERROR DETECTION - A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected. | 2022-08-18 |
20220263526 | CIRCUIT ARRANGEMENT FOR TRANSMITTING RADIO SIGNALS AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT - The invention relates to a circuit arrangement and a method for operating a circuit arrangement for transmitting up-link and downlink signals between a terminal ( | 2022-08-18 |
20220263527 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes a module board, a transmission power amplifier, a first inductance element mounted on a first principal surface and connected to an output terminal of the transmission power amplifier, a reception low-noise amplifier, and a second inductance element mounted on a first principal surface connected to an input terminal of the reception low-noise amplifier. In a plan view of the module board, a conductive member mounted on the first principal surface is disposed between the first inductance element and the second inductance element. | 2022-08-18 |
20220263528 | Universal Notch Filter - Systems, methods, and computer program product embodiments are disclosed for removing any fixed frequency interfering signal from an input signal without introducing artifacts that are not part of the original signal of interest. An embodiment operates by using a virtual buffer with a length that matches a length of one cycle of an interfering signal. The embodiment extracts the interfering signal into the virtual buffer. For a sample in the next cycle of the interfering signal that corresponds to a virtual memory location for the virtual buffer, the embodiment can update one or more physical memory locations of the virtual buffer that are in the vicinity of the virtual memory location. This use of virtual buffer can remove any interfering signal without creating the artifacts associated with conventional notch filters. | 2022-08-18 |
20220263529 | Maximizing Efficiency of Communication Systems with Self-Interference Cancellation Subsystems - A wireless communication device can include a transmitter subsystem configured to transmit a transmit signal that, once propagated from the wireless communication device, may be reflected back and received by a receiver subsystem as interference. The wireless communication device can include a self-interference cancellation subsystem configured to generate a cancellation signal to mix with received signals to mitigate self-interference effects. A performance floor for the self-interference cancellation subsystem may be determined based on a phase noise profile of an oscillator of either or both the transmitter subsystem or the receiver subsystem. The performance floor metric can be thereafter used to inform an operation or operational setting of the wireless communication device. | 2022-08-18 |
20220263530 | TUNER IC - The present technology relates to a tuner IC capable of reducing the cost of a demodulation LSI. | 2022-08-18 |
20220263531 | ANTENNA DEVICE AND METHOD FOR CONFIGURING THE SAME - An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device. | 2022-08-18 |
20220263532 | PROTECTIVE CASE FOR ELECTRONIC DEVICE - A protective case for a mobile electronic device is disclosed herein. The protective case includes a front portion and a back portion that is configured to slide into a side of the front portion to effectuate the sealing and closure of the case. The front portion is configured to cover the front face and sides of the device and includes rails or protrusions on opposing sides of its internal surface. The back portion is configured to cover the back side of the device and includes channels on opposing sides that are configured to be slid along the rails on the opposing sides of the internal surface of the front component arid thereby open and close the case. The protective case is configured to be reversibly attached to a stand that facilitates multiple viewing/operating positions. | 2022-08-18 |
20220263533 | HIGH FREQUENCY MODULE AND COMMUNICATION APPARATUS - A power amplifier is capable of operating in a first power mode and a second power mode with a gain lower than a gain of the first power mode. The power amplifier is connected to a first common terminal of the first switch. Two or more filters are connected to two or more first selection terminals other than at least one first selection terminal among three or more first selection terminals of the first switch. The at least one first selection terminal of the first switch and at least one second selection terminal of a second switch are connected. The first switch is capable of switching between a first path passing through at least one of the two or more filters and a second path not passing through any of the two or more filters but passing through the at least one first selection terminal. | 2022-08-18 |
20220263534 | RADIO-FREQUENCY CIRCUIT, RADIO-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION APPARATUS - In a radio-frequency circuit, a first switch is connected to an antenna terminal. A second switch is connected to the antenna terminal via the first switch. A first filter is an acoustic wave filter that is connected to the first switch via the second switch and that allows a radio-frequency signal of a first communication band to pass through the first filter. A second filter is an acoustic wave filter that is connected to the first switch without necessarily having the second switch interposed therebetween and that allows a radio-frequency signal of a second communication band to pass through the second filter. The second communication band is higher than the first communication band. The radio-frequency circuit further includes a capacitor. The capacitor is connected in series with the first switch and the second switch between the first switch and the second switch. | 2022-08-18 |
20220263535 | RADIO-FREQUENCY CIRCUIT, RADIO-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION APPARATUS - In a radio-frequency circuit, a first switch is connected to an antenna terminal. A second switch is connected to the first switch and is connected to the antenna terminal via the first switch. A first filter is connected to the first switch without having the second switch interposed therebetween and allows a radio-frequency signal of a first communication band to pass through the first filter. A second filter is connected to the first switch via the second switch and allows a radio-frequency signal of a second communication band to pass through the second filter. The second communication band is higher than the first communication band. The radio-frequency circuit further includes an inductor. The inductor is not connected in series with the first filter and is connected in series with the first switch and the second switch between the first switch and the second switch. | 2022-08-18 |
20220263536 | HYBRID HIGH-SPEED AND HIGH-PERFORMANCE SWITCH SYSTEM - One example includes a switch system. The system includes a first signal port and a second signal port. The system also includes a first switching path arranged between the first and second signal ports. The first switching path includes at least one first switch and at least one of the at least one first switch being configured as a high-speed switching device. The system further includes a second switching path arranged between the first and second signal ports in parallel with the first switching path. The second switching path includes at least one second switch and at least one of the at least one second switch being configured as a high-performance switching device. | 2022-08-18 |
20220263537 | CLOCK AND DATA RECOVERY CIRCUIT - Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle. | 2022-08-18 |
20220263538 | MULTI-RADIO SYNCHRONIZATION WITHIN A SINGLE CONNECTED SYSTEM - A multi-radio border router for synchronizing communications of multiple border router radios is provided. For example, the border router includes a border router component connected to each of the plurality of border router radios. The border router component configured for selecting one of the plurality of border router radios as a master radio and assigning channel offset parameters for each of the plurality of border router radios. The master radio is configured for broadcasting synchronization beacons based on which the non-master radios synchronize their respective clocks with that of the master radio. After the synchronization, each of the border router radios communicates with endpoints associated therewith according to a channel hopping pattern modified by applying a channel offset determined based on the channel offset parameters assigned to the respective radio. | 2022-08-18 |
20220263539 | BEAM FAILURE RECOVERY DETERMINING METHOD, TERMINAL DEVICE, AND STORAGE MEDIUM - A method for determining beam failure recovery, a terminal device, and a non-transitory computer-readable storage medium are provided. The method includes in a case of a beam failure, initiating a contention-based random access process triggered for beam failure recovery. The method further includes receiving a downlink response message and determining that the beam failure recovery is completed. The downlink response message is a response message corresponding to the random access process. | 2022-08-18 |
20220263540 | ADAPTIVE CABLE EQUALIZER - A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver. | 2022-08-18 |
20220263541 | METHOD OF OPERATING A COMMUNICATION NETWORK, CORRESPONDING COMMUNICATION NETWORK AND DEVICES - A communication network comprises a plurality of electronic devices coupled via a plurality of communication links. The communication links comprise links over a first physical medium and links over a second physical medium. A method of operating the network comprises issuing, at an originator device, a path request message directed towards a destination device, transmitting the path request message from the originator device to the destination device through a first set of intermediate devices via a forward sequence of links, issuing, at the destination device, a path reply message directed towards the originator device, and transmitting the path reply message from the destination device to the originator device through a second set of intermediate devices via a reverse sequence of links. | 2022-08-18 |
20220263542 | SYSTEM AND METHOD FOR MANAGING COMMUNICATION BETWEEN CONTACTLESS DEVICES - The disclosure relates to a modified NFC framing is used by a reader and selected devices during at least a part of the communication between the reader and the selected devices. The reader and the selected devices store modification rules for modifying the frames. Devices not storing those modification rules will discard the received modified frames. | 2022-08-18 |
20220263543 | METHOD AND APPARATUS FOR FEEDING BACK LAYER INFORMATION, METHOD AND APPARATUS FOR RECEIVING LAYER INFORMATION, COMMUNICATION NODE AND MEDIUM - Provided are a method and apparatus for feeding back layer information, a method and apparatus for receiving layer information, a communication node and a medium. The method for feeding back layer information includes: receiving configuration information of a first communication node; determining layer information of the first communication node according to the configuration information; and feeding back the layer information to the first communication node. | 2022-08-18 |
20220263544 | NEURAL NETWORK BASED NONLINEAR MU-MIMO PRECODING - A base station may apply a nonlinear precoding to data for MU-MIMO transmission to a set of paired UEs to generate a first set of precoder symbols, and apply a linear precoding to the first set of precoder symbols to generate a second set of precoder symbols using a linear precoding matrix. The base station may normalize the second set of precoder symbols, and scale the second set of precoder symbols, before transmission of the data, using a scaling factor based on one or more of modulation symbols or a channel matrix. The base station may apply the linear precoding to DMRS associated with the data. The base station may transmit the second set of precoder symbols based on the second set of precoder symbols and the DMRS to the set of paired UEs. | 2022-08-18 |
20220263545 | Method and Network Element for User Equipment Scheduling - The present disclosure proposes a method, a network element, and a non-transitory computer readable storage medium for scheduling a user equipment (UE) for transmission. The method comprises: determining, for the UE, a first downlink channel status at a first time point and a second downlink channel status at a second time point which is later than the first time point, respectively, determining, for the UE, a temporal coherence between the first downlink channel status and the second downlink channel status; and scheduling the UE based on the determined temporal coherence. | 2022-08-18 |
20220263546 | UPLINK SINGLE USER MULTIPLE INPUT MULTIPLE OUTPUT (SU-MIMO) PRECODING IN WIRELESS CELLULAR SYSTEMS - A method and network node for single user multiple input multiple output (SU-MEMO) codebook-based precoder selection and for rank adaptation are provided. According to one aspect, a method includes, for each one of a plurality of rank hypotheses: selecting a precoder matrix based on an uplink transmit covariance matrix; and estimating a respective information carrying capacity, ICC, for the rank hypothesis based at least in part on the selected precoder matrix. The method further includes selecting an uplink SU-MIMO precoding matrix based at least in part on the estimated ICC for each rank hypothesis. | 2022-08-18 |
20220263547 | TX MU-MIMO CAPABILITY FOR MCS - A method of communication between a first node and a second node operating in a communications network. The method includes sending, by the first node, to the second node, a first transmission to configure a communication channel between the first node and the second node. The first transmission includes a first frame including a first capability indicator. The first capability indicator indicates a first MU-MIMO capability of a transmitter of the first node. The first multi-user (MU)-MIMO capability includes a first Modulation and Coding Scheme (MCS) processable by the first node or a first number of spatial streams (NSS) processable by the first node. | 2022-08-18 |
20220263548 | DEVICE AND METHOD IN RADIO COMMUNICATION SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM - Provided in the present disclosure are a device and method in a radio communication system, and a computer-readable storage medium. The device comprises a processing circuit configured to: decode a group common physical downlink control channel (group common PDCCH) of a user equipment group comprising a target user equipment so as to acquire control information related to multi-user multiple input multiple output (MU-MIMO) transmission of a control channel; and decode a user equipment-specific physical downlink control channel (UE-specific PDCCH) of the target user equipment on the basis of the control information so as to acquire specific transmission control information related to the target user equipment, where the UE-specific PDCCH of the target user equipment and UE-specific PDCCH of the other user equipment are stacked on a same transmission resource for transmission. MU-MIMO transmission with respect to a downlink control channel is effectively implemented, thus increasing resource utilization rate. | 2022-08-18 |
20220263549 | Antenna Arrangement for Distributed Massive MIMO - An antenna arrangement comprises a body which in turn comprises a plurality of antenna devices, the antenna arrangement being characterized in that the body has a flexible structure and an elongated shape. | 2022-08-18 |
20220263550 | WIRELESS COMMUNICATION DEVICE, WIRELESS COMMUNICATION TERMINAL AND WIRELESS COMMUNICATION METHOD - A wireless communication device includes a receiver and a transmitter. The receiver receives a plurality of first frames each including first information for generation of a trigger frame for uplink multi-user transmission. The transmitter transmits a second frame generated on the basis of the first information included in the plurality of first frames, the second frame being the trigger frame and designating at least one target terminal for the uplink multi-user transmission. Each of the first frames is transmitted by a respective one of terminals, each of which accesses a wireless medium using an access category associated with the first frame under CSMA/CA (Carrier Sense Multiple Access with Carrier Avoidance) to transmit the first frame. The second frame instructs the at least one target terminal to transmit third frames including data in a SIFS (Short Interframe Space) after the second frame is received. | 2022-08-18 |
20220263551 | BASE STATION APPARATUS, TERMINAL APPARATUS, WIRELESS COMMUNICATION SYSTEM AND INTEGRATED CIRCUIT - A base station apparatus is capable of adjusting antenna gains in a horizontal direction and a vertical direction of the plurality of antennas included in the base station apparatus, by adjusting a phase and an amplitude of a signal addressed and transmitted to a terminal apparatus, stores a codebook which is shared with the terminal apparatus and describes a plurality of linear filters associated with antenna gains in the horizontal direction and antenna gains in the vertical direction, acquires control information indicating at least one out of a plurality of linear filters described in the codebook, of which notification is sent from the terminal apparatus, performs precoding on the signal addressed to the terminal apparatus, based on the control information and the first codebook, and transmits the signal subjected to the precoding. | 2022-08-18 |
20220263552 | CODEBOOK SUBSET RESTRICTION (CBSR) ON PER SPATIAL DOMAIN AMPLITUDE - Certain aspects of the present disclosure provide techniques for channel state information (CSI) reporting with frequency domain (FD) compression. More particularly, aspects of the present disclosure provide for codebook subset restriction (CBSR) on per spatial domain (SD) basis amplitude. | 2022-08-18 |
20220263553 | PHYSICAL DOWNLINK SHARED CHANNEL (PDSCH) POWER BACKOFF IN ACTIVE ANTENNA SYSTEMS (AAS) - A method, network node and wireless device to apply power backoff to the physical downlink shared channel (PDSCH) based at least in part on a power backoff value are provided. According to one aspect, a method in a wireless device (WD) includes determining a beamforming gain based at least in part on a difference 5 between a physical downlink shared channel, Determine A Beamforming Gain Of A Physical Downlink PDSCH, received power and a reference signal received power. The method also includes transmitting the determined beamforming gain to a network node. 10 1008949 | 2022-08-18 |
20220263554 | MASSIVE MIMO BEAM DOMAIN ROBUST PRECODING TRANSMISSION METHOD AND SYSTEM - The present invention discloses a massive multiple-input multiple-output (MIMO) beam domain robust precoding transmission method and system. The method is based on base station (BS)-side and user-side refined sampling steering vector matrices, and considers the influence of channel aging caused by mobility, where obtained channel state information is refined beam domain a posteriori statistical channel information including channel mean and variance information. In the present invention, the BS performs robust precoding transmission by using the refined beam domain a posteriori statistical channel information, where a channel model on which the adopted refined beam domain a posteriori statistical channel information depends is a channel model which corresponds to a refined sampling space angle and adopts a steering vector matrix; the used statistical channel information is more sufficient and accurate, so that the problem of universality of massive MIMO to various typical mobile scenarios under the condition that the antenna size is limited can be solved; and high spectral efficiency is achieved, and the provided robust precoding design utilizes the sparsity of a beam domain channel and the structural characteristics of a sampling steering vector matrix, so that the calculation complexity can be greatly reduced. | 2022-08-18 |
20220263555 | STEERING MATRIX DERIVATION - An example method may include obtaining first beamforming feedback from a station based on first sounding signals from a first set of antennas selected from multiple antennas of an access point, and obtaining second beamforming feedback from the station based on second sounding signals from a second set of antennas selected from the multiple antennas of the access point. The method may also include, using the first beamforming feedback and the second beamforming feedback, determining correlational relationships between pairs of the multiple antennas of the access point, and deriving a beamforming steering matrix from the correlational relationships. | 2022-08-18 |
20220263556 | COEFFICIENT REPORTING FOR TYPE II CHANNEL STATE INFORMATION (CSI) - Systems, devices, and techniques associated with coefficients for channel state information (CSI) reports are described. A described technique includes receiving, at a user equipment (UE), a CSI configuration and a codebook configuration, the codebook configuration specifying a codebook; determining a precoding matrix indicator (PMI) that specifies a precoding matrix associated with the codebook, wherein the precoding matrix is based on spatial-domain (SD) vectors and linear combining coefficients; and transmitting CSI report containing the PMI in accordance with the CSI configuration. | 2022-08-18 |
20220263557 | A METHOD OF REPORTING CHANNEL STATE INFORMATION, A COMMUNICATION SYSTEM, AND A METHOD OF SCHEDULING TCI - This present disclosure provides a mechanism to classify CSI report(s) into valid/partially valid/invalid CSI report(s) by defining a new CSI evaluation methodology. The present disclosure also introduces a new UE behaviour of sending different (valid/partially valid/invalid) type of CSI report to inform the gNB about the TCI state known status at the UE. The present disclosure also introduces an implicit or explicit signalling method to inform the type of CSI report to the gNB. The present disclosure also discloses new UE behaviour of skipping CSI reports between partially valid/invalid CSI report and valid CSI report during TCI state switching/SCell activation. | 2022-08-18 |
20220263558 | METHOD AND APPARATUS OF GROUP-BASED BEAM REPORTING - Methods and apparatuses for beam measurement and reporting in a wireless communication system. A method of operating a user equipment (UE) includes identifying an indication for reporting, in a channel state information (CSI) report, at least a first group of two resource indicators and corresponding beam metrics associated with a first entity identity (ID) and a second entity ID, respectively, and transmitting, in the CSI report, the first group of two resource indicators and the corresponding beam metrics. The first or second entity IDs correspond to at least one of: a physical cell identity (PCI) corresponding to a serving cell PCI or a PCI different from the serving cell PCI; and a PCI index pointing to a PCI corresponding to the serving cell PCI or a PCI different from the serving cell PCI in a list of PCIs that are higher layer configured to the UE. | 2022-08-18 |
20220263559 | MULTIPLE-INPUT MULTIPLE-OUTPUT SYSTEM PERFORMANCE USING ADVANCED RECEIVERS FOR 5G OR OTHER NEXT GENERATION NETWORKS - Fast calculation of channel state information using demodulation reference signals (DM-RS) is provided herein. The channel state information can be calculated by estimating the signal to noise ratio of a communication link based on the DM-RS, and then estimating the channel quality indicator based on the SINR. The advanced receivers can use list-based detection methods which the estimated SINR can improve the performance thereof. Channel state information is traditionally calculated based on the channel state reference signals (CS-RS). Demodulation reference signals, which are used for channel estimation for a data channel, are transmitted at different times than CS-RS however, and so some portions of the channel state information including layer indicator (LI) and channel quality indicator (CQI) can be calculated based on the demodulation reference signals, allowing a network to adapt more quickly to changing channel conditions, without having to transmit a CS-RS. | 2022-08-18 |
20220263560 | CHANNEL STATE INFORMATION REPORTING METHOD AND COMMUNICATIONS APPARATUS - This application provides channel state information reporting methods and communications apparatuses. One method includes: generating first indication information and a plurality of groups of second indication information, where the first indication information indicates a plurality of frequency domain component vectors, each group in the plurality of groups of second indication information corresponds to a spatial layer and a plurality of spatial domain component vectors and constructs precoding vectors of the spatial layer in a plurality of frequency bands, and each piece of second indication information in each group corresponds to a spatial domain component vector in the plurality of spatial domain component vectors and indicates at least one of the plurality of frequency domain component vectors that corresponds to the spatial domain component vector; and sending the first indication information and the second indication information. | 2022-08-18 |
20220263561 | TRANSMISSION PROCESSING METHOD AND TERMINAL - A transmission processing method and a terminal are provided. The method includes: transmitting a first message according to a priority of the first message, where the first message is CSI or the first message includes CSI and a non-CSI message, and the CSI is sidelink CSI. | 2022-08-18 |
20220263562 | TRANSMISSION ANTENNA SELECTION METHOD AND ELECTRONIC DEVICE - In a method for operating an electronic device according to various embodiments: signal transmission in a first frequency band and signal transmission in a second frequency band are determined whether to be performed simultaneously by a first selected antenna selected from a plurality of first antennas configured to transmit a signal in the first frequency band and a second selected antenna selected from a plurality of second antennas configured to transmit a signal in the second frequency band, respectively; based on the signal transmission in the first frequency band and the signal transmission in the second frequency band being determined to be performed simultaneously, the first selected antenna and/or the second selected antenna are decided based on a look-up table created in accordance with the placements of the plurality of first antennas and the plurality of second antennas in the electronic device; and a signal is transmitted in the first frequency band by the first selected antenna, and a signal is transmitted in the second frequency band by the second selected antenna. | 2022-08-18 |
20220263563 | METHOD AND DEVICE IN NODES USED FOR WIRELESS COMMUNICATION - The present disclosure provides a method and device in a node for wireless communications. A first node receives a first information block; receives a first signaling; and as a response to a behavior of receiving the first signaling, stops a first behavior; the first information block indicates a first reference signal set, and the first reference signal set comprises at least one reference signal; the first signaling comprises DCI, the first signaling is used to determine a first transmission state, and the first transmission state indicates a first reference signal; the first transmission state is applied to a first channel and a second channel. The above method temporarily stops the beam failure discovery and/or recovery request for the mismatched reference signals when a reference signal configured by RRC for beam failure monitoring does not match a beam used by a downlink control channel, thus avoiding the waste of resources. | 2022-08-18 |
20220263564 | METHOD AND APPARATUS FOR ANTENNA SELECTION FOR DISTRIBUTED MIMO SYSTEM - A user equipment (UE) in a wireless communication system includes a transceiver and a processor. The transceiver receives information about an antenna system of a base station. The information includes a number of collocated antenna groups, and a number of antenna modules for each type of antenna modules in each of the collocated antenna groups. A collocated antenna group has at least two types of antenna modules: a first module with first antenna type and a second module with second antenna type. The transceiver also receives configuration information for a channel state information-reference signal (CSI-RS) resource. The transceiver also receives a CSI-RS based on the configuration information and acquires measurements. The processor determines a subset of antenna modules based on a comparison between the measurements and a criterion. The processor generates CSI for the subset of antenna modules. The transceiver transmits a CSI report comprising the CSI. | 2022-08-18 |
20220263565 | REPEATER DEVICE AND OPERATION OF REPEATER DEVICE FOR NON-LINE-OF-SIGHT COMMUNICATON - A repeater device includes a first antenna array on a first surface, a second antenna array on a second surface opposite to the first surface, and control circuitry. The first antenna array includes a plurality of first antenna elements and the second antenna array includes a plurality of second antenna elements, where each first antenna element is coupled to at least one second antenna element. The control circuitry selects at least one first antenna element and a corresponding second antenna element based on a first direction of signal reception with respect to the first antenna array. The selected first antenna element receives a beam of radio frequency (RF) signal in a first radiation pattern from a first network node in the first direction and corresponding second antenna element transmits the received beam of RF signal in a second radiation pattern to a second network node in a second direction. | 2022-08-18 |
20220263566 | REPEATER SYSTEM AND METHOD FOR HIGH-PERFORMANCE COMMUNICATION - A repeater system includes a first repeater device to receive a first beam of radio frequency (RF) signal from a first network node, and a second repeater device to receive a second beam of RF signal from the first network node. The first repeater device controls the second repeater device to provide the first beam and the second beam of RF signal to a second network node. A plurality of signal parameters is selected at the first and second repeater devices for a first beam and a second beam of RF signal, respectively. The first repeater device establishes an additional link with the second repeater device, where based on the additional link, a first data stream carried by the first beam of RF signal is provided to the second network node through the first repeater device as well as the second repeater device. | 2022-08-18 |
20220263567 | DIFFERENTIAL ROUTING FOR NON-GEOSTATIONARY ORBIT (NGSO) SATELLITE SYSTEMS - A Non-Geostationary Orbit (NGSO) satellite system is described that utilizes backbone route tables at its satellites that define different snapshots of a time-varying backbone topology of the NGSO satellite system. Because each satellite may see a different portion of the backbone topology, the backbone route tables at different satellites may be different from each other. Also, the backbone route tables at the satellites may be active at different times as the backbone topology changes over time. Different routing groups of backbone route tables may be defined in order to represent different routing options for packets arriving at a satellite. The routing options for a routing group may emphasis various network performance and security goals for traffic assigned to the routing group. | 2022-08-18 |
20220263568 | Forward Deployable Deck Box System for the Aggregation and Visualization of Distributed Assets - A method including configuring, an Iridium antenna of a deck box device, to receive satellite communications based in the L band frequency range, establishing a point-to-point connection with an L-band satellite communication device via a gateway device, the L-hand satellite communication device configured to receive sampled data from one or more sampling devices and receiving, by the Iridium antenna, one or more data messages from a respective sampling device via the established point-to-point connection. The method including parsing the Short Burst Data packets of each data message to retrieve the sampled data, converting, the retrieved sampled data from each respective data message into a common format, determining, one or more characteristics associated with the converted sampled data, generating a visualization based on the one or more determined characteristics, and actuating a strategic operation associated with the one or more sampling devices based on the generated visualization. | 2022-08-18 |
20220263569 | MEASUREMENT SYNCHRONIZATION METHOD, NETWORK DEVICE AND TERMINAL DEVICE - Disclosed are a measurement synchronization method, a network device and a terminal device. The method includes: determining delay-related parameters, wherein the delay-related parameters are used to represent a delay between a satellite service link corresponding to a serving cell and a satellite service link corresponding to a neighboring cell; adjusting a measurement window according to the delay-related parameters, wherein the measurement window is acquired from measurement interval parameters configured for a network device; and measuring a synchronization signal block corresponding to the neighboring cell according to the adjusted measurement window. | 2022-08-18 |
20220263570 | SATELLITE COMMUNICATION METHOD AND RELATED COMMUNICATION DEVICE - The disclosure provides satellite communication methods and related devices. One example method includes that a device receives a first common timing advance (TA) parameter and a first common TA change amount calculation parameter, where the first common TA parameter is used to obtain a first common TA, and the first common TA change amount calculation parameter is used to update the first common TA to obtain an updated common TA. The device sends a random access preamble by using the updated common TA. | 2022-08-18 |
20220263571 | PATH PROTECTION METHOD AND NETWORK NODE - A path protection method includes receiving, by a source node of a first path, a path event notify message from a first node on the first path. The path event notify message includes indication information that the first path is predicted to fail. The path protection method further includes obtaining, by the source node, information about a predicted protection path. The information about the predicted protection path includes resource information of a second path useable to protect a service on the first path. The first path and the second path include the source node and a same sink node. The path protection method further includes storing, by the source node, the resource information of the second path. | 2022-08-18 |