33rd week of 2022 patent applcation highlights part 62 |
Patent application number | Title | Published |
20220262872 | Foldable Display Apparatus - A foldable display apparatus includes: a non-folding area, and a folding area, in which an aperture ratio of a plurality of red sub pixels in the folding area is lower than an aperture ratio of a plurality in red sub pixels of the non-folding area, an aperture ratio of the plurality of green sub pixels in the folding area is lower than an aperture ratio of the plurality of green sub pixels of the non-folding area, and an aperture ratio of the plurality in blue sub pixels of the folding area is lower than an aperture ratio of the plurality of blue sub pixels of the non-folding area. | 2022-08-18 |
20220262873 | DISPLAY PANEL, PACKAGED EVAPORATION SHADOW MASK, DISPLAY DEVICE AND PREPARATION METHOD - Provided are a display panel, a packaged evaporation shadow mask, a display device, and a preparation method. The display panel includes a display area and a non-display area; the display area includes multiple first sub-pixel minimum repeating units; the multiple first sub-pixel minimum repeating units are sequentially and periodically arranged in a first direction, and in the first direction, a center distance between any two adjacent ones of the multiple first sub-pixel minimum repeating units is d | 2022-08-18 |
20220262874 | DISPLAY DEVICE - In a display device including a first area and a plurality of second areas spaced apart from each other by the first area, the display device includes: a substrate including a plurality of islands distinguished by a plurality of cutouts, and a plurality of bridges respectively adjacent to the plurality of islands; a common electrode on the substrate in the first area; and a dummy conductive pattern on the substrate in the second area, physically separated from the common electrode, and including a same material as the common electrode, wherein the first area is over the plurality of islands and the plurality of bridges, and each of the plurality of second areas is around at least one of both ends of the cutout. | 2022-08-18 |
20220262875 | DISPLAY PANEL - A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure. | 2022-08-18 |
20220262876 | DISPLAY DEVICE - A display device includes a pixel electrode electrically connected to a circuit layer, a pixel definition layer defining a first opening which exposes the pixel electrode and a second opening spaced apart from the pixel electrode, an auxiliary electrode in the second opening and including a material different from the pixel electrode, a light emitting functional layer on the pixel electrode, the pixel definition layer and the auxiliary electrode and defining a through hole corresponding to the auxiliary electrode, and a common electrode on the light emitting functional layer and electrically connected to the auxiliary electrode at the through hole. | 2022-08-18 |
20220262877 | DISPLAY DEVICE - A display device includes a first electrode and a second electrode extending in a first direction and spaced apart from each other in a second direction, a first insulating layer disposed on the first electrode and the second electrode, a bank layer disposed on the first insulating layer and comprising an outer bank part extending in the first direction and the second direction and inner bank parts extending in the first direction in an area surrounded by the outer bank part, a second insulating layer disposed on the inner bank parts and the first insulating layer, and light emitting elements disposed on the second insulating layer between the inner bank parts, wherein each of the inner bank parts is connected to a part of the outer bank part extending in the second direction. | 2022-08-18 |
20220262878 | DISPLAY DEVICE WITH REDUCED CROSSTALK AND MANUFACTURING METHOD OF THE SAME - A display device includes a substrate, a plurality of first electrodes disposed on the substrate, a pixel defining layer disposed on the substrate, and defining a plurality of opening areas by exposing a portion of an upper surface of each of the plurality of first electrodes,
| 2022-08-18 |
20220262879 | ARRAY SUBSTRATE, PREPARATION METHOD, DISPLAY PANEL, ANDDISPLAY DEVICE - Disclosed are an array substrate, a preparation method, a display panel, and a display device. A pixel limiting layer includes a first limiting sublayer and a second limiting sublayer which contact each other, and a first height of the first limiting sublayer in a direction perpendicular to a plane where a base substrate is located is greater than a second height of the second limiting sublayer in the direction perpendicular to the plane where the base substrate is located. Thus, when light emitting layers are formed in pixel openings by an ink jet printing process, light emitting layers having different colors can be spaced apart by the first limiting sublayer. | 2022-08-18 |
20220262880 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a bank including an opening exposing a surface of a base. The bank further includes side surfaces adjacent to an upper surface. The side surfaces slope downward from the upper surface toward an opening in an organic film pattern. A plurality of fine holes is formed on the upper surface and the side surfaces, the bank may also include a plurality of inner holes. | 2022-08-18 |
20220262881 | DISPLAY DEVICE - A display device may include a substrate, a first active layer disposed on the substrate and including a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region, a first gate insulating layer covering the first active layer on the substrate, first gate electrodes disposed in opposite sides of the first channel region on the first gate insulating layer, a second gate insulating layer covering the first gate electrodes on the first gate insulating layer, a second gate electrode disposed in a central portion of the first channel region on the second gate insulating layer, and a first connection electrode disposed on the second gate electrode and connected to the first and second gate electrodes. | 2022-08-18 |
20220262882 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - Provided is a display substrate, including a base substrate and a plurality of pixel units arranged on the base substrate; each pixel unit includes constant voltage terminals and a dual-gate transistor; a part of an active region of each dual-gate transistor, which is located between two gates, is an intermediate part; except the pixel units closest to the first side, each pixel unit includes a compensation structure; the compensation structure is connected to one of the constant voltage terminals of the pixel unit where the compensation structure is located, and compensates for at least one dual-gate transistor of a pixel unit adjacent to the pixel unit where the compensation structure is located in a direction toward the first side; the compensation structure overlaps and is insulated from the intermediate part of the dual-gate transistor for which the compensation structure compensates. | 2022-08-18 |
20220262883 | DISPLAY DEVICE - A display device includes a substrate, a first semiconductor pattern, a first gate insulating film covering the first semiconductor pattern, a first conductive layer and a second semiconductor pattern are on the first gate insulating film, a second gate insulating film on the second semiconductor pattern, a third gate insulating film covering the first gate insulating film and the second gate insulating film, a second conductive layer on the third gate insulating film, an interlayer insulating film covering the second conductive layer, and a third conductive layer on the interlayer insulating film, wherein the first and second semiconductor patterns respectively form semiconductor layers of the first and second transistors, wherein the first conductive layer includes a gate electrode of the first transistor and a first electrode of the capacitor, and wherein the second conductive layer includes a gate electrode of the second transistor and a second electrode of the capacitor. | 2022-08-18 |
20220262884 | Display Device - Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor. | 2022-08-18 |
20220262885 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer. | 2022-08-18 |
20220262886 | DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY APPARATUS - Provided are a display substrate and a preparation method therefor, and a display apparatus, which can not only avoid jumpers generated when a light-emitting device in a sub-pixel is electrically connected to a storage capacitor, in order to avoid the risk of crosstalk, but can also increase the pixel aperture ratio of the display substrate and increase the capacitance of the storage capacitor in a pixel driving circuit. The display substrate comprises: a base, and a pixel driving circuit and a bottom-emission-type light-emitting device which are arranged in a display region on the base and are located in each sub-pixel, wherein the light-emitting device comprises a first electrode connected to the pixel driving circuit; the pixel driving circuit comprises a first storage capacitor; the first storage capacitor comprises a first storage electrode and a second storage electrode which are arranged opposite each other; the first electrode is multiplexed as the first storage electrode; and the second storage electrode and the first electrode are both transparent electrodes. | 2022-08-18 |
20220262887 | COVER FILM AND A DISPLAY DEVICE INCLUDING THE SAME - A display device including: a substrate including a display area and a non-display area adjacent to the display area; a data driver disposed in the non-display area, and configured to provide a data voltage to the display area; a first power line disposed in the non-display area, adjacent to the data driver, and configured to transfer a first power voltage to the display area; and a cover film overlapping the data driver and the first power line, wherein the cover film includes a first layer including a first shielding portion overlapping the first power line. | 2022-08-18 |
20220262888 | DISPLAY PANEL AND DISPLAY DEVICE - Disclosed are a display panel and a display device. The display panel includes: a plane display unit; and a corner display unit. The corner display unit is located at the corner position on the periphery of the plane display unit, and has a plurality of corner pixels. Each corner pixel includes four corner sub-pixels, i.e., a first corner sub-pixel and a second corner sub-pixel respectively located on two opposite vertexes of a quadrilateral, and a third corner sub-pixel and a fourth corner sub-pixel located another two opposite vertexes of the quadrilateral. The first corner pixel drive circuit, the second corner pixel drive circuit, the third corner pixel drive circuit, and the fourth corner pixel drive circuit are located in the same corner pixel drive circuit row. | 2022-08-18 |
20220262889 | DISPLAY MOTHERBOARD AND METHOD FOR MANUFACTURING DISPLAY SUBSTRATE - A display motherboard and a manufacturing method of a display substrate are provided. The display motherboard includes: a substrate including a valid area and an edge area, the valid area including a plurality of panel areas and a to-be-cut area, and the panel area including a display area and a frame area; multiple first power lines in each display area and the edge area and extending along a first direction; multiple first display electrodes in each display area and multiple virtual electrodes in the edge area, the first display electrodes and the virtual electrodes being in the same layer; wherein an orthographic projection of each first display electrode on the substrate overlaps an orthographic projection of at most one first power line on the substrate, and an orthographic projection of each virtual electrode on the substrate overlaps orthographic projections of at least two first power lines on the substrate. | 2022-08-18 |
20220262890 | DISPLAY SUBSTRATE AND DISPLAY APPARATUS - A display substrate includes: a base; a cathode power line disposed on the base and located in the peripheral region; a first insulating layer located on a side of a layer in which the cathode power line is located away from the base and having first via hole(s); a cathode layer located on the first insulating layer and electrically connected to the cathode power line through the first via hole(s); and spacer(s) located on a side of the cathode layer proximate to the base, a spacer covering at least a side wall of a first via hole, a thickness of a portion of the spacer covering the side wall decreasing along the side wall and in a direction pointing from an end of the side wall proximate to the base toward an end of the side wall of the first via hole away from the base. | 2022-08-18 |
20220262891 | CONNECTING SUBSTRATE, FABRICATION METHOD, SPLICING SCREEN AND DISPLAY APPARATUS - Disclosed are a connecting substrate and a fabrication method, a splicing screen, and a display apparatus. The connecting substrate has panel areas ( | 2022-08-18 |
20220262892 | SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT - A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element. | 2022-08-18 |
20220262893 | TEMPERATURE-DEPENDENT CAPACITOR - A temperature-dependent capacitor comprises a first conductive plate, a second conductive plate located in a parallel-planar orientation to the first conductive plate, and a dielectric material located between the first conductive plate and the second conductive plate, the dielectric material having a temperature-dependent dielectric constant (ε) value, wherein the temperature-dependent capacitor has a positive correlation of an operating temperature of the temperature-dependent capacitor to a capacitance value of the temperature-dependent capacitor. | 2022-08-18 |
20220262894 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CAPACITORS HAVING SHARED ELECTRODE - The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit. | 2022-08-18 |
20220262895 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a terminal portion including a second external terminal, an insulating sheet disposed on the second external terminal, and a first external terminal disposed on the insulating sheet. The first external terminal has a first end portion with a first end. At the first end portion, a rear surface of the first external terminal is not parallel to a front surface of the second external terminal so that, in a thickness direction of the first external terminal, a distance between the first external terminal and the second external terminal increases with as the first end is approached. | 2022-08-18 |
20220262896 | SIC MOSFET WITH REDUCED CHANNEL LENGTH AND HIGH VTH - A silicon carbide MOSFET device and method for making thereof are disclosed. The silicon carbide MOSFET device comprises a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type. A body region of a second conductivity type opposite the first is formed in epitaxial layer and an accumulation mode region of the first conductivity type is formed in the body region and an inversion mode region of the second conductivity type formed in the body region. The accumulation mode region is located between the inversion mode region and a junction field effect transistor (JFET) region of the epitaxial layer. | 2022-08-18 |
20220262897 | SELF-BALANCING SUPER JUNCTION STRUCTURE AND PREPARATION METHOD THEREOF - A self-balancing super junction structure and a preparation method thereof. The method includes: forming an initial epitaxial layer on a surface of a substrate of a first doping type; respectively forming an implantation region of the first doping type and an implantation region of a second doping type in the initial epitaxial layer; forming an intrinsic epitaxial layer on the surface of the initial epitaxial layer; respectively forming an implantation region of the first doping type and an implantation region of the second doping type in the intrinsic epitaxial layer; and repeating the steps to form a structure with stacked epitaxial layers, and then performing thermal diffusion treatment to form a self-balancing super junction structure. Ions of the first doping type and ions of the second doping type in a same layer of the epitaxial layer stack structure are implanted after a same lithography step. | 2022-08-18 |
20220262898 | IGBT LIGHT LOAD EFFICIENCY - An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled. | 2022-08-18 |
20220262899 | HIGH VOLTAGE DEVICE WITH GATE EXTENSIONS - The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess;
| 2022-08-18 |
20220262900 | TRANSISTOR WITH EMBEDDED ISOLATION LAYER IN BULK SUBSTRATE - The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate. | 2022-08-18 |
20220262901 | INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES - A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region. | 2022-08-18 |
20220262902 | ENHANCEMENT ON-STATE POWER SEMICONDUCTOR DEVICE CHARACTERISTICS UTILIZING NEW CELL GEOMETRIES - A semiconductor device and a method of making thereof are disclosed. The device includes a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type formed on the substrate. A buffer layer between the substrate and the epitaxial layer is doped with the first conductivity type at a doping level between that of the substrate and that of the epitaxial layer. A cell includes a body region doped with the second conductivity formed in the epitaxial layer. The second conductivity type is opposite the first conductivity type. The cell includes a source region doped with the first conductivity type and formed in at least the body region. The device further includes a short region doped with the second conductivity type formed in the epitaxial layer separated from source region of the cell by the body region of the cell wherein the short region is conductively coupled with the source region. | 2022-08-18 |
20220262903 | SEMICONDUCTOR DEVICE INCLUDING METAL-2 DIMENSIONAL MATERIAL-SEMICONDUCTOR CONTACT - A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure. | 2022-08-18 |
20220262904 | HYBRID FIELD-EFFECT TRANSISTOR - The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate. | 2022-08-18 |
20220262905 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device, including a semiconductor substrate containing silicon carbide, a bonding wire, and a surface electrode of an aluminum alloy containing silicon, the surface electrode being provided on a surface of the semiconductor substrate, and having a joint portion to which the bonding wire is bonded. The surface electrode has a plurality of silicon nodules formed therein, which include a number of the silicon nodules formed in the joint portion. One of the number of the silicon nodules is of a dendrite structure, and is included at an area percentage of at least 10% relative to a total area of the number of the silicon nodules in the joint portion. | 2022-08-18 |
20220262906 | SIC MOSFET WITH REDUCED ON-RESISTANCE - A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer. | 2022-08-18 |
20220262907 | Lateral Double Diffused MOS Device - An apparatus includes a substrate of a first conductivity, an extended drain region of a second conductivity formed over the substrate, a body region of the first conductivity formed in the extended drain region, a source region of the second conductivity formed in the body region, a drain region of the second conductivity formed in the extended drain region, a first dielectric layer formed over the body region and the extended drain region, a second dielectric layer formed over the extended drain region, and between the first dielectric layer and the drain region, a first gate formed over the first dielectric layer, and a second gate formed over the second dielectric layer, wherein the second gate is electrically connected to the source region. | 2022-08-18 |
20220262908 | FIELD PLATE STRUCTURE FOR HIGH VOLTAGE DEVICE - Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material. | 2022-08-18 |
20220262909 | POWER SEMICONDUCTOR DEVICE WITH REDUCED STRAIN - Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die. | 2022-08-18 |
20220262910 | CONTACT STRUCTURE FOR TRANSISTOR DEVICES - A transistor device includes field plate contacts that electrically connect a final metallization layer to field electrodes in underlying trenches, and mesa contacts that electrically connect the final metallization layer to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts. | 2022-08-18 |
20220262911 | Semiconductor Device and Method - In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region. | 2022-08-18 |
20220262912 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 2022-08-18 |
20220262913 | VERTICAL-CONDUCTION SILICON CARBIDE MOSFET DEVICE HAVING IMPROVED GATE BIASING STRUCTURE AND MANUFACTURING PROCESS THEREOF - A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer. | 2022-08-18 |
20220262914 | GATE STRUCTURE IN HIGH-K METAL GATE TECHNOLOGY - Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a gate dielectric structure on a substrate. A sidewall spacer is formed around the gate dielectric structure. A metal structure is formed over the gate dielectric structure. A gate body layer is formed over the metal structure. A lower portion of the gate body layer is cupped by the metal structure. A top surface of the gate body layer is vertically offset from a top surface of the metal structure. A conductive via is formed over the metal structure. The conductive via is disposed between outer sidewalls of the gate body layer. | 2022-08-18 |
20220262915 | Semiconductor Device With Gate Cut Feature And Method For Forming The Same - Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece that has a substrate, a first plurality of channel members, a second plurality of channel members, a first gate structure engaging the first plurality of channel members, a second gate structure engaging the second plurality of channel members, a hybrid fin disposed between the first and second gate structures, and an isolation feature disposed under the hybrid fin. The method also includes forming a metal cap layer at a frontside of the workpiece. The metal cap layer electrically connects the first and second gate structures. The method also includes etching the isolation feature, etching the hybrid fin, etching the metal cap layer, and depositing a dielectric material to form a gate isolation feature disposed between the first and second gate structures. | 2022-08-18 |
20220262916 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device of an embodiment includes: a silicon carbide layer including a first silicon carbide region of n-type containing one metal element selected from a group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) and a second silicon carbide region of p-type containing the metal element; and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. Among the metal elements contained in the first silicon carbide region, a proportion of the metal element positioned at a carbon site is higher than a proportion of the metal element positioned at an interstitial position. Among the metal elements contained in the second silicon carbide region, a proportion of the metal element positioned at an interstitial position is higher than a proportion of the metal element positioned at a carbon site. | 2022-08-18 |
20220262917 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a channel layer not containing Al; a barrier layer above the channel layer containing Al; a recess; and an ohmic electrode in the recess, which is in ohmic contact with a two-dimensional electron gas layer. An Al composition ratio distribution of the barrier layer has a maximum point at a first position. The semiconductor device includes: a first inclined surface of the barrier layer which includes the first position and is in contact with the ohmic electrode; and a second inclined surface of the barrier layer which intersects the first inclined surface on a lower side of the first inclined surface, and is in contact with the ohmic electrode. To the surface of the substrate, an angle of the second inclined surface is smaller than an angle of the first inclined surface. A position of the first intersection line is lower than the first position. | 2022-08-18 |
20220262918 | METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR WITH SPACER STRUCTURE - Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants. | 2022-08-18 |
20220262919 | METHODS OF FORMING AN ELECTRONIC DEVICE COMPRISING DEUTERIUM-CONTAINING DIELECTRIC MATERIALS AND RELATED ELECTRONIC DEVICES AND SYSTEMS - A method of forming an electronic device comprising forming an initial dielectric material comprising silicon-hydrogen bonds. A deuterium source gas and an oxygen source gas are reacted to produce deuterium species, and the initial dielectric material is exposed to the deuterium species. Deuterium of the deuterium species is incorporated into the initial dielectric material to form a deuterium-containing dielectric material. Additional methods are also disclosed, as are electronic devices and systems comprising the deuterium-containing dielectric material. | 2022-08-18 |
20220262920 | Semiconductor Device and Method of Manufacture - A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening. | 2022-08-18 |
20220262921 | Semiconductor Processing System with In-Situ Electrical Bias and Methods Thereof - A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage. | 2022-08-18 |
20220262922 | HIGH-ELECTRON-MOBILITY TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer. | 2022-08-18 |
20220262923 | SACRIFICIAL FIN FOR CONTACT SELF-ALIGNMENT - A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion. | 2022-08-18 |
20220262924 | SEMICONDUCTOR DEVICE WITH REDUCED TRAP DEFECT AND METHOD OF FORMING THE SAME - A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions. | 2022-08-18 |
20220262925 | Nano-Fet Semiconductor Device and Method of Forming - Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density. | 2022-08-18 |
20220262926 | Fin Field-Effect Transistor Device and Method - A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess. | 2022-08-18 |
20220262927 | SEMICONDUCTOR DEVICE WITH CONTROLLABLE CHANNEL LENGTH AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE WITH CONTROLLABLE CHANNEL LENGTH - A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region. | 2022-08-18 |
20220262928 | Device Providing Multiple Threshold Voltages And Methods Of Making The Same - A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer. | 2022-08-18 |
20220262929 | Pulsed-laser modification of quantum-particle cells - A pulsed-laser applies short (e.g., less than 10 pico-seconds) pulses to modify quantum particle (e.g., alkali-metal and alkaline-earth-metal atoms) ultra-high vacuum (UHV) cells to bond, ablate, and/or chemically modify vacuum-facing surfaces of the cell. The pulses are generated outside the cell and are transmitted through a vacuum-boundary wall. In one example, one vacuum-boundary wall is first contact bonded to other vacuum boundary walls at a relatively low temperature (below 200° C.), sufficient to form a temporary hermetic seal. Pulsed laser bonding is used to reinforce the contact bonds, correcting defects and generally increasing the robustness of the seal. The pulses provide high peak power to ensure strong bonds, but low total heat so as to avoid heat damage to nearby cell components and to limit quantum-particle sorbtion to and into cell walls. | 2022-08-18 |
20220262930 | BIPOLAR JUNCTION TRANSISTORS WITH A WRAPAROUND BASE LAYER - Device structures and fabrication methods for a bipolar junction transistor. The device structure includes a substrate and a trench isolation region in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure further includes a collector in the active region of the substrate, a base layer having a first section positioned on the active region and a second section oriented at an angle relative to the first section, an emitter positioned on the first section of the base layer, and an extrinsic base layer positioned over the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally positioned between the extrinsic base layer and the emitter. | 2022-08-18 |
20220262931 | EXTENDED SHALLOW TRENCH ISOLATION FOR ULTRA-LOW LEAKAGE IN FIN-TYPE LATERAL BIPOLAR JUNCTION TRANSISTOR DEVICES - A lateral bipolar junction transistor (BJT) device includes: an emitter region, a collector region, and a base region, the base region positioned between and laterally separating the emitter region and the collector region, the base region including an intrinsic base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating a lower surface of the intrinsic base region from the semiconductor substrate. | 2022-08-18 |
20220262932 | AMORPHOUS METAL THIN FILM TRANSISTORS - Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described. | 2022-08-18 |
20220262933 | SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF - The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface. By use of the directivity of wet etching, etching is started from the N surface of the second P-type semiconductor layer and automatically stopped on the Ga surface of the first P-type semiconductor layer | 2022-08-18 |
20220262934 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region. | 2022-08-18 |
20220262935 | VOLTAGE-CONTROLLED SWITCHING DEVICE WITH CHANNEL REGION - A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region. | 2022-08-18 |
20220262936 | TUNNEL FIELD-EFFECT TRANSISTOR WITH REDUCED TRAP-ASSISTED TUNNELING LEAKAGE - The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage. | 2022-08-18 |
20220262937 | RARE-EARTH III-NITRIDE N-POLAR HEMT - A high electron mobility transistor (HEMT) heterostructure includes a substrate; a N-polar channel layer; and a N-polar barrier layer positioned between the substrate and the channel layer, wherein the barrier layer comprises a rare-earth III-nitride material. The rare earth III-nitride material can be ScAlN. | 2022-08-18 |
20220262938 | TRANSISTOR - A device including a first transistor, having a gate region partially penetrating into a gallium nitride layer, and a second transistor located inside of the gate region of the first transistor. | 2022-08-18 |
20220262939 | HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF - A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer. | 2022-08-18 |
20220262940 | HEMT DEVICES WITH REDUCED SIZE AND HIGH ALIGNMENT TOLERANCE - A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width. | 2022-08-18 |
20220262941 | CAPACITANCE NETWORKS FOR ENHANCING HIGH VOLTAGE OPERATION OF A HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD THEREIN - Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region. | 2022-08-18 |
20220262942 | HIGH ELECTRON MOBILITY TRANSISTOR - An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode. | 2022-08-18 |
20220262943 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate. | 2022-08-18 |
20220262944 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer. | 2022-08-18 |
20220262945 | SEMICONDUCTOR DEVICES WITH CLASS IV CHANNEL REGION AND CLASS III-V DRIFT REGION - Diodes, transistors, and other devices having a class IV channel region and a class III-V drift region are described. The class IV channel region, such as a Si channel region, is able to provide all associated advantages, such as ease of manufacturing of many different types of devices, using cost-effective materials and techniques. Meanwhile, the III-V drift region provides substantially lower R | 2022-08-18 |
20220262946 | SEMICONDUCTOR POWER DEVICE AND METHOD OF MANUFACTURING THE SAME - The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region. | 2022-08-18 |
20220262947 | LDMOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced. | 2022-08-18 |
20220262948 | LDMOS DEVICE AND METHOD FOR PREPARING SAME - The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area. | 2022-08-18 |
20220262949 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks. | 2022-08-18 |
20220262950 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the conductive layers and the memory patterns and second parts extending between the memory patterns; and air gaps respectively located between the blocking layer and the insulating layers. | 2022-08-18 |
20220262951 | Semiconductor Structure and Methods of Forming Same - A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin. | 2022-08-18 |
20220262952 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second metal layers, a dielectric layer, first, second, and third semiconductor regions, a first control electrode, and a first electrode. The dielectric layer is located on the first metal layer. The second metal layer is located on the dielectric layer, and electrically connected with the first metal layer. The first semiconductor region is located on the second metal layer and electrically connected with the second metal layer. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The first control electrode faces the second semiconductor region via a first insulating film. The first electrode is located on the third semiconductor region and the first control electrode, electrically connected with the third semiconductor region, and insulated from the first control electrode by a first insulating portion. | 2022-08-18 |
20220262953 | SEMICONDUCTOR DEVICE - A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region. | 2022-08-18 |
20220262954 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode. | 2022-08-18 |
20220262955 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure. | 2022-08-18 |
20220262956 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a substrate layer, a gate layer, an insulating layer, and an active layer. The gate layer is disposed on the substrate layer and includes a first gate layer and a second gate layer. The second gate layer is disposed on a surface of the first gate layer. The insulating layer covers the gate layer and the substrate layer. The active layer is disposed on a surface of the insulating layer away from the gate layer. The active layer includes a first layer section and a second layer section connected to the first layer section, and a surface of the second layer section is above a surface of the first section layer. | 2022-08-18 |
20220262957 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES - Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure. | 2022-08-18 |
20220262958 | SEMICONDUCTOR DEVICE WITH FISH BONE STRUCTURE AND METHODS OF FORMING THE SAME - Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks. | 2022-08-18 |
20220262959 | VERTICAL ETCH HETEROLITHIC INTEGRATED CIRCUIT DEVICES - Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes. | 2022-08-18 |
20220262960 | Power Semiconductor Component for Voltage Limiting, Arrangement Having Two Power Semiconductor Components, and a Method for Voltage Limiting - A power semiconductor component for voltage limiting includes a rear-side base zone electrically contacted with a rear-side electrode and a front-side base zone electrically contacted with a front-side electrode. At least one switch-on structure is embedded at least into one of the rear-side base zone and the front-side base zone and is electrically contacted by the electrode contacting the embedding base zone. At least one triggering structure is provided as a breakdown structure of a first type, present between the front-side and rear-side electrodes. At least one further triggering structure is provided as a breakdown structure of a second type, present between the front-side and rear-side electrodes. The front-side and rear-side electrodes are each electrically conductively pressure-contacted by an electrically conductive contact plate at least one of which functions as a heat sink for dissipating heat generated in the semiconductor body. | 2022-08-18 |
20220262961 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a wiring board including a first surface and a second surface, a cover disposed to face the first surface, an optical semiconductor element disposed on the first surface, a plurality of electrodes disposed on the second surface, and a resist layer disposed on the second surface and located at least between the plurality of electrodes. A ventilation hole that penetrates the first surface and the second surface is formed in the wiring board. The second surface includes a disposition region in which the resist layer is disposed and a non-disposition region in which the resist layer is not disposed. The non-disposition region includes a first region in which the ventilation hole is disposed and a second region that reaches an edge of the second surface from the first region. | 2022-08-18 |
20220262962 | OPTOELECTRONIC MODULE PACKAGE - An optoelectronic module. In some embodiments, the optoelectronic module includes a substrate; a digital integrated circuit, on an upper surface of the substrate; a photonic integrated circuit, secured in a pocket of the substrate, the pocket being in the upper surface of the substrate; and an analog integrated circuit, on the photonic integrated circuit. | 2022-08-18 |
20220262963 | OPTOELECTRONIC DEVICE COMPRISING PEROVSKITES - The invention provides an optoelectronic device comprising a porous material, which porous material comprises a semiconductor comprising a perovskite. The porous material may comprise a porous perovskite. Thus, the porous material may be a perovskite material which is itself porous. Additionally or alternatively, the porous material may comprise a porous dielectric scaffold material, such as alumina, and a coating disposed on a surface thereof, which coating comprises the semiconductor comprising the perovskite. Thus, in some embodiments the porosity arises from the dielectric scaffold rather than from the perovskite itself. The porous material is usually infiltrated by a charge transporting material such as a hole conductor, a liquid electrolyte, or an electron conductor. The invention further provides the use of the porous material as a semiconductor in an optoelectronic device. Further provided is the use of the porous material as a photosensitizing, semiconducting material in an optoelectronic device. The invention additionally provides the use of a layer comprising the porous material as a photoactive layer in an optoelectronic device. Further provided is a photoactive layer for an optoelectronic device, which photoactive layer comprises the porous material. | 2022-08-18 |
20220262964 | SEMICONDUCTOR DEVICE AND SOLAR CELL AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - The present invention realizes a hole-selective film provided with both hole selectivity and passivation characteristics. This production method for a semiconductor device is provided with a step for forming a titanium oxide film on a crystalline silicon layer by means of a thermal atomic layer deposition method, and a step for carrying out a hydrogen plasma process on the titanium oxide film. | 2022-08-18 |
20220262965 | METALLIZATION OF SOLAR CELLS WITH DIFFERENTIATED P-TYPE AND N-TYPE REGION ARCHITECTURES - Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and resulting solar cells, are described. In an example a solar cell includes a first emitter region of a first conductivity type disposed on a first dielectric region, the first dielectric region disposed on a surface of a substrate. A second dielectric region is disposed laterally adjacent to the first and second emitter region. The second emitter region of a second, different, conductivity type is disposed on a third dielectric region, the third dielectric region disposed on the surface of the substrate, over the second dielectric region, and partially over the first emitter region. A first metal foil is disposed over the first emitter region. A second metal foil is disposed over the second emitter region. | 2022-08-18 |
20220262966 | TRI-LAYER SEMICONDUCTOR STACKS FOR PATTERNING FEATURES ON SOLAR CELLS - Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure. | 2022-08-18 |
20220262967 | SOLAR CELL AND MANUFACTURING METHOD THEREFOR - A solar cell according to an embodiment of the present disclosure includes a first passivation layer including a first aluminum oxide layer positioned on a first conductivity-type region composed of a polycrystalline silicon layer having an n-type conductivity and having hydrogen, and a first dielectric layer positioned on the first aluminum oxide layer and including a material different from the first aluminum oxide layer. | 2022-08-18 |
20220262968 | OPTO-ELECTRONIC DEVICE AND IMAGE SENSOR INCLUDING THE SAME - An opto-electronic device includes a base portion, a first electrode and a second electrode formed on an upper surface of the base portion apart from each other, a quantum dot layer, and a bank structure. The quantum dot layer is between the first electrode and the second electrode on the base portion and includes a plurality of quantum dots. The bank structure covers at least partial regions of the first electrode and the second electrode, defines a region where the quantum dot layer is formed, and is formed of an inorganic material. | 2022-08-18 |
20220262969 | COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR COMPATIBLE PATTERNING OF SUPERCONDUCTING NANOWIRE SINGLE-PHOTON DETECTORS - A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer. | 2022-08-18 |
20220262970 | LIGHT RECEIVING ELEMENT AND ELECTRONIC DEVICE - An embodiment of the present technology includes an avalanche photodiode including a substrate including a first side with a first surface and a second side with a second surface that is opposite the first surface. The second surface is a light-incident surface of the substrate. The avalanche photodiode includes an anode region disposed in the substrate at the first side of the substrate, an anode electrode coupled to the anode region, a cathode region disposed in the substrate at the first side of the substrate, a cathode electrode coupled to the cathode region, and an insulating layer disposed in the substrate at the first side of the substrate. The anode electrode or the cathode electrode passes through the insulating layer. | 2022-08-18 |
20220262971 | MIRROR FOR A PHOTOVOLTAIC CELL, PHOTOVOLTAIC CELL AND PHOTOVOLTAIC MODULE - The invention concerns a mirror ( | 2022-08-18 |