33rd week of 2022 patent applcation highlights part 60 |
Patent application number | Title | Published |
20220262672 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a semiconductor substrate having a substrate upper surface; and an embedded oxide film provided in the substrate upper surface and at least partially embedded below the substrate upper surface. An upper surface of the embedded oxide film has an end portion and a central portion in a direction parallel to the substrate upper surface. The end portion of the upper surface of the embedded oxide film is disposed at the same height position as the substrate upper surface or below the substrate upper surface. The central portion of the upper surface of the embedded oxide film is disposed at a position higher than the end portion of the upper surface. | 2022-08-18 |
20220262673 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate. | 2022-08-18 |
20220262674 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer. | 2022-08-18 |
20220262675 | Interconnect Structure without Barrier Layer on Bottom Surface of Via - Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure. | 2022-08-18 |
20220262676 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess. | 2022-08-18 |
20220262677 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer. | 2022-08-18 |
20220262678 | Conductive Via Of Integrated Circuitry, Memory Array Comprising Strings Of Memory Cells, Method Of Forming A Conductive Via Of Integrated Circuitry, And Method Of Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed. | 2022-08-18 |
20220262679 | Methods for Forming Self-Aligned Contacts Using Spin-on Silicon Carbide - Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield. | 2022-08-18 |
20220262680 | SEMICONDUCTOR DEVICE HAVING PLANAR TRANSISTOR AND FINFET - A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region. | 2022-08-18 |
20220262681 | Semiconductor Device with Multi-Layered Source/Drain Regions Having Different Dopant Concentrations and Manufacturing Method Thereof - A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer. | 2022-08-18 |
20220262682 | SEMICONDUCTOR STRUCTURE AND RELATED METHODS - Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening. | 2022-08-18 |
20220262683 | SEMICONDUCTOR STRUCTURE WITH GATE-ALL-AROUND DEVICES AND STACKED FINFET DEVICES - An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features. | 2022-08-18 |
20220262684 | TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS - Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed. | 2022-08-18 |
20220262685 | Pre-Deposition Treatment for FET Technology and Devices Formed Thereby - Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers. | 2022-08-18 |
20220262686 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region. A surface of the first region of the semiconductor substrate contains a gate structure, a surface of the second region of the semiconductor substrate contains a dummy gate structure, and the semiconductor substrate under the dummy gate structure contains an isolation structure. The semiconductor structure further includes a bulk layer having a substantially flat reshaped surface formed in the semiconductor substrate at each of two sides of the gate structure; and a protective layer formed on the reshaped surface of the bulk layer. | 2022-08-18 |
20220262687 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region, removing part of the first fin-shaped structure to form a first trench, forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure, forming a first gate structure and a second gate structure on the DDB structure as a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure, and forming a contact plug between the first gate structure and the second gate structure on the DDB structure. | 2022-08-18 |
20220262688 | ADHESION DEVICE, MICRO DEVICE OPTICAL INSPECTION AND REPAIRING EQUIPMENT AND OPTICAL INSPECTION AND REPAIRING METHOD - Micro device optical inspection and repairing equipment adopting an adhesion device is provided. The micro device optical inspection and repairing equipment includes a carrying stage, an optical inspection module and at least one adhesion device. The optical inspection module is arranged corresponding to the carrying stage so as to capture image information and obtain a position coordinate from the image information. The adhesion device includes a main body and an adhesive portion. The adhesive portion is connected to the main body. The adhesion device can move to a target position of the carrying stage according to the position coordinate. The main body is adapted to drive the adhesive portion to move to the target position along a moving axis. An optical inspection and repairing method adopting the micro device optical inspection and repairing equipment is also provided. | 2022-08-18 |
20220262689 | CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME - A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium. | 2022-08-18 |
20220262690 | POWER MODULE - A power module includes a base plate, a casing, a substrate unit, a terminal plate, a first resin layer, and a second resin layer. The substrate unit includes a substrate fixed on the base plate, a dam part, a semiconductor chip, a metal member, and a wire. The dam part is formed along an edge of the substrate. The wire includes an electrode plate connection portion, and a chip connection portion. The first resin layer is located inward of the dam part. The chip connection portion and the electrode plate connection portion are located inside the first resin layer. The second resin layer is located on the first resin layer. The upper surface of the metal member is located inside the second resin layer. An elastic modulus of the second resin layer is less than that of the first resin layer. | 2022-08-18 |
20220262691 | SEMICONDUCTOR PACKAGE HAVING A STIFFENER RING - A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate. | 2022-08-18 |
20220262692 | RESIN COMPOSITION FOR ENCAPSULATING LIGHT-EMITTING DEVICE, LIGHT SOURCE UNIT, AND METHOD FOR MANUFACTURING LIGHT SOURCE UNIT - The present invention provides a resin composition for producing an encapsulating member having high heat resistance and high encapsulation performance. In the resin composition for encapsulating a light-emitting device according to the present invention, at least one of (i) and (ii) is satisfied:
| 2022-08-18 |
20220262693 | MOLDED SEMICONDUCTOR MODULE HAVING A MOLD STEP FOR INCREASING CREEPAGE DISTANCE - A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm. | 2022-08-18 |
20220262694 | Packages with Multiple Encapsulated Substrate Blocks - A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate. | 2022-08-18 |
20220262695 | SEMICONDUCTOR PACKAGE INCLUDING PACKAGE SEAL RING AND METHODS FOR FORMING THE SAME - A semiconductor package includes a first die; a second die stacked on the first die in a vertical direction; a dielectric encapsulation (DE) structure surrounding the first die and the second die in a lateral direction perpendicular to the vertical direction; and a package seal ring that extends through the DE structure and surrounds the second die and at least a portion of the first die, in the lateral direction. | 2022-08-18 |
20220262696 | METHODS OF FABRICATING SEMICONDUCTOR PACKAGE - Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure. | 2022-08-18 |
20220262697 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts. | 2022-08-18 |
20220262698 | Passivation Structure with Planar Top Surfaces - A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening. | 2022-08-18 |
20220262699 | SEMICONDUCTOR PACKAGE INCLUDING THERMAL EXHAUST PATHWAY - A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip. | 2022-08-18 |
20220262700 | SEMICONDUCTOR PACKAGE - A heat spreader ( | 2022-08-18 |
20220262701 | HEAT DISSIPATION STRUCTURE, SEMICONDUCTOR PACKAGING DEVICE, AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGING DEVICE - A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board. | 2022-08-18 |
20220262702 | THERMALLY CONDUCTIVE SHEET AND METHOD FOR MANUFACTURING THERMALLY CONDUCTIVE SHEET - A thermally conductive sheet having a binder resin, a first thermally conductive filler, and a second thermally conductive filler, wherein the first thermally conductive filler and the second thermally conductive filler are dispersed in the binder resin, and the specific permittivity and the thermal conductivity are different in the thickness direction B and the surface direction A of the thermally conductive sheet. A thermally conductive sheet includes step A of preparing a resin composition for forming a thermally conductive sheet by dispersing a first thermally conductive filler and a second thermally conductive filler in a binder resin, step B of forming a molded block from the resin composition for forming a thermally conductive sheet, and step C of slicing the molded block into a sheet and obtaining a thermally conductive sheet having different relative permittivity and thermal conductivity in the thickness direction and the surface direction. | 2022-08-18 |
20220262703 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a wafer-form semiconductor package and a thermal dissipating system. The wafer-form semiconductor package includes semiconductor dies electrically connected with each other. The thermal dissipating system is located on and thermally coupled to the wafer-form semiconductor package, where the thermal dissipating system has a hollow structure with a fluidic space, and the fluidic space includes a ceiling and a floor. The thermal dissipating system includes at least one inlet opening, at least one outlet opening and a plurality of first microstructures. The at least one inlet opening and the at least one outlet opening are spatially communicated with the fluidic space. The first microstructures are located on the floor, and at least one of the first microstructures is corresponding to the at least one outlet opening. | 2022-08-18 |
20220262704 | IC PACKAGE WITH EMBEDDED LIQUID-BASED COOLING SYSTEM - The disclosed IC package may include (1) an IC die carrying electronic circuitry, (2) an encapsulation material at least partially covering the IC die, where (a) the encapsulation material defines a plurality of microchannels within the encapsulation material and (b) the plurality of microchannels are configured to carry fluid through the encapsulation material between one or more microchannel inlets and one or more microchannel outlets located at an exterior of the encapsulation material, (3) a plurality of flow valves positioned in the plurality of microchannels, and (4) a plurality of sensors, where each sensor of the plurality of sensors produces a signal indicating a temperature at a location of the sensor. Various other IC packages, as well as associated cooling systems and methods, are also disclosed. | 2022-08-18 |
20220262705 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches. | 2022-08-18 |
20220262706 | THERMOELECTRIC GENERATOR USING IN SITU PASSIVE COOLING - A portable electrical power generation system using thermoelectric modules to produce voltage from a temperature differential. The temperature differential is maintained using a passive cooling system including a retained liquid coolant and heat from a heated fluid. | 2022-08-18 |
20220262707 | Arrangement Comprising a Baseplate for a Power Semiconductor Module and a Cooler - An apparatus includes a baseplate and a cooler providing a cooling channel adapted for providing a coolant flow. An electronic circuit includes a power semiconductor device disposed at the first side of baseplate. A footprint of the power semiconductor device defines a device area on the first side. A cooling area at the second side of the baseplate opposite the device area is adapted for dissipating heat from the baseplate by bringing the cooling area into thermal contact with the coolant flow in the cooling channel. An auxiliary area is located on the second side of the baseplate adjacent to the cooling area. The auxiliary area includes a flow guide for reducing a flow rate of the coolant flow in the auxiliary area and the cooling channel is adapted to receive the cooling area and the flow guide. | 2022-08-18 |
20220262708 | Air Gap Seal for Interconnect Air Gap and Method of Fabricating Thereof - Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide. | 2022-08-18 |
20220262709 | HIGH POWER TRANSISTORS - High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of contacts in parallel. Thereby, the total gate width and the power rating of a high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating. | 2022-08-18 |
20220262710 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip in which a field effect transistor mainly containing GaN is formed on a surface of a SiC semiconductor substrate. The semiconductor device includes a metal base on which a back surface of the semiconductor chip is mounted through a conductive adhesive material containing Ag and a resin mold configured to seal the semiconductor chip. A metal having wettability lower than wettability of Au or Cu with respect to Ag is exposed in a region extending along an edge of the back surface. | 2022-08-18 |
20220262711 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided, including a lead frame, a metal pad and the metal pad is connected to a back side of the semiconductor device via the lead frame. The semiconductor device further includes a die pad, and the die pad is attached to the lead frame via a die attach material, and an encapsulant that is disposed on the top surface of the lead frame. The encapsulant isolates the metal pad from the die pad. | 2022-08-18 |
20220262712 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided, including a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. The second GaN die is positioned in an inverted orientation. The MOSFET die controls the first GaN die and the second GaN die. | 2022-08-18 |
20220262713 | PRINTED CIRCUIT BOARD AND PACKAGE SUBSTRATE INCLUDING SAME - A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion. | 2022-08-18 |
20220262714 | METHOD AND APPARATUS FOR THROUGH INTERPOSER DIE LEVEL INTERCONNECT WITH THERMAL MANAGEMENT - An electronic assembly is disclosed. The electronic assembly includes a first attachment layer, a second attachment layer, a first interposer redistribution layer, a second interposer redistribution layer, at least one of a thermal spreader layer or a thermal management layer, and an interposer cavity. The interposer further includes an interconnect header fixed within the interposer cavity comprising a plurality of interconnect filaments configured to electrically couple to at least one of the first interposer redistribution layer or the second interposer redistribution layer. The interconnect header is generated by applying electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking the wafers, attaching the wafers into a wafer stack, and dicing the wafer stack. | 2022-08-18 |
20220262715 | METHOD AND APPARATUS FOR THROUGH SILICON DIE LEVEL INTERCONNECT - An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack. | 2022-08-18 |
20220262716 | Semiconductor Package and Passive Element with Interposer - A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer. | 2022-08-18 |
20220262717 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device capable of reducing inductance between a high potential terminal and a low potential terminal while achieving downsizing of the semiconductor device. A semiconductor device includes: the insulating substrate; the circuit pattern including a low potential circuit pattern and a high potential circuit pattern provided on a region adjacent to the low potential circuit pattern; a plurality of semiconductor chips mounted on the circuit pattern; a low potential terminal having one end portion connected to the low potential circuit pattern; and a high potential terminal having one end portion connected to the high potential circuit pattern, wherein the high potential terminal and the low potential terminal include electrode parts and constituting parallel flat plates vertically disposed in parallel to each other and extending on a side of the low potential circuit pattern and electrode parts and protruding from the insulating substrate. | 2022-08-18 |
20220262718 | ISOLATING ELECTRIC PATHS IN SEMICONDUCTOR DEVICE PACKAGES - Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path. | 2022-08-18 |
20220262719 | DEEP LINES AND SHALLOW LINES IN SIGNAL CONDUCTING PATHS - An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer. | 2022-08-18 |
20220262720 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first stacked region, a second stacked region, and a connection region arranged between the first and second stacked regions. In the connection region, one of a plurality of conductor layers in an upper stepped portion is connected to one of the plurality of conductor layers in the first stacked region via one of the plurality of conductor layers in a bridge portion. | 2022-08-18 |
20220262721 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device includes; a semiconductor substrate including a first region and a second region, a first interlayer insulating layer on the second region, a capping layer disposed on the first interlayer insulating layer, an upper surface of the capping layer includes a first trench, conductive patterns spaced apart on the capping layer, side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench, and a peripheral separation pattern disposed in the first trench to cover the side surfaces of the conductive patterns. The peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns and a second thickness greater than or equal to the first thickness on a lower surface. | 2022-08-18 |
20220262722 | ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES - Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described. | 2022-08-18 |
20220262723 | SUBTRACTIVE DAMASCENE FORMATION OF HYBRID INTERCONNECTIONS - An integrated circuit (IC) having an interconnect structure with metal lines with different conductive materials for different widths and a method for fabricating such an IC. An example IC generally includes an active layer and an interconnect structure disposed thereabove and comprising a plurality of metal layers and one or more vias landing on metal lines. At least one of the plurality of metal layers comprises one or more first metal lines and one or more second metal lines. The one or more first metal lines have one or more first widths and comprise a first conductive material including copper. The one or more second metal lines have one or more second widths and comprise a second conductive material different from the first conductive material, where the second widths are narrower than the first widths. The vias have one or more third widths and comprise a third conductive material. | 2022-08-18 |
20220262724 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate; a plurality of first conductive layers arranged in a first direction; a first semiconductor column; a first bit line being disposed at a position overlapping the first semiconductor column viewed in the first direction; a first wiring including a part overlapping the first bit line viewed in the first direction; and a second wiring including a part overlapping the first bit line viewed in the first direction. When a period in which a voltage of the first wiring transitions from a high to a low voltage state is assumed to be a first period, and when a period in which a voltage of the second wiring transitions from a low to a high voltage state is assumed to be a second period, at least a part of the second period overlaps at least a part of the first period. | 2022-08-18 |
20220262725 | INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME - An interconnect structure includes an interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer. | 2022-08-18 |
20220262726 | Semiconductor Structure and Method Making the Same - The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer. | 2022-08-18 |
20220262727 | METHOD FOR FORMING VIA STRUCTURE HAVING LOW INTERFACE RESISTANCE - A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via. | 2022-08-18 |
20220262728 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a conductive line including a metal layer and an insulation capping structure covering the conductive line. The first insulation capping structure includes a first insulation capping pattern that is adjacent to the metal layer in the insulation capping structure and has a first density, and a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween and having a second density that is greater than the first density. In order to manufacture the integrated circuit device, the conductive line having a metal layer is formed on a substrate, a first insulation capping layer having the first density is formed directly on the metal layer, and a second insulation capping layer having the second density that is greater than the first density is formed on the first insulation capping layer. | 2022-08-18 |
20220262729 | Chip-type Fuse - A chip-type fuse includes a plated-shape fusible body ( | 2022-08-18 |
20220262730 | Interconnect Structure for Improving Memory Performance and/or Logic Performance - Configurations of metal layers of interconnect structures are disclosed herein that can improve memory performance, such as static random-access memory (SRAM) memory performance, and/or logic performance. For example, embodiments herein place bit lines in a metal one (M1) layer, which is a lowest metallization level of an interconnect structure of a memory cell, to minimize bit line capacitance, and configure bit lines as the widest metal lines of the metal one layer to minimize bit line resistance. In some embodiments, the interconnect structure has a double word line structure to reduce word line resistance. In some embodiments, the interconnect structure has a double voltage line structure to reduce voltage line resistance. In some embodiments, jogs are added to a word line and/or a voltage line to reduce its respective resistance. In some embodiments, via shapes of the interconnect structure are configured to reduce resistance of the interconnect structure. | 2022-08-18 |
20220262731 | SEMICONDUCTOR DEVICES - A semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plugs, first and second conductive structures, and a third contact plug. The gate structure may be on a substrate. The first and second source/drain layers may be at upper portions, respectively, of the substrate on opposite sidewalls of the gate structure and adjacent thereto. The first and second contact plugs may be on the first and second source/drain layers, respectively, and each contact plugs may extend in a vertical direction. The first and second conductive structures may contact upper surfaces of the first and second contact plugs, respectively. The third contact plug may contact an upper surface of the second conductive structure. A height and a width of the second conductive structure may be greater than a height and a width of the first conductive structure. | 2022-08-18 |
20220262732 | Standard Cell Layout for Better Routability - A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths. | 2022-08-18 |
20220262733 | Through-Core Via - A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard. | 2022-08-18 |
20220262734 | SEMICONDUCTOR PACKAGES AND FORMING METHODS THEREOF - A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure. | 2022-08-18 |
20220262735 | INTEGRATED POWER MODULE - A power module includes a power substrate, a number of power semiconductor die, and a number of connector pins. The power substrate includes a number of conductive traces. The power semiconductor die are mounted on the power substrate and electrically coupled to the conductive traces. The connector pins are each electrically coupled to a different one of the conductive traces and configured to be interconnected such that the power semiconductor die provide an active front-end and a switching power converter. By providing the power semiconductor die such that they can be interconnected to form an active front-end and a switching power converter in the same power module, the power module may provide a significantly more compact power converter system using both an active front-end and switching power converter. | 2022-08-18 |
20220262736 | FORMING SELF-ALIGNED MULTI-METAL INTERCONNECTS - An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances. | 2022-08-18 |
20220262737 | SEMICONDUCTOR DEVICE, ELECTRONIC MODULE, ELECTRONIC APPARATUS, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - To provide a semiconductor device further reduced in size. A semiconductor device including: a multilayer wiring board one surface of which is provided with an external connection terminal; and a plurality of active components that are provided to be stacked inside the multilayer wiring board and are connected to the external connection terminal via a connection via. The plurality of active components include a first active component provided on another surface side that is opposite to the one surface, and a second active component that is provided closer to the one surface than the first active component is and has a smaller planar area than the first active component. | 2022-08-18 |
20220262738 | INTEGRATED CIRCUIT CHIP INCLUDING WIRING STRUCTURE - An integrated circuit chip includes a base layer. A first wiring layer is disposed on the base layer and includes a plurality of first wiring structures. A second wiring layer is disposed on the first wiring layer and includes a plurality of second wiring structures. Each of the plurality of second wiring structures has a first metal layer and a second metal layer respectively having different resistivities. A third wiring layer is disposed on the second wiring layer and includes a plurality of third wiring structures. Each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures. | 2022-08-18 |
20220262739 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench. | 2022-08-18 |
20220262740 | ELECTRONIC ASSEMBLY, ELECTRONIC APPARATUS INCLUDING THE SAME AND METHOD FOR FABRICATING ELECTRONIC ASSEMBLY - An electronic assembly according to an embodiment includes: a circuit board including a first edge surface and a trace having an electrical conductivity; an electronic element including a lateral edge spatially spaced apart from the first edge surface, and mounted on the circuit board and electrically connected to the trace; a protection layer including a second edge surface and disposed on the electronic element to substantially cover the electronic element; a magnetic field shielding film including a third edge surface and disposed on the protection layer; and a first metal layer. The first edge surface connects a main top surface of the circuit board and a main bottom surface of the circuit board, the second edge surface connects a main top surface of the protection layer and a main bottom surface of the protection layer, and the third edge surface connects a main top surface of the magnetic field shielding film and a main bottom surface of the magnetic field shielding film, and the first edge surface, the second edge surface, and the third edge surface are substantially aligned with one another to form a coupling edge surface which is substantially planar. In addition, the first metal layer is disposed on the magnetic field shielding film, and covers the main top surface of the magnetic field shielding film and the coupling edge surface. | 2022-08-18 |
20220262741 | SEMICONDUCTOR PACKAGE WITH EMI SHIELDING STRUCTURE - A semiconductor package includes a carrier substrate having a top surface; a semiconductor die mounted on the top surface; first bonding wires connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the plurality of first bonding wires; a component having a metal layer mounted on the insulating material; second bonding wires connecting the metal layer of the component to the carrier substrate; and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the component, the first bonding wires, the second bonding wires, and the insulating material. The metal layer and the second bonding wires constitute an electromagnetic interference (EMI) shielding structure. | 2022-08-18 |
20220262742 | CHIPLET INTERPOSER - Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures. | 2022-08-18 |
20220262743 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions. | 2022-08-18 |
20220262744 | SEMICONDUCTOR MEMORY DEVICE - Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction. | 2022-08-18 |
20220262745 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating. | 2022-08-18 |
20220262746 | SEMICONDUCTOR DEVICE PACKAGE WITH WARPAGE CONTROL STRUCTURE - A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer. | 2022-08-18 |
20220262747 | ELECTRONIC PACKAGE - An electronic package is provided, including at least an electronic element and at least an antenna structure disposed on a carrier structure. The antenna structure includes a base portion configured with an antenna body and a plurality of support portions disposed on the base portion. As such, the base portion is disposed over the carrier structure through the support portions and a plurality of open areas are formed between the base portion and the carrier structure to serve as an air gap, thereby effectively improving the performance gain and efficiency of the antenna body. | 2022-08-18 |
20220262748 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a connection structure having a first surface and a second, and including a redistribution layer; a passive component disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip; a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the passive component; an antenna substrate disposed on the first encapsulant and including a wiring layer, at least a portion of the wiring layer including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate. | 2022-08-18 |
20220262749 | INTEGRATED CIRCUIT STRUCTURE AND FABRICATION METHOD THEREOF - An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer. | 2022-08-18 |
20220262750 | A Semiconductor Device and a Method Making the Same - A semiconductor structure includes a supporting layer including a pad area; and a groove formed in the pad area of the supporting layer, wherein a bottom width of the groove is greater than a top width of the groove; and a pad disposed in the pad area on the supporting layer, wherein the pad is partially embedded in the groove. This structure can help to release the bonding pressure during the wire bonding process. When the pad is squeezed out, it can enter the air cavity, which can prevent the protective layer from being lifted up or cracked, and avoid the pad from overflowing. At the same time, the bonding wire squeezed into the air cavity during bonding process increases the contact area between the pad and the supporting layer, thereby enhancing the stability of the overall structure. | 2022-08-18 |
20220262751 | Chip Package on Package Structure, Packaging Method Thereof, and Electronic Device - A chip package on package structure includes a primary chip stack unit having pins insulated and spaced from each other on a first surface; a first bonding layer disposed on the first surface, where the first bonding layer includes bonding components insulated and spaced from each other, each bonding component includes a bonding part, and any two bonding parts are insulated and have a same cross-sectional area, and the bonding components are separately bonded to the pins; and secondary chip stack units, disposed on a surface of a side that is of the first bonding layer and that is away from the primary chip stack unit, where the secondary chip stack unit has micro bumps insulated and spaced from each other, and each of the micro bumps is bonded to one of the bonding components. | 2022-08-18 |
20220262752 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device. | 2022-08-18 |
20220262753 | SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS - A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer. | 2022-08-18 |
20220262754 | SINTERING A NANOPARTICLE PASTE FOR SEMICONDUCTOR CHIP JOIN - An approach to provide a method of joining a semiconductor chip to a semiconductor substrate, the approach includes depositing a nanoparticle paste and aligning each of one or more solder contacts on a semiconductor chip to a substrate bond pad. The approach includes sintering, in a reducing gaseous environment, the nanoparticle paste to connect the semiconductor chip to a semiconductor substrate bond pad. | 2022-08-18 |
20220262755 | TEMPORARY BONDING AND DEBONDING PROCESS TO PREVENT DEFORMATION OF METAL CONNECTION IN THERMOCOMPRESSION BONDING - Achieving homogeneous and heterogeneous integration for 2.5D and 3D integrated circuit, chip-to-wafer, chip-to-substrate, or wafer-to-wafer bonding is an essential technology. The landing wafer or substrate is bonded with a carrier by using a temporary bonding material before thinning the landing wafer to the desired thickness. Upon completion of redistribution layer formation, Cu pad formation, or other backside processing, dies or wafers with through-silicon vias are stacked onto the landing substrate before molding and singulation. As the landing wafer usually has interconnection metals in the bond line, and those interconnection metals are typically made from lead-free solder alloys, deformation of those solder alloys during thermocompression bonding becomes an issue for manufacturers. To address this issue, a polymeric material with desired strengths is coated on the device wafer to form a conformal protective layer on top of solder alloys, thus enabling temporary bonding and debonding processes. | 2022-08-18 |
20220262756 | CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS - Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed. | 2022-08-18 |
20220262757 | SEMICONDUCTOR DEVICES INCLUDING THICK PAD - A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring. | 2022-08-18 |
20220262758 | PACKAGE STRUCTURE AND MANUFACTURING METHOD OF PACKAGE STRUCTURE THEREOF - A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line. | 2022-08-18 |
20220262759 | ELECTRONIC APPARATUS, SEMICONDUCTOR DEVICE, INSULATING SHEET, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a structure using a metal having fluidity as a thermally conductive material, the thermally conductive material is prevented from entering an unintended region even in a case where a change in attitude of a semiconductor device or vibration occurs. An electronic apparatus has a thermally conductive material ( | 2022-08-18 |
20220262760 | ANISOTROPIC CONDUCTIVE FILM AND METHOD OF PRODUCING THE SAME - An anisotropic conductive film has a three-layer structure in which a first connection layer is sandwiched between a second connection layer and a third connection layer that each are formed mainly of an insulating resin. The first connection layer has a structure in which conductive particles are arranged in a single layer in the plane direction of an insulating resin layer on a side of the second connection layer, and the thickness of the insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than that of the insulating resin layer in regions in proximity to the conductive particles. | 2022-08-18 |
20220262761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The semiconductor device includes: a semiconductor element including a body portion formed in a plate shape, a protection film provided at an outer periphery on one surface of the body portion, and a metal thin film provided adjacently to an inner side of the protection film on the one surface of the body portion; a metal member joined to a surface of the metal thin film on a side opposite to the body portion, by solder; and a mold resin sealing the semiconductor element and the metal member, wherein the surface of the metal thin film on the side opposite to the body portion has, on at least a part of an outer periphery thereof, a projection portion projecting from the surface of the metal thin film, and the solder is not provided on an outer peripheral side from a top of the projection portion. | 2022-08-18 |
20220262762 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein. | 2022-08-18 |
20220262763 | PRESS-PACK SEMICONDUCTOR FIXTURES - A press-pack semiconductor fixture | 2022-08-18 |
20220262764 | MANUFACTURING APPARATUS, OPERATION METHOD THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing apparatus includes: a storage configured to store a work; a transfer arm configured to transfer the work; a hot bath configured to store a liquid; a mounting table configured to mount the work in the hot bath; and an upper arm configured to apply pressure to the work mounted on the mounting table. | 2022-08-18 |
20220262765 | Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices - Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon. | 2022-08-18 |
20220262766 | Through-Dielectric Vias for Direct Connection and Method Forming Same - A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die. | 2022-08-18 |
20220262767 | SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME - A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via. | 2022-08-18 |
20220262768 | INACTIVE STRUCTURE ON SOIC - A package device includes a first device die and second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more inactive structures having a semiconductor substrate is also bonded to the first device die so that the combined area of the second device die and the one or more inactive structures is greater than half the area of the first device die. | 2022-08-18 |
20220262769 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad. | 2022-08-18 |
20220262770 | HYBRID BONDING TECHNOLOGY FOR STACKING INTEGRATED CIRCUITS - A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the | 2022-08-18 |
20220262771 | PACKAGE AND MANUFACTURING METHOD THEREOF - A package includes a first die, a second die, and an encapsulant. The first die has a first interconnection structure, and the first interconnection structure includes a first capacitor embedded therein. The second die has a second interconnection structure, and the second interconnection structure includes a second capacitor embedded therein. The first interconnection structure faces the second interconnection structure. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die. | 2022-08-18 |